1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/video/aty/radeon_pm.c 4 * 5 * Copyright 2003,2004 Ben. Herrenschmidt <benh@kernel.crashing.org> 6 * Copyright 2004 Paul Mackerras <paulus@samba.org> 7 * 8 * This is the power management code for ATI radeon chipsets. It contains 9 * some dynamic clock PM enable/disable code similar to what X.org does, 10 * some D2-state (APM-style) sleep/wakeup code for use on some PowerMacs, 11 * and the necessary bits to re-initialize from scratch a few chips found 12 * on PowerMacs as well. The later could be extended to more platforms 13 * provided the memory controller configuration code be made more generic, 14 * and you can get the proper mode register commands for your RAMs. 15 * Those things may be found in the BIOS image... 16 */ 17 18 #include "radeonfb.h" 19 20 #include <linux/console.h> 21 #include <linux/agp_backend.h> 22 23 #ifdef CONFIG_PPC_PMAC 24 #include <asm/machdep.h> 25 #include <asm/prom.h> 26 #include <asm/pmac_feature.h> 27 #endif 28 29 #include "ati_ids.h" 30 31 /* 32 * Workarounds for bugs in PC laptops: 33 * - enable D2 sleep in some IBM Thinkpads 34 * - special case for Samsung P35 35 * 36 * Whitelist by subsystem vendor/device because 37 * its the subsystem vendor's fault! 38 */ 39 40 #if defined(CONFIG_PM) && defined(CONFIG_X86) 41 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo); 42 43 struct radeon_device_id { 44 const char *ident; /* (arbitrary) Name */ 45 const unsigned short subsystem_vendor; /* Subsystem Vendor ID */ 46 const unsigned short subsystem_device; /* Subsystem Device ID */ 47 const enum radeon_pm_mode pm_mode_modifier; /* modify pm_mode */ 48 const reinit_function_ptr new_reinit_func; /* changed reinit_func */ 49 }; 50 51 #define BUGFIX(model, sv, sd, pm, fn) { \ 52 .ident = model, \ 53 .subsystem_vendor = sv, \ 54 .subsystem_device = sd, \ 55 .pm_mode_modifier = pm, \ 56 .new_reinit_func = fn \ 57 } 58 59 static struct radeon_device_id radeon_workaround_list[] = { 60 BUGFIX("IBM Thinkpad R32", 61 PCI_VENDOR_ID_IBM, 0x1905, 62 radeon_pm_d2, NULL), 63 BUGFIX("IBM Thinkpad R40", 64 PCI_VENDOR_ID_IBM, 0x0526, 65 radeon_pm_d2, NULL), 66 BUGFIX("IBM Thinkpad R40", 67 PCI_VENDOR_ID_IBM, 0x0527, 68 radeon_pm_d2, NULL), 69 BUGFIX("IBM Thinkpad R50/R51/T40/T41", 70 PCI_VENDOR_ID_IBM, 0x0531, 71 radeon_pm_d2, NULL), 72 BUGFIX("IBM Thinkpad R51/T40/T41/T42", 73 PCI_VENDOR_ID_IBM, 0x0530, 74 radeon_pm_d2, NULL), 75 BUGFIX("IBM Thinkpad T30", 76 PCI_VENDOR_ID_IBM, 0x0517, 77 radeon_pm_d2, NULL), 78 BUGFIX("IBM Thinkpad T40p", 79 PCI_VENDOR_ID_IBM, 0x054d, 80 radeon_pm_d2, NULL), 81 BUGFIX("IBM Thinkpad T42", 82 PCI_VENDOR_ID_IBM, 0x0550, 83 radeon_pm_d2, NULL), 84 BUGFIX("IBM Thinkpad X31/X32", 85 PCI_VENDOR_ID_IBM, 0x052f, 86 radeon_pm_d2, NULL), 87 BUGFIX("Samsung P35", 88 PCI_VENDOR_ID_SAMSUNG, 0xc00c, 89 radeon_pm_off, radeon_reinitialize_M10), 90 BUGFIX("Acer Aspire 2010", 91 PCI_VENDOR_ID_AI, 0x0061, 92 radeon_pm_off, radeon_reinitialize_M10), 93 BUGFIX("Acer Travelmate 290D/292LMi", 94 PCI_VENDOR_ID_AI, 0x005a, 95 radeon_pm_off, radeon_reinitialize_M10), 96 { .ident = NULL } 97 }; 98 99 static int radeon_apply_workarounds(struct radeonfb_info *rinfo) 100 { 101 struct radeon_device_id *id; 102 103 for (id = radeon_workaround_list; id->ident != NULL; id++ ) 104 if ((id->subsystem_vendor == rinfo->pdev->subsystem_vendor ) && 105 (id->subsystem_device == rinfo->pdev->subsystem_device )) { 106 107 /* we found a device that requires workaround */ 108 printk(KERN_DEBUG "radeonfb: %s detected" 109 ", enabling workaround\n", id->ident); 110 111 rinfo->pm_mode |= id->pm_mode_modifier; 112 113 if (id->new_reinit_func != NULL) 114 rinfo->reinit_func = id->new_reinit_func; 115 116 return 1; 117 } 118 return 0; /* not found */ 119 } 120 121 #else /* defined(CONFIG_PM) && defined(CONFIG_X86) */ 122 static inline int radeon_apply_workarounds(struct radeonfb_info *rinfo) 123 { 124 return 0; 125 } 126 #endif /* defined(CONFIG_PM) && defined(CONFIG_X86) */ 127 128 129 130 static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo) 131 { 132 u32 tmp; 133 134 /* RV100 */ 135 if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) { 136 if (rinfo->has_CRTC2) { 137 tmp = INPLL(pllSCLK_CNTL); 138 tmp &= ~SCLK_CNTL__DYN_STOP_LAT_MASK; 139 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | SCLK_CNTL__FORCEON_MASK; 140 OUTPLL(pllSCLK_CNTL, tmp); 141 } 142 tmp = INPLL(pllMCLK_CNTL); 143 tmp |= (MCLK_CNTL__FORCE_MCLKA | 144 MCLK_CNTL__FORCE_MCLKB | 145 MCLK_CNTL__FORCE_YCLKA | 146 MCLK_CNTL__FORCE_YCLKB | 147 MCLK_CNTL__FORCE_AIC | 148 MCLK_CNTL__FORCE_MC); 149 OUTPLL(pllMCLK_CNTL, tmp); 150 return; 151 } 152 /* R100 */ 153 if (!rinfo->has_CRTC2) { 154 tmp = INPLL(pllSCLK_CNTL); 155 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_HDP | 156 SCLK_CNTL__FORCE_DISP1 | SCLK_CNTL__FORCE_TOP | 157 SCLK_CNTL__FORCE_E2 | SCLK_CNTL__FORCE_SE | 158 SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_VIP | 159 SCLK_CNTL__FORCE_RE | SCLK_CNTL__FORCE_PB | 160 SCLK_CNTL__FORCE_TAM | SCLK_CNTL__FORCE_TDM | 161 SCLK_CNTL__FORCE_RB); 162 OUTPLL(pllSCLK_CNTL, tmp); 163 return; 164 } 165 /* RV350 (M10/M11) */ 166 if (rinfo->family == CHIP_FAMILY_RV350) { 167 /* for RV350/M10/M11, no delays are required. */ 168 tmp = INPLL(pllSCLK_CNTL2); 169 tmp |= (SCLK_CNTL2__R300_FORCE_TCL | 170 SCLK_CNTL2__R300_FORCE_GA | 171 SCLK_CNTL2__R300_FORCE_CBA); 172 OUTPLL(pllSCLK_CNTL2, tmp); 173 174 tmp = INPLL(pllSCLK_CNTL); 175 tmp |= (SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP | 176 SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 | 177 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 | 178 SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT | 179 SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR | 180 SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX | 181 SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK | 182 SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0); 183 OUTPLL(pllSCLK_CNTL, tmp); 184 185 tmp = INPLL(pllSCLK_MORE_CNTL); 186 tmp |= (SCLK_MORE_CNTL__FORCE_DISPREGS | SCLK_MORE_CNTL__FORCE_MC_GUI | 187 SCLK_MORE_CNTL__FORCE_MC_HOST); 188 OUTPLL(pllSCLK_MORE_CNTL, tmp); 189 190 tmp = INPLL(pllMCLK_CNTL); 191 tmp |= (MCLK_CNTL__FORCE_MCLKA | 192 MCLK_CNTL__FORCE_MCLKB | 193 MCLK_CNTL__FORCE_YCLKA | 194 MCLK_CNTL__FORCE_YCLKB | 195 MCLK_CNTL__FORCE_MC); 196 OUTPLL(pllMCLK_CNTL, tmp); 197 198 tmp = INPLL(pllVCLK_ECP_CNTL); 199 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | 200 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb | 201 VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); 202 OUTPLL(pllVCLK_ECP_CNTL, tmp); 203 204 tmp = INPLL(pllPIXCLKS_CNTL); 205 tmp &= ~(PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | 206 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb | 207 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 208 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb | 209 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb | 210 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb | 211 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb | 212 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb | 213 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb | 214 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb | 215 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb | 216 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb | 217 PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); 218 OUTPLL(pllPIXCLKS_CNTL, tmp); 219 220 return; 221 } 222 223 /* Default */ 224 225 /* Force Core Clocks */ 226 tmp = INPLL(pllSCLK_CNTL); 227 tmp |= (SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_E2); 228 229 /* XFree doesn't do that case, but we had this code from Apple and it 230 * seem necessary for proper suspend/resume operations 231 */ 232 if (rinfo->is_mobility) { 233 tmp |= SCLK_CNTL__FORCE_HDP| 234 SCLK_CNTL__FORCE_DISP1| 235 SCLK_CNTL__FORCE_DISP2| 236 SCLK_CNTL__FORCE_TOP| 237 SCLK_CNTL__FORCE_SE| 238 SCLK_CNTL__FORCE_IDCT| 239 SCLK_CNTL__FORCE_VIP| 240 SCLK_CNTL__FORCE_PB| 241 SCLK_CNTL__FORCE_RE| 242 SCLK_CNTL__FORCE_TAM| 243 SCLK_CNTL__FORCE_TDM| 244 SCLK_CNTL__FORCE_RB| 245 SCLK_CNTL__FORCE_TV_SCLK| 246 SCLK_CNTL__FORCE_SUBPIC| 247 SCLK_CNTL__FORCE_OV0; 248 } 249 else if (rinfo->family == CHIP_FAMILY_R300 || 250 rinfo->family == CHIP_FAMILY_R350) { 251 tmp |= SCLK_CNTL__FORCE_HDP | 252 SCLK_CNTL__FORCE_DISP1 | 253 SCLK_CNTL__FORCE_DISP2 | 254 SCLK_CNTL__FORCE_TOP | 255 SCLK_CNTL__FORCE_IDCT | 256 SCLK_CNTL__FORCE_VIP; 257 } 258 OUTPLL(pllSCLK_CNTL, tmp); 259 radeon_msleep(16); 260 261 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) { 262 tmp = INPLL(pllSCLK_CNTL2); 263 tmp |= SCLK_CNTL2__R300_FORCE_TCL | 264 SCLK_CNTL2__R300_FORCE_GA | 265 SCLK_CNTL2__R300_FORCE_CBA; 266 OUTPLL(pllSCLK_CNTL2, tmp); 267 radeon_msleep(16); 268 } 269 270 tmp = INPLL(pllCLK_PIN_CNTL); 271 tmp &= ~CLK_PIN_CNTL__SCLK_DYN_START_CNTL; 272 OUTPLL(pllCLK_PIN_CNTL, tmp); 273 radeon_msleep(15); 274 275 if (rinfo->is_IGP) { 276 /* Weird ... X is _un_ forcing clocks here, I think it's 277 * doing backward. Imitate it for now... 278 */ 279 tmp = INPLL(pllMCLK_CNTL); 280 tmp &= ~(MCLK_CNTL__FORCE_MCLKA | 281 MCLK_CNTL__FORCE_YCLKA); 282 OUTPLL(pllMCLK_CNTL, tmp); 283 radeon_msleep(16); 284 } 285 /* Hrm... same shit, X doesn't do that but I have to */ 286 else if (rinfo->is_mobility) { 287 tmp = INPLL(pllMCLK_CNTL); 288 tmp |= (MCLK_CNTL__FORCE_MCLKA | 289 MCLK_CNTL__FORCE_MCLKB | 290 MCLK_CNTL__FORCE_YCLKA | 291 MCLK_CNTL__FORCE_YCLKB); 292 OUTPLL(pllMCLK_CNTL, tmp); 293 radeon_msleep(16); 294 295 tmp = INPLL(pllMCLK_MISC); 296 tmp &= ~(MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT| 297 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT| 298 MCLK_MISC__MC_MCLK_DYN_ENABLE| 299 MCLK_MISC__IO_MCLK_DYN_ENABLE); 300 OUTPLL(pllMCLK_MISC, tmp); 301 radeon_msleep(15); 302 } 303 304 if (rinfo->is_mobility) { 305 tmp = INPLL(pllSCLK_MORE_CNTL); 306 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS| 307 SCLK_MORE_CNTL__FORCE_MC_GUI| 308 SCLK_MORE_CNTL__FORCE_MC_HOST; 309 OUTPLL(pllSCLK_MORE_CNTL, tmp); 310 radeon_msleep(16); 311 } 312 313 tmp = INPLL(pllPIXCLKS_CNTL); 314 tmp &= ~(PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb | 315 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb| 316 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb | 317 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb| 318 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb| 319 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb| 320 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb); 321 OUTPLL(pllPIXCLKS_CNTL, tmp); 322 radeon_msleep(16); 323 324 tmp = INPLL( pllVCLK_ECP_CNTL); 325 tmp &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | 326 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb); 327 OUTPLL( pllVCLK_ECP_CNTL, tmp); 328 radeon_msleep(16); 329 } 330 331 static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo) 332 { 333 u32 tmp; 334 335 /* R100 */ 336 if (!rinfo->has_CRTC2) { 337 tmp = INPLL(pllSCLK_CNTL); 338 339 if ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13) 340 tmp &= ~(SCLK_CNTL__FORCE_CP | SCLK_CNTL__FORCE_RB); 341 tmp &= ~(SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 | 342 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_SE | 343 SCLK_CNTL__FORCE_IDCT | SCLK_CNTL__FORCE_RE | 344 SCLK_CNTL__FORCE_PB | SCLK_CNTL__FORCE_TAM | 345 SCLK_CNTL__FORCE_TDM); 346 OUTPLL(pllSCLK_CNTL, tmp); 347 return; 348 } 349 350 /* M10/M11 */ 351 if (rinfo->family == CHIP_FAMILY_RV350) { 352 tmp = INPLL(pllSCLK_CNTL2); 353 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL | 354 SCLK_CNTL2__R300_FORCE_GA | 355 SCLK_CNTL2__R300_FORCE_CBA); 356 tmp |= (SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT | 357 SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT | 358 SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT); 359 OUTPLL(pllSCLK_CNTL2, tmp); 360 361 tmp = INPLL(pllSCLK_CNTL); 362 tmp &= ~(SCLK_CNTL__FORCE_DISP2 | SCLK_CNTL__FORCE_CP | 363 SCLK_CNTL__FORCE_HDP | SCLK_CNTL__FORCE_DISP1 | 364 SCLK_CNTL__FORCE_TOP | SCLK_CNTL__FORCE_E2 | 365 SCLK_CNTL__R300_FORCE_VAP | SCLK_CNTL__FORCE_IDCT | 366 SCLK_CNTL__FORCE_VIP | SCLK_CNTL__R300_FORCE_SR | 367 SCLK_CNTL__R300_FORCE_PX | SCLK_CNTL__R300_FORCE_TX | 368 SCLK_CNTL__R300_FORCE_US | SCLK_CNTL__FORCE_TV_SCLK | 369 SCLK_CNTL__R300_FORCE_SU | SCLK_CNTL__FORCE_OV0); 370 tmp |= SCLK_CNTL__DYN_STOP_LAT_MASK; 371 OUTPLL(pllSCLK_CNTL, tmp); 372 373 tmp = INPLL(pllSCLK_MORE_CNTL); 374 tmp &= ~SCLK_MORE_CNTL__FORCEON; 375 tmp |= SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT | 376 SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT | 377 SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT; 378 OUTPLL(pllSCLK_MORE_CNTL, tmp); 379 380 tmp = INPLL(pllVCLK_ECP_CNTL); 381 tmp |= (VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | 382 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb); 383 OUTPLL(pllVCLK_ECP_CNTL, tmp); 384 385 tmp = INPLL(pllPIXCLKS_CNTL); 386 tmp |= (PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | 387 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb | 388 PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 389 PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb | 390 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb | 391 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb | 392 PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb | 393 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb | 394 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb | 395 PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb | 396 PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb | 397 PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb | 398 PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb); 399 OUTPLL(pllPIXCLKS_CNTL, tmp); 400 401 tmp = INPLL(pllMCLK_MISC); 402 tmp |= (MCLK_MISC__MC_MCLK_DYN_ENABLE | 403 MCLK_MISC__IO_MCLK_DYN_ENABLE); 404 OUTPLL(pllMCLK_MISC, tmp); 405 406 tmp = INPLL(pllMCLK_CNTL); 407 tmp |= (MCLK_CNTL__FORCE_MCLKA | MCLK_CNTL__FORCE_MCLKB); 408 tmp &= ~(MCLK_CNTL__FORCE_YCLKA | 409 MCLK_CNTL__FORCE_YCLKB | 410 MCLK_CNTL__FORCE_MC); 411 412 /* Some releases of vbios have set DISABLE_MC_MCLKA 413 * and DISABLE_MC_MCLKB bits in the vbios table. Setting these 414 * bits will cause H/W hang when reading video memory with dynamic 415 * clocking enabled. 416 */ 417 if ((tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKA) && 418 (tmp & MCLK_CNTL__R300_DISABLE_MC_MCLKB)) { 419 /* If both bits are set, then check the active channels */ 420 tmp = INPLL(pllMCLK_CNTL); 421 if (rinfo->vram_width == 64) { 422 if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY) 423 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKB; 424 else 425 tmp &= ~MCLK_CNTL__R300_DISABLE_MC_MCLKA; 426 } else { 427 tmp &= ~(MCLK_CNTL__R300_DISABLE_MC_MCLKA | 428 MCLK_CNTL__R300_DISABLE_MC_MCLKB); 429 } 430 } 431 OUTPLL(pllMCLK_CNTL, tmp); 432 return; 433 } 434 435 /* R300 */ 436 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) { 437 tmp = INPLL(pllSCLK_CNTL); 438 tmp &= ~(SCLK_CNTL__R300_FORCE_VAP); 439 tmp |= SCLK_CNTL__FORCE_CP; 440 OUTPLL(pllSCLK_CNTL, tmp); 441 radeon_msleep(15); 442 443 tmp = INPLL(pllSCLK_CNTL2); 444 tmp &= ~(SCLK_CNTL2__R300_FORCE_TCL | 445 SCLK_CNTL2__R300_FORCE_GA | 446 SCLK_CNTL2__R300_FORCE_CBA); 447 OUTPLL(pllSCLK_CNTL2, tmp); 448 } 449 450 /* Others */ 451 452 tmp = INPLL( pllCLK_PWRMGT_CNTL); 453 tmp &= ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK| 454 CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK| 455 CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK); 456 tmp |= CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK | 457 (0x01 << CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT); 458 OUTPLL( pllCLK_PWRMGT_CNTL, tmp); 459 radeon_msleep(15); 460 461 tmp = INPLL(pllCLK_PIN_CNTL); 462 tmp |= CLK_PIN_CNTL__SCLK_DYN_START_CNTL; 463 OUTPLL(pllCLK_PIN_CNTL, tmp); 464 radeon_msleep(15); 465 466 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 467 * to lockup randomly, leave them as set by BIOS. 468 */ 469 tmp = INPLL(pllSCLK_CNTL); 470 tmp &= ~SCLK_CNTL__FORCEON_MASK; 471 472 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/ 473 if ((rinfo->family == CHIP_FAMILY_RV250 && 474 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) || 475 ((rinfo->family == CHIP_FAMILY_RV100) && 476 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) { 477 tmp |= SCLK_CNTL__FORCE_CP; 478 tmp |= SCLK_CNTL__FORCE_VIP; 479 } 480 OUTPLL(pllSCLK_CNTL, tmp); 481 radeon_msleep(15); 482 483 if ((rinfo->family == CHIP_FAMILY_RV200) || 484 (rinfo->family == CHIP_FAMILY_RV250) || 485 (rinfo->family == CHIP_FAMILY_RV280)) { 486 tmp = INPLL(pllSCLK_MORE_CNTL); 487 tmp &= ~SCLK_MORE_CNTL__FORCEON; 488 489 /* RV200::A11 A12 RV250::A11 A12 */ 490 if (((rinfo->family == CHIP_FAMILY_RV200) || 491 (rinfo->family == CHIP_FAMILY_RV250)) && 492 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) 493 tmp |= SCLK_MORE_CNTL__FORCEON; 494 495 OUTPLL(pllSCLK_MORE_CNTL, tmp); 496 radeon_msleep(15); 497 } 498 499 500 /* RV200::A11 A12, RV250::A11 A12 */ 501 if (((rinfo->family == CHIP_FAMILY_RV200) || 502 (rinfo->family == CHIP_FAMILY_RV250)) && 503 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) { 504 tmp = INPLL(pllPLL_PWRMGT_CNTL); 505 tmp |= PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE; 506 OUTPLL(pllPLL_PWRMGT_CNTL, tmp); 507 radeon_msleep(15); 508 } 509 510 tmp = INPLL(pllPIXCLKS_CNTL); 511 tmp |= PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb | 512 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb| 513 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb| 514 PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb| 515 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb| 516 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb| 517 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb; 518 OUTPLL(pllPIXCLKS_CNTL, tmp); 519 radeon_msleep(15); 520 521 tmp = INPLL(pllVCLK_ECP_CNTL); 522 tmp |= VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb | 523 VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb; 524 OUTPLL(pllVCLK_ECP_CNTL, tmp); 525 526 /* X doesn't do that ... hrm, we do on mobility && Macs */ 527 #ifdef CONFIG_PPC 528 if (rinfo->is_mobility) { 529 tmp = INPLL(pllMCLK_CNTL); 530 tmp &= ~(MCLK_CNTL__FORCE_MCLKA | 531 MCLK_CNTL__FORCE_MCLKB | 532 MCLK_CNTL__FORCE_YCLKA | 533 MCLK_CNTL__FORCE_YCLKB); 534 OUTPLL(pllMCLK_CNTL, tmp); 535 radeon_msleep(15); 536 537 tmp = INPLL(pllMCLK_MISC); 538 tmp |= MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT| 539 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT| 540 MCLK_MISC__MC_MCLK_DYN_ENABLE| 541 MCLK_MISC__IO_MCLK_DYN_ENABLE; 542 OUTPLL(pllMCLK_MISC, tmp); 543 radeon_msleep(15); 544 } 545 #endif /* CONFIG_PPC */ 546 } 547 548 #ifdef CONFIG_PM 549 550 static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value) 551 { 552 OUTREG( MC_IND_INDEX, indx | MC_IND_INDEX__MC_IND_WR_EN); 553 OUTREG( MC_IND_DATA, value); 554 } 555 556 static u32 INMC(struct radeonfb_info *rinfo, u8 indx) 557 { 558 OUTREG( MC_IND_INDEX, indx); 559 return INREG( MC_IND_DATA); 560 } 561 562 static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3) 563 { 564 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL); 565 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL); 566 rinfo->save_regs[2] = INPLL(MCLK_CNTL); 567 rinfo->save_regs[3] = INPLL(SCLK_CNTL); 568 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL); 569 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL); 570 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL); 571 rinfo->save_regs[7] = INPLL(MCLK_MISC); 572 rinfo->save_regs[8] = INPLL(P2PLL_CNTL); 573 574 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL); 575 rinfo->save_regs[10] = INREG(DISP_PWR_MAN); 576 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL); 577 rinfo->save_regs[13] = INREG(TV_DAC_CNTL); 578 rinfo->save_regs[14] = INREG(BUS_CNTL1); 579 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL); 580 rinfo->save_regs[16] = INREG(AGP_CNTL); 581 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000; 582 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000; 583 rinfo->save_regs[19] = INREG(GPIOPAD_A); 584 rinfo->save_regs[20] = INREG(GPIOPAD_EN); 585 rinfo->save_regs[21] = INREG(GPIOPAD_MASK); 586 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A); 587 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN); 588 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK); 589 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC); 590 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC); 591 rinfo->save_regs[27] = INREG(GPIO_MONID); 592 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC); 593 594 rinfo->save_regs[29] = INREG(SURFACE_CNTL); 595 rinfo->save_regs[30] = INREG(MC_FB_LOCATION); 596 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR); 597 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION); 598 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR); 599 600 rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL); 601 rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG); 602 rinfo->save_regs[36] = INREG(BUS_CNTL); 603 rinfo->save_regs[39] = INREG(RBBM_CNTL); 604 rinfo->save_regs[40] = INREG(DAC_CNTL); 605 rinfo->save_regs[41] = INREG(HOST_PATH_CNTL); 606 rinfo->save_regs[37] = INREG(MPP_TB_CONFIG); 607 rinfo->save_regs[38] = INREG(FCP_CNTL); 608 609 if (rinfo->is_mobility) { 610 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL); 611 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL); 612 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV); 613 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0); 614 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL); 615 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL); 616 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL); 617 } 618 619 if (rinfo->family >= CHIP_FAMILY_RV200) { 620 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL); 621 rinfo->save_regs[46] = INREG(MC_CNTL); 622 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER); 623 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER); 624 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL); 625 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB); 626 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL); 627 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB); 628 rinfo->save_regs[53] = INREG(MC_DEBUG); 629 } 630 rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL); 631 rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL); 632 rinfo->save_regs[56] = INREG(PAD_CTLR_MISC); 633 rinfo->save_regs[57] = INREG(FW_CNTL); 634 635 if (rinfo->family >= CHIP_FAMILY_R300) { 636 rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER); 637 rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL); 638 rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0); 639 rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1); 640 rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0); 641 rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1); 642 rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3); 643 rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0); 644 rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1); 645 rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0); 646 rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1); 647 rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL); 648 rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL); 649 rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0); 650 rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL); 651 rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD); 652 } else { 653 rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL); 654 rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0); 655 rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1); 656 rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0); 657 rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1); 658 rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0); 659 } 660 661 rinfo->save_regs[73] = INPLL(pllMPLL_CNTL); 662 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL); 663 rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL); 664 rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL); 665 rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV); 666 rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL); 667 rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL); 668 669 rinfo->save_regs[80] = INREG(OV0_BASE_ADDR); 670 rinfo->save_regs[82] = INREG(FP_GEN_CNTL); 671 rinfo->save_regs[83] = INREG(FP2_GEN_CNTL); 672 rinfo->save_regs[84] = INREG(TMDS_CNTL); 673 rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL); 674 rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL); 675 rinfo->save_regs[87] = INREG(DISP_HW_DEBUG); 676 rinfo->save_regs[88] = INREG(TV_MASTER_CNTL); 677 rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV); 678 rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0); 679 rinfo->save_regs[93] = INPLL(pllPPLL_CNTL); 680 rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL); 681 rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL); 682 rinfo->save_regs[96] = INREG(HDP_DEBUG); 683 rinfo->save_regs[97] = INPLL(pllMDLL_CKO); 684 rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA); 685 rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB); 686 } 687 688 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo) 689 { 690 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */ 691 692 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]); 693 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]); 694 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]); 695 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]); 696 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]); 697 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]); 698 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]); 699 OUTPLL(MCLK_MISC, rinfo->save_regs[7]); 700 if (rinfo->family == CHIP_FAMILY_RV350) 701 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]); 702 703 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); 704 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); 705 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); 706 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); 707 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); 708 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); 709 710 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); 711 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]); 712 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]); 713 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]); 714 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]); 715 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); 716 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]); 717 OUTREG(AGP_CNTL, rinfo->save_regs[16]); 718 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]); 719 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]); 720 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]); 721 722 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); 723 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); 724 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); 725 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]); 726 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]); 727 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]); 728 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]); 729 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]); 730 OUTREG(GPIO_MONID, rinfo->save_regs[27]); 731 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]); 732 } 733 734 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo) 735 { 736 OUTREG(GPIOPAD_MASK, 0x0001ffff); 737 OUTREG(GPIOPAD_EN, 0x00000400); 738 OUTREG(GPIOPAD_A, 0x00000000); 739 OUTREG(ZV_LCDPAD_MASK, 0x00000000); 740 OUTREG(ZV_LCDPAD_EN, 0x00000000); 741 OUTREG(ZV_LCDPAD_A, 0x00000000); 742 OUTREG(GPIO_VGA_DDC, 0x00030000); 743 OUTREG(GPIO_DVI_DDC, 0x00000000); 744 OUTREG(GPIO_MONID, 0x00030000); 745 OUTREG(GPIO_CRT2_DDC, 0x00000000); 746 } 747 748 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo) 749 { 750 /* Set v2clk to 65MHz */ 751 if (rinfo->family <= CHIP_FAMILY_RV280) { 752 OUTPLL(pllPIXCLKS_CNTL, 753 __INPLL(rinfo, pllPIXCLKS_CNTL) 754 & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK); 755 756 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c); 757 OUTPLL(pllP2PLL_CNTL, 0x0000bf00); 758 } else { 759 OUTPLL(pllP2PLL_REF_DIV, 0x0000000c); 760 INPLL(pllP2PLL_REF_DIV); 761 OUTPLL(pllP2PLL_CNTL, 0x0000a700); 762 } 763 764 OUTPLL(pllP2PLL_DIV_0, 0x00020074 | P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W); 765 766 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_SLEEP); 767 mdelay(1); 768 769 OUTPLL(pllP2PLL_CNTL, INPLL(pllP2PLL_CNTL) & ~P2PLL_CNTL__P2PLL_RESET); 770 mdelay( 1); 771 772 OUTPLL(pllPIXCLKS_CNTL, 773 (INPLL(pllPIXCLKS_CNTL) & ~PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK) 774 | (0x03 << PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT)); 775 mdelay( 1); 776 } 777 778 static void radeon_pm_low_current(struct radeonfb_info *rinfo) 779 { 780 u32 reg; 781 782 reg = INREG(BUS_CNTL1); 783 if (rinfo->family <= CHIP_FAMILY_RV280) { 784 reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK; 785 reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT); 786 } else { 787 reg |= 0x4080; 788 } 789 OUTREG(BUS_CNTL1, reg); 790 791 reg = INPLL(PLL_PWRMGT_CNTL); 792 reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF | 793 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF; 794 reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK; 795 reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU; 796 OUTPLL(PLL_PWRMGT_CNTL, reg); 797 798 reg = INREG(TV_DAC_CNTL); 799 reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK); 800 reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD | 801 TV_DAC_CNTL_BDACPD | 802 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT); 803 OUTREG(TV_DAC_CNTL, reg); 804 805 reg = INREG(TMDS_TRANSMITTER_CNTL); 806 reg &= ~(TMDS_PLL_EN | TMDS_PLLRST); 807 OUTREG(TMDS_TRANSMITTER_CNTL, reg); 808 809 reg = INREG(DAC_CNTL); 810 reg &= ~DAC_CMP_EN; 811 OUTREG(DAC_CNTL, reg); 812 813 reg = INREG(DAC_CNTL2); 814 reg &= ~DAC2_CMP_EN; 815 OUTREG(DAC_CNTL2, reg); 816 817 reg = INREG(TV_DAC_CNTL); 818 reg &= ~TV_DAC_CNTL_DETECT; 819 OUTREG(TV_DAC_CNTL, reg); 820 } 821 822 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo) 823 { 824 825 u32 sclk_cntl, mclk_cntl, sclk_more_cntl; 826 827 u32 pll_pwrmgt_cntl; 828 u32 clk_pwrmgt_cntl; 829 u32 clk_pin_cntl; 830 u32 vclk_ecp_cntl; 831 u32 pixclks_cntl; 832 u32 disp_mis_cntl; 833 u32 disp_pwr_man; 834 u32 tmp; 835 836 /* Force Core Clocks */ 837 sclk_cntl = INPLL( pllSCLK_CNTL); 838 sclk_cntl |= SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT| 839 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT| 840 SCLK_CNTL__RE_MAX_DYN_STOP_LAT| 841 SCLK_CNTL__PB_MAX_DYN_STOP_LAT| 842 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT| 843 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT| 844 SCLK_CNTL__RB_MAX_DYN_STOP_LAT| 845 846 SCLK_CNTL__FORCE_DISP2| 847 SCLK_CNTL__FORCE_CP| 848 SCLK_CNTL__FORCE_HDP| 849 SCLK_CNTL__FORCE_DISP1| 850 SCLK_CNTL__FORCE_TOP| 851 SCLK_CNTL__FORCE_E2| 852 SCLK_CNTL__FORCE_SE| 853 SCLK_CNTL__FORCE_IDCT| 854 SCLK_CNTL__FORCE_VIP| 855 856 SCLK_CNTL__FORCE_PB| 857 SCLK_CNTL__FORCE_TAM| 858 SCLK_CNTL__FORCE_TDM| 859 SCLK_CNTL__FORCE_RB| 860 SCLK_CNTL__FORCE_TV_SCLK| 861 SCLK_CNTL__FORCE_SUBPIC| 862 SCLK_CNTL__FORCE_OV0; 863 if (rinfo->family <= CHIP_FAMILY_RV280) 864 sclk_cntl |= SCLK_CNTL__FORCE_RE; 865 else 866 sclk_cntl |= SCLK_CNTL__SE_MAX_DYN_STOP_LAT | 867 SCLK_CNTL__E2_MAX_DYN_STOP_LAT | 868 SCLK_CNTL__TV_MAX_DYN_STOP_LAT | 869 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT | 870 SCLK_CNTL__CP_MAX_DYN_STOP_LAT; 871 872 OUTPLL( pllSCLK_CNTL, sclk_cntl); 873 874 sclk_more_cntl = INPLL(pllSCLK_MORE_CNTL); 875 sclk_more_cntl |= SCLK_MORE_CNTL__FORCE_DISPREGS | 876 SCLK_MORE_CNTL__FORCE_MC_GUI | 877 SCLK_MORE_CNTL__FORCE_MC_HOST; 878 879 OUTPLL(pllSCLK_MORE_CNTL, sclk_more_cntl); 880 881 882 mclk_cntl = INPLL( pllMCLK_CNTL); 883 mclk_cntl &= ~( MCLK_CNTL__FORCE_MCLKA | 884 MCLK_CNTL__FORCE_MCLKB | 885 MCLK_CNTL__FORCE_YCLKA | 886 MCLK_CNTL__FORCE_YCLKB | 887 MCLK_CNTL__FORCE_MC 888 ); 889 OUTPLL( pllMCLK_CNTL, mclk_cntl); 890 891 /* Force Display clocks */ 892 vclk_ecp_cntl = INPLL( pllVCLK_ECP_CNTL); 893 vclk_ecp_cntl &= ~(VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 894 | VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb); 895 vclk_ecp_cntl |= VCLK_ECP_CNTL__ECP_FORCE_ON; 896 OUTPLL( pllVCLK_ECP_CNTL, vclk_ecp_cntl); 897 898 899 pixclks_cntl = INPLL( pllPIXCLKS_CNTL); 900 pixclks_cntl &= ~( PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb | 901 PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb| 902 PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb | 903 PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb| 904 PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb| 905 PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb| 906 PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb); 907 908 OUTPLL( pllPIXCLKS_CNTL, pixclks_cntl); 909 910 /* Switch off LVDS interface */ 911 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & 912 ~(LVDS_BLON | LVDS_EN | LVDS_ON | LVDS_DIGON)); 913 914 /* Enable System power management */ 915 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL); 916 917 pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__SPLL_TURNOFF | 918 PLL_PWRMGT_CNTL__MPLL_TURNOFF| 919 PLL_PWRMGT_CNTL__PPLL_TURNOFF| 920 PLL_PWRMGT_CNTL__P2PLL_TURNOFF| 921 PLL_PWRMGT_CNTL__TVPLL_TURNOFF; 922 923 OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl); 924 925 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL); 926 927 clk_pwrmgt_cntl &= ~( CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF| 928 CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF| 929 CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF| 930 CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF| 931 CLK_PWRMGT_CNTL__MCLK_TURNOFF| 932 CLK_PWRMGT_CNTL__SCLK_TURNOFF| 933 CLK_PWRMGT_CNTL__PCLK_TURNOFF| 934 CLK_PWRMGT_CNTL__P2CLK_TURNOFF| 935 CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF| 936 CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN| 937 CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE| 938 CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK| 939 CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 940 ); 941 942 clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 943 | CLK_PWRMGT_CNTL__DISP_PM; 944 945 OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl); 946 947 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL); 948 949 clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND; 950 951 /* because both INPLL and OUTPLL take the same lock, that's why. */ 952 tmp = INPLL( pllMCLK_MISC) | MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND; 953 OUTPLL( pllMCLK_MISC, tmp); 954 955 /* BUS_CNTL1__MOBILE_PLATORM_SEL setting is northbridge chipset 956 * and radeon chip dependent. Thus we only enable it on Mac for 957 * now (until we get more info on how to compute the correct 958 * value for various X86 bridges). 959 */ 960 #ifdef CONFIG_PPC_PMAC 961 if (machine_is(powermac)) { 962 /* AGP PLL control */ 963 if (rinfo->family <= CHIP_FAMILY_RV280) { 964 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID); 965 OUTREG(BUS_CNTL1, 966 (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK) 967 | (2<<BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT)); // 440BX 968 } else { 969 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1)); 970 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000); 971 } 972 } 973 #endif 974 975 OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL) 976 & ~CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN)); 977 978 clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN; 979 clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb; 980 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl); 981 982 /* Solano2M */ 983 OUTREG(AGP_CNTL, 984 (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK)) 985 | (0x20<<AGP_CNTL__MAX_IDLE_CLK__SHIFT)); 986 987 /* ACPI mode */ 988 /* because both INPLL and OUTPLL take the same lock, that's why. */ 989 tmp = INPLL( pllPLL_PWRMGT_CNTL) & ~PLL_PWRMGT_CNTL__PM_MODE_SEL; 990 OUTPLL( pllPLL_PWRMGT_CNTL, tmp); 991 992 993 disp_mis_cntl = INREG(DISP_MISC_CNTL); 994 995 disp_mis_cntl &= ~( DISP_MISC_CNTL__SOFT_RESET_GRPH_PP | 996 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP | 997 DISP_MISC_CNTL__SOFT_RESET_OV0_PP | 998 DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK| 999 DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK| 1000 DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK| 1001 DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP| 1002 DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK| 1003 DISP_MISC_CNTL__SOFT_RESET_LVDS| 1004 DISP_MISC_CNTL__SOFT_RESET_TMDS| 1005 DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS| 1006 DISP_MISC_CNTL__SOFT_RESET_TV); 1007 1008 OUTREG(DISP_MISC_CNTL, disp_mis_cntl); 1009 1010 disp_pwr_man = INREG(DISP_PWR_MAN); 1011 1012 disp_pwr_man &= ~( DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN | 1013 DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN | 1014 DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK| 1015 DISP_PWR_MAN__DISP_D3_RST| 1016 DISP_PWR_MAN__DISP_D3_REG_RST 1017 ); 1018 1019 disp_pwr_man |= DISP_PWR_MAN__DISP_D3_GRPH_RST| 1020 DISP_PWR_MAN__DISP_D3_SUBPIC_RST| 1021 DISP_PWR_MAN__DISP_D3_OV0_RST| 1022 DISP_PWR_MAN__DISP_D1D2_GRPH_RST| 1023 DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST| 1024 DISP_PWR_MAN__DISP_D1D2_OV0_RST| 1025 DISP_PWR_MAN__DIG_TMDS_ENABLE_RST| 1026 DISP_PWR_MAN__TV_ENABLE_RST| 1027 // DISP_PWR_MAN__AUTO_PWRUP_EN| 1028 0; 1029 1030 OUTREG(DISP_PWR_MAN, disp_pwr_man); 1031 1032 clk_pwrmgt_cntl = INPLL( pllCLK_PWRMGT_CNTL); 1033 pll_pwrmgt_cntl = INPLL( pllPLL_PWRMGT_CNTL) ; 1034 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL); 1035 disp_pwr_man = INREG(DISP_PWR_MAN); 1036 1037 1038 /* D2 */ 1039 clk_pwrmgt_cntl |= CLK_PWRMGT_CNTL__DISP_PM; 1040 pll_pwrmgt_cntl |= PLL_PWRMGT_CNTL__MOBILE_SU | PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK; 1041 clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb; 1042 disp_pwr_man &= ~(DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 1043 | DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK); 1044 1045 OUTPLL( pllCLK_PWRMGT_CNTL, clk_pwrmgt_cntl); 1046 OUTPLL( pllPLL_PWRMGT_CNTL, pll_pwrmgt_cntl); 1047 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl); 1048 OUTREG(DISP_PWR_MAN, disp_pwr_man); 1049 1050 /* disable display request & disable display */ 1051 OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN) 1052 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B); 1053 OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN) 1054 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B); 1055 1056 mdelay(17); 1057 1058 } 1059 1060 static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo) 1061 { 1062 u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1; 1063 1064 mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1) 1065 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK; 1066 mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1) 1067 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK; 1068 1069 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1 1070 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT)); 1071 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1 1072 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT)); 1073 1074 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1); 1075 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1); 1076 1077 mdelay( 1); 1078 } 1079 1080 static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo) 1081 { 1082 u32 mc_chp_io_cntl_a1, mc_chp_io_cntl_b1; 1083 1084 mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1) 1085 & ~MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK; 1086 mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1) 1087 & ~MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK; 1088 1089 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, 1090 mc_chp_io_cntl_a1 | (1<<MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT)); 1091 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, 1092 mc_chp_io_cntl_b1 | (1<<MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT)); 1093 1094 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1); 1095 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1); 1096 1097 mdelay( 1); 1098 } 1099 1100 static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value, 1101 u8 delay_required) 1102 { 1103 u32 mem_sdram_mode; 1104 1105 mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG); 1106 1107 mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK; 1108 mem_sdram_mode |= (value<<MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT) 1109 | MEM_SDRAM_MODE_REG__MEM_CFG_TYPE; 1110 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); 1111 if (delay_required >= 2) 1112 mdelay(1); 1113 1114 mem_sdram_mode |= MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET; 1115 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); 1116 if (delay_required >= 2) 1117 mdelay(1); 1118 1119 mem_sdram_mode &= ~MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET; 1120 OUTREG( MEM_SDRAM_MODE_REG, mem_sdram_mode); 1121 if (delay_required >= 2) 1122 mdelay(1); 1123 1124 if (delay_required) { 1125 do { 1126 if (delay_required >= 2) 1127 mdelay(1); 1128 } while ((INREG(MC_STATUS) 1129 & (MC_STATUS__MEM_PWRUP_COMPL_A | 1130 MC_STATUS__MEM_PWRUP_COMPL_B)) == 0); 1131 } 1132 } 1133 1134 static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo) 1135 { 1136 int cnt; 1137 1138 for (cnt = 0; cnt < 100; ++cnt) { 1139 mdelay(1); 1140 if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A 1141 | MC_STATUS__MEM_PWRUP_COMPL_B)) 1142 break; 1143 } 1144 } 1145 1146 1147 static void radeon_pm_enable_dll(struct radeonfb_info *rinfo) 1148 { 1149 #define DLL_RESET_DELAY 5 1150 #define DLL_SLEEP_DELAY 1 1151 1152 u32 cko = INPLL(pllMDLL_CKO) | MDLL_CKO__MCKOA_SLEEP 1153 | MDLL_CKO__MCKOA_RESET; 1154 u32 cka = INPLL(pllMDLL_RDCKA) | MDLL_RDCKA__MRDCKA0_SLEEP 1155 | MDLL_RDCKA__MRDCKA1_SLEEP | MDLL_RDCKA__MRDCKA0_RESET 1156 | MDLL_RDCKA__MRDCKA1_RESET; 1157 u32 ckb = INPLL(pllMDLL_RDCKB) | MDLL_RDCKB__MRDCKB0_SLEEP 1158 | MDLL_RDCKB__MRDCKB1_SLEEP | MDLL_RDCKB__MRDCKB0_RESET 1159 | MDLL_RDCKB__MRDCKB1_RESET; 1160 1161 /* Setting up the DLL range for write */ 1162 OUTPLL(pllMDLL_CKO, cko); 1163 OUTPLL(pllMDLL_RDCKA, cka); 1164 OUTPLL(pllMDLL_RDCKB, ckb); 1165 1166 mdelay(DLL_RESET_DELAY*2); 1167 1168 cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP); 1169 OUTPLL(pllMDLL_CKO, cko); 1170 mdelay(DLL_SLEEP_DELAY); 1171 cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET); 1172 OUTPLL(pllMDLL_CKO, cko); 1173 mdelay(DLL_RESET_DELAY); 1174 1175 cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP); 1176 OUTPLL(pllMDLL_RDCKA, cka); 1177 mdelay(DLL_SLEEP_DELAY); 1178 cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET); 1179 OUTPLL(pllMDLL_RDCKA, cka); 1180 mdelay(DLL_RESET_DELAY); 1181 1182 ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP); 1183 OUTPLL(pllMDLL_RDCKB, ckb); 1184 mdelay(DLL_SLEEP_DELAY); 1185 ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET); 1186 OUTPLL(pllMDLL_RDCKB, ckb); 1187 mdelay(DLL_RESET_DELAY); 1188 1189 1190 #undef DLL_RESET_DELAY 1191 #undef DLL_SLEEP_DELAY 1192 } 1193 1194 static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo) 1195 { 1196 u32 dll_value; 1197 u32 dll_sleep_mask = 0; 1198 u32 dll_reset_mask = 0; 1199 u32 mc; 1200 1201 #define DLL_RESET_DELAY 5 1202 #define DLL_SLEEP_DELAY 1 1203 1204 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]); 1205 mc = INREG(MC_CNTL); 1206 /* Check which channels are enabled */ 1207 switch (mc & 0x3) { 1208 case 1: 1209 if (mc & 0x4) 1210 break; 1211 fallthrough; 1212 case 2: 1213 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKB_SLEEP; 1214 dll_reset_mask |= MDLL_R300_RDCK__MRDCKB_RESET; 1215 fallthrough; 1216 case 0: 1217 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKA_SLEEP; 1218 dll_reset_mask |= MDLL_R300_RDCK__MRDCKA_RESET; 1219 } 1220 switch (mc & 0x3) { 1221 case 1: 1222 if (!(mc & 0x4)) 1223 break; 1224 fallthrough; 1225 case 2: 1226 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKD_SLEEP; 1227 dll_reset_mask |= MDLL_R300_RDCK__MRDCKD_RESET; 1228 dll_sleep_mask |= MDLL_R300_RDCK__MRDCKC_SLEEP; 1229 dll_reset_mask |= MDLL_R300_RDCK__MRDCKC_RESET; 1230 } 1231 1232 dll_value = INPLL(pllMDLL_RDCKA); 1233 1234 /* Power Up */ 1235 dll_value &= ~(dll_sleep_mask); 1236 OUTPLL(pllMDLL_RDCKA, dll_value); 1237 mdelay( DLL_SLEEP_DELAY); 1238 1239 dll_value &= ~(dll_reset_mask); 1240 OUTPLL(pllMDLL_RDCKA, dll_value); 1241 mdelay( DLL_RESET_DELAY); 1242 1243 #undef DLL_RESET_DELAY 1244 #undef DLL_SLEEP_DELAY 1245 } 1246 1247 1248 static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo) 1249 { 1250 u32 crtcGenCntl, crtcGenCntl2, memRefreshCntl, crtc_more_cntl, 1251 fp_gen_cntl, fp2_gen_cntl; 1252 1253 crtcGenCntl = INREG( CRTC_GEN_CNTL); 1254 crtcGenCntl2 = INREG( CRTC2_GEN_CNTL); 1255 1256 crtc_more_cntl = INREG( CRTC_MORE_CNTL); 1257 fp_gen_cntl = INREG( FP_GEN_CNTL); 1258 fp2_gen_cntl = INREG( FP2_GEN_CNTL); 1259 1260 1261 OUTREG( CRTC_MORE_CNTL, 0); 1262 OUTREG( FP_GEN_CNTL, 0); 1263 OUTREG( FP2_GEN_CNTL,0); 1264 1265 OUTREG( CRTC_GEN_CNTL, (crtcGenCntl | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B) ); 1266 OUTREG( CRTC2_GEN_CNTL, (crtcGenCntl2 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B) ); 1267 1268 /* This is the code for the Aluminium PowerBooks M10 / iBooks M11 */ 1269 if (rinfo->family == CHIP_FAMILY_RV350) { 1270 u32 sdram_mode_reg = rinfo->save_regs[35]; 1271 static const u32 default_mrtable[] = 1272 { 0x21320032, 1273 0x21321000, 0xa1321000, 0x21321000, 0xffffffff, 1274 0x21320032, 0xa1320032, 0x21320032, 0xffffffff, 1275 0x21321002, 0xa1321002, 0x21321002, 0xffffffff, 1276 0x21320132, 0xa1320132, 0x21320132, 0xffffffff, 1277 0x21320032, 0xa1320032, 0x21320032, 0xffffffff, 1278 0x31320032 }; 1279 1280 const u32 *mrtable = default_mrtable; 1281 int i, mrtable_size = ARRAY_SIZE(default_mrtable); 1282 1283 mdelay(30); 1284 1285 /* Disable refresh */ 1286 memRefreshCntl = INREG( MEM_REFRESH_CNTL) 1287 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS; 1288 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl 1289 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS); 1290 1291 /* Configure and enable M & SPLLs */ 1292 radeon_pm_enable_dll_m10(rinfo); 1293 radeon_pm_yclk_mclk_sync_m10(rinfo); 1294 1295 #ifdef CONFIG_PPC 1296 if (rinfo->of_node != NULL) { 1297 int size; 1298 1299 mrtable = of_get_property(rinfo->of_node, "ATY,MRT", &size); 1300 if (mrtable) 1301 mrtable_size = size >> 2; 1302 else 1303 mrtable = default_mrtable; 1304 } 1305 #endif /* CONFIG_PPC */ 1306 1307 /* Program the SDRAM */ 1308 sdram_mode_reg = mrtable[0]; 1309 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg); 1310 for (i = 0; i < mrtable_size; i++) { 1311 if (mrtable[i] == 0xffffffffu) 1312 radeon_pm_m10_program_mode_wait(rinfo); 1313 else { 1314 sdram_mode_reg &= ~(MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 1315 | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 1316 | MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET); 1317 sdram_mode_reg |= mrtable[i]; 1318 1319 OUTREG(MEM_SDRAM_MODE_REG, sdram_mode_reg); 1320 mdelay(1); 1321 } 1322 } 1323 1324 /* Restore memory refresh */ 1325 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl); 1326 mdelay(30); 1327 1328 } 1329 /* Here come the desktop RV200 "QW" card */ 1330 else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) { 1331 /* Disable refresh */ 1332 memRefreshCntl = INREG( MEM_REFRESH_CNTL) 1333 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS; 1334 OUTREG(MEM_REFRESH_CNTL, memRefreshCntl 1335 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS); 1336 mdelay(30); 1337 1338 /* Reset memory */ 1339 OUTREG(MEM_SDRAM_MODE_REG, 1340 INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); 1341 1342 radeon_pm_program_mode_reg(rinfo, 0x2002, 2); 1343 radeon_pm_program_mode_reg(rinfo, 0x0132, 2); 1344 radeon_pm_program_mode_reg(rinfo, 0x0032, 2); 1345 1346 OUTREG(MEM_SDRAM_MODE_REG, 1347 INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); 1348 1349 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl); 1350 1351 } 1352 /* The M6 */ 1353 else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) { 1354 /* Disable refresh */ 1355 memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20); 1356 OUTREG( EXT_MEM_CNTL, memRefreshCntl | (1 << 20)); 1357 1358 /* Reset memory */ 1359 OUTREG( MEM_SDRAM_MODE_REG, 1360 INREG( MEM_SDRAM_MODE_REG) 1361 & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); 1362 1363 /* DLL */ 1364 radeon_pm_enable_dll(rinfo); 1365 1366 /* MLCK / YCLK sync */ 1367 radeon_pm_yclk_mclk_sync(rinfo); 1368 1369 /* Program Mode Register */ 1370 radeon_pm_program_mode_reg(rinfo, 0x2000, 1); 1371 radeon_pm_program_mode_reg(rinfo, 0x2001, 1); 1372 radeon_pm_program_mode_reg(rinfo, 0x2002, 1); 1373 radeon_pm_program_mode_reg(rinfo, 0x0132, 1); 1374 radeon_pm_program_mode_reg(rinfo, 0x0032, 1); 1375 1376 /* Complete & re-enable refresh */ 1377 OUTREG( MEM_SDRAM_MODE_REG, 1378 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); 1379 1380 OUTREG(EXT_MEM_CNTL, memRefreshCntl); 1381 } 1382 /* And finally, the M7..M9 models, including M9+ (RV280) */ 1383 else if (rinfo->is_mobility) { 1384 1385 /* Disable refresh */ 1386 memRefreshCntl = INREG( MEM_REFRESH_CNTL) 1387 & ~MEM_REFRESH_CNTL__MEM_REFRESH_DIS; 1388 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl 1389 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS); 1390 1391 /* Reset memory */ 1392 OUTREG( MEM_SDRAM_MODE_REG, 1393 INREG( MEM_SDRAM_MODE_REG) 1394 & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); 1395 1396 /* DLL */ 1397 radeon_pm_enable_dll(rinfo); 1398 1399 /* MLCK / YCLK sync */ 1400 radeon_pm_yclk_mclk_sync(rinfo); 1401 1402 /* M6, M7 and M9 so far ... */ 1403 if (rinfo->family <= CHIP_FAMILY_RV250) { 1404 radeon_pm_program_mode_reg(rinfo, 0x2000, 1); 1405 radeon_pm_program_mode_reg(rinfo, 0x2001, 1); 1406 radeon_pm_program_mode_reg(rinfo, 0x2002, 1); 1407 radeon_pm_program_mode_reg(rinfo, 0x0132, 1); 1408 radeon_pm_program_mode_reg(rinfo, 0x0032, 1); 1409 } 1410 /* M9+ (iBook G4) */ 1411 else if (rinfo->family == CHIP_FAMILY_RV280) { 1412 radeon_pm_program_mode_reg(rinfo, 0x2000, 1); 1413 radeon_pm_program_mode_reg(rinfo, 0x0132, 1); 1414 radeon_pm_program_mode_reg(rinfo, 0x0032, 1); 1415 } 1416 1417 /* Complete & re-enable refresh */ 1418 OUTREG( MEM_SDRAM_MODE_REG, 1419 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); 1420 1421 OUTREG( MEM_REFRESH_CNTL, memRefreshCntl); 1422 } 1423 1424 OUTREG( CRTC_GEN_CNTL, crtcGenCntl); 1425 OUTREG( CRTC2_GEN_CNTL, crtcGenCntl2); 1426 OUTREG( FP_GEN_CNTL, fp_gen_cntl); 1427 OUTREG( FP2_GEN_CNTL, fp2_gen_cntl); 1428 1429 OUTREG( CRTC_MORE_CNTL, crtc_more_cntl); 1430 1431 mdelay( 15); 1432 } 1433 1434 #if defined(CONFIG_X86) || defined(CONFIG_PPC_PMAC) 1435 static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo) 1436 { 1437 u32 tmp, tmp2; 1438 int i,j; 1439 1440 /* Reset the PAD_CTLR_STRENGTH & wait for it to be stable */ 1441 INREG(PAD_CTLR_STRENGTH); 1442 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE); 1443 tmp = INREG(PAD_CTLR_STRENGTH); 1444 for (i = j = 0; i < 65; ++i) { 1445 mdelay(1); 1446 tmp2 = INREG(PAD_CTLR_STRENGTH); 1447 if (tmp != tmp2) { 1448 tmp = tmp2; 1449 i = 0; 1450 j++; 1451 if (j > 10) { 1452 printk(KERN_WARNING "radeon: PAD_CTLR_STRENGTH doesn't " 1453 "stabilize !\n"); 1454 break; 1455 } 1456 } 1457 } 1458 } 1459 1460 static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo) 1461 { 1462 u32 tmp; 1463 1464 tmp = INPLL(pllPPLL_CNTL); 1465 OUTPLL(pllPPLL_CNTL, tmp | 0x3); 1466 tmp = INPLL(pllP2PLL_CNTL); 1467 OUTPLL(pllP2PLL_CNTL, tmp | 0x3); 1468 tmp = INPLL(pllSPLL_CNTL); 1469 OUTPLL(pllSPLL_CNTL, tmp | 0x3); 1470 tmp = INPLL(pllMPLL_CNTL); 1471 OUTPLL(pllMPLL_CNTL, tmp | 0x3); 1472 } 1473 1474 static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo) 1475 { 1476 u32 tmp; 1477 1478 /* Switch SPLL to PCI source */ 1479 tmp = INPLL(pllSCLK_CNTL); 1480 OUTPLL(pllSCLK_CNTL, tmp & ~SCLK_CNTL__SCLK_SRC_SEL_MASK); 1481 1482 /* Reconfigure SPLL charge pump, VCO gain, duty cycle */ 1483 tmp = INPLL(pllSPLL_CNTL); 1484 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); 1485 radeon_pll_errata_after_index(rinfo); 1486 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); 1487 radeon_pll_errata_after_data(rinfo); 1488 1489 /* Set SPLL feedback divider */ 1490 tmp = INPLL(pllM_SPLL_REF_FB_DIV); 1491 tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul); 1492 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp); 1493 1494 /* Power up SPLL */ 1495 tmp = INPLL(pllSPLL_CNTL); 1496 OUTPLL(pllSPLL_CNTL, tmp & ~1); 1497 (void)INPLL(pllSPLL_CNTL); 1498 1499 mdelay(10); 1500 1501 /* Release SPLL reset */ 1502 tmp = INPLL(pllSPLL_CNTL); 1503 OUTPLL(pllSPLL_CNTL, tmp & ~0x2); 1504 (void)INPLL(pllSPLL_CNTL); 1505 1506 mdelay(10); 1507 1508 /* Select SCLK source */ 1509 tmp = INPLL(pllSCLK_CNTL); 1510 tmp &= ~SCLK_CNTL__SCLK_SRC_SEL_MASK; 1511 tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK; 1512 OUTPLL(pllSCLK_CNTL, tmp); 1513 (void)INPLL(pllSCLK_CNTL); 1514 1515 mdelay(10); 1516 1517 /* Reconfigure MPLL charge pump, VCO gain, duty cycle */ 1518 tmp = INPLL(pllMPLL_CNTL); 1519 OUTREG8(CLOCK_CNTL_INDEX, pllMPLL_CNTL + PLL_WR_EN); 1520 radeon_pll_errata_after_index(rinfo); 1521 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); 1522 radeon_pll_errata_after_data(rinfo); 1523 1524 /* Set MPLL feedback divider */ 1525 tmp = INPLL(pllM_SPLL_REF_FB_DIV); 1526 tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul); 1527 1528 OUTPLL(pllM_SPLL_REF_FB_DIV, tmp); 1529 /* Power up MPLL */ 1530 tmp = INPLL(pllMPLL_CNTL); 1531 OUTPLL(pllMPLL_CNTL, tmp & ~0x2); 1532 (void)INPLL(pllMPLL_CNTL); 1533 1534 mdelay(10); 1535 1536 /* Un-reset MPLL */ 1537 tmp = INPLL(pllMPLL_CNTL); 1538 OUTPLL(pllMPLL_CNTL, tmp & ~0x1); 1539 (void)INPLL(pllMPLL_CNTL); 1540 1541 mdelay(10); 1542 1543 /* Select source for MCLK */ 1544 tmp = INPLL(pllMCLK_CNTL); 1545 tmp |= rinfo->save_regs[2] & 0xffff; 1546 OUTPLL(pllMCLK_CNTL, tmp); 1547 (void)INPLL(pllMCLK_CNTL); 1548 1549 mdelay(10); 1550 } 1551 1552 static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo) 1553 { 1554 u32 r2ec; 1555 1556 /* GACK ! I though we didn't have a DDA on Radeon's anymore 1557 * here we rewrite with the same value, ... I suppose we clear 1558 * some bits that are already clear ? Or maybe this 0x2ec 1559 * register is something new ? 1560 */ 1561 mdelay(20); 1562 r2ec = INREG(VGA_DDA_ON_OFF); 1563 OUTREG(VGA_DDA_ON_OFF, r2ec); 1564 mdelay(1); 1565 1566 /* Spread spectrum PLLL off */ 1567 OUTPLL(pllSSPLL_CNTL, 0xbf03); 1568 1569 /* Spread spectrum disabled */ 1570 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3); 1571 1572 /* The trace shows read & rewrite of LVDS_PLL_CNTL here with same 1573 * value, not sure what for... 1574 */ 1575 1576 r2ec |= 0x3f0; 1577 OUTREG(VGA_DDA_ON_OFF, r2ec); 1578 mdelay(1); 1579 } 1580 1581 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo) 1582 { 1583 u32 r2ec, tmp; 1584 1585 /* GACK (bis) ! I though we didn't have a DDA on Radeon's anymore 1586 * here we rewrite with the same value, ... I suppose we clear/set 1587 * some bits that are already clear/set ? 1588 */ 1589 r2ec = INREG(VGA_DDA_ON_OFF); 1590 OUTREG(VGA_DDA_ON_OFF, r2ec); 1591 mdelay(1); 1592 1593 /* Enable spread spectrum */ 1594 OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3); 1595 mdelay(3); 1596 1597 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]); 1598 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]); 1599 tmp = INPLL(pllSSPLL_CNTL); 1600 OUTPLL(pllSSPLL_CNTL, tmp & ~0x2); 1601 mdelay(6); 1602 tmp = INPLL(pllSSPLL_CNTL); 1603 OUTPLL(pllSSPLL_CNTL, tmp & ~0x1); 1604 mdelay(5); 1605 1606 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]); 1607 1608 r2ec |= 8; 1609 OUTREG(VGA_DDA_ON_OFF, r2ec); 1610 mdelay(20); 1611 1612 /* Enable LVDS interface */ 1613 tmp = INREG(LVDS_GEN_CNTL); 1614 OUTREG(LVDS_GEN_CNTL, tmp | LVDS_EN); 1615 1616 /* Enable LVDS_PLL */ 1617 tmp = INREG(LVDS_PLL_CNTL); 1618 tmp &= ~0x30000; 1619 tmp |= 0x10000; 1620 OUTREG(LVDS_PLL_CNTL, tmp); 1621 1622 OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]); 1623 OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]); 1624 1625 /* The trace reads that one here, waiting for something to settle down ? */ 1626 INREG(RBBM_STATUS); 1627 1628 /* Ugh ? SS_TST_DEC is supposed to be a read register in the 1629 * R300 register spec at least... 1630 */ 1631 tmp = INPLL(pllSS_TST_CNTL); 1632 tmp |= 0x00400000; 1633 OUTPLL(pllSS_TST_CNTL, tmp); 1634 } 1635 1636 static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo) 1637 { 1638 u32 tmp; 1639 1640 OUTREG8(CLOCK_CNTL_INDEX, pllHTOTAL_CNTL + PLL_WR_EN); 1641 radeon_pll_errata_after_index(rinfo); 1642 OUTREG8(CLOCK_CNTL_DATA, 0); 1643 radeon_pll_errata_after_data(rinfo); 1644 1645 tmp = INPLL(pllVCLK_ECP_CNTL); 1646 OUTPLL(pllVCLK_ECP_CNTL, tmp | 0x80); 1647 mdelay(5); 1648 1649 tmp = INPLL(pllPPLL_REF_DIV); 1650 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; 1651 OUTPLL(pllPPLL_REF_DIV, tmp); 1652 INPLL(pllPPLL_REF_DIV); 1653 1654 /* Reconfigure SPLL charge pump, VCO gain, duty cycle, 1655 * probably useless since we already did it ... 1656 */ 1657 tmp = INPLL(pllPPLL_CNTL); 1658 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); 1659 radeon_pll_errata_after_index(rinfo); 1660 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); 1661 radeon_pll_errata_after_data(rinfo); 1662 1663 /* Restore our "reference" PPLL divider set by firmware 1664 * according to proper spread spectrum calculations 1665 */ 1666 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]); 1667 1668 tmp = INPLL(pllPPLL_CNTL); 1669 OUTPLL(pllPPLL_CNTL, tmp & ~0x2); 1670 mdelay(5); 1671 1672 tmp = INPLL(pllPPLL_CNTL); 1673 OUTPLL(pllPPLL_CNTL, tmp & ~0x1); 1674 mdelay(5); 1675 1676 tmp = INPLL(pllVCLK_ECP_CNTL); 1677 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3); 1678 mdelay(5); 1679 1680 tmp = INPLL(pllVCLK_ECP_CNTL); 1681 OUTPLL(pllVCLK_ECP_CNTL, tmp | 3); 1682 mdelay(5); 1683 1684 /* Switch pixel clock to firmware default div 0 */ 1685 OUTREG8(CLOCK_CNTL_INDEX+1, 0); 1686 radeon_pll_errata_after_index(rinfo); 1687 radeon_pll_errata_after_data(rinfo); 1688 } 1689 1690 static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo) 1691 { 1692 OUTREG(MC_CNTL, rinfo->save_regs[46]); 1693 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]); 1694 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]); 1695 OUTREG(MEM_SDRAM_MODE_REG, 1696 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); 1697 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]); 1698 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]); 1699 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]); 1700 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]); 1701 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]); 1702 OUTREG(MC_DEBUG, rinfo->save_regs[53]); 1703 1704 OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]); 1705 OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]); 1706 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]); 1707 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]); 1708 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]); 1709 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]); 1710 OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]); 1711 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]); 1712 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]); 1713 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]); 1714 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]); 1715 OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]); 1716 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]); 1717 OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]); 1718 OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]); 1719 OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]); 1720 OUTREG(MC_IND_INDEX, 0); 1721 } 1722 1723 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo) 1724 { 1725 u32 tmp, i; 1726 1727 /* Restore a bunch of registers first */ 1728 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); 1729 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); 1730 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); 1731 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); 1732 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]); 1733 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); 1734 OUTREG(BUS_CNTL, rinfo->save_regs[36]); 1735 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); 1736 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]); 1737 OUTREG(FCP_CNTL, rinfo->save_regs[38]); 1738 OUTREG(RBBM_CNTL, rinfo->save_regs[39]); 1739 OUTREG(DAC_CNTL, rinfo->save_regs[40]); 1740 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8); 1741 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8); 1742 1743 /* Hrm... */ 1744 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE); 1745 1746 /* Reset the PAD CTLR */ 1747 radeon_pm_reset_pad_ctlr_strength(rinfo); 1748 1749 /* Some PLLs are Read & written identically in the trace here... 1750 * I suppose it's actually to switch them all off & reset, 1751 * let's assume off is what we want. I'm just doing that for all major PLLs now. 1752 */ 1753 radeon_pm_all_ppls_off(rinfo); 1754 1755 /* Clear tiling, reset swappers */ 1756 INREG(SURFACE_CNTL); 1757 OUTREG(SURFACE_CNTL, 0); 1758 1759 /* Some black magic with TV_DAC_CNTL, we should restore those from backups 1760 * rather than hard coding... 1761 */ 1762 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; 1763 tmp |= 8 << TV_DAC_CNTL_BGADJ__SHIFT; 1764 OUTREG(TV_DAC_CNTL, tmp); 1765 1766 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; 1767 tmp |= 7 << TV_DAC_CNTL_DACADJ__SHIFT; 1768 OUTREG(TV_DAC_CNTL, tmp); 1769 1770 /* More registers restored */ 1771 OUTREG(AGP_CNTL, rinfo->save_regs[16]); 1772 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); 1773 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); 1774 1775 /* Hrmmm ... What is that ? */ 1776 tmp = rinfo->save_regs[1] 1777 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK | 1778 CLK_PWRMGT_CNTL__MC_BUSY); 1779 OUTPLL(pllCLK_PWRMGT_CNTL, tmp); 1780 1781 OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]); 1782 OUTREG(FW_CNTL, rinfo->save_regs[57]); 1783 OUTREG(HDP_DEBUG, rinfo->save_regs[96]); 1784 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]); 1785 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]); 1786 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]); 1787 1788 /* Restore Memory Controller configuration */ 1789 radeon_pm_m10_reconfigure_mc(rinfo); 1790 1791 /* Make sure CRTC's dont touch memory */ 1792 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL) 1793 | CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B); 1794 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL) 1795 | CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B); 1796 mdelay(30); 1797 1798 /* Disable SDRAM refresh */ 1799 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL) 1800 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS); 1801 1802 /* Restore XTALIN routing (CLK_PIN_CNTL) */ 1803 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]); 1804 1805 /* Switch MCLK, YCLK and SCLK PLLs to PCI source & force them ON */ 1806 tmp = rinfo->save_regs[2] & 0xff000000; 1807 tmp |= MCLK_CNTL__FORCE_MCLKA | 1808 MCLK_CNTL__FORCE_MCLKB | 1809 MCLK_CNTL__FORCE_YCLKA | 1810 MCLK_CNTL__FORCE_YCLKB | 1811 MCLK_CNTL__FORCE_MC; 1812 OUTPLL(pllMCLK_CNTL, tmp); 1813 1814 /* Force all clocks on in SCLK */ 1815 tmp = INPLL(pllSCLK_CNTL); 1816 tmp |= SCLK_CNTL__FORCE_DISP2| 1817 SCLK_CNTL__FORCE_CP| 1818 SCLK_CNTL__FORCE_HDP| 1819 SCLK_CNTL__FORCE_DISP1| 1820 SCLK_CNTL__FORCE_TOP| 1821 SCLK_CNTL__FORCE_E2| 1822 SCLK_CNTL__FORCE_SE| 1823 SCLK_CNTL__FORCE_IDCT| 1824 SCLK_CNTL__FORCE_VIP| 1825 SCLK_CNTL__FORCE_PB| 1826 SCLK_CNTL__FORCE_TAM| 1827 SCLK_CNTL__FORCE_TDM| 1828 SCLK_CNTL__FORCE_RB| 1829 SCLK_CNTL__FORCE_TV_SCLK| 1830 SCLK_CNTL__FORCE_SUBPIC| 1831 SCLK_CNTL__FORCE_OV0; 1832 tmp |= SCLK_CNTL__CP_MAX_DYN_STOP_LAT | 1833 SCLK_CNTL__HDP_MAX_DYN_STOP_LAT | 1834 SCLK_CNTL__TV_MAX_DYN_STOP_LAT | 1835 SCLK_CNTL__E2_MAX_DYN_STOP_LAT | 1836 SCLK_CNTL__SE_MAX_DYN_STOP_LAT | 1837 SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT| 1838 SCLK_CNTL__VIP_MAX_DYN_STOP_LAT | 1839 SCLK_CNTL__RE_MAX_DYN_STOP_LAT | 1840 SCLK_CNTL__PB_MAX_DYN_STOP_LAT | 1841 SCLK_CNTL__TAM_MAX_DYN_STOP_LAT | 1842 SCLK_CNTL__TDM_MAX_DYN_STOP_LAT | 1843 SCLK_CNTL__RB_MAX_DYN_STOP_LAT; 1844 OUTPLL(pllSCLK_CNTL, tmp); 1845 1846 OUTPLL(pllVCLK_ECP_CNTL, 0); 1847 OUTPLL(pllPIXCLKS_CNTL, 0); 1848 OUTPLL(pllMCLK_MISC, 1849 MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT | 1850 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT); 1851 1852 mdelay(5); 1853 1854 /* Restore the M_SPLL_REF_FB_DIV, MPLL_AUX_CNTL and SPLL_AUX_CNTL values */ 1855 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]); 1856 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]); 1857 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]); 1858 1859 /* Now restore the major PLLs settings, keeping them off & reset though */ 1860 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3); 1861 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3); 1862 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03); 1863 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); 1864 1865 /* Restore MC DLL state and switch it off/reset too */ 1866 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]); 1867 1868 /* Switch MDLL off & reset */ 1869 OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff); 1870 mdelay(5); 1871 1872 /* Setup some black magic bits in PLL_PWRMGT_CNTL. Hrm... we saved 1873 * 0xa1100007... and MacOS writes 0xa1000007 .. 1874 */ 1875 OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]); 1876 1877 /* Restore more stuffs */ 1878 OUTPLL(pllHTOTAL_CNTL, 0); 1879 OUTPLL(pllHTOTAL2_CNTL, 0); 1880 1881 /* More PLL initial configuration */ 1882 tmp = INPLL(pllSCLK_CNTL2); /* What for ? */ 1883 OUTPLL(pllSCLK_CNTL2, tmp); 1884 1885 tmp = INPLL(pllSCLK_MORE_CNTL); 1886 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS | /* a guess */ 1887 SCLK_MORE_CNTL__FORCE_MC_GUI | 1888 SCLK_MORE_CNTL__FORCE_MC_HOST; 1889 OUTPLL(pllSCLK_MORE_CNTL, tmp); 1890 1891 /* Now we actually start MCLK and SCLK */ 1892 radeon_pm_start_mclk_sclk(rinfo); 1893 1894 /* Full reset sdrams, this also re-inits the MDLL */ 1895 radeon_pm_full_reset_sdram(rinfo); 1896 1897 /* Fill palettes */ 1898 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20); 1899 for (i=0; i<256; i++) 1900 OUTREG(PALETTE_30_DATA, 0x15555555); 1901 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20); 1902 udelay(20); 1903 for (i=0; i<256; i++) 1904 OUTREG(PALETTE_30_DATA, 0x15555555); 1905 1906 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20); 1907 mdelay(3); 1908 1909 /* Restore TMDS */ 1910 OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]); 1911 OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]); 1912 1913 /* Set LVDS registers but keep interface & pll down */ 1914 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] & 1915 ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN)); 1916 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); 1917 1918 OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]); 1919 1920 /* Restore GPIOPAD state */ 1921 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); 1922 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); 1923 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); 1924 1925 /* write some stuff to the framebuffer... */ 1926 for (i = 0; i < 0x8000; ++i) 1927 writeb(0, rinfo->fb_base + i); 1928 1929 mdelay(40); 1930 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON); 1931 mdelay(40); 1932 1933 /* Restore a few more things */ 1934 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]); 1935 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]); 1936 1937 /* Take care of spread spectrum & PPLLs now */ 1938 radeon_pm_m10_disable_spread_spectrum(rinfo); 1939 radeon_pm_restore_pixel_pll(rinfo); 1940 1941 /* GRRRR... I can't figure out the proper LVDS power sequence, and the 1942 * code I have for blank/unblank doesn't quite work on some laptop models 1943 * it seems ... Hrm. What I have here works most of the time ... 1944 */ 1945 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo); 1946 } 1947 #endif 1948 1949 #ifdef CONFIG_PPC 1950 #ifdef CONFIG_PPC_PMAC 1951 static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo) 1952 { 1953 OUTREG(MC_CNTL, rinfo->save_regs[46]); 1954 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]); 1955 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]); 1956 OUTREG(MEM_SDRAM_MODE_REG, 1957 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); 1958 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]); 1959 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]); 1960 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]); 1961 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]); 1962 OUTREG(MC_DEBUG, rinfo->save_regs[53]); 1963 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]); 1964 1965 OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/); 1966 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/); 1967 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/); 1968 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/); 1969 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/); 1970 OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/); 1971 OUTREG(MC_IND_INDEX, 0); 1972 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); 1973 1974 mdelay(20); 1975 } 1976 1977 static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo) 1978 { 1979 u32 tmp, i; 1980 1981 /* Restore a bunch of registers first */ 1982 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); 1983 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); 1984 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); 1985 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); 1986 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); 1987 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]); 1988 OUTREG(BUS_CNTL, rinfo->save_regs[36]); 1989 OUTREG(BUS_CNTL1, rinfo->save_regs[14]); 1990 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]); 1991 OUTREG(FCP_CNTL, rinfo->save_regs[38]); 1992 OUTREG(RBBM_CNTL, rinfo->save_regs[39]); 1993 1994 OUTREG(DAC_CNTL, rinfo->save_regs[40]); 1995 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE); 1996 1997 /* Reset the PAD CTLR */ 1998 radeon_pm_reset_pad_ctlr_strength(rinfo); 1999 2000 /* Some PLLs are Read & written identically in the trace here... 2001 * I suppose it's actually to switch them all off & reset, 2002 * let's assume off is what we want. I'm just doing that for all major PLLs now. 2003 */ 2004 radeon_pm_all_ppls_off(rinfo); 2005 2006 /* Clear tiling, reset swappers */ 2007 INREG(SURFACE_CNTL); 2008 OUTREG(SURFACE_CNTL, 0); 2009 2010 /* Some black magic with TV_DAC_CNTL, we should restore those from backups 2011 * rather than hard coding... 2012 */ 2013 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; 2014 tmp |= 6 << TV_DAC_CNTL_BGADJ__SHIFT; 2015 OUTREG(TV_DAC_CNTL, tmp); 2016 2017 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; 2018 tmp |= 6 << TV_DAC_CNTL_DACADJ__SHIFT; 2019 OUTREG(TV_DAC_CNTL, tmp); 2020 2021 OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]); 2022 2023 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]); 2024 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]); 2025 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]); 2026 2027 OUTREG(AGP_CNTL, rinfo->save_regs[16]); 2028 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */ 2029 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); 2030 2031 tmp = rinfo->save_regs[1] 2032 & ~(CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK | 2033 CLK_PWRMGT_CNTL__MC_BUSY); 2034 OUTPLL(pllCLK_PWRMGT_CNTL, tmp); 2035 2036 OUTREG(FW_CNTL, rinfo->save_regs[57]); 2037 2038 /* Disable SDRAM refresh */ 2039 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL) 2040 | MEM_REFRESH_CNTL__MEM_REFRESH_DIS); 2041 2042 /* Restore XTALIN routing (CLK_PIN_CNTL) */ 2043 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]); 2044 2045 /* Force MCLK to be PCI sourced and forced ON */ 2046 tmp = rinfo->save_regs[2] & 0xff000000; 2047 tmp |= MCLK_CNTL__FORCE_MCLKA | 2048 MCLK_CNTL__FORCE_MCLKB | 2049 MCLK_CNTL__FORCE_YCLKA | 2050 MCLK_CNTL__FORCE_YCLKB | 2051 MCLK_CNTL__FORCE_MC | 2052 MCLK_CNTL__FORCE_AIC; 2053 OUTPLL(pllMCLK_CNTL, tmp); 2054 2055 /* Force SCLK to be PCI sourced with a bunch forced */ 2056 tmp = 0 | 2057 SCLK_CNTL__FORCE_DISP2| 2058 SCLK_CNTL__FORCE_CP| 2059 SCLK_CNTL__FORCE_HDP| 2060 SCLK_CNTL__FORCE_DISP1| 2061 SCLK_CNTL__FORCE_TOP| 2062 SCLK_CNTL__FORCE_E2| 2063 SCLK_CNTL__FORCE_SE| 2064 SCLK_CNTL__FORCE_IDCT| 2065 SCLK_CNTL__FORCE_VIP| 2066 SCLK_CNTL__FORCE_RE| 2067 SCLK_CNTL__FORCE_PB| 2068 SCLK_CNTL__FORCE_TAM| 2069 SCLK_CNTL__FORCE_TDM| 2070 SCLK_CNTL__FORCE_RB; 2071 OUTPLL(pllSCLK_CNTL, tmp); 2072 2073 /* Clear VCLK_ECP_CNTL & PIXCLKS_CNTL */ 2074 OUTPLL(pllVCLK_ECP_CNTL, 0); 2075 OUTPLL(pllPIXCLKS_CNTL, 0); 2076 2077 /* Setup MCLK_MISC, non dynamic mode */ 2078 OUTPLL(pllMCLK_MISC, 2079 MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT | 2080 MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT); 2081 2082 mdelay(5); 2083 2084 /* Set back the default clock dividers */ 2085 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]); 2086 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]); 2087 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]); 2088 2089 /* PPLL and P2PLL default values & off */ 2090 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3); 2091 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3); 2092 2093 /* S and M PLLs are reset & off, configure them */ 2094 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03); 2095 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); 2096 2097 /* Default values for MDLL ... fixme */ 2098 OUTPLL(pllMDLL_CKO, 0x9c009c); 2099 OUTPLL(pllMDLL_RDCKA, 0x08830883); 2100 OUTPLL(pllMDLL_RDCKB, 0x08830883); 2101 mdelay(5); 2102 2103 /* Restore PLL_PWRMGT_CNTL */ // XXXX 2104 tmp = rinfo->save_regs[0]; 2105 tmp &= ~PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK; 2106 tmp |= PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK; 2107 OUTPLL(PLL_PWRMGT_CNTL, tmp); 2108 2109 /* Clear HTOTAL_CNTL & HTOTAL2_CNTL */ 2110 OUTPLL(pllHTOTAL_CNTL, 0); 2111 OUTPLL(pllHTOTAL2_CNTL, 0); 2112 2113 /* All outputs off */ 2114 OUTREG(CRTC_GEN_CNTL, 0x04000000); 2115 OUTREG(CRTC2_GEN_CNTL, 0x04000000); 2116 OUTREG(FP_GEN_CNTL, 0x00004008); 2117 OUTREG(FP2_GEN_CNTL, 0x00000008); 2118 OUTREG(LVDS_GEN_CNTL, 0x08000008); 2119 2120 /* Restore Memory Controller configuration */ 2121 radeon_pm_m9p_reconfigure_mc(rinfo); 2122 2123 /* Now we actually start MCLK and SCLK */ 2124 radeon_pm_start_mclk_sclk(rinfo); 2125 2126 /* Full reset sdrams, this also re-inits the MDLL */ 2127 radeon_pm_full_reset_sdram(rinfo); 2128 2129 /* Fill palettes */ 2130 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20); 2131 for (i=0; i<256; i++) 2132 OUTREG(PALETTE_30_DATA, 0x15555555); 2133 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20); 2134 udelay(20); 2135 for (i=0; i<256; i++) 2136 OUTREG(PALETTE_30_DATA, 0x15555555); 2137 2138 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20); 2139 mdelay(3); 2140 2141 /* Restore TV stuff, make sure TV DAC is down */ 2142 OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]); 2143 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000); 2144 2145 /* Restore GPIOS. MacOS does some magic here with one of the GPIO bits, 2146 * possibly related to the weird PLL related workarounds and to the 2147 * fact that CLK_PIN_CNTL is tweaked in ways I don't fully understand, 2148 * but we keep things the simple way here 2149 */ 2150 OUTREG(GPIOPAD_A, rinfo->save_regs[19]); 2151 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]); 2152 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]); 2153 2154 /* Now do things with SCLK_MORE_CNTL. Force bits are already set, copy 2155 * high bits from backup 2156 */ 2157 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; 2158 tmp |= rinfo->save_regs[34] & 0xffff0000; 2159 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS; 2160 OUTPLL(pllSCLK_MORE_CNTL, tmp); 2161 2162 tmp = INPLL(pllSCLK_MORE_CNTL) & 0x0000ffff; 2163 tmp |= rinfo->save_regs[34] & 0xffff0000; 2164 tmp |= SCLK_MORE_CNTL__FORCE_DISPREGS; 2165 OUTPLL(pllSCLK_MORE_CNTL, tmp); 2166 2167 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] & 2168 ~(LVDS_EN | LVDS_ON | LVDS_DIGON | LVDS_BLON | LVDS_BL_MOD_EN)); 2169 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON); 2170 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000); 2171 mdelay(20); 2172 2173 /* write some stuff to the framebuffer... */ 2174 for (i = 0; i < 0x8000; ++i) 2175 writeb(0, rinfo->fb_base + i); 2176 2177 OUTREG(0x2ec, 0x6332a020); 2178 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */); 2179 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */); 2180 tmp = INPLL(pllSSPLL_CNTL); 2181 tmp &= ~2; 2182 OUTPLL(pllSSPLL_CNTL, tmp); 2183 mdelay(6); 2184 tmp &= ~1; 2185 OUTPLL(pllSSPLL_CNTL, tmp); 2186 mdelay(5); 2187 tmp |= 3; 2188 OUTPLL(pllSSPLL_CNTL, tmp); 2189 mdelay(5); 2190 2191 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/ 2192 OUTREG(0x2ec, 0x6332a3f0); 2193 mdelay(17); 2194 2195 OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div); 2196 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]); 2197 2198 mdelay(40); 2199 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON); 2200 mdelay(40); 2201 2202 /* Restore a few more things */ 2203 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]); 2204 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]); 2205 2206 /* Restore PPLL, spread spectrum & LVDS */ 2207 radeon_pm_m10_disable_spread_spectrum(rinfo); 2208 radeon_pm_restore_pixel_pll(rinfo); 2209 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo); 2210 } 2211 #endif 2212 2213 #if 0 /* Not ready yet */ 2214 static void radeon_reinitialize_QW(struct radeonfb_info *rinfo) 2215 { 2216 int i; 2217 u32 tmp, tmp2; 2218 u32 cko, cka, ckb; 2219 u32 cgc, cec, c2gc; 2220 2221 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]); 2222 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]); 2223 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]); 2224 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]); 2225 OUTREG(BUS_CNTL, rinfo->save_regs[36]); 2226 OUTREG(RBBM_CNTL, rinfo->save_regs[39]); 2227 2228 INREG(PAD_CTLR_STRENGTH); 2229 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000); 2230 for (i = 0; i < 65; ++i) { 2231 mdelay(1); 2232 INREG(PAD_CTLR_STRENGTH); 2233 } 2234 2235 OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000); 2236 OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100); 2237 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL)); 2238 OUTREG(DAC_CNTL, 0xff00410a); 2239 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL)); 2240 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000); 2241 2242 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]); 2243 OUTREG(AGP_CNTL, rinfo->save_regs[16]); 2244 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); 2245 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]); 2246 2247 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433); 2248 OUTREG(MC_IND_INDEX, 0); 2249 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433); 2250 OUTREG(MC_IND_INDEX, 0); 2251 2252 OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL)); 2253 2254 tmp = INPLL(pllVCLK_ECP_CNTL); 2255 OUTPLL(pllVCLK_ECP_CNTL, tmp); 2256 tmp = INPLL(pllPIXCLKS_CNTL); 2257 OUTPLL(pllPIXCLKS_CNTL, tmp); 2258 2259 OUTPLL(MCLK_CNTL, 0xaa3f0000); 2260 OUTPLL(SCLK_CNTL, 0xffff0000); 2261 OUTPLL(pllMPLL_AUX_CNTL, 6); 2262 OUTPLL(pllSPLL_AUX_CNTL, 1); 2263 OUTPLL(MDLL_CKO, 0x9f009f); 2264 OUTPLL(MDLL_RDCKA, 0x830083); 2265 OUTPLL(pllMDLL_RDCKB, 0x830083); 2266 OUTPLL(PPLL_CNTL, 0xa433); 2267 OUTPLL(P2PLL_CNTL, 0xa433); 2268 OUTPLL(MPLL_CNTL, 0x0400a403); 2269 OUTPLL(SPLL_CNTL, 0x0400a433); 2270 2271 tmp = INPLL(M_SPLL_REF_FB_DIV); 2272 OUTPLL(M_SPLL_REF_FB_DIV, tmp); 2273 tmp = INPLL(M_SPLL_REF_FB_DIV); 2274 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0xc); 2275 INPLL(M_SPLL_REF_FB_DIV); 2276 2277 tmp = INPLL(MPLL_CNTL); 2278 OUTREG8(CLOCK_CNTL_INDEX, MPLL_CNTL + PLL_WR_EN); 2279 radeon_pll_errata_after_index(rinfo); 2280 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); 2281 radeon_pll_errata_after_data(rinfo); 2282 2283 tmp = INPLL(M_SPLL_REF_FB_DIV); 2284 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x5900); 2285 2286 tmp = INPLL(MPLL_CNTL); 2287 OUTPLL(MPLL_CNTL, tmp & ~0x2); 2288 mdelay(1); 2289 tmp = INPLL(MPLL_CNTL); 2290 OUTPLL(MPLL_CNTL, tmp & ~0x1); 2291 mdelay(10); 2292 2293 OUTPLL(MCLK_CNTL, 0xaa3f1212); 2294 mdelay(1); 2295 2296 INPLL(M_SPLL_REF_FB_DIV); 2297 INPLL(MCLK_CNTL); 2298 INPLL(M_SPLL_REF_FB_DIV); 2299 2300 tmp = INPLL(SPLL_CNTL); 2301 OUTREG8(CLOCK_CNTL_INDEX, SPLL_CNTL + PLL_WR_EN); 2302 radeon_pll_errata_after_index(rinfo); 2303 OUTREG8(CLOCK_CNTL_DATA + 1, (tmp >> 8) & 0xff); 2304 radeon_pll_errata_after_data(rinfo); 2305 2306 tmp = INPLL(M_SPLL_REF_FB_DIV); 2307 OUTPLL(M_SPLL_REF_FB_DIV, tmp | 0x780000); 2308 2309 tmp = INPLL(SPLL_CNTL); 2310 OUTPLL(SPLL_CNTL, tmp & ~0x1); 2311 mdelay(1); 2312 tmp = INPLL(SPLL_CNTL); 2313 OUTPLL(SPLL_CNTL, tmp & ~0x2); 2314 mdelay(10); 2315 2316 tmp = INPLL(SCLK_CNTL); 2317 OUTPLL(SCLK_CNTL, tmp | 2); 2318 mdelay(1); 2319 2320 cko = INPLL(pllMDLL_CKO); 2321 cka = INPLL(pllMDLL_RDCKA); 2322 ckb = INPLL(pllMDLL_RDCKB); 2323 2324 cko &= ~(MDLL_CKO__MCKOA_SLEEP | MDLL_CKO__MCKOB_SLEEP); 2325 OUTPLL(pllMDLL_CKO, cko); 2326 mdelay(1); 2327 cko &= ~(MDLL_CKO__MCKOA_RESET | MDLL_CKO__MCKOB_RESET); 2328 OUTPLL(pllMDLL_CKO, cko); 2329 mdelay(5); 2330 2331 cka &= ~(MDLL_RDCKA__MRDCKA0_SLEEP | MDLL_RDCKA__MRDCKA1_SLEEP); 2332 OUTPLL(pllMDLL_RDCKA, cka); 2333 mdelay(1); 2334 cka &= ~(MDLL_RDCKA__MRDCKA0_RESET | MDLL_RDCKA__MRDCKA1_RESET); 2335 OUTPLL(pllMDLL_RDCKA, cka); 2336 mdelay(5); 2337 2338 ckb &= ~(MDLL_RDCKB__MRDCKB0_SLEEP | MDLL_RDCKB__MRDCKB1_SLEEP); 2339 OUTPLL(pllMDLL_RDCKB, ckb); 2340 mdelay(1); 2341 ckb &= ~(MDLL_RDCKB__MRDCKB0_RESET | MDLL_RDCKB__MRDCKB1_RESET); 2342 OUTPLL(pllMDLL_RDCKB, ckb); 2343 mdelay(5); 2344 2345 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff); 2346 OUTREG(MC_IND_INDEX, 0); 2347 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff); 2348 OUTREG(MC_IND_INDEX, 0); 2349 mdelay(1); 2350 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff); 2351 OUTREG(MC_IND_INDEX, 0); 2352 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff); 2353 OUTREG(MC_IND_INDEX, 0); 2354 mdelay(1); 2355 2356 OUTPLL(pllHTOTAL_CNTL, 0); 2357 OUTPLL(pllHTOTAL2_CNTL, 0); 2358 2359 OUTREG(MEM_CNTL, 0x29002901); 2360 OUTREG(MEM_SDRAM_MODE_REG, 0x45320032); /* XXX use save_regs[35]? */ 2361 OUTREG(EXT_MEM_CNTL, 0x1a394333); 2362 OUTREG(MEM_IO_CNTL_A1, 0x0aac0aac); 2363 OUTREG(MEM_INIT_LATENCY_TIMER, 0x34444444); 2364 OUTREG(MEM_REFRESH_CNTL, 0x1f1f7218); /* XXX or save_regs[42]? */ 2365 OUTREG(MC_DEBUG, 0); 2366 OUTREG(MEM_IO_OE_CNTL, 0x04300430); 2367 2368 OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6); 2369 OUTREG(MC_IND_INDEX, 0); 2370 OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249); 2371 OUTREG(MC_IND_INDEX, 0); 2372 2373 OUTREG(CNFG_MEMSIZE, rinfo->video_ram); 2374 2375 radeon_pm_full_reset_sdram(rinfo); 2376 2377 INREG(FP_GEN_CNTL); 2378 OUTREG(TMDS_CNTL, 0x01000000); /* XXX ? */ 2379 tmp = INREG(FP_GEN_CNTL); 2380 tmp |= FP_CRTC_DONT_SHADOW_HEND | FP_CRTC_DONT_SHADOW_VPAR | 0x200; 2381 OUTREG(FP_GEN_CNTL, tmp); 2382 2383 tmp = INREG(DISP_OUTPUT_CNTL); 2384 tmp &= ~0x400; 2385 OUTREG(DISP_OUTPUT_CNTL, tmp); 2386 2387 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]); 2388 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]); 2389 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]); 2390 2391 tmp = INPLL(MCLK_MISC); 2392 tmp |= MCLK_MISC__MC_MCLK_DYN_ENABLE | MCLK_MISC__IO_MCLK_DYN_ENABLE; 2393 OUTPLL(MCLK_MISC, tmp); 2394 2395 tmp = INPLL(SCLK_CNTL); 2396 OUTPLL(SCLK_CNTL, tmp); 2397 2398 OUTREG(CRTC_MORE_CNTL, 0); 2399 OUTREG8(CRTC_GEN_CNTL+1, 6); 2400 OUTREG8(CRTC_GEN_CNTL+3, 1); 2401 OUTREG(CRTC_PITCH, 32); 2402 2403 tmp = INPLL(VCLK_ECP_CNTL); 2404 OUTPLL(VCLK_ECP_CNTL, tmp); 2405 2406 tmp = INPLL(PPLL_CNTL); 2407 OUTPLL(PPLL_CNTL, tmp); 2408 2409 /* palette stuff and BIOS_1_SCRATCH... */ 2410 2411 tmp = INREG(FP_GEN_CNTL); 2412 tmp2 = INREG(TMDS_TRANSMITTER_CNTL); 2413 tmp |= 2; 2414 OUTREG(FP_GEN_CNTL, tmp); 2415 mdelay(5); 2416 OUTREG(FP_GEN_CNTL, tmp); 2417 mdelay(5); 2418 OUTREG(TMDS_TRANSMITTER_CNTL, tmp2); 2419 OUTREG(CRTC_MORE_CNTL, 0); 2420 mdelay(20); 2421 2422 tmp = INREG(CRTC_MORE_CNTL); 2423 OUTREG(CRTC_MORE_CNTL, tmp); 2424 2425 cgc = INREG(CRTC_GEN_CNTL); 2426 cec = INREG(CRTC_EXT_CNTL); 2427 c2gc = INREG(CRTC2_GEN_CNTL); 2428 2429 OUTREG(CRTC_H_SYNC_STRT_WID, 0x008e0580); 2430 OUTREG(CRTC_H_TOTAL_DISP, 0x009f00d2); 2431 OUTREG8(CLOCK_CNTL_INDEX, HTOTAL_CNTL + PLL_WR_EN); 2432 radeon_pll_errata_after_index(rinfo); 2433 OUTREG8(CLOCK_CNTL_DATA, 0); 2434 radeon_pll_errata_after_data(rinfo); 2435 OUTREG(CRTC_V_SYNC_STRT_WID, 0x00830403); 2436 OUTREG(CRTC_V_TOTAL_DISP, 0x03ff0429); 2437 OUTREG(FP_CRTC_H_TOTAL_DISP, 0x009f0033); 2438 OUTREG(FP_H_SYNC_STRT_WID, 0x008e0080); 2439 OUTREG(CRT_CRTC_H_SYNC_STRT_WID, 0x008e0080); 2440 OUTREG(FP_CRTC_V_TOTAL_DISP, 0x03ff002a); 2441 OUTREG(FP_V_SYNC_STRT_WID, 0x00830004); 2442 OUTREG(CRT_CRTC_V_SYNC_STRT_WID, 0x00830004); 2443 OUTREG(FP_HORZ_VERT_ACTIVE, 0x009f03ff); 2444 OUTREG(FP_HORZ_STRETCH, 0); 2445 OUTREG(FP_VERT_STRETCH, 0); 2446 OUTREG(OVR_CLR, 0); 2447 OUTREG(OVR_WID_LEFT_RIGHT, 0); 2448 OUTREG(OVR_WID_TOP_BOTTOM, 0); 2449 2450 tmp = INPLL(PPLL_REF_DIV); 2451 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; 2452 OUTPLL(PPLL_REF_DIV, tmp); 2453 INPLL(PPLL_REF_DIV); 2454 2455 OUTREG8(CLOCK_CNTL_INDEX, PPLL_CNTL + PLL_WR_EN); 2456 radeon_pll_errata_after_index(rinfo); 2457 OUTREG8(CLOCK_CNTL_DATA + 1, 0xbc); 2458 radeon_pll_errata_after_data(rinfo); 2459 2460 tmp = INREG(CLOCK_CNTL_INDEX); 2461 radeon_pll_errata_after_index(rinfo); 2462 OUTREG(CLOCK_CNTL_INDEX, tmp & 0xff); 2463 radeon_pll_errata_after_index(rinfo); 2464 radeon_pll_errata_after_data(rinfo); 2465 2466 OUTPLL(PPLL_DIV_0, 0x48090); 2467 2468 tmp = INPLL(PPLL_CNTL); 2469 OUTPLL(PPLL_CNTL, tmp & ~0x2); 2470 mdelay(1); 2471 tmp = INPLL(PPLL_CNTL); 2472 OUTPLL(PPLL_CNTL, tmp & ~0x1); 2473 mdelay(10); 2474 2475 tmp = INPLL(VCLK_ECP_CNTL); 2476 OUTPLL(VCLK_ECP_CNTL, tmp | 3); 2477 mdelay(1); 2478 2479 tmp = INPLL(VCLK_ECP_CNTL); 2480 OUTPLL(VCLK_ECP_CNTL, tmp); 2481 2482 c2gc |= CRTC2_DISP_REQ_EN_B; 2483 OUTREG(CRTC2_GEN_CNTL, c2gc); 2484 cgc |= CRTC_EN; 2485 OUTREG(CRTC_GEN_CNTL, cgc); 2486 OUTREG(CRTC_EXT_CNTL, cec); 2487 OUTREG(CRTC_PITCH, 0xa0); 2488 OUTREG(CRTC_OFFSET, 0); 2489 OUTREG(CRTC_OFFSET_CNTL, 0); 2490 2491 OUTREG(GRPH_BUFFER_CNTL, 0x20117c7c); 2492 OUTREG(GRPH2_BUFFER_CNTL, 0x00205c5c); 2493 2494 tmp2 = INREG(FP_GEN_CNTL); 2495 tmp = INREG(TMDS_TRANSMITTER_CNTL); 2496 OUTREG(0x2a8, 0x0000061b); 2497 tmp |= TMDS_PLL_EN; 2498 OUTREG(TMDS_TRANSMITTER_CNTL, tmp); 2499 mdelay(1); 2500 tmp &= ~TMDS_PLLRST; 2501 OUTREG(TMDS_TRANSMITTER_CNTL, tmp); 2502 tmp2 &= ~2; 2503 tmp2 |= FP_TMDS_EN; 2504 OUTREG(FP_GEN_CNTL, tmp2); 2505 mdelay(5); 2506 tmp2 |= FP_FPON; 2507 OUTREG(FP_GEN_CNTL, tmp2); 2508 2509 OUTREG(CUR_HORZ_VERT_OFF, CUR_LOCK | 1); 2510 cgc = INREG(CRTC_GEN_CNTL); 2511 OUTREG(CUR_HORZ_VERT_POSN, 0xbfff0fff); 2512 cgc |= 0x10000; 2513 OUTREG(CUR_OFFSET, 0); 2514 } 2515 #endif /* 0 */ 2516 2517 #endif /* CONFIG_PPC */ 2518 2519 static void radeonfb_whack_power_state(struct radeonfb_info *rinfo, pci_power_t state) 2520 { 2521 u16 pwr_cmd; 2522 2523 for (;;) { 2524 pci_read_config_word(rinfo->pdev, 2525 rinfo->pdev->pm_cap + PCI_PM_CTRL, 2526 &pwr_cmd); 2527 if (pwr_cmd & state) 2528 break; 2529 pwr_cmd = (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | state; 2530 pci_write_config_word(rinfo->pdev, 2531 rinfo->pdev->pm_cap + PCI_PM_CTRL, 2532 pwr_cmd); 2533 msleep(500); 2534 } 2535 rinfo->pdev->current_state = state; 2536 } 2537 2538 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend) 2539 { 2540 u32 tmp; 2541 2542 if (!rinfo->pdev->pm_cap) 2543 return; 2544 2545 /* Set the chip into appropriate suspend mode (we use D2, 2546 * D3 would require a compete re-initialization of the chip, 2547 * including PCI config registers, clocks, AGP conf, ...) 2548 */ 2549 if (suspend) { 2550 printk(KERN_DEBUG "radeonfb (%s): switching to D2 state...\n", 2551 pci_name(rinfo->pdev)); 2552 2553 /* Disable dynamic power management of clocks for the 2554 * duration of the suspend/resume process 2555 */ 2556 radeon_pm_disable_dynamic_mode(rinfo); 2557 2558 /* Save some registers */ 2559 radeon_pm_save_regs(rinfo, 0); 2560 2561 /* Prepare mobility chips for suspend. 2562 */ 2563 if (rinfo->is_mobility) { 2564 /* Program V2CLK */ 2565 radeon_pm_program_v2clk(rinfo); 2566 2567 /* Disable IO PADs */ 2568 radeon_pm_disable_iopad(rinfo); 2569 2570 /* Set low current */ 2571 radeon_pm_low_current(rinfo); 2572 2573 /* Prepare chip for power management */ 2574 radeon_pm_setup_for_suspend(rinfo); 2575 2576 if (rinfo->family <= CHIP_FAMILY_RV280) { 2577 /* Reset the MDLL */ 2578 /* because both INPLL and OUTPLL take the same 2579 * lock, that's why. */ 2580 tmp = INPLL( pllMDLL_CKO) | MDLL_CKO__MCKOA_RESET 2581 | MDLL_CKO__MCKOB_RESET; 2582 OUTPLL( pllMDLL_CKO, tmp ); 2583 } 2584 } 2585 2586 /* Switch PCI power management to D2. */ 2587 pci_disable_device(rinfo->pdev); 2588 pci_save_state(rinfo->pdev); 2589 /* The chip seems to need us to whack the PM register 2590 * repeatedly until it sticks. We do that -prior- to 2591 * calling pci_set_power_state() 2592 */ 2593 radeonfb_whack_power_state(rinfo, PCI_D2); 2594 pci_platform_power_transition(rinfo->pdev, PCI_D2); 2595 } else { 2596 printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n", 2597 pci_name(rinfo->pdev)); 2598 2599 if (rinfo->family <= CHIP_FAMILY_RV250) { 2600 /* Reset the SDRAM controller */ 2601 radeon_pm_full_reset_sdram(rinfo); 2602 2603 /* Restore some registers */ 2604 radeon_pm_restore_regs(rinfo); 2605 } else { 2606 /* Restore registers first */ 2607 radeon_pm_restore_regs(rinfo); 2608 /* init sdram controller */ 2609 radeon_pm_full_reset_sdram(rinfo); 2610 } 2611 } 2612 } 2613 2614 static int radeonfb_pci_suspend_late(struct device *dev, pm_message_t mesg) 2615 { 2616 struct pci_dev *pdev = to_pci_dev(dev); 2617 struct fb_info *info = pci_get_drvdata(pdev); 2618 struct radeonfb_info *rinfo = info->par; 2619 2620 if (mesg.event == pdev->dev.power.power_state.event) 2621 return 0; 2622 2623 printk(KERN_DEBUG "radeonfb (%s): suspending for event: %d...\n", 2624 pci_name(pdev), mesg.event); 2625 2626 /* For suspend-to-disk, we cheat here. We don't suspend anything and 2627 * let fbcon continue drawing until we are all set. That shouldn't 2628 * really cause any problem at this point, provided that the wakeup 2629 * code knows that any state in memory may not match the HW 2630 */ 2631 switch (mesg.event) { 2632 case PM_EVENT_FREEZE: /* about to take snapshot */ 2633 case PM_EVENT_PRETHAW: /* before restoring snapshot */ 2634 goto done; 2635 } 2636 2637 console_lock(); 2638 2639 fb_set_suspend(info, 1); 2640 2641 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { 2642 /* Make sure engine is reset */ 2643 radeon_engine_idle(); 2644 radeonfb_engine_reset(rinfo); 2645 radeon_engine_idle(); 2646 } 2647 2648 /* Blank display and LCD */ 2649 radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1); 2650 2651 /* Sleep */ 2652 rinfo->asleep = 1; 2653 rinfo->lock_blank = 1; 2654 del_timer_sync(&rinfo->lvds_timer); 2655 2656 #ifdef CONFIG_PPC_PMAC 2657 /* On powermac, we have hooks to properly suspend/resume AGP now, 2658 * use them here. We'll ultimately need some generic support here, 2659 * but the generic code isn't quite ready for that yet 2660 */ 2661 pmac_suspend_agp_for_card(pdev); 2662 #endif /* CONFIG_PPC_PMAC */ 2663 2664 /* If we support wakeup from poweroff, we save all regs we can including cfg 2665 * space 2666 */ 2667 if (rinfo->pm_mode & radeon_pm_off) { 2668 /* Always disable dynamic clocks or weird things are happening when 2669 * the chip goes off (basically the panel doesn't shut down properly 2670 * and we crash on wakeup), 2671 * also, we want the saved regs context to have no dynamic clocks in 2672 * it, we'll restore the dynamic clocks state on wakeup 2673 */ 2674 radeon_pm_disable_dynamic_mode(rinfo); 2675 msleep(50); 2676 radeon_pm_save_regs(rinfo, 1); 2677 2678 if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) { 2679 /* Switch off LVDS interface */ 2680 usleep_range(1000, 2000); 2681 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN)); 2682 usleep_range(1000, 2000); 2683 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON)); 2684 OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000); 2685 msleep(20); 2686 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON)); 2687 } 2688 } 2689 /* If we support D2, we go to it (should be fixed later with a flag forcing 2690 * D3 only for some laptops) 2691 */ 2692 if (rinfo->pm_mode & radeon_pm_d2) 2693 radeon_set_suspend(rinfo, 1); 2694 2695 console_unlock(); 2696 2697 done: 2698 pdev->dev.power.power_state = mesg; 2699 2700 return 0; 2701 } 2702 2703 static int radeonfb_pci_suspend(struct device *dev) 2704 { 2705 return radeonfb_pci_suspend_late(dev, PMSG_SUSPEND); 2706 } 2707 2708 static int radeonfb_pci_hibernate(struct device *dev) 2709 { 2710 return radeonfb_pci_suspend_late(dev, PMSG_HIBERNATE); 2711 } 2712 2713 static int radeonfb_pci_freeze(struct device *dev) 2714 { 2715 return radeonfb_pci_suspend_late(dev, PMSG_FREEZE); 2716 } 2717 2718 static int radeon_check_power_loss(struct radeonfb_info *rinfo) 2719 { 2720 return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) || 2721 rinfo->save_regs[2] != INPLL(MCLK_CNTL) || 2722 rinfo->save_regs[3] != INPLL(SCLK_CNTL); 2723 } 2724 2725 static int radeonfb_pci_resume(struct device *dev) 2726 { 2727 struct pci_dev *pdev = to_pci_dev(dev); 2728 struct fb_info *info = pci_get_drvdata(pdev); 2729 struct radeonfb_info *rinfo = info->par; 2730 int rc = 0; 2731 2732 if (pdev->dev.power.power_state.event == PM_EVENT_ON) 2733 return 0; 2734 2735 if (rinfo->no_schedule) { 2736 if (!console_trylock()) 2737 return 0; 2738 } else 2739 console_lock(); 2740 2741 printk(KERN_DEBUG "radeonfb (%s): resuming from state: %d...\n", 2742 pci_name(pdev), pdev->dev.power.power_state.event); 2743 2744 /* PCI state will have been restored by the core, so 2745 * we should be in D0 now with our config space fully 2746 * restored 2747 */ 2748 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 2749 /* Wakeup chip */ 2750 if ((rinfo->pm_mode & radeon_pm_off) && radeon_check_power_loss(rinfo)) { 2751 if (rinfo->reinit_func != NULL) 2752 rinfo->reinit_func(rinfo); 2753 else { 2754 printk(KERN_ERR "radeonfb (%s): can't resume radeon from" 2755 " D3 cold, need softboot !", pci_name(pdev)); 2756 rc = -EIO; 2757 goto bail; 2758 } 2759 } 2760 /* If we support D2, try to resume... we should check what was our 2761 * state though... (were we really in D2 state ?). Right now, this code 2762 * is only enable on Macs so it's fine. 2763 */ 2764 else if (rinfo->pm_mode & radeon_pm_d2) 2765 radeon_set_suspend(rinfo, 0); 2766 2767 rinfo->asleep = 0; 2768 } else 2769 radeon_engine_idle(); 2770 2771 /* Restore display & engine */ 2772 radeon_write_mode (rinfo, &rinfo->state, 1); 2773 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) 2774 radeonfb_engine_init (rinfo); 2775 2776 fb_pan_display(info, &info->var); 2777 fb_set_cmap(&info->cmap, info); 2778 2779 /* Refresh */ 2780 fb_set_suspend(info, 0); 2781 2782 /* Unblank */ 2783 rinfo->lock_blank = 0; 2784 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1); 2785 2786 #ifdef CONFIG_PPC_PMAC 2787 /* On powermac, we have hooks to properly suspend/resume AGP now, 2788 * use them here. We'll ultimately need some generic support here, 2789 * but the generic code isn't quite ready for that yet 2790 */ 2791 pmac_resume_agp_for_card(pdev); 2792 #endif /* CONFIG_PPC_PMAC */ 2793 2794 2795 /* Check status of dynclk */ 2796 if (rinfo->dynclk == 1) 2797 radeon_pm_enable_dynamic_mode(rinfo); 2798 else if (rinfo->dynclk == 0) 2799 radeon_pm_disable_dynamic_mode(rinfo); 2800 2801 pdev->dev.power.power_state = PMSG_ON; 2802 2803 bail: 2804 console_unlock(); 2805 2806 return rc; 2807 } 2808 2809 const struct dev_pm_ops radeonfb_pci_pm_ops = { 2810 .suspend = radeonfb_pci_suspend, 2811 .resume = radeonfb_pci_resume, 2812 .freeze = radeonfb_pci_freeze, 2813 .thaw = radeonfb_pci_resume, 2814 .poweroff = radeonfb_pci_hibernate, 2815 .restore = radeonfb_pci_resume, 2816 }; 2817 2818 #ifdef CONFIG_PPC__disabled 2819 static void radeonfb_early_resume(void *data) 2820 { 2821 struct radeonfb_info *rinfo = data; 2822 2823 rinfo->no_schedule = 1; 2824 pci_restore_state(rinfo->pdev); 2825 radeonfb_pci_resume(rinfo->pdev); 2826 rinfo->no_schedule = 0; 2827 } 2828 #endif /* CONFIG_PPC */ 2829 2830 #endif /* CONFIG_PM */ 2831 2832 void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep) 2833 { 2834 /* Enable/Disable dynamic clocks: TODO add sysfs access */ 2835 if (rinfo->family == CHIP_FAMILY_RS480) 2836 rinfo->dynclk = -1; 2837 else 2838 rinfo->dynclk = dynclk; 2839 2840 if (rinfo->dynclk == 1) { 2841 radeon_pm_enable_dynamic_mode(rinfo); 2842 printk("radeonfb: Dynamic Clock Power Management enabled\n"); 2843 } else if (rinfo->dynclk == 0) { 2844 radeon_pm_disable_dynamic_mode(rinfo); 2845 printk("radeonfb: Dynamic Clock Power Management disabled\n"); 2846 } 2847 2848 #if defined(CONFIG_PM) 2849 #if defined(CONFIG_PPC_PMAC) 2850 /* Check if we can power manage on suspend/resume. We can do 2851 * D2 on M6, M7 and M9, and we can resume from D3 cold a few other 2852 * "Mac" cards, but that's all. We need more infos about what the 2853 * BIOS does tho. Right now, all this PM stuff is pmac-only for that 2854 * reason. --BenH 2855 */ 2856 if (machine_is(powermac) && rinfo->of_node) { 2857 if (rinfo->is_mobility && rinfo->pdev->pm_cap && 2858 rinfo->family <= CHIP_FAMILY_RV250) 2859 rinfo->pm_mode |= radeon_pm_d2; 2860 2861 /* We can restart Jasper (M10 chip in albooks), BlueStone (7500 chip 2862 * in some desktop G4s), Via (M9+ chip on iBook G4) and 2863 * Snowy (M11 chip on iBook G4 manufactured after July 2005) 2864 */ 2865 if (of_node_name_eq(rinfo->of_node, "ATY,JasperParent") || 2866 of_node_name_eq(rinfo->of_node, "ATY,SnowyParent")) { 2867 rinfo->reinit_func = radeon_reinitialize_M10; 2868 rinfo->pm_mode |= radeon_pm_off; 2869 } 2870 #if 0 /* Not ready yet */ 2871 if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) { 2872 rinfo->reinit_func = radeon_reinitialize_QW; 2873 rinfo->pm_mode |= radeon_pm_off; 2874 } 2875 #endif 2876 if (of_node_name_eq(rinfo->of_node, "ATY,ViaParent")) { 2877 rinfo->reinit_func = radeon_reinitialize_M9P; 2878 rinfo->pm_mode |= radeon_pm_off; 2879 } 2880 2881 /* If any of the above is set, we assume the machine can sleep/resume. 2882 * It's a bit of a "shortcut" but will work fine. Ideally, we need infos 2883 * from the platform about what happens to the chip... 2884 * Now we tell the platform about our capability 2885 */ 2886 if (rinfo->pm_mode != radeon_pm_none) { 2887 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1); 2888 #if 0 /* Disable the early video resume hack for now as it's causing problems, among 2889 * others we now rely on the PCI core restoring the config space for us, which 2890 * isn't the case with that hack, and that code path causes various things to 2891 * be called with interrupts off while they shouldn't. I'm leaving the code in 2892 * as it can be useful for debugging purposes 2893 */ 2894 pmac_set_early_video_resume(radeonfb_early_resume, rinfo); 2895 #endif 2896 } 2897 2898 #if 0 2899 /* Power down TV DAC, that saves a significant amount of power, 2900 * we'll have something better once we actually have some TVOut 2901 * support 2902 */ 2903 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000); 2904 #endif 2905 } 2906 #endif /* defined(CONFIG_PPC_PMAC) */ 2907 #endif /* defined(CONFIG_PM) */ 2908 2909 if (ignore_devlist) 2910 printk(KERN_DEBUG 2911 "radeonfb: skipping test for device workarounds\n"); 2912 else 2913 radeon_apply_workarounds(rinfo); 2914 2915 if (force_sleep) { 2916 printk(KERN_DEBUG 2917 "radeonfb: forcefully enabling D2 sleep mode\n"); 2918 rinfo->pm_mode |= radeon_pm_d2; 2919 } 2920 } 2921 2922 void radeonfb_pm_exit(struct radeonfb_info *rinfo) 2923 { 2924 #if defined(CONFIG_PM) && defined(CONFIG_PPC_PMAC) 2925 if (rinfo->pm_mode != radeon_pm_none) 2926 pmac_set_early_video_resume(NULL, NULL); 2927 #endif 2928 } 2929