1 /* 2 * drivers/video/aty/radeon_base.c 3 * 4 * framebuffer driver for ATI Radeon chipset video boards 5 * 6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org> 7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org> 8 * 9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net> 10 * 11 * Special thanks to ATI DevRel team for their hardware donations. 12 * 13 * ...Insert GPL boilerplate here... 14 * 15 * Significant portions of this driver apdated from XFree86 Radeon 16 * driver which has the following copyright notice: 17 * 18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 19 * VA Linux Systems Inc., Fremont, California. 20 * 21 * All Rights Reserved. 22 * 23 * Permission is hereby granted, free of charge, to any person obtaining 24 * a copy of this software and associated documentation files (the 25 * "Software"), to deal in the Software without restriction, including 26 * without limitation on the rights to use, copy, modify, merge, 27 * publish, distribute, sublicense, and/or sell copies of the Software, 28 * and to permit persons to whom the Software is furnished to do so, 29 * subject to the following conditions: 30 * 31 * The above copyright notice and this permission notice (including the 32 * next paragraph) shall be included in all copies or substantial 33 * portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 42 * DEALINGS IN THE SOFTWARE. 43 * 44 * XFree86 driver authors: 45 * 46 * Kevin E. Martin <martin@xfree86.org> 47 * Rickard E. Faith <faith@valinux.com> 48 * Alan Hourihane <alanh@fairlite.demon.co.uk> 49 * 50 */ 51 52 53 #define RADEON_VERSION "0.2.0" 54 55 #include "radeonfb.h" 56 57 #include <linux/module.h> 58 #include <linux/moduleparam.h> 59 #include <linux/kernel.h> 60 #include <linux/errno.h> 61 #include <linux/string.h> 62 #include <linux/ctype.h> 63 #include <linux/mm.h> 64 #include <linux/slab.h> 65 #include <linux/delay.h> 66 #include <linux/time.h> 67 #include <linux/fb.h> 68 #include <linux/ioport.h> 69 #include <linux/init.h> 70 #include <linux/pci.h> 71 #include <linux/vmalloc.h> 72 #include <linux/device.h> 73 74 #include <asm/io.h> 75 #include <linux/uaccess.h> 76 77 #ifdef CONFIG_PPC 78 79 #include <asm/pci-bridge.h> 80 #include "../macmodes.h" 81 82 #ifdef CONFIG_BOOTX_TEXT 83 #include <asm/btext.h> 84 #endif 85 86 #endif /* CONFIG_PPC */ 87 88 #include <video/radeon.h> 89 #include <linux/radeonfb.h> 90 91 #include "../edid.h" // MOVE THAT TO include/video 92 #include "ati_ids.h" 93 94 #define MAX_MAPPED_VRAM (2048*2048*4) 95 #define MIN_MAPPED_VRAM (1024*768*1) 96 97 #define CHIP_DEF(id, family, flags) \ 98 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) } 99 100 static struct pci_device_id radeonfb_pci_table[] = { 101 /* Radeon Xpress 200m */ 102 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 103 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 104 /* Mobility M6 */ 105 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 106 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 107 /* Radeon VE/7000 */ 108 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2), 109 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2), 110 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2), 111 /* Radeon IGP320M (U1) */ 112 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 113 /* Radeon IGP320 (A3) */ 114 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 115 /* IGP330M/340M/350M (U2) */ 116 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 117 /* IGP330/340/350 (A4) */ 118 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 119 /* Mobility 7000 IGP */ 120 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 121 /* 7000 IGP (A4+) */ 122 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 123 /* 8500 AIW */ 124 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2), 125 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2), 126 /* 8700/8800 */ 127 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2), 128 /* 8500 */ 129 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2), 130 /* 9100 */ 131 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2), 132 /* Mobility M7 */ 133 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 134 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 135 /* 7500 */ 136 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2), 137 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2), 138 /* Mobility M9 */ 139 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 140 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 141 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 142 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 143 /* 9000/Pro */ 144 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2), 145 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2), 146 147 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 148 /* Mobility 9100 IGP (U3) */ 149 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 150 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 151 /* 9100 IGP (A5) */ 152 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 153 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 154 /* Mobility 9200 (M9+) */ 155 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 156 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 157 /* 9200 */ 158 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2), 159 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2), 160 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2), 161 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2), 162 /* 9500 */ 163 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2), 164 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2), 165 /* 9600TX / FireGL Z1 */ 166 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2), 167 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2), 168 /* 9700/9500/Pro/FireGL X1 */ 169 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2), 170 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2), 171 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2), 172 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2), 173 /* Mobility M10/M11 */ 174 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 175 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 176 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 177 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 178 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 179 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 180 /* 9600/FireGL T2 */ 181 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2), 182 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2), 183 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2), 184 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2), 185 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2), 186 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2), 187 /* 9800/Pro/FileGL X2 */ 188 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2), 189 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2), 190 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2), 191 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2), 192 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2), 193 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2), 194 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2), 195 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2), 196 /* Newer stuff */ 197 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2), 198 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2), 199 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 200 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 201 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2), 202 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2), 203 CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2), 204 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2), 205 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2), 206 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 207 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 208 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2), 209 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2), 210 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2), 211 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2), 212 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2), 213 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2), 214 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 215 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2), 216 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2), 217 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2), 218 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2), 219 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2), 220 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2), 221 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2), 222 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2), 223 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2), 224 /* Original Radeon/7200 */ 225 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0), 226 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0), 227 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0), 228 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0), 229 { 0, } 230 }; 231 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table); 232 233 234 typedef struct { 235 u16 reg; 236 u32 val; 237 } reg_val; 238 239 240 /* these common regs are cleared before mode setting so they do not 241 * interfere with anything 242 */ 243 static reg_val common_regs[] = { 244 { OVR_CLR, 0 }, 245 { OVR_WID_LEFT_RIGHT, 0 }, 246 { OVR_WID_TOP_BOTTOM, 0 }, 247 { OV0_SCALE_CNTL, 0 }, 248 { SUBPIC_CNTL, 0 }, 249 { VIPH_CONTROL, 0 }, 250 { I2C_CNTL_1, 0 }, 251 { GEN_INT_CNTL, 0 }, 252 { CAP0_TRIG_CNTL, 0 }, 253 { CAP1_TRIG_CNTL, 0 }, 254 }; 255 256 /* 257 * globals 258 */ 259 260 static char *mode_option; 261 static char *monitor_layout; 262 static bool noaccel = 0; 263 static int default_dynclk = -2; 264 static bool nomodeset = 0; 265 static bool ignore_edid = 0; 266 static bool mirror = 0; 267 static int panel_yres = 0; 268 static bool force_dfp = 0; 269 static bool force_measure_pll = 0; 270 static bool nomtrr = 0; 271 static bool force_sleep; 272 static bool ignore_devlist; 273 #ifdef CONFIG_PMAC_BACKLIGHT 274 static int backlight = 1; 275 #else 276 static int backlight = 0; 277 #endif 278 279 /* Note about this function: we have some rare cases where we must not schedule, 280 * this typically happen with our special "wake up early" hook which allows us to 281 * wake up the graphic chip (and thus get the console back) before everything else 282 * on some machines that support that mechanism. At this point, interrupts are off 283 * and scheduling is not permitted 284 */ 285 void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms) 286 { 287 if (rinfo->no_schedule || oops_in_progress) 288 mdelay(ms); 289 else 290 msleep(ms); 291 } 292 293 void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo) 294 { 295 /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */ 296 (void)INREG(CLOCK_CNTL_DATA); 297 (void)INREG(CRTC_GEN_CNTL); 298 } 299 300 void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo) 301 { 302 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) { 303 /* we can't deal with posted writes here ... */ 304 _radeon_msleep(rinfo, 5); 305 } 306 if (rinfo->errata & CHIP_ERRATA_R300_CG) { 307 u32 save, tmp; 308 save = INREG(CLOCK_CNTL_INDEX); 309 tmp = save & ~(0x3f | PLL_WR_EN); 310 OUTREG(CLOCK_CNTL_INDEX, tmp); 311 tmp = INREG(CLOCK_CNTL_DATA); 312 OUTREG(CLOCK_CNTL_INDEX, save); 313 } 314 } 315 316 void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask) 317 { 318 unsigned long flags; 319 unsigned int tmp; 320 321 spin_lock_irqsave(&rinfo->reg_lock, flags); 322 tmp = INREG(addr); 323 tmp &= (mask); 324 tmp |= (val); 325 OUTREG(addr, tmp); 326 spin_unlock_irqrestore(&rinfo->reg_lock, flags); 327 } 328 329 u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) 330 { 331 u32 data; 332 333 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); 334 radeon_pll_errata_after_index(rinfo); 335 data = INREG(CLOCK_CNTL_DATA); 336 radeon_pll_errata_after_data(rinfo); 337 return data; 338 } 339 340 void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val) 341 { 342 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); 343 radeon_pll_errata_after_index(rinfo); 344 OUTREG(CLOCK_CNTL_DATA, val); 345 radeon_pll_errata_after_data(rinfo); 346 } 347 348 void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, 349 u32 val, u32 mask) 350 { 351 unsigned int tmp; 352 353 tmp = __INPLL(rinfo, index); 354 tmp &= (mask); 355 tmp |= (val); 356 __OUTPLL(rinfo, index, tmp); 357 } 358 359 void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) 360 { 361 int i; 362 363 for (i=0; i<2000000; i++) { 364 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) 365 return; 366 udelay(1); 367 } 368 printk(KERN_ERR "radeonfb: FIFO Timeout !\n"); 369 } 370 371 void radeon_engine_flush(struct radeonfb_info *rinfo) 372 { 373 int i; 374 375 /* Initiate flush */ 376 OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, 377 ~RB2D_DC_FLUSH_ALL); 378 379 /* Ensure FIFO is empty, ie, make sure the flush commands 380 * has reached the cache 381 */ 382 _radeon_fifo_wait(rinfo, 64); 383 384 /* Wait for the flush to complete */ 385 for (i=0; i < 2000000; i++) { 386 if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) 387 return; 388 udelay(1); 389 } 390 printk(KERN_ERR "radeonfb: Flush Timeout !\n"); 391 } 392 393 void _radeon_engine_idle(struct radeonfb_info *rinfo) 394 { 395 int i; 396 397 /* ensure FIFO is empty before waiting for idle */ 398 _radeon_fifo_wait(rinfo, 64); 399 400 for (i=0; i<2000000; i++) { 401 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { 402 radeon_engine_flush(rinfo); 403 return; 404 } 405 udelay(1); 406 } 407 printk(KERN_ERR "radeonfb: Idle Timeout !\n"); 408 } 409 410 411 412 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev) 413 { 414 if (!rinfo->bios_seg) 415 return; 416 pci_unmap_rom(dev, rinfo->bios_seg); 417 } 418 419 static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev) 420 { 421 void __iomem *rom; 422 u16 dptr; 423 u8 rom_type; 424 size_t rom_size; 425 426 /* If this is a primary card, there is a shadow copy of the 427 * ROM somewhere in the first meg. We will just ignore the copy 428 * and use the ROM directly. 429 */ 430 431 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */ 432 unsigned int temp; 433 temp = INREG(MPP_TB_CONFIG); 434 temp &= 0x00ffffffu; 435 temp |= 0x04 << 24; 436 OUTREG(MPP_TB_CONFIG, temp); 437 temp = INREG(MPP_TB_CONFIG); 438 439 rom = pci_map_rom(dev, &rom_size); 440 if (!rom) { 441 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n", 442 pci_name(rinfo->pdev)); 443 return -ENOMEM; 444 } 445 446 rinfo->bios_seg = rom; 447 448 /* Very simple test to make sure it appeared */ 449 if (BIOS_IN16(0) != 0xaa55) { 450 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x " 451 "should be 0xaa55\n", 452 pci_name(rinfo->pdev), BIOS_IN16(0)); 453 goto failed; 454 } 455 /* Look for the PCI data to check the ROM type */ 456 dptr = BIOS_IN16(0x18); 457 458 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM 459 * for now, until I've verified this works everywhere. The goal here is more 460 * to phase out Open Firmware images. 461 * 462 * Currently, we only look at the first PCI data, we could iteratre and deal with 463 * them all, and we should use fb_bios_start relative to start of image and not 464 * relative start of ROM, but so far, I never found a dual-image ATI card 465 * 466 * typedef struct { 467 * u32 signature; + 0x00 468 * u16 vendor; + 0x04 469 * u16 device; + 0x06 470 * u16 reserved_1; + 0x08 471 * u16 dlen; + 0x0a 472 * u8 drevision; + 0x0c 473 * u8 class_hi; + 0x0d 474 * u16 class_lo; + 0x0e 475 * u16 ilen; + 0x10 476 * u16 irevision; + 0x12 477 * u8 type; + 0x14 478 * u8 indicator; + 0x15 479 * u16 reserved_2; + 0x16 480 * } pci_data_t; 481 */ 482 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 483 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM" 484 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr)); 485 goto anyway; 486 } 487 rom_type = BIOS_IN8(dptr + 0x14); 488 switch(rom_type) { 489 case 0: 490 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n"); 491 break; 492 case 1: 493 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n"); 494 goto failed; 495 case 2: 496 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n"); 497 goto failed; 498 default: 499 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type); 500 goto failed; 501 } 502 anyway: 503 /* Locate the flat panel infos, do some sanity checking !!! */ 504 rinfo->fp_bios_start = BIOS_IN16(0x48); 505 return 0; 506 507 failed: 508 rinfo->bios_seg = NULL; 509 radeon_unmap_ROM(rinfo, dev); 510 return -ENXIO; 511 } 512 513 #ifdef CONFIG_X86 514 static int radeon_find_mem_vbios(struct radeonfb_info *rinfo) 515 { 516 /* I simplified this code as we used to miss the signatures in 517 * a lot of case. It's now closer to XFree, we just don't check 518 * for signatures at all... Something better will have to be done 519 * if we end up having conflicts 520 */ 521 u32 segstart; 522 void __iomem *rom_base = NULL; 523 524 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { 525 rom_base = ioremap(segstart, 0x10000); 526 if (rom_base == NULL) 527 return -ENOMEM; 528 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) 529 break; 530 iounmap(rom_base); 531 rom_base = NULL; 532 } 533 if (rom_base == NULL) 534 return -ENXIO; 535 536 /* Locate the flat panel infos, do some sanity checking !!! */ 537 rinfo->bios_seg = rom_base; 538 rinfo->fp_bios_start = BIOS_IN16(0x48); 539 540 return 0; 541 } 542 #endif 543 544 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) 545 /* 546 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device 547 * tree. Hopefully, ATI OF driver is kind enough to fill these 548 */ 549 static int radeon_read_xtal_OF(struct radeonfb_info *rinfo) 550 { 551 struct device_node *dp = rinfo->of_node; 552 const u32 *val; 553 554 if (dp == NULL) 555 return -ENODEV; 556 val = of_get_property(dp, "ATY,RefCLK", NULL); 557 if (!val || !*val) { 558 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n"); 559 return -EINVAL; 560 } 561 562 rinfo->pll.ref_clk = (*val) / 10; 563 564 val = of_get_property(dp, "ATY,SCLK", NULL); 565 if (val && *val) 566 rinfo->pll.sclk = (*val) / 10; 567 568 val = of_get_property(dp, "ATY,MCLK", NULL); 569 if (val && *val) 570 rinfo->pll.mclk = (*val) / 10; 571 572 return 0; 573 } 574 #endif /* CONFIG_PPC || CONFIG_SPARC */ 575 576 /* 577 * Read PLL infos from chip registers 578 */ 579 static int radeon_probe_pll_params(struct radeonfb_info *rinfo) 580 { 581 unsigned char ppll_div_sel; 582 unsigned Ns, Nm, M; 583 unsigned sclk, mclk, tmp, ref_div; 584 int hTotal, vTotal, num, denom, m, n; 585 unsigned long long hz, vclk; 586 long xtal; 587 struct timeval start_tv, stop_tv; 588 long total_secs, total_usecs; 589 int i; 590 591 /* Ugh, we cut interrupts, bad bad bad, but we want some precision 592 * here, so... --BenH 593 */ 594 595 /* Flush PCI buffers ? */ 596 tmp = INREG16(DEVICE_ID); 597 598 local_irq_disable(); 599 600 for(i=0; i<1000000; i++) 601 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) 602 break; 603 604 do_gettimeofday(&start_tv); 605 606 for(i=0; i<1000000; i++) 607 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0) 608 break; 609 610 for(i=0; i<1000000; i++) 611 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) 612 break; 613 614 do_gettimeofday(&stop_tv); 615 616 local_irq_enable(); 617 618 total_secs = stop_tv.tv_sec - start_tv.tv_sec; 619 if (total_secs > 10) 620 return -1; 621 total_usecs = stop_tv.tv_usec - start_tv.tv_usec; 622 total_usecs += total_secs * 1000000; 623 if (total_usecs < 0) 624 total_usecs = -total_usecs; 625 hz = 1000000/total_usecs; 626 627 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8; 628 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1); 629 vclk = (long long)hTotal * (long long)vTotal * hz; 630 631 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) { 632 case 0: 633 default: 634 num = 1; 635 denom = 1; 636 break; 637 case 1: 638 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff); 639 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); 640 num = 2*n; 641 denom = 2*m; 642 break; 643 case 2: 644 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff); 645 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); 646 num = 2*n; 647 denom = 2*m; 648 break; 649 } 650 651 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3; 652 radeon_pll_errata_after_index(rinfo); 653 654 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff); 655 m = (INPLL(PPLL_REF_DIV) & 0x3ff); 656 657 num *= n; 658 denom *= m; 659 660 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { 661 case 1: 662 denom *= 2; 663 break; 664 case 2: 665 denom *= 4; 666 break; 667 case 3: 668 denom *= 8; 669 break; 670 case 4: 671 denom *= 3; 672 break; 673 case 6: 674 denom *= 6; 675 break; 676 case 7: 677 denom *= 12; 678 break; 679 } 680 681 vclk *= denom; 682 do_div(vclk, 1000 * num); 683 xtal = vclk; 684 685 if ((xtal > 26900) && (xtal < 27100)) 686 xtal = 2700; 687 else if ((xtal > 14200) && (xtal < 14400)) 688 xtal = 1432; 689 else if ((xtal > 29400) && (xtal < 29600)) 690 xtal = 2950; 691 else { 692 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal); 693 return -1; 694 } 695 696 tmp = INPLL(M_SPLL_REF_FB_DIV); 697 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; 698 699 Ns = (tmp & 0xff0000) >> 16; 700 Nm = (tmp & 0xff00) >> 8; 701 M = (tmp & 0xff); 702 sclk = round_div((2 * Ns * xtal), (2 * M)); 703 mclk = round_div((2 * Nm * xtal), (2 * M)); 704 705 /* we're done, hopefully these are sane values */ 706 rinfo->pll.ref_clk = xtal; 707 rinfo->pll.ref_div = ref_div; 708 rinfo->pll.sclk = sclk; 709 rinfo->pll.mclk = mclk; 710 711 return 0; 712 } 713 714 /* 715 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...) 716 */ 717 static void radeon_get_pllinfo(struct radeonfb_info *rinfo) 718 { 719 /* 720 * In the case nothing works, these are defaults; they are mostly 721 * incomplete, however. It does provide ppll_max and _min values 722 * even for most other methods, however. 723 */ 724 switch (rinfo->chipset) { 725 case PCI_DEVICE_ID_ATI_RADEON_QW: 726 case PCI_DEVICE_ID_ATI_RADEON_QX: 727 rinfo->pll.ppll_max = 35000; 728 rinfo->pll.ppll_min = 12000; 729 rinfo->pll.mclk = 23000; 730 rinfo->pll.sclk = 23000; 731 rinfo->pll.ref_clk = 2700; 732 break; 733 case PCI_DEVICE_ID_ATI_RADEON_QL: 734 case PCI_DEVICE_ID_ATI_RADEON_QN: 735 case PCI_DEVICE_ID_ATI_RADEON_QO: 736 case PCI_DEVICE_ID_ATI_RADEON_Ql: 737 case PCI_DEVICE_ID_ATI_RADEON_BB: 738 rinfo->pll.ppll_max = 35000; 739 rinfo->pll.ppll_min = 12000; 740 rinfo->pll.mclk = 27500; 741 rinfo->pll.sclk = 27500; 742 rinfo->pll.ref_clk = 2700; 743 break; 744 case PCI_DEVICE_ID_ATI_RADEON_Id: 745 case PCI_DEVICE_ID_ATI_RADEON_Ie: 746 case PCI_DEVICE_ID_ATI_RADEON_If: 747 case PCI_DEVICE_ID_ATI_RADEON_Ig: 748 rinfo->pll.ppll_max = 35000; 749 rinfo->pll.ppll_min = 12000; 750 rinfo->pll.mclk = 25000; 751 rinfo->pll.sclk = 25000; 752 rinfo->pll.ref_clk = 2700; 753 break; 754 case PCI_DEVICE_ID_ATI_RADEON_ND: 755 case PCI_DEVICE_ID_ATI_RADEON_NE: 756 case PCI_DEVICE_ID_ATI_RADEON_NF: 757 case PCI_DEVICE_ID_ATI_RADEON_NG: 758 rinfo->pll.ppll_max = 40000; 759 rinfo->pll.ppll_min = 20000; 760 rinfo->pll.mclk = 27000; 761 rinfo->pll.sclk = 27000; 762 rinfo->pll.ref_clk = 2700; 763 break; 764 case PCI_DEVICE_ID_ATI_RADEON_QD: 765 case PCI_DEVICE_ID_ATI_RADEON_QE: 766 case PCI_DEVICE_ID_ATI_RADEON_QF: 767 case PCI_DEVICE_ID_ATI_RADEON_QG: 768 default: 769 rinfo->pll.ppll_max = 35000; 770 rinfo->pll.ppll_min = 12000; 771 rinfo->pll.mclk = 16600; 772 rinfo->pll.sclk = 16600; 773 rinfo->pll.ref_clk = 2700; 774 break; 775 } 776 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; 777 778 779 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) 780 /* 781 * Retrieve PLL infos from Open Firmware first 782 */ 783 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) { 784 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n"); 785 goto found; 786 } 787 #endif /* CONFIG_PPC || CONFIG_SPARC */ 788 789 /* 790 * Check out if we have an X86 which gave us some PLL informations 791 * and if yes, retrieve them 792 */ 793 if (!force_measure_pll && rinfo->bios_seg) { 794 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); 795 796 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); 797 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a); 798 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); 799 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); 800 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); 801 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); 802 803 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n"); 804 goto found; 805 } 806 807 /* 808 * We didn't get PLL parameters from either OF or BIOS, we try to 809 * probe them 810 */ 811 if (radeon_probe_pll_params(rinfo) == 0) { 812 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n"); 813 goto found; 814 } 815 816 /* 817 * Fall back to already-set defaults... 818 */ 819 printk(KERN_INFO "radeonfb: Used default PLL infos\n"); 820 821 found: 822 /* 823 * Some methods fail to retrieve SCLK and MCLK values, we apply default 824 * settings in this case (200Mhz). If that really happens often, we 825 * could fetch from registers instead... 826 */ 827 if (rinfo->pll.mclk == 0) 828 rinfo->pll.mclk = 20000; 829 if (rinfo->pll.sclk == 0) 830 rinfo->pll.sclk = 20000; 831 832 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n", 833 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100, 834 rinfo->pll.ref_div, 835 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100, 836 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100); 837 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max); 838 } 839 840 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info) 841 { 842 struct radeonfb_info *rinfo = info->par; 843 struct fb_var_screeninfo v; 844 int nom, den; 845 unsigned int pitch; 846 847 if (radeon_match_mode(rinfo, &v, var)) 848 return -EINVAL; 849 850 switch (v.bits_per_pixel) { 851 case 0 ... 8: 852 v.bits_per_pixel = 8; 853 break; 854 case 9 ... 16: 855 v.bits_per_pixel = 16; 856 break; 857 case 17 ... 24: 858 #if 0 /* Doesn't seem to work */ 859 v.bits_per_pixel = 24; 860 break; 861 #endif 862 return -EINVAL; 863 case 25 ... 32: 864 v.bits_per_pixel = 32; 865 break; 866 default: 867 return -EINVAL; 868 } 869 870 switch (var_to_depth(&v)) { 871 case 8: 872 nom = den = 1; 873 v.red.offset = v.green.offset = v.blue.offset = 0; 874 v.red.length = v.green.length = v.blue.length = 8; 875 v.transp.offset = v.transp.length = 0; 876 break; 877 case 15: 878 nom = 2; 879 den = 1; 880 v.red.offset = 10; 881 v.green.offset = 5; 882 v.blue.offset = 0; 883 v.red.length = v.green.length = v.blue.length = 5; 884 v.transp.offset = v.transp.length = 0; 885 break; 886 case 16: 887 nom = 2; 888 den = 1; 889 v.red.offset = 11; 890 v.green.offset = 5; 891 v.blue.offset = 0; 892 v.red.length = 5; 893 v.green.length = 6; 894 v.blue.length = 5; 895 v.transp.offset = v.transp.length = 0; 896 break; 897 case 24: 898 nom = 4; 899 den = 1; 900 v.red.offset = 16; 901 v.green.offset = 8; 902 v.blue.offset = 0; 903 v.red.length = v.blue.length = v.green.length = 8; 904 v.transp.offset = v.transp.length = 0; 905 break; 906 case 32: 907 nom = 4; 908 den = 1; 909 v.red.offset = 16; 910 v.green.offset = 8; 911 v.blue.offset = 0; 912 v.red.length = v.blue.length = v.green.length = 8; 913 v.transp.offset = 24; 914 v.transp.length = 8; 915 break; 916 default: 917 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n", 918 var->xres, var->yres, var->bits_per_pixel); 919 return -EINVAL; 920 } 921 922 if (v.yres_virtual < v.yres) 923 v.yres_virtual = v.yres; 924 if (v.xres_virtual < v.xres) 925 v.xres_virtual = v.xres; 926 927 928 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree 929 * with some panels, though I don't quite like this solution 930 */ 931 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) { 932 v.xres_virtual = v.xres_virtual & ~7ul; 933 } else { 934 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f) 935 & ~(0x3f)) >> 6; 936 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8); 937 } 938 939 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram) 940 return -EINVAL; 941 942 if (v.xres_virtual < v.xres) 943 v.xres = v.xres_virtual; 944 945 if (v.xoffset > v.xres_virtual - v.xres) 946 v.xoffset = v.xres_virtual - v.xres - 1; 947 948 if (v.yoffset > v.yres_virtual - v.yres) 949 v.yoffset = v.yres_virtual - v.yres - 1; 950 951 v.red.msb_right = v.green.msb_right = v.blue.msb_right = 952 v.transp.offset = v.transp.length = 953 v.transp.msb_right = 0; 954 955 memcpy(var, &v, sizeof(v)); 956 957 return 0; 958 } 959 960 961 static int radeonfb_pan_display (struct fb_var_screeninfo *var, 962 struct fb_info *info) 963 { 964 struct radeonfb_info *rinfo = info->par; 965 966 if ((var->xoffset + info->var.xres > info->var.xres_virtual) 967 || (var->yoffset + info->var.yres > info->var.yres_virtual)) 968 return -EINVAL; 969 970 if (rinfo->asleep) 971 return 0; 972 973 radeon_fifo_wait(2); 974 OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length + 975 var->xoffset * info->var.bits_per_pixel / 8) & ~7); 976 return 0; 977 } 978 979 980 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd, 981 unsigned long arg) 982 { 983 struct radeonfb_info *rinfo = info->par; 984 unsigned int tmp; 985 u32 value = 0; 986 int rc; 987 988 switch (cmd) { 989 /* 990 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's 991 * and do something better using 2nd CRTC instead of just hackish 992 * routing to second output 993 */ 994 case FBIO_RADEON_SET_MIRROR: 995 if (!rinfo->is_mobility) 996 return -EINVAL; 997 998 rc = get_user(value, (__u32 __user *)arg); 999 1000 if (rc) 1001 return rc; 1002 1003 radeon_fifo_wait(2); 1004 if (value & 0x01) { 1005 tmp = INREG(LVDS_GEN_CNTL); 1006 1007 tmp |= (LVDS_ON | LVDS_BLON); 1008 } else { 1009 tmp = INREG(LVDS_GEN_CNTL); 1010 1011 tmp &= ~(LVDS_ON | LVDS_BLON); 1012 } 1013 1014 OUTREG(LVDS_GEN_CNTL, tmp); 1015 1016 if (value & 0x02) { 1017 tmp = INREG(CRTC_EXT_CNTL); 1018 tmp |= CRTC_CRT_ON; 1019 1020 mirror = 1; 1021 } else { 1022 tmp = INREG(CRTC_EXT_CNTL); 1023 tmp &= ~CRTC_CRT_ON; 1024 1025 mirror = 0; 1026 } 1027 1028 OUTREG(CRTC_EXT_CNTL, tmp); 1029 1030 return 0; 1031 case FBIO_RADEON_GET_MIRROR: 1032 if (!rinfo->is_mobility) 1033 return -EINVAL; 1034 1035 tmp = INREG(LVDS_GEN_CNTL); 1036 if ((LVDS_ON | LVDS_BLON) & tmp) 1037 value |= 0x01; 1038 1039 tmp = INREG(CRTC_EXT_CNTL); 1040 if (CRTC_CRT_ON & tmp) 1041 value |= 0x02; 1042 1043 return put_user(value, (__u32 __user *)arg); 1044 default: 1045 return -EINVAL; 1046 } 1047 1048 return -EINVAL; 1049 } 1050 1051 1052 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch) 1053 { 1054 u32 val; 1055 u32 tmp_pix_clks; 1056 int unblank = 0; 1057 1058 if (rinfo->lock_blank) 1059 return 0; 1060 1061 radeon_engine_idle(); 1062 1063 val = INREG(CRTC_EXT_CNTL); 1064 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | 1065 CRTC_VSYNC_DIS); 1066 switch (blank) { 1067 case FB_BLANK_VSYNC_SUSPEND: 1068 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS); 1069 break; 1070 case FB_BLANK_HSYNC_SUSPEND: 1071 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS); 1072 break; 1073 case FB_BLANK_POWERDOWN: 1074 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | 1075 CRTC_HSYNC_DIS); 1076 break; 1077 case FB_BLANK_NORMAL: 1078 val |= CRTC_DISPLAY_DIS; 1079 break; 1080 case FB_BLANK_UNBLANK: 1081 default: 1082 unblank = 1; 1083 } 1084 OUTREG(CRTC_EXT_CNTL, val); 1085 1086 1087 switch (rinfo->mon1_type) { 1088 case MT_DFP: 1089 if (unblank) 1090 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN), 1091 ~(FP_FPON | FP_TMDS_EN)); 1092 else { 1093 if (mode_switch || blank == FB_BLANK_NORMAL) 1094 break; 1095 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN)); 1096 } 1097 break; 1098 case MT_LCD: 1099 del_timer_sync(&rinfo->lvds_timer); 1100 val = INREG(LVDS_GEN_CNTL); 1101 if (unblank) { 1102 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON 1103 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl 1104 & (LVDS_DIGON | LVDS_BL_MOD_EN)); 1105 if ((val ^ target_val) == LVDS_DISPLAY_DIS) 1106 OUTREG(LVDS_GEN_CNTL, target_val); 1107 else if ((val ^ target_val) != 0) { 1108 OUTREG(LVDS_GEN_CNTL, target_val 1109 & ~(LVDS_ON | LVDS_BL_MOD_EN)); 1110 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; 1111 rinfo->init_state.lvds_gen_cntl |= 1112 target_val & LVDS_STATE_MASK; 1113 if (mode_switch) { 1114 radeon_msleep(rinfo->panel_info.pwr_delay); 1115 OUTREG(LVDS_GEN_CNTL, target_val); 1116 } 1117 else { 1118 rinfo->pending_lvds_gen_cntl = target_val; 1119 mod_timer(&rinfo->lvds_timer, 1120 jiffies + 1121 msecs_to_jiffies(rinfo->panel_info.pwr_delay)); 1122 } 1123 } 1124 } else { 1125 val |= LVDS_DISPLAY_DIS; 1126 OUTREG(LVDS_GEN_CNTL, val); 1127 1128 /* We don't do a full switch-off on a simple mode switch */ 1129 if (mode_switch || blank == FB_BLANK_NORMAL) 1130 break; 1131 1132 /* Asic bug, when turning off LVDS_ON, we have to make sure 1133 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off 1134 */ 1135 tmp_pix_clks = INPLL(PIXCLKS_CNTL); 1136 if (rinfo->is_mobility || rinfo->is_IGP) 1137 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb); 1138 val &= ~(LVDS_BL_MOD_EN); 1139 OUTREG(LVDS_GEN_CNTL, val); 1140 udelay(100); 1141 val &= ~(LVDS_ON | LVDS_EN); 1142 OUTREG(LVDS_GEN_CNTL, val); 1143 val &= ~LVDS_DIGON; 1144 rinfo->pending_lvds_gen_cntl = val; 1145 mod_timer(&rinfo->lvds_timer, 1146 jiffies + 1147 msecs_to_jiffies(rinfo->panel_info.pwr_delay)); 1148 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; 1149 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK; 1150 if (rinfo->is_mobility || rinfo->is_IGP) 1151 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks); 1152 } 1153 break; 1154 case MT_CRT: 1155 // todo: powerdown DAC 1156 default: 1157 break; 1158 } 1159 1160 return 0; 1161 } 1162 1163 static int radeonfb_blank (int blank, struct fb_info *info) 1164 { 1165 struct radeonfb_info *rinfo = info->par; 1166 1167 if (rinfo->asleep) 1168 return 0; 1169 1170 return radeon_screen_blank(rinfo, blank, 0); 1171 } 1172 1173 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green, 1174 unsigned blue, unsigned transp, 1175 struct radeonfb_info *rinfo) 1176 { 1177 u32 pindex; 1178 unsigned int i; 1179 1180 1181 if (regno > 255) 1182 return -EINVAL; 1183 1184 red >>= 8; 1185 green >>= 8; 1186 blue >>= 8; 1187 rinfo->palette[regno].red = red; 1188 rinfo->palette[regno].green = green; 1189 rinfo->palette[regno].blue = blue; 1190 1191 /* default */ 1192 pindex = regno; 1193 1194 if (!rinfo->asleep) { 1195 radeon_fifo_wait(9); 1196 1197 if (rinfo->bpp == 16) { 1198 pindex = regno * 8; 1199 1200 if (rinfo->depth == 16 && regno > 63) 1201 return -EINVAL; 1202 if (rinfo->depth == 15 && regno > 31) 1203 return -EINVAL; 1204 1205 /* For 565, the green component is mixed one order 1206 * below 1207 */ 1208 if (rinfo->depth == 16) { 1209 OUTREG(PALETTE_INDEX, pindex>>1); 1210 OUTREG(PALETTE_DATA, 1211 (rinfo->palette[regno>>1].red << 16) | 1212 (green << 8) | 1213 (rinfo->palette[regno>>1].blue)); 1214 green = rinfo->palette[regno<<1].green; 1215 } 1216 } 1217 1218 if (rinfo->depth != 16 || regno < 32) { 1219 OUTREG(PALETTE_INDEX, pindex); 1220 OUTREG(PALETTE_DATA, (red << 16) | 1221 (green << 8) | blue); 1222 } 1223 } 1224 if (regno < 16) { 1225 u32 *pal = rinfo->info->pseudo_palette; 1226 switch (rinfo->depth) { 1227 case 15: 1228 pal[regno] = (regno << 10) | (regno << 5) | regno; 1229 break; 1230 case 16: 1231 pal[regno] = (regno << 11) | (regno << 5) | regno; 1232 break; 1233 case 24: 1234 pal[regno] = (regno << 16) | (regno << 8) | regno; 1235 break; 1236 case 32: 1237 i = (regno << 8) | regno; 1238 pal[regno] = (i << 16) | i; 1239 break; 1240 } 1241 } 1242 return 0; 1243 } 1244 1245 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green, 1246 unsigned blue, unsigned transp, 1247 struct fb_info *info) 1248 { 1249 struct radeonfb_info *rinfo = info->par; 1250 u32 dac_cntl2, vclk_cntl = 0; 1251 int rc; 1252 1253 if (!rinfo->asleep) { 1254 if (rinfo->is_mobility) { 1255 vclk_cntl = INPLL(VCLK_ECP_CNTL); 1256 OUTPLL(VCLK_ECP_CNTL, 1257 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb); 1258 } 1259 1260 /* Make sure we are on first palette */ 1261 if (rinfo->has_CRTC2) { 1262 dac_cntl2 = INREG(DAC_CNTL2); 1263 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL; 1264 OUTREG(DAC_CNTL2, dac_cntl2); 1265 } 1266 } 1267 1268 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo); 1269 1270 if (!rinfo->asleep && rinfo->is_mobility) 1271 OUTPLL(VCLK_ECP_CNTL, vclk_cntl); 1272 1273 return rc; 1274 } 1275 1276 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info) 1277 { 1278 struct radeonfb_info *rinfo = info->par; 1279 u16 *red, *green, *blue, *transp; 1280 u32 dac_cntl2, vclk_cntl = 0; 1281 int i, start, rc = 0; 1282 1283 if (!rinfo->asleep) { 1284 if (rinfo->is_mobility) { 1285 vclk_cntl = INPLL(VCLK_ECP_CNTL); 1286 OUTPLL(VCLK_ECP_CNTL, 1287 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb); 1288 } 1289 1290 /* Make sure we are on first palette */ 1291 if (rinfo->has_CRTC2) { 1292 dac_cntl2 = INREG(DAC_CNTL2); 1293 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL; 1294 OUTREG(DAC_CNTL2, dac_cntl2); 1295 } 1296 } 1297 1298 red = cmap->red; 1299 green = cmap->green; 1300 blue = cmap->blue; 1301 transp = cmap->transp; 1302 start = cmap->start; 1303 1304 for (i = 0; i < cmap->len; i++) { 1305 u_int hred, hgreen, hblue, htransp = 0xffff; 1306 1307 hred = *red++; 1308 hgreen = *green++; 1309 hblue = *blue++; 1310 if (transp) 1311 htransp = *transp++; 1312 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp, 1313 rinfo); 1314 if (rc) 1315 break; 1316 } 1317 1318 if (!rinfo->asleep && rinfo->is_mobility) 1319 OUTPLL(VCLK_ECP_CNTL, vclk_cntl); 1320 1321 return rc; 1322 } 1323 1324 static void radeon_save_state (struct radeonfb_info *rinfo, 1325 struct radeon_regs *save) 1326 { 1327 /* CRTC regs */ 1328 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); 1329 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); 1330 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); 1331 save->dac_cntl = INREG(DAC_CNTL); 1332 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); 1333 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID); 1334 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP); 1335 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID); 1336 save->crtc_pitch = INREG(CRTC_PITCH); 1337 save->surface_cntl = INREG(SURFACE_CNTL); 1338 1339 /* FP regs */ 1340 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP); 1341 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP); 1342 save->fp_gen_cntl = INREG(FP_GEN_CNTL); 1343 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID); 1344 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH); 1345 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID); 1346 save->fp_vert_stretch = INREG(FP_VERT_STRETCH); 1347 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); 1348 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); 1349 save->tmds_crc = INREG(TMDS_CRC); 1350 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); 1351 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL); 1352 1353 /* PLL regs */ 1354 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; 1355 radeon_pll_errata_after_index(rinfo); 1356 save->ppll_div_3 = INPLL(PPLL_DIV_3); 1357 save->ppll_ref_div = INPLL(PPLL_REF_DIV); 1358 } 1359 1360 1361 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) 1362 { 1363 int i; 1364 1365 radeon_fifo_wait(20); 1366 1367 /* Workaround from XFree */ 1368 if (rinfo->is_mobility) { 1369 /* A temporal workaround for the occasional blanking on certain laptop 1370 * panels. This appears to related to the PLL divider registers 1371 * (fail to lock?). It occurs even when all dividers are the same 1372 * with their old settings. In this case we really don't need to 1373 * fiddle with PLL registers. By doing this we can avoid the blanking 1374 * problem with some panels. 1375 */ 1376 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && 1377 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & 1378 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { 1379 /* We still have to force a switch to selected PPLL div thanks to 1380 * an XFree86 driver bug which will switch it away in some cases 1381 * even when using UseFDev */ 1382 OUTREGP(CLOCK_CNTL_INDEX, 1383 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 1384 ~PPLL_DIV_SEL_MASK); 1385 radeon_pll_errata_after_index(rinfo); 1386 radeon_pll_errata_after_data(rinfo); 1387 return; 1388 } 1389 } 1390 1391 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ 1392 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); 1393 1394 /* Reset PPLL & enable atomic update */ 1395 OUTPLLP(PPLL_CNTL, 1396 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, 1397 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 1398 1399 /* Switch to selected PPLL divider */ 1400 OUTREGP(CLOCK_CNTL_INDEX, 1401 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 1402 ~PPLL_DIV_SEL_MASK); 1403 radeon_pll_errata_after_index(rinfo); 1404 radeon_pll_errata_after_data(rinfo); 1405 1406 /* Set PPLL ref. div */ 1407 if (IS_R300_VARIANT(rinfo) || 1408 rinfo->family == CHIP_FAMILY_RS300 || 1409 rinfo->family == CHIP_FAMILY_RS400 || 1410 rinfo->family == CHIP_FAMILY_RS480) { 1411 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 1412 /* When restoring console mode, use saved PPLL_REF_DIV 1413 * setting. 1414 */ 1415 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); 1416 } else { 1417 /* R300 uses ref_div_acc field as real ref divider */ 1418 OUTPLLP(PPLL_REF_DIV, 1419 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 1420 ~R300_PPLL_REF_DIV_ACC_MASK); 1421 } 1422 } else 1423 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); 1424 1425 /* Set PPLL divider 3 & post divider*/ 1426 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); 1427 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); 1428 1429 /* Write update */ 1430 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) 1431 ; 1432 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); 1433 1434 /* Wait read update complete */ 1435 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 1436 the cause yet, but this workaround will mask the problem for now. 1437 Other chips usually will pass at the very first test, so the 1438 workaround shouldn't have any effect on them. */ 1439 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) 1440 ; 1441 1442 OUTPLL(HTOTAL_CNTL, 0); 1443 1444 /* Clear reset & atomic update */ 1445 OUTPLLP(PPLL_CNTL, 0, 1446 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 1447 1448 /* We may want some locking ... oh well */ 1449 radeon_msleep(5); 1450 1451 /* Switch back VCLK source to PPLL */ 1452 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); 1453 } 1454 1455 /* 1456 * Timer function for delayed LVDS panel power up/down 1457 */ 1458 static void radeon_lvds_timer_func(unsigned long data) 1459 { 1460 struct radeonfb_info *rinfo = (struct radeonfb_info *)data; 1461 1462 radeon_engine_idle(); 1463 1464 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); 1465 } 1466 1467 /* 1468 * Apply a video mode. This will apply the whole register set, including 1469 * the PLL registers, to the card 1470 */ 1471 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, 1472 int regs_only) 1473 { 1474 int i; 1475 int primary_mon = PRIMARY_MONITOR(rinfo); 1476 1477 if (nomodeset) 1478 return; 1479 1480 if (!regs_only) 1481 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); 1482 1483 radeon_fifo_wait(31); 1484 for (i=0; i<10; i++) 1485 OUTREG(common_regs[i].reg, common_regs[i].val); 1486 1487 /* Apply surface registers */ 1488 for (i=0; i<8; i++) { 1489 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]); 1490 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]); 1491 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]); 1492 } 1493 1494 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); 1495 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 1496 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 1497 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl); 1498 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); 1499 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); 1500 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); 1501 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); 1502 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); 1503 OUTREG(CRTC_OFFSET, 0); 1504 OUTREG(CRTC_OFFSET_CNTL, 0); 1505 OUTREG(CRTC_PITCH, mode->crtc_pitch); 1506 OUTREG(SURFACE_CNTL, mode->surface_cntl); 1507 1508 radeon_write_pll_regs(rinfo, mode); 1509 1510 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1511 radeon_fifo_wait(10); 1512 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); 1513 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); 1514 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); 1515 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid); 1516 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch); 1517 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); 1518 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); 1519 OUTREG(TMDS_CRC, mode->tmds_crc); 1520 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); 1521 } 1522 1523 if (!regs_only) 1524 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); 1525 1526 radeon_fifo_wait(2); 1527 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); 1528 1529 return; 1530 } 1531 1532 /* 1533 * Calculate the PLL values for a given mode 1534 */ 1535 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs, 1536 unsigned long freq) 1537 { 1538 const struct { 1539 int divider; 1540 int bitvalue; 1541 } *post_div, 1542 post_divs[] = { 1543 { 1, 0 }, 1544 { 2, 1 }, 1545 { 4, 2 }, 1546 { 8, 3 }, 1547 { 3, 4 }, 1548 { 16, 5 }, 1549 { 6, 6 }, 1550 { 12, 7 }, 1551 { 0, 0 }, 1552 }; 1553 int fb_div, pll_output_freq = 0; 1554 int uses_dvo = 0; 1555 1556 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm 1557 * not sure which model starts having FP2_GEN_CNTL, I assume anything more 1558 * recent than an r(v)100... 1559 */ 1560 #if 1 1561 /* XXX I had reports of flicker happening with the cinema display 1562 * on TMDS1 that seem to be fixed if I also forbit odd dividers in 1563 * this case. This could just be a bandwidth calculation issue, I 1564 * haven't implemented the bandwidth code yet, but in the meantime, 1565 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects, 1566 * I haven't seen a case were were absolutely needed an odd PLL 1567 * divider. I'll find a better fix once I have more infos on the 1568 * real cause of the problem. 1569 */ 1570 while (rinfo->has_CRTC2) { 1571 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL); 1572 u32 disp_output_cntl; 1573 int source; 1574 1575 /* FP2 path not enabled */ 1576 if ((fp2_gen_cntl & FP2_ON) == 0) 1577 break; 1578 /* Not all chip revs have the same format for this register, 1579 * extract the source selection 1580 */ 1581 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) { 1582 source = (fp2_gen_cntl >> 10) & 0x3; 1583 /* sourced from transform unit, check for transform unit 1584 * own source 1585 */ 1586 if (source == 3) { 1587 disp_output_cntl = INREG(DISP_OUTPUT_CNTL); 1588 source = (disp_output_cntl >> 12) & 0x3; 1589 } 1590 } else 1591 source = (fp2_gen_cntl >> 13) & 0x1; 1592 /* sourced from CRTC2 -> exit */ 1593 if (source == 1) 1594 break; 1595 1596 /* so we end up on CRTC1, let's set uses_dvo to 1 now */ 1597 uses_dvo = 1; 1598 break; 1599 } 1600 #else 1601 uses_dvo = 1; 1602 #endif 1603 if (freq > rinfo->pll.ppll_max) 1604 freq = rinfo->pll.ppll_max; 1605 if (freq*12 < rinfo->pll.ppll_min) 1606 freq = rinfo->pll.ppll_min / 12; 1607 pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n", 1608 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max); 1609 1610 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 1611 pll_output_freq = post_div->divider * freq; 1612 /* If we output to the DVO port (external TMDS), we don't allow an 1613 * odd PLL divider as those aren't supported on this path 1614 */ 1615 if (uses_dvo && (post_div->divider & 1)) 1616 continue; 1617 if (pll_output_freq >= rinfo->pll.ppll_min && 1618 pll_output_freq <= rinfo->pll.ppll_max) 1619 break; 1620 } 1621 1622 /* If we fall through the bottom, try the "default value" 1623 given by the terminal post_div->bitvalue */ 1624 if ( !post_div->divider ) { 1625 post_div = &post_divs[post_div->bitvalue]; 1626 pll_output_freq = post_div->divider * freq; 1627 } 1628 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n", 1629 rinfo->pll.ref_div, rinfo->pll.ref_clk, 1630 pll_output_freq); 1631 1632 /* If we fall through the bottom, try the "default value" 1633 given by the terminal post_div->bitvalue */ 1634 if ( !post_div->divider ) { 1635 post_div = &post_divs[post_div->bitvalue]; 1636 pll_output_freq = post_div->divider * freq; 1637 } 1638 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n", 1639 rinfo->pll.ref_div, rinfo->pll.ref_clk, 1640 pll_output_freq); 1641 1642 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, 1643 rinfo->pll.ref_clk); 1644 regs->ppll_ref_div = rinfo->pll.ref_div; 1645 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); 1646 1647 pr_debug("post div = 0x%x\n", post_div->bitvalue); 1648 pr_debug("fb_div = 0x%x\n", fb_div); 1649 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3); 1650 } 1651 1652 static int radeonfb_set_par(struct fb_info *info) 1653 { 1654 struct radeonfb_info *rinfo = info->par; 1655 struct fb_var_screeninfo *mode = &info->var; 1656 struct radeon_regs *newmode; 1657 int hTotal, vTotal, hSyncStart, hSyncEnd, 1658 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync; 1659 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5}; 1660 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5}; 1661 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock; 1662 int i, freq; 1663 int format = 0; 1664 int nopllcalc = 0; 1665 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid; 1666 int primary_mon = PRIMARY_MONITOR(rinfo); 1667 int depth = var_to_depth(mode); 1668 int use_rmx = 0; 1669 1670 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL); 1671 if (!newmode) 1672 return -ENOMEM; 1673 1674 /* We always want engine to be idle on a mode switch, even 1675 * if we won't actually change the mode 1676 */ 1677 radeon_engine_idle(); 1678 1679 hSyncStart = mode->xres + mode->right_margin; 1680 hSyncEnd = hSyncStart + mode->hsync_len; 1681 hTotal = hSyncEnd + mode->left_margin; 1682 1683 vSyncStart = mode->yres + mode->lower_margin; 1684 vSyncEnd = vSyncStart + mode->vsync_len; 1685 vTotal = vSyncEnd + mode->upper_margin; 1686 pixClock = mode->pixclock; 1687 1688 sync = mode->sync; 1689 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 1690 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 1691 1692 if (primary_mon == MT_DFP || primary_mon == MT_LCD) { 1693 if (rinfo->panel_info.xres < mode->xres) 1694 mode->xres = rinfo->panel_info.xres; 1695 if (rinfo->panel_info.yres < mode->yres) 1696 mode->yres = rinfo->panel_info.yres; 1697 1698 hTotal = mode->xres + rinfo->panel_info.hblank; 1699 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus; 1700 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width; 1701 1702 vTotal = mode->yres + rinfo->panel_info.vblank; 1703 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus; 1704 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width; 1705 1706 h_sync_pol = !rinfo->panel_info.hAct_high; 1707 v_sync_pol = !rinfo->panel_info.vAct_high; 1708 1709 pixClock = 100000000 / rinfo->panel_info.clock; 1710 1711 if (rinfo->panel_info.use_bios_dividers) { 1712 nopllcalc = 1; 1713 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider | 1714 (rinfo->panel_info.post_divider << 16); 1715 newmode->ppll_ref_div = rinfo->panel_info.ref_divider; 1716 } 1717 } 1718 dotClock = 1000000000 / pixClock; 1719 freq = dotClock / 10; /* x100 */ 1720 1721 pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n", 1722 hSyncStart, hSyncEnd, hTotal); 1723 pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n", 1724 vSyncStart, vSyncEnd, vTotal); 1725 1726 hsync_wid = (hSyncEnd - hSyncStart) / 8; 1727 vsync_wid = vSyncEnd - vSyncStart; 1728 if (hsync_wid == 0) 1729 hsync_wid = 1; 1730 else if (hsync_wid > 0x3f) /* max */ 1731 hsync_wid = 0x3f; 1732 1733 if (vsync_wid == 0) 1734 vsync_wid = 1; 1735 else if (vsync_wid > 0x1f) /* max */ 1736 vsync_wid = 0x1f; 1737 1738 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 1739 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 1740 1741 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; 1742 1743 format = radeon_get_dstbpp(depth); 1744 bytpp = mode->bits_per_pixel >> 3; 1745 1746 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) 1747 hsync_fudge = hsync_fudge_fp[format-1]; 1748 else 1749 hsync_fudge = hsync_adj_tab[format-1]; 1750 1751 hsync_start = hSyncStart - 8 + hsync_fudge; 1752 1753 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | 1754 (format << 8); 1755 1756 /* Clear auto-center etc... */ 1757 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl; 1758 newmode->crtc_more_cntl &= 0xfffffff0; 1759 1760 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1761 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN; 1762 if (mirror) 1763 newmode->crtc_ext_cntl |= CRTC_CRT_ON; 1764 1765 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN | 1766 CRTC_INTERLACE_EN); 1767 } else { 1768 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | 1769 CRTC_CRT_ON; 1770 } 1771 1772 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN | 1773 DAC_8BIT_EN; 1774 1775 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) | 1776 (((mode->xres / 8) - 1) << 16)); 1777 1778 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) | 1779 (hsync_wid << 16) | (h_sync_pol << 23)); 1780 1781 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | 1782 ((mode->yres - 1) << 16); 1783 1784 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) | 1785 (vsync_wid << 16) | (v_sync_pol << 23)); 1786 1787 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { 1788 /* We first calculate the engine pitch */ 1789 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f) 1790 & ~(0x3f)) >> 6; 1791 1792 /* Then, re-multiply it to get the CRTC pitch */ 1793 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8); 1794 } else 1795 newmode->crtc_pitch = (mode->xres_virtual >> 3); 1796 1797 newmode->crtc_pitch |= (newmode->crtc_pitch << 16); 1798 1799 /* 1800 * It looks like recent chips have a problem with SURFACE_CNTL, 1801 * setting SURF_TRANSLATION_DIS completely disables the 1802 * swapper as well, so we leave it unset now. 1803 */ 1804 newmode->surface_cntl = 0; 1805 1806 #if defined(__BIG_ENDIAN) 1807 1808 /* Setup swapping on both apertures, though we currently 1809 * only use aperture 0, enabling swapper on aperture 1 1810 * won't harm 1811 */ 1812 switch (mode->bits_per_pixel) { 1813 case 16: 1814 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP; 1815 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP; 1816 break; 1817 case 24: 1818 case 32: 1819 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP; 1820 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP; 1821 break; 1822 } 1823 #endif 1824 1825 /* Clear surface registers */ 1826 for (i=0; i<8; i++) { 1827 newmode->surf_lower_bound[i] = 0; 1828 newmode->surf_upper_bound[i] = 0x1f; 1829 newmode->surf_info[i] = 0; 1830 } 1831 1832 pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n", 1833 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid); 1834 pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n", 1835 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid); 1836 1837 rinfo->bpp = mode->bits_per_pixel; 1838 rinfo->depth = depth; 1839 1840 pr_debug("pixclock = %lu\n", (unsigned long)pixClock); 1841 pr_debug("freq = %lu\n", (unsigned long)freq); 1842 1843 /* We use PPLL_DIV_3 */ 1844 newmode->clk_cntl_index = 0x300; 1845 1846 /* Calculate PPLL value if necessary */ 1847 if (!nopllcalc) 1848 radeon_calc_pll_regs(rinfo, newmode, freq); 1849 1850 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl; 1851 1852 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1853 unsigned int hRatio, vRatio; 1854 1855 if (mode->xres > rinfo->panel_info.xres) 1856 mode->xres = rinfo->panel_info.xres; 1857 if (mode->yres > rinfo->panel_info.yres) 1858 mode->yres = rinfo->panel_info.yres; 1859 1860 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1) 1861 << HORZ_PANEL_SHIFT); 1862 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1) 1863 << VERT_PANEL_SHIFT); 1864 1865 if (mode->xres != rinfo->panel_info.xres) { 1866 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX, 1867 rinfo->panel_info.xres); 1868 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) | 1869 (newmode->fp_horz_stretch & 1870 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH | 1871 HORZ_AUTO_RATIO_INC))); 1872 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND | 1873 HORZ_STRETCH_ENABLE); 1874 use_rmx = 1; 1875 } 1876 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO; 1877 1878 if (mode->yres != rinfo->panel_info.yres) { 1879 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX, 1880 rinfo->panel_info.yres); 1881 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) | 1882 (newmode->fp_vert_stretch & 1883 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED))); 1884 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND | 1885 VERT_STRETCH_ENABLE); 1886 use_rmx = 1; 1887 } 1888 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN; 1889 1890 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32) 1891 ~(FP_SEL_CRTC2 | 1892 FP_RMX_HVSYNC_CONTROL_EN | 1893 FP_DFP_SYNC_SEL | 1894 FP_CRT_SYNC_SEL | 1895 FP_CRTC_LOCK_8DOT | 1896 FP_USE_SHADOW_EN | 1897 FP_CRTC_USE_SHADOW_VEND | 1898 FP_CRT_SYNC_ALT)); 1899 1900 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR | 1901 FP_CRTC_DONT_SHADOW_HEND | 1902 FP_PANEL_FORMAT); 1903 1904 if (IS_R300_VARIANT(rinfo) || 1905 (rinfo->family == CHIP_FAMILY_R200)) { 1906 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 1907 if (use_rmx) 1908 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; 1909 else 1910 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; 1911 } else 1912 newmode->fp_gen_cntl |= FP_SEL_CRTC1; 1913 1914 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl; 1915 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl; 1916 newmode->tmds_crc = rinfo->init_state.tmds_crc; 1917 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl; 1918 1919 if (primary_mon == MT_LCD) { 1920 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON); 1921 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN); 1922 } else { 1923 /* DFP */ 1924 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); 1925 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST); 1926 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */ 1927 if (IS_R300_VARIANT(rinfo) || 1928 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2) 1929 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN; 1930 else 1931 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN; 1932 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON; 1933 } 1934 1935 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) | 1936 (((mode->xres / 8) - 1) << 16)); 1937 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) | 1938 ((mode->yres - 1) << 16); 1939 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) | 1940 (hsync_wid << 16) | (h_sync_pol << 23)); 1941 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) | 1942 (vsync_wid << 16) | (v_sync_pol << 23)); 1943 } 1944 1945 /* do it! */ 1946 if (!rinfo->asleep) { 1947 memcpy(&rinfo->state, newmode, sizeof(*newmode)); 1948 radeon_write_mode (rinfo, newmode, 0); 1949 /* (re)initialize the engine */ 1950 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) 1951 radeonfb_engine_init (rinfo); 1952 } 1953 /* Update fix */ 1954 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) 1955 info->fix.line_length = rinfo->pitch*64; 1956 else 1957 info->fix.line_length = mode->xres_virtual 1958 * ((mode->bits_per_pixel + 1) / 8); 1959 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR 1960 : FB_VISUAL_DIRECTCOLOR; 1961 1962 #ifdef CONFIG_BOOTX_TEXT 1963 /* Update debug text engine */ 1964 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres, 1965 rinfo->depth, info->fix.line_length); 1966 #endif 1967 1968 kfree(newmode); 1969 return 0; 1970 } 1971 1972 1973 static struct fb_ops radeonfb_ops = { 1974 .owner = THIS_MODULE, 1975 .fb_check_var = radeonfb_check_var, 1976 .fb_set_par = radeonfb_set_par, 1977 .fb_setcolreg = radeonfb_setcolreg, 1978 .fb_setcmap = radeonfb_setcmap, 1979 .fb_pan_display = radeonfb_pan_display, 1980 .fb_blank = radeonfb_blank, 1981 .fb_ioctl = radeonfb_ioctl, 1982 .fb_sync = radeonfb_sync, 1983 .fb_fillrect = radeonfb_fillrect, 1984 .fb_copyarea = radeonfb_copyarea, 1985 .fb_imageblit = radeonfb_imageblit, 1986 }; 1987 1988 1989 static int radeon_set_fbinfo(struct radeonfb_info *rinfo) 1990 { 1991 struct fb_info *info = rinfo->info; 1992 1993 info->par = rinfo; 1994 info->pseudo_palette = rinfo->pseudo_palette; 1995 info->flags = FBINFO_DEFAULT 1996 | FBINFO_HWACCEL_COPYAREA 1997 | FBINFO_HWACCEL_FILLRECT 1998 | FBINFO_HWACCEL_XPAN 1999 | FBINFO_HWACCEL_YPAN; 2000 info->fbops = &radeonfb_ops; 2001 info->screen_base = rinfo->fb_base; 2002 info->screen_size = rinfo->mapped_vram; 2003 /* Fill fix common fields */ 2004 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); 2005 info->fix.smem_start = rinfo->fb_base_phys; 2006 info->fix.smem_len = rinfo->video_ram; 2007 info->fix.type = FB_TYPE_PACKED_PIXELS; 2008 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 2009 info->fix.xpanstep = 8; 2010 info->fix.ypanstep = 1; 2011 info->fix.ywrapstep = 0; 2012 info->fix.type_aux = 0; 2013 info->fix.mmio_start = rinfo->mmio_base_phys; 2014 info->fix.mmio_len = RADEON_REGSIZE; 2015 info->fix.accel = FB_ACCEL_ATI_RADEON; 2016 2017 fb_alloc_cmap(&info->cmap, 256, 0); 2018 2019 if (noaccel) 2020 info->flags |= FBINFO_HWACCEL_DISABLED; 2021 2022 return 0; 2023 } 2024 2025 /* 2026 * This reconfigure the card's internal memory map. In theory, we'd like 2027 * to setup the card's memory at the same address as it's PCI bus address, 2028 * and the AGP aperture right after that so that system RAM on 32 bits 2029 * machines at least, is directly accessible. However, doing so would 2030 * conflict with the current XFree drivers... 2031 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree 2032 * on the proper way to set this up and duplicate this here. In the meantime, 2033 * I put the card's memory at 0 in card space and AGP at some random high 2034 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway 2035 */ 2036 #ifdef CONFIG_PPC 2037 #undef SET_MC_FB_FROM_APERTURE 2038 static void fixup_memory_mappings(struct radeonfb_info *rinfo) 2039 { 2040 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0; 2041 u32 save_crtc_ext_cntl; 2042 u32 aper_base, aper_size; 2043 u32 agp_base; 2044 2045 /* First, we disable display to avoid interfering */ 2046 if (rinfo->has_CRTC2) { 2047 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL); 2048 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B); 2049 } 2050 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL); 2051 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL); 2052 2053 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS); 2054 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B); 2055 mdelay(100); 2056 2057 aper_base = INREG(CNFG_APER_0_BASE); 2058 aper_size = INREG(CNFG_APER_SIZE); 2059 2060 #ifdef SET_MC_FB_FROM_APERTURE 2061 /* Set framebuffer to be at the same address as set in PCI BAR */ 2062 OUTREG(MC_FB_LOCATION, 2063 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16)); 2064 rinfo->fb_local_base = aper_base; 2065 #else 2066 OUTREG(MC_FB_LOCATION, 0x7fff0000); 2067 rinfo->fb_local_base = 0; 2068 #endif 2069 agp_base = aper_base + aper_size; 2070 if (agp_base & 0xf0000000) 2071 agp_base = (aper_base | 0x0fffffff) + 1; 2072 2073 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This 2074 * assumes the FB isn't mapped to 0xf0000000 or above, but this is 2075 * always the case on PPCs afaik. 2076 */ 2077 #ifdef SET_MC_FB_FROM_APERTURE 2078 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16)); 2079 #else 2080 OUTREG(MC_AGP_LOCATION, 0xffffe000); 2081 #endif 2082 2083 /* Fixup the display base addresses & engine offsets while we 2084 * are at it as well 2085 */ 2086 #ifdef SET_MC_FB_FROM_APERTURE 2087 OUTREG(DISPLAY_BASE_ADDR, aper_base); 2088 if (rinfo->has_CRTC2) 2089 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base); 2090 OUTREG(OV0_BASE_ADDR, aper_base); 2091 #else 2092 OUTREG(DISPLAY_BASE_ADDR, 0); 2093 if (rinfo->has_CRTC2) 2094 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0); 2095 OUTREG(OV0_BASE_ADDR, 0); 2096 #endif 2097 mdelay(100); 2098 2099 /* Restore display settings */ 2100 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl); 2101 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl); 2102 if (rinfo->has_CRTC2) 2103 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl); 2104 2105 pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n", 2106 aper_base, 2107 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16), 2108 0xffff0000 | (agp_base >> 16)); 2109 } 2110 #endif /* CONFIG_PPC */ 2111 2112 2113 static void radeon_identify_vram(struct radeonfb_info *rinfo) 2114 { 2115 u32 tmp; 2116 2117 /* framebuffer size */ 2118 if ((rinfo->family == CHIP_FAMILY_RS100) || 2119 (rinfo->family == CHIP_FAMILY_RS200) || 2120 (rinfo->family == CHIP_FAMILY_RS300) || 2121 (rinfo->family == CHIP_FAMILY_RC410) || 2122 (rinfo->family == CHIP_FAMILY_RS400) || 2123 (rinfo->family == CHIP_FAMILY_RS480) ) { 2124 u32 tom = INREG(NB_TOM); 2125 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); 2126 2127 radeon_fifo_wait(6); 2128 OUTREG(MC_FB_LOCATION, tom); 2129 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2130 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2131 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); 2132 2133 /* This is supposed to fix the crtc2 noise problem. */ 2134 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); 2135 2136 if ((rinfo->family == CHIP_FAMILY_RS100) || 2137 (rinfo->family == CHIP_FAMILY_RS200)) { 2138 /* This is to workaround the asic bug for RMX, some versions 2139 of BIOS doesn't have this register initialized correctly. 2140 */ 2141 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, 2142 ~CRTC_H_CUTOFF_ACTIVE_EN); 2143 } 2144 } else { 2145 tmp = INREG(CNFG_MEMSIZE); 2146 } 2147 2148 /* mem size is bits [28:0], mask off the rest */ 2149 rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK; 2150 2151 /* 2152 * Hack to get around some busted production M6's 2153 * reporting no ram 2154 */ 2155 if (rinfo->video_ram == 0) { 2156 switch (rinfo->pdev->device) { 2157 case PCI_CHIP_RADEON_LY: 2158 case PCI_CHIP_RADEON_LZ: 2159 rinfo->video_ram = 8192 * 1024; 2160 break; 2161 default: 2162 break; 2163 } 2164 } 2165 2166 2167 /* 2168 * Now try to identify VRAM type 2169 */ 2170 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) || 2171 (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) 2172 rinfo->vram_ddr = 1; 2173 else 2174 rinfo->vram_ddr = 0; 2175 2176 tmp = INREG(MEM_CNTL); 2177 if (IS_R300_VARIANT(rinfo)) { 2178 tmp &= R300_MEM_NUM_CHANNELS_MASK; 2179 switch (tmp) { 2180 case 0: rinfo->vram_width = 64; break; 2181 case 1: rinfo->vram_width = 128; break; 2182 case 2: rinfo->vram_width = 256; break; 2183 default: rinfo->vram_width = 128; break; 2184 } 2185 } else if ((rinfo->family == CHIP_FAMILY_RV100) || 2186 (rinfo->family == CHIP_FAMILY_RS100) || 2187 (rinfo->family == CHIP_FAMILY_RS200)){ 2188 if (tmp & RV100_MEM_HALF_MODE) 2189 rinfo->vram_width = 32; 2190 else 2191 rinfo->vram_width = 64; 2192 } else { 2193 if (tmp & MEM_NUM_CHANNELS_MASK) 2194 rinfo->vram_width = 128; 2195 else 2196 rinfo->vram_width = 64; 2197 } 2198 2199 /* This may not be correct, as some cards can have half of channel disabled 2200 * ToDo: identify these cases 2201 */ 2202 2203 pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n", 2204 pci_name(rinfo->pdev), 2205 rinfo->video_ram / 1024, 2206 rinfo->vram_ddr ? "DDR" : "SDRAM", 2207 rinfo->vram_width); 2208 } 2209 2210 /* 2211 * Sysfs 2212 */ 2213 2214 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid) 2215 { 2216 return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH); 2217 } 2218 2219 2220 static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj, 2221 struct bin_attribute *bin_attr, 2222 char *buf, loff_t off, size_t count) 2223 { 2224 struct device *dev = container_of(kobj, struct device, kobj); 2225 struct pci_dev *pdev = to_pci_dev(dev); 2226 struct fb_info *info = pci_get_drvdata(pdev); 2227 struct radeonfb_info *rinfo = info->par; 2228 2229 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID); 2230 } 2231 2232 2233 static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj, 2234 struct bin_attribute *bin_attr, 2235 char *buf, loff_t off, size_t count) 2236 { 2237 struct device *dev = container_of(kobj, struct device, kobj); 2238 struct pci_dev *pdev = to_pci_dev(dev); 2239 struct fb_info *info = pci_get_drvdata(pdev); 2240 struct radeonfb_info *rinfo = info->par; 2241 2242 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID); 2243 } 2244 2245 static struct bin_attribute edid1_attr = { 2246 .attr = { 2247 .name = "edid1", 2248 .mode = 0444, 2249 }, 2250 .size = EDID_LENGTH, 2251 .read = radeon_show_edid1, 2252 }; 2253 2254 static struct bin_attribute edid2_attr = { 2255 .attr = { 2256 .name = "edid2", 2257 .mode = 0444, 2258 }, 2259 .size = EDID_LENGTH, 2260 .read = radeon_show_edid2, 2261 }; 2262 2263 2264 static int radeonfb_pci_register(struct pci_dev *pdev, 2265 const struct pci_device_id *ent) 2266 { 2267 struct fb_info *info; 2268 struct radeonfb_info *rinfo; 2269 int ret; 2270 unsigned char c1, c2; 2271 int err = 0; 2272 2273 pr_debug("radeonfb_pci_register BEGIN\n"); 2274 2275 /* Enable device in PCI config */ 2276 ret = pci_enable_device(pdev); 2277 if (ret < 0) { 2278 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n", 2279 pci_name(pdev)); 2280 goto err_out; 2281 } 2282 2283 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev); 2284 if (!info) { 2285 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n", 2286 pci_name(pdev)); 2287 ret = -ENOMEM; 2288 goto err_disable; 2289 } 2290 rinfo = info->par; 2291 rinfo->info = info; 2292 rinfo->pdev = pdev; 2293 2294 spin_lock_init(&rinfo->reg_lock); 2295 init_timer(&rinfo->lvds_timer); 2296 rinfo->lvds_timer.function = radeon_lvds_timer_func; 2297 rinfo->lvds_timer.data = (unsigned long)rinfo; 2298 2299 c1 = ent->device >> 8; 2300 c2 = ent->device & 0xff; 2301 if (isprint(c1) && isprint(c2)) 2302 snprintf(rinfo->name, sizeof(rinfo->name), 2303 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2); 2304 else 2305 snprintf(rinfo->name, sizeof(rinfo->name), 2306 "ATI Radeon %x", ent->device & 0xffff); 2307 2308 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK; 2309 rinfo->chipset = pdev->device; 2310 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0; 2311 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0; 2312 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0; 2313 2314 /* Set base addrs */ 2315 rinfo->fb_base_phys = pci_resource_start (pdev, 0); 2316 rinfo->mmio_base_phys = pci_resource_start (pdev, 2); 2317 2318 /* request the mem regions */ 2319 ret = pci_request_region(pdev, 0, "radeonfb framebuffer"); 2320 if (ret < 0) { 2321 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n", 2322 pci_name(rinfo->pdev)); 2323 goto err_release_fb; 2324 } 2325 2326 ret = pci_request_region(pdev, 2, "radeonfb mmio"); 2327 if (ret < 0) { 2328 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n", 2329 pci_name(rinfo->pdev)); 2330 goto err_release_pci0; 2331 } 2332 2333 /* map the regions */ 2334 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE); 2335 if (!rinfo->mmio_base) { 2336 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n", 2337 pci_name(rinfo->pdev)); 2338 ret = -EIO; 2339 goto err_release_pci2; 2340 } 2341 2342 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; 2343 2344 /* 2345 * Check for errata 2346 */ 2347 rinfo->errata = 0; 2348 if (rinfo->family == CHIP_FAMILY_R300 && 2349 (INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) 2350 == CFG_ATI_REV_A11) 2351 rinfo->errata |= CHIP_ERRATA_R300_CG; 2352 2353 if (rinfo->family == CHIP_FAMILY_RV200 || 2354 rinfo->family == CHIP_FAMILY_RS200) 2355 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2356 2357 if (rinfo->family == CHIP_FAMILY_RV100 || 2358 rinfo->family == CHIP_FAMILY_RS100 || 2359 rinfo->family == CHIP_FAMILY_RS200) 2360 rinfo->errata |= CHIP_ERRATA_PLL_DELAY; 2361 2362 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) 2363 /* On PPC, we obtain the OF device-node pointer to the firmware 2364 * data for this chip 2365 */ 2366 rinfo->of_node = pci_device_to_OF_node(pdev); 2367 if (rinfo->of_node == NULL) 2368 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n", 2369 pci_name(rinfo->pdev)); 2370 2371 #endif /* CONFIG_PPC || CONFIG_SPARC */ 2372 #ifdef CONFIG_PPC 2373 /* On PPC, the firmware sets up a memory mapping that tends 2374 * to cause lockups when enabling the engine. We reconfigure 2375 * the card internal memory mappings properly 2376 */ 2377 fixup_memory_mappings(rinfo); 2378 #endif /* CONFIG_PPC */ 2379 2380 /* Get VRAM size and type */ 2381 radeon_identify_vram(rinfo); 2382 2383 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram); 2384 2385 do { 2386 rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys, 2387 rinfo->mapped_vram); 2388 } while (rinfo->fb_base == NULL && 2389 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM)); 2390 2391 if (rinfo->fb_base == NULL) { 2392 printk (KERN_ERR "radeonfb (%s): cannot map FB\n", 2393 pci_name(rinfo->pdev)); 2394 ret = -EIO; 2395 goto err_unmap_rom; 2396 } 2397 2398 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev), 2399 rinfo->mapped_vram/1024); 2400 2401 /* 2402 * Map the BIOS ROM if any and retrieve PLL parameters from 2403 * the BIOS. We skip that on mobility chips as the real panel 2404 * values we need aren't in the ROM but in the BIOS image in 2405 * memory. This is definitely not the best meacnism though, 2406 * we really need the arch code to tell us which is the "primary" 2407 * video adapter to use the memory image (or better, the arch 2408 * should provide us a copy of the BIOS image to shield us from 2409 * archs who would store that elsewhere and/or could initialize 2410 * more than one adapter during boot). 2411 */ 2412 if (!rinfo->is_mobility) 2413 radeon_map_ROM(rinfo, pdev); 2414 2415 /* 2416 * On x86, the primary display on laptop may have it's BIOS 2417 * ROM elsewhere, try to locate it at the legacy memory hole. 2418 * We probably need to make sure this is the primary display, 2419 * but that is difficult without some arch support. 2420 */ 2421 #ifdef CONFIG_X86 2422 if (rinfo->bios_seg == NULL) 2423 radeon_find_mem_vbios(rinfo); 2424 #endif 2425 2426 /* If both above failed, try the BIOS ROM again for mobility 2427 * chips 2428 */ 2429 if (rinfo->bios_seg == NULL && rinfo->is_mobility) 2430 radeon_map_ROM(rinfo, pdev); 2431 2432 /* Get informations about the board's PLL */ 2433 radeon_get_pllinfo(rinfo); 2434 2435 #ifdef CONFIG_FB_RADEON_I2C 2436 /* Register I2C bus */ 2437 radeon_create_i2c_busses(rinfo); 2438 #endif 2439 2440 /* set all the vital stuff */ 2441 radeon_set_fbinfo (rinfo); 2442 2443 /* Probe screen types */ 2444 radeon_probe_screens(rinfo, monitor_layout, ignore_edid); 2445 2446 /* Build mode list, check out panel native model */ 2447 radeon_check_modes(rinfo, mode_option); 2448 2449 /* Register some sysfs stuff (should be done better) */ 2450 if (rinfo->mon1_EDID) 2451 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, 2452 &edid1_attr); 2453 if (rinfo->mon2_EDID) 2454 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, 2455 &edid2_attr); 2456 if (err) 2457 pr_warning("%s() Creating sysfs files failed, continuing\n", 2458 __func__); 2459 2460 /* save current mode regs before we switch into the new one 2461 * so we can restore this upon __exit 2462 */ 2463 radeon_save_state (rinfo, &rinfo->init_state); 2464 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs)); 2465 2466 /* Setup Power Management capabilities */ 2467 if (default_dynclk < -1) { 2468 /* -2 is special: means ON on mobility chips and do not 2469 * change on others 2470 */ 2471 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep); 2472 } else 2473 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep); 2474 2475 pci_set_drvdata(pdev, info); 2476 2477 /* Register with fbdev layer */ 2478 ret = register_framebuffer(info); 2479 if (ret < 0) { 2480 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n", 2481 pci_name(rinfo->pdev)); 2482 goto err_unmap_fb; 2483 } 2484 2485 if (!nomtrr) 2486 rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys, 2487 rinfo->video_ram); 2488 2489 if (backlight) 2490 radeonfb_bl_init(rinfo); 2491 2492 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name); 2493 2494 if (rinfo->bios_seg) 2495 radeon_unmap_ROM(rinfo, pdev); 2496 pr_debug("radeonfb_pci_register END\n"); 2497 2498 return 0; 2499 err_unmap_fb: 2500 iounmap(rinfo->fb_base); 2501 err_unmap_rom: 2502 kfree(rinfo->mon1_EDID); 2503 kfree(rinfo->mon2_EDID); 2504 if (rinfo->mon1_modedb) 2505 fb_destroy_modedb(rinfo->mon1_modedb); 2506 fb_dealloc_cmap(&info->cmap); 2507 #ifdef CONFIG_FB_RADEON_I2C 2508 radeon_delete_i2c_busses(rinfo); 2509 #endif 2510 if (rinfo->bios_seg) 2511 radeon_unmap_ROM(rinfo, pdev); 2512 iounmap(rinfo->mmio_base); 2513 err_release_pci2: 2514 pci_release_region(pdev, 2); 2515 err_release_pci0: 2516 pci_release_region(pdev, 0); 2517 err_release_fb: 2518 framebuffer_release(info); 2519 err_disable: 2520 err_out: 2521 return ret; 2522 } 2523 2524 2525 2526 static void radeonfb_pci_unregister(struct pci_dev *pdev) 2527 { 2528 struct fb_info *info = pci_get_drvdata(pdev); 2529 struct radeonfb_info *rinfo = info->par; 2530 2531 if (!rinfo) 2532 return; 2533 2534 radeonfb_pm_exit(rinfo); 2535 2536 if (rinfo->mon1_EDID) 2537 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr); 2538 if (rinfo->mon2_EDID) 2539 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr); 2540 2541 #if 0 2542 /* restore original state 2543 * 2544 * Doesn't quite work yet, I suspect if we come from a legacy 2545 * VGA mode (or worse, text mode), we need to do some VGA black 2546 * magic here that I know nothing about. --BenH 2547 */ 2548 radeon_write_mode (rinfo, &rinfo->init_state, 1); 2549 #endif 2550 2551 del_timer_sync(&rinfo->lvds_timer); 2552 arch_phys_wc_del(rinfo->wc_cookie); 2553 unregister_framebuffer(info); 2554 2555 radeonfb_bl_exit(rinfo); 2556 2557 iounmap(rinfo->mmio_base); 2558 iounmap(rinfo->fb_base); 2559 2560 pci_release_region(pdev, 2); 2561 pci_release_region(pdev, 0); 2562 2563 kfree(rinfo->mon1_EDID); 2564 kfree(rinfo->mon2_EDID); 2565 if (rinfo->mon1_modedb) 2566 fb_destroy_modedb(rinfo->mon1_modedb); 2567 #ifdef CONFIG_FB_RADEON_I2C 2568 radeon_delete_i2c_busses(rinfo); 2569 #endif 2570 fb_dealloc_cmap(&info->cmap); 2571 framebuffer_release(info); 2572 } 2573 2574 2575 static struct pci_driver radeonfb_driver = { 2576 .name = "radeonfb", 2577 .id_table = radeonfb_pci_table, 2578 .probe = radeonfb_pci_register, 2579 .remove = radeonfb_pci_unregister, 2580 #ifdef CONFIG_PM 2581 .suspend = radeonfb_pci_suspend, 2582 .resume = radeonfb_pci_resume, 2583 #endif /* CONFIG_PM */ 2584 }; 2585 2586 #ifndef MODULE 2587 static int __init radeonfb_setup (char *options) 2588 { 2589 char *this_opt; 2590 2591 if (!options || !*options) 2592 return 0; 2593 2594 while ((this_opt = strsep (&options, ",")) != NULL) { 2595 if (!*this_opt) 2596 continue; 2597 2598 if (!strncmp(this_opt, "noaccel", 7)) { 2599 noaccel = 1; 2600 } else if (!strncmp(this_opt, "mirror", 6)) { 2601 mirror = 1; 2602 } else if (!strncmp(this_opt, "force_dfp", 9)) { 2603 force_dfp = 1; 2604 } else if (!strncmp(this_opt, "panel_yres:", 11)) { 2605 panel_yres = simple_strtoul((this_opt+11), NULL, 0); 2606 } else if (!strncmp(this_opt, "backlight:", 10)) { 2607 backlight = simple_strtoul(this_opt+10, NULL, 0); 2608 } else if (!strncmp(this_opt, "nomtrr", 6)) { 2609 nomtrr = 1; 2610 } else if (!strncmp(this_opt, "nomodeset", 9)) { 2611 nomodeset = 1; 2612 } else if (!strncmp(this_opt, "force_measure_pll", 17)) { 2613 force_measure_pll = 1; 2614 } else if (!strncmp(this_opt, "ignore_edid", 11)) { 2615 ignore_edid = 1; 2616 #if defined(CONFIG_PM) && defined(CONFIG_X86) 2617 } else if (!strncmp(this_opt, "force_sleep", 11)) { 2618 force_sleep = 1; 2619 } else if (!strncmp(this_opt, "ignore_devlist", 14)) { 2620 ignore_devlist = 1; 2621 #endif 2622 } else 2623 mode_option = this_opt; 2624 } 2625 return 0; 2626 } 2627 #endif /* MODULE */ 2628 2629 static int __init radeonfb_init (void) 2630 { 2631 #ifndef MODULE 2632 char *option = NULL; 2633 2634 if (fb_get_options("radeonfb", &option)) 2635 return -ENODEV; 2636 radeonfb_setup(option); 2637 #endif 2638 return pci_register_driver (&radeonfb_driver); 2639 } 2640 2641 2642 static void __exit radeonfb_exit (void) 2643 { 2644 pci_unregister_driver (&radeonfb_driver); 2645 } 2646 2647 module_init(radeonfb_init); 2648 module_exit(radeonfb_exit); 2649 2650 MODULE_AUTHOR("Ani Joshi"); 2651 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset"); 2652 MODULE_LICENSE("GPL"); 2653 module_param(noaccel, bool, 0); 2654 module_param(default_dynclk, int, 0); 2655 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on"); 2656 MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); 2657 module_param(nomodeset, bool, 0); 2658 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode"); 2659 module_param(mirror, bool, 0); 2660 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors"); 2661 module_param(force_dfp, bool, 0); 2662 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp"); 2663 module_param(ignore_edid, bool, 0); 2664 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe"); 2665 module_param(monitor_layout, charp, 0); 2666 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)"); 2667 module_param(force_measure_pll, bool, 0); 2668 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)"); 2669 module_param(nomtrr, bool, 0); 2670 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers"); 2671 module_param(panel_yres, int, 0); 2672 MODULE_PARM_DESC(panel_yres, "int: set panel yres"); 2673 module_param(mode_option, charp, 0); 2674 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); 2675 #if defined(CONFIG_PM) && defined(CONFIG_X86) 2676 module_param(force_sleep, bool, 0); 2677 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware"); 2678 module_param(ignore_devlist, bool, 0); 2679 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops"); 2680 #endif 2681