1 /* 2 * drivers/video/aty/radeon_base.c 3 * 4 * framebuffer driver for ATI Radeon chipset video boards 5 * 6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org> 7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org> 8 * 9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net> 10 * 11 * Special thanks to ATI DevRel team for their hardware donations. 12 * 13 * ...Insert GPL boilerplate here... 14 * 15 * Significant portions of this driver apdated from XFree86 Radeon 16 * driver which has the following copyright notice: 17 * 18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 19 * VA Linux Systems Inc., Fremont, California. 20 * 21 * All Rights Reserved. 22 * 23 * Permission is hereby granted, free of charge, to any person obtaining 24 * a copy of this software and associated documentation files (the 25 * "Software"), to deal in the Software without restriction, including 26 * without limitation on the rights to use, copy, modify, merge, 27 * publish, distribute, sublicense, and/or sell copies of the Software, 28 * and to permit persons to whom the Software is furnished to do so, 29 * subject to the following conditions: 30 * 31 * The above copyright notice and this permission notice (including the 32 * next paragraph) shall be included in all copies or substantial 33 * portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 42 * DEALINGS IN THE SOFTWARE. 43 * 44 * XFree86 driver authors: 45 * 46 * Kevin E. Martin <martin@xfree86.org> 47 * Rickard E. Faith <faith@valinux.com> 48 * Alan Hourihane <alanh@fairlite.demon.co.uk> 49 * 50 */ 51 52 53 #define RADEON_VERSION "0.2.0" 54 55 #include "radeonfb.h" 56 57 #include <linux/module.h> 58 #include <linux/moduleparam.h> 59 #include <linux/kernel.h> 60 #include <linux/errno.h> 61 #include <linux/string.h> 62 #include <linux/ctype.h> 63 #include <linux/mm.h> 64 #include <linux/slab.h> 65 #include <linux/delay.h> 66 #include <linux/time.h> 67 #include <linux/fb.h> 68 #include <linux/ioport.h> 69 #include <linux/init.h> 70 #include <linux/pci.h> 71 #include <linux/vmalloc.h> 72 #include <linux/device.h> 73 74 #include <asm/io.h> 75 #include <linux/uaccess.h> 76 77 #ifdef CONFIG_PPC 78 79 #include "../macmodes.h" 80 81 #ifdef CONFIG_BOOTX_TEXT 82 #include <asm/btext.h> 83 #endif 84 85 #endif /* CONFIG_PPC */ 86 87 #include <video/radeon.h> 88 #include <linux/radeonfb.h> 89 90 #include "../edid.h" // MOVE THAT TO include/video 91 #include "ati_ids.h" 92 93 #define MAX_MAPPED_VRAM (2048*2048*4) 94 #define MIN_MAPPED_VRAM (1024*768*1) 95 96 #define CHIP_DEF(id, family, flags) \ 97 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) } 98 99 static const struct pci_device_id radeonfb_pci_table[] = { 100 /* Radeon Xpress 200m */ 101 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 102 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 103 /* Mobility M6 */ 104 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 105 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 106 /* Radeon VE/7000 */ 107 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2), 108 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2), 109 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2), 110 /* Radeon IGP320M (U1) */ 111 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 112 /* Radeon IGP320 (A3) */ 113 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 114 /* IGP330M/340M/350M (U2) */ 115 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 116 /* IGP330/340/350 (A4) */ 117 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 118 /* Mobility 7000 IGP */ 119 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 120 /* 7000 IGP (A4+) */ 121 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 122 /* 8500 AIW */ 123 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2), 124 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2), 125 /* 8700/8800 */ 126 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2), 127 /* 8500 */ 128 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2), 129 /* 9100 */ 130 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2), 131 /* Mobility M7 */ 132 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 133 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 134 /* 7500 */ 135 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2), 136 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2), 137 /* Mobility M9 */ 138 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 139 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 140 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 141 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 142 /* 9000/Pro */ 143 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2), 144 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2), 145 146 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 147 /* Mobility 9100 IGP (U3) */ 148 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 149 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), 150 /* 9100 IGP (A5) */ 151 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 152 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), 153 /* Mobility 9200 (M9+) */ 154 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 155 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 156 /* 9200 */ 157 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2), 158 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2), 159 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2), 160 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2), 161 /* 9500 */ 162 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2), 163 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2), 164 /* 9600TX / FireGL Z1 */ 165 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2), 166 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2), 167 /* 9700/9500/Pro/FireGL X1 */ 168 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2), 169 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2), 170 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2), 171 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2), 172 /* Mobility M10/M11 */ 173 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 174 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 175 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 176 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 177 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 178 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 179 /* 9600/FireGL T2 */ 180 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2), 181 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2), 182 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2), 183 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2), 184 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2), 185 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2), 186 /* 9800/Pro/FileGL X2 */ 187 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2), 188 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2), 189 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2), 190 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2), 191 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2), 192 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2), 193 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2), 194 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2), 195 /* Newer stuff */ 196 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2), 197 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2), 198 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 199 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 200 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2), 201 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2), 202 CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2), 203 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2), 204 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2), 205 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 206 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 207 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2), 208 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2), 209 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2), 210 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2), 211 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2), 212 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2), 213 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), 214 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2), 215 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2), 216 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2), 217 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2), 218 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2), 219 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2), 220 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2), 221 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2), 222 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2), 223 /* Original Radeon/7200 */ 224 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0), 225 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0), 226 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0), 227 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0), 228 { 0, } 229 }; 230 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table); 231 232 233 typedef struct { 234 u16 reg; 235 u32 val; 236 } reg_val; 237 238 239 /* these common regs are cleared before mode setting so they do not 240 * interfere with anything 241 */ 242 static reg_val common_regs[] = { 243 { OVR_CLR, 0 }, 244 { OVR_WID_LEFT_RIGHT, 0 }, 245 { OVR_WID_TOP_BOTTOM, 0 }, 246 { OV0_SCALE_CNTL, 0 }, 247 { SUBPIC_CNTL, 0 }, 248 { VIPH_CONTROL, 0 }, 249 { I2C_CNTL_1, 0 }, 250 { GEN_INT_CNTL, 0 }, 251 { CAP0_TRIG_CNTL, 0 }, 252 { CAP1_TRIG_CNTL, 0 }, 253 }; 254 255 /* 256 * globals 257 */ 258 259 static char *mode_option; 260 static char *monitor_layout; 261 static bool noaccel = 0; 262 static int default_dynclk = -2; 263 static bool nomodeset = 0; 264 static bool ignore_edid = 0; 265 static bool mirror = 0; 266 static int panel_yres = 0; 267 static bool force_dfp = 0; 268 static bool force_measure_pll = 0; 269 static bool nomtrr = 0; 270 static bool force_sleep; 271 static bool ignore_devlist; 272 #ifdef CONFIG_PMAC_BACKLIGHT 273 static int backlight = 1; 274 #else 275 static int backlight = 0; 276 #endif 277 278 /* Note about this function: we have some rare cases where we must not schedule, 279 * this typically happen with our special "wake up early" hook which allows us to 280 * wake up the graphic chip (and thus get the console back) before everything else 281 * on some machines that support that mechanism. At this point, interrupts are off 282 * and scheduling is not permitted 283 */ 284 void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms) 285 { 286 if (rinfo->no_schedule || oops_in_progress) 287 mdelay(ms); 288 else 289 msleep(ms); 290 } 291 292 void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo) 293 { 294 /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */ 295 (void)INREG(CLOCK_CNTL_DATA); 296 (void)INREG(CRTC_GEN_CNTL); 297 } 298 299 void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo) 300 { 301 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) { 302 /* we can't deal with posted writes here ... */ 303 _radeon_msleep(rinfo, 5); 304 } 305 if (rinfo->errata & CHIP_ERRATA_R300_CG) { 306 u32 save, tmp; 307 save = INREG(CLOCK_CNTL_INDEX); 308 tmp = save & ~(0x3f | PLL_WR_EN); 309 OUTREG(CLOCK_CNTL_INDEX, tmp); 310 tmp = INREG(CLOCK_CNTL_DATA); 311 OUTREG(CLOCK_CNTL_INDEX, save); 312 } 313 } 314 315 void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask) 316 { 317 unsigned long flags; 318 unsigned int tmp; 319 320 spin_lock_irqsave(&rinfo->reg_lock, flags); 321 tmp = INREG(addr); 322 tmp &= (mask); 323 tmp |= (val); 324 OUTREG(addr, tmp); 325 spin_unlock_irqrestore(&rinfo->reg_lock, flags); 326 } 327 328 u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) 329 { 330 u32 data; 331 332 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); 333 radeon_pll_errata_after_index(rinfo); 334 data = INREG(CLOCK_CNTL_DATA); 335 radeon_pll_errata_after_data(rinfo); 336 return data; 337 } 338 339 void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val) 340 { 341 OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); 342 radeon_pll_errata_after_index(rinfo); 343 OUTREG(CLOCK_CNTL_DATA, val); 344 radeon_pll_errata_after_data(rinfo); 345 } 346 347 void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, 348 u32 val, u32 mask) 349 { 350 unsigned int tmp; 351 352 tmp = __INPLL(rinfo, index); 353 tmp &= (mask); 354 tmp |= (val); 355 __OUTPLL(rinfo, index, tmp); 356 } 357 358 void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) 359 { 360 int i; 361 362 for (i=0; i<2000000; i++) { 363 if ((INREG(RBBM_STATUS) & 0x7f) >= entries) 364 return; 365 udelay(1); 366 } 367 printk(KERN_ERR "radeonfb: FIFO Timeout !\n"); 368 } 369 370 void radeon_engine_flush(struct radeonfb_info *rinfo) 371 { 372 int i; 373 374 /* Initiate flush */ 375 OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, 376 ~RB2D_DC_FLUSH_ALL); 377 378 /* Ensure FIFO is empty, ie, make sure the flush commands 379 * has reached the cache 380 */ 381 _radeon_fifo_wait(rinfo, 64); 382 383 /* Wait for the flush to complete */ 384 for (i=0; i < 2000000; i++) { 385 if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) 386 return; 387 udelay(1); 388 } 389 printk(KERN_ERR "radeonfb: Flush Timeout !\n"); 390 } 391 392 void _radeon_engine_idle(struct radeonfb_info *rinfo) 393 { 394 int i; 395 396 /* ensure FIFO is empty before waiting for idle */ 397 _radeon_fifo_wait(rinfo, 64); 398 399 for (i=0; i<2000000; i++) { 400 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { 401 radeon_engine_flush(rinfo); 402 return; 403 } 404 udelay(1); 405 } 406 printk(KERN_ERR "radeonfb: Idle Timeout !\n"); 407 } 408 409 410 411 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev) 412 { 413 if (!rinfo->bios_seg) 414 return; 415 pci_unmap_rom(dev, rinfo->bios_seg); 416 } 417 418 static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev) 419 { 420 void __iomem *rom; 421 u16 dptr; 422 u8 rom_type; 423 size_t rom_size; 424 425 /* If this is a primary card, there is a shadow copy of the 426 * ROM somewhere in the first meg. We will just ignore the copy 427 * and use the ROM directly. 428 */ 429 430 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */ 431 unsigned int temp; 432 temp = INREG(MPP_TB_CONFIG); 433 temp &= 0x00ffffffu; 434 temp |= 0x04 << 24; 435 OUTREG(MPP_TB_CONFIG, temp); 436 temp = INREG(MPP_TB_CONFIG); 437 438 rom = pci_map_rom(dev, &rom_size); 439 if (!rom) { 440 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n", 441 pci_name(rinfo->pdev)); 442 return -ENOMEM; 443 } 444 445 rinfo->bios_seg = rom; 446 447 /* Very simple test to make sure it appeared */ 448 if (BIOS_IN16(0) != 0xaa55) { 449 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x " 450 "should be 0xaa55\n", 451 pci_name(rinfo->pdev), BIOS_IN16(0)); 452 goto failed; 453 } 454 /* Look for the PCI data to check the ROM type */ 455 dptr = BIOS_IN16(0x18); 456 457 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM 458 * for now, until I've verified this works everywhere. The goal here is more 459 * to phase out Open Firmware images. 460 * 461 * Currently, we only look at the first PCI data, we could iteratre and deal with 462 * them all, and we should use fb_bios_start relative to start of image and not 463 * relative start of ROM, but so far, I never found a dual-image ATI card 464 * 465 * typedef struct { 466 * u32 signature; + 0x00 467 * u16 vendor; + 0x04 468 * u16 device; + 0x06 469 * u16 reserved_1; + 0x08 470 * u16 dlen; + 0x0a 471 * u8 drevision; + 0x0c 472 * u8 class_hi; + 0x0d 473 * u16 class_lo; + 0x0e 474 * u16 ilen; + 0x10 475 * u16 irevision; + 0x12 476 * u8 type; + 0x14 477 * u8 indicator; + 0x15 478 * u16 reserved_2; + 0x16 479 * } pci_data_t; 480 */ 481 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 482 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM" 483 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr)); 484 goto anyway; 485 } 486 rom_type = BIOS_IN8(dptr + 0x14); 487 switch(rom_type) { 488 case 0: 489 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n"); 490 break; 491 case 1: 492 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n"); 493 goto failed; 494 case 2: 495 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n"); 496 goto failed; 497 default: 498 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type); 499 goto failed; 500 } 501 anyway: 502 /* Locate the flat panel infos, do some sanity checking !!! */ 503 rinfo->fp_bios_start = BIOS_IN16(0x48); 504 return 0; 505 506 failed: 507 rinfo->bios_seg = NULL; 508 radeon_unmap_ROM(rinfo, dev); 509 return -ENXIO; 510 } 511 512 #ifdef CONFIG_X86 513 static int radeon_find_mem_vbios(struct radeonfb_info *rinfo) 514 { 515 /* I simplified this code as we used to miss the signatures in 516 * a lot of case. It's now closer to XFree, we just don't check 517 * for signatures at all... Something better will have to be done 518 * if we end up having conflicts 519 */ 520 u32 segstart; 521 void __iomem *rom_base = NULL; 522 523 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { 524 rom_base = ioremap(segstart, 0x10000); 525 if (rom_base == NULL) 526 return -ENOMEM; 527 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) 528 break; 529 iounmap(rom_base); 530 rom_base = NULL; 531 } 532 if (rom_base == NULL) 533 return -ENXIO; 534 535 /* Locate the flat panel infos, do some sanity checking !!! */ 536 rinfo->bios_seg = rom_base; 537 rinfo->fp_bios_start = BIOS_IN16(0x48); 538 539 return 0; 540 } 541 #endif 542 543 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) 544 /* 545 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device 546 * tree. Hopefully, ATI OF driver is kind enough to fill these 547 */ 548 static int radeon_read_xtal_OF(struct radeonfb_info *rinfo) 549 { 550 struct device_node *dp = rinfo->of_node; 551 const u32 *val; 552 553 if (dp == NULL) 554 return -ENODEV; 555 val = of_get_property(dp, "ATY,RefCLK", NULL); 556 if (!val || !*val) { 557 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n"); 558 return -EINVAL; 559 } 560 561 rinfo->pll.ref_clk = (*val) / 10; 562 563 val = of_get_property(dp, "ATY,SCLK", NULL); 564 if (val && *val) 565 rinfo->pll.sclk = (*val) / 10; 566 567 val = of_get_property(dp, "ATY,MCLK", NULL); 568 if (val && *val) 569 rinfo->pll.mclk = (*val) / 10; 570 571 return 0; 572 } 573 #endif /* CONFIG_PPC || CONFIG_SPARC */ 574 575 /* 576 * Read PLL infos from chip registers 577 */ 578 static int radeon_probe_pll_params(struct radeonfb_info *rinfo) 579 { 580 unsigned char ppll_div_sel; 581 unsigned Ns, Nm, M; 582 unsigned sclk, mclk, tmp, ref_div; 583 int hTotal, vTotal, num, denom, m, n; 584 unsigned long long hz, vclk; 585 long xtal; 586 ktime_t start_time, stop_time; 587 u64 total_usecs; 588 int i; 589 590 /* Ugh, we cut interrupts, bad bad bad, but we want some precision 591 * here, so... --BenH 592 */ 593 594 /* Flush PCI buffers ? */ 595 tmp = INREG16(DEVICE_ID); 596 597 local_irq_disable(); 598 599 for(i=0; i<1000000; i++) 600 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) 601 break; 602 603 start_time = ktime_get(); 604 605 for(i=0; i<1000000; i++) 606 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0) 607 break; 608 609 for(i=0; i<1000000; i++) 610 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) 611 break; 612 613 stop_time = ktime_get(); 614 615 local_irq_enable(); 616 617 total_usecs = ktime_us_delta(stop_time, start_time); 618 if (total_usecs >= 10 * USEC_PER_SEC || total_usecs == 0) 619 return -1; 620 hz = USEC_PER_SEC/(u32)total_usecs; 621 622 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8; 623 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1); 624 vclk = (long long)hTotal * (long long)vTotal * hz; 625 626 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) { 627 case 0: 628 default: 629 num = 1; 630 denom = 1; 631 break; 632 case 1: 633 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff); 634 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); 635 num = 2*n; 636 denom = 2*m; 637 break; 638 case 2: 639 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff); 640 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); 641 num = 2*n; 642 denom = 2*m; 643 break; 644 } 645 646 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3; 647 radeon_pll_errata_after_index(rinfo); 648 649 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff); 650 m = (INPLL(PPLL_REF_DIV) & 0x3ff); 651 652 num *= n; 653 denom *= m; 654 655 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { 656 case 1: 657 denom *= 2; 658 break; 659 case 2: 660 denom *= 4; 661 break; 662 case 3: 663 denom *= 8; 664 break; 665 case 4: 666 denom *= 3; 667 break; 668 case 6: 669 denom *= 6; 670 break; 671 case 7: 672 denom *= 12; 673 break; 674 } 675 676 vclk *= denom; 677 do_div(vclk, 1000 * num); 678 xtal = vclk; 679 680 if ((xtal > 26900) && (xtal < 27100)) 681 xtal = 2700; 682 else if ((xtal > 14200) && (xtal < 14400)) 683 xtal = 1432; 684 else if ((xtal > 29400) && (xtal < 29600)) 685 xtal = 2950; 686 else { 687 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal); 688 return -1; 689 } 690 691 tmp = INPLL(M_SPLL_REF_FB_DIV); 692 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; 693 694 Ns = (tmp & 0xff0000) >> 16; 695 Nm = (tmp & 0xff00) >> 8; 696 M = (tmp & 0xff); 697 sclk = round_div((2 * Ns * xtal), (2 * M)); 698 mclk = round_div((2 * Nm * xtal), (2 * M)); 699 700 /* we're done, hopefully these are sane values */ 701 rinfo->pll.ref_clk = xtal; 702 rinfo->pll.ref_div = ref_div; 703 rinfo->pll.sclk = sclk; 704 rinfo->pll.mclk = mclk; 705 706 return 0; 707 } 708 709 /* 710 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...) 711 */ 712 static void radeon_get_pllinfo(struct radeonfb_info *rinfo) 713 { 714 /* 715 * In the case nothing works, these are defaults; they are mostly 716 * incomplete, however. It does provide ppll_max and _min values 717 * even for most other methods, however. 718 */ 719 switch (rinfo->chipset) { 720 case PCI_DEVICE_ID_ATI_RADEON_QW: 721 case PCI_DEVICE_ID_ATI_RADEON_QX: 722 rinfo->pll.ppll_max = 35000; 723 rinfo->pll.ppll_min = 12000; 724 rinfo->pll.mclk = 23000; 725 rinfo->pll.sclk = 23000; 726 rinfo->pll.ref_clk = 2700; 727 break; 728 case PCI_DEVICE_ID_ATI_RADEON_QL: 729 case PCI_DEVICE_ID_ATI_RADEON_QN: 730 case PCI_DEVICE_ID_ATI_RADEON_QO: 731 case PCI_DEVICE_ID_ATI_RADEON_Ql: 732 case PCI_DEVICE_ID_ATI_RADEON_BB: 733 rinfo->pll.ppll_max = 35000; 734 rinfo->pll.ppll_min = 12000; 735 rinfo->pll.mclk = 27500; 736 rinfo->pll.sclk = 27500; 737 rinfo->pll.ref_clk = 2700; 738 break; 739 case PCI_DEVICE_ID_ATI_RADEON_Id: 740 case PCI_DEVICE_ID_ATI_RADEON_Ie: 741 case PCI_DEVICE_ID_ATI_RADEON_If: 742 case PCI_DEVICE_ID_ATI_RADEON_Ig: 743 rinfo->pll.ppll_max = 35000; 744 rinfo->pll.ppll_min = 12000; 745 rinfo->pll.mclk = 25000; 746 rinfo->pll.sclk = 25000; 747 rinfo->pll.ref_clk = 2700; 748 break; 749 case PCI_DEVICE_ID_ATI_RADEON_ND: 750 case PCI_DEVICE_ID_ATI_RADEON_NE: 751 case PCI_DEVICE_ID_ATI_RADEON_NF: 752 case PCI_DEVICE_ID_ATI_RADEON_NG: 753 rinfo->pll.ppll_max = 40000; 754 rinfo->pll.ppll_min = 20000; 755 rinfo->pll.mclk = 27000; 756 rinfo->pll.sclk = 27000; 757 rinfo->pll.ref_clk = 2700; 758 break; 759 case PCI_DEVICE_ID_ATI_RADEON_QD: 760 case PCI_DEVICE_ID_ATI_RADEON_QE: 761 case PCI_DEVICE_ID_ATI_RADEON_QF: 762 case PCI_DEVICE_ID_ATI_RADEON_QG: 763 default: 764 rinfo->pll.ppll_max = 35000; 765 rinfo->pll.ppll_min = 12000; 766 rinfo->pll.mclk = 16600; 767 rinfo->pll.sclk = 16600; 768 rinfo->pll.ref_clk = 2700; 769 break; 770 } 771 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; 772 773 774 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) 775 /* 776 * Retrieve PLL infos from Open Firmware first 777 */ 778 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) { 779 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n"); 780 goto found; 781 } 782 #endif /* CONFIG_PPC || CONFIG_SPARC */ 783 784 /* 785 * Check out if we have an X86 which gave us some PLL informations 786 * and if yes, retrieve them 787 */ 788 if (!force_measure_pll && rinfo->bios_seg) { 789 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); 790 791 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); 792 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a); 793 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); 794 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); 795 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); 796 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); 797 798 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n"); 799 goto found; 800 } 801 802 /* 803 * We didn't get PLL parameters from either OF or BIOS, we try to 804 * probe them 805 */ 806 if (radeon_probe_pll_params(rinfo) == 0) { 807 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n"); 808 goto found; 809 } 810 811 /* 812 * Fall back to already-set defaults... 813 */ 814 printk(KERN_INFO "radeonfb: Used default PLL infos\n"); 815 816 found: 817 /* 818 * Some methods fail to retrieve SCLK and MCLK values, we apply default 819 * settings in this case (200Mhz). If that really happens often, we 820 * could fetch from registers instead... 821 */ 822 if (rinfo->pll.mclk == 0) 823 rinfo->pll.mclk = 20000; 824 if (rinfo->pll.sclk == 0) 825 rinfo->pll.sclk = 20000; 826 827 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n", 828 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100, 829 rinfo->pll.ref_div, 830 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100, 831 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100); 832 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max); 833 } 834 835 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info) 836 { 837 struct radeonfb_info *rinfo = info->par; 838 struct fb_var_screeninfo v; 839 int nom, den; 840 unsigned int pitch; 841 842 if (radeon_match_mode(rinfo, &v, var)) 843 return -EINVAL; 844 845 switch (v.bits_per_pixel) { 846 case 0 ... 8: 847 v.bits_per_pixel = 8; 848 break; 849 case 9 ... 16: 850 v.bits_per_pixel = 16; 851 break; 852 case 25 ... 32: 853 v.bits_per_pixel = 32; 854 break; 855 default: 856 return -EINVAL; 857 } 858 859 switch (var_to_depth(&v)) { 860 case 8: 861 nom = den = 1; 862 v.red.offset = v.green.offset = v.blue.offset = 0; 863 v.red.length = v.green.length = v.blue.length = 8; 864 v.transp.offset = v.transp.length = 0; 865 break; 866 case 15: 867 nom = 2; 868 den = 1; 869 v.red.offset = 10; 870 v.green.offset = 5; 871 v.blue.offset = 0; 872 v.red.length = v.green.length = v.blue.length = 5; 873 v.transp.offset = v.transp.length = 0; 874 break; 875 case 16: 876 nom = 2; 877 den = 1; 878 v.red.offset = 11; 879 v.green.offset = 5; 880 v.blue.offset = 0; 881 v.red.length = 5; 882 v.green.length = 6; 883 v.blue.length = 5; 884 v.transp.offset = v.transp.length = 0; 885 break; 886 case 24: 887 nom = 4; 888 den = 1; 889 v.red.offset = 16; 890 v.green.offset = 8; 891 v.blue.offset = 0; 892 v.red.length = v.blue.length = v.green.length = 8; 893 v.transp.offset = v.transp.length = 0; 894 break; 895 case 32: 896 nom = 4; 897 den = 1; 898 v.red.offset = 16; 899 v.green.offset = 8; 900 v.blue.offset = 0; 901 v.red.length = v.blue.length = v.green.length = 8; 902 v.transp.offset = 24; 903 v.transp.length = 8; 904 break; 905 default: 906 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n", 907 var->xres, var->yres, var->bits_per_pixel); 908 return -EINVAL; 909 } 910 911 if (v.yres_virtual < v.yres) 912 v.yres_virtual = v.yres; 913 if (v.xres_virtual < v.xres) 914 v.xres_virtual = v.xres; 915 916 917 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree 918 * with some panels, though I don't quite like this solution 919 */ 920 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) { 921 v.xres_virtual = v.xres_virtual & ~7ul; 922 } else { 923 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f) 924 & ~(0x3f)) >> 6; 925 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8); 926 } 927 928 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram) 929 return -EINVAL; 930 931 if (v.xres_virtual < v.xres) 932 v.xres = v.xres_virtual; 933 934 if (v.xoffset > v.xres_virtual - v.xres) 935 v.xoffset = v.xres_virtual - v.xres - 1; 936 937 if (v.yoffset > v.yres_virtual - v.yres) 938 v.yoffset = v.yres_virtual - v.yres - 1; 939 940 v.red.msb_right = v.green.msb_right = v.blue.msb_right = 941 v.transp.offset = v.transp.length = 942 v.transp.msb_right = 0; 943 944 memcpy(var, &v, sizeof(v)); 945 946 return 0; 947 } 948 949 950 static int radeonfb_pan_display (struct fb_var_screeninfo *var, 951 struct fb_info *info) 952 { 953 struct radeonfb_info *rinfo = info->par; 954 955 if ((var->xoffset + info->var.xres > info->var.xres_virtual) 956 || (var->yoffset + info->var.yres > info->var.yres_virtual)) 957 return -EINVAL; 958 959 if (rinfo->asleep) 960 return 0; 961 962 radeon_fifo_wait(2); 963 OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length + 964 var->xoffset * info->var.bits_per_pixel / 8) & ~7); 965 return 0; 966 } 967 968 969 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd, 970 unsigned long arg) 971 { 972 struct radeonfb_info *rinfo = info->par; 973 unsigned int tmp; 974 u32 value = 0; 975 int rc; 976 977 switch (cmd) { 978 /* 979 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's 980 * and do something better using 2nd CRTC instead of just hackish 981 * routing to second output 982 */ 983 case FBIO_RADEON_SET_MIRROR: 984 if (!rinfo->is_mobility) 985 return -EINVAL; 986 987 rc = get_user(value, (__u32 __user *)arg); 988 989 if (rc) 990 return rc; 991 992 radeon_fifo_wait(2); 993 if (value & 0x01) { 994 tmp = INREG(LVDS_GEN_CNTL); 995 996 tmp |= (LVDS_ON | LVDS_BLON); 997 } else { 998 tmp = INREG(LVDS_GEN_CNTL); 999 1000 tmp &= ~(LVDS_ON | LVDS_BLON); 1001 } 1002 1003 OUTREG(LVDS_GEN_CNTL, tmp); 1004 1005 if (value & 0x02) { 1006 tmp = INREG(CRTC_EXT_CNTL); 1007 tmp |= CRTC_CRT_ON; 1008 1009 mirror = 1; 1010 } else { 1011 tmp = INREG(CRTC_EXT_CNTL); 1012 tmp &= ~CRTC_CRT_ON; 1013 1014 mirror = 0; 1015 } 1016 1017 OUTREG(CRTC_EXT_CNTL, tmp); 1018 1019 return 0; 1020 case FBIO_RADEON_GET_MIRROR: 1021 if (!rinfo->is_mobility) 1022 return -EINVAL; 1023 1024 tmp = INREG(LVDS_GEN_CNTL); 1025 if ((LVDS_ON | LVDS_BLON) & tmp) 1026 value |= 0x01; 1027 1028 tmp = INREG(CRTC_EXT_CNTL); 1029 if (CRTC_CRT_ON & tmp) 1030 value |= 0x02; 1031 1032 return put_user(value, (__u32 __user *)arg); 1033 default: 1034 return -EINVAL; 1035 } 1036 1037 return -EINVAL; 1038 } 1039 1040 1041 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch) 1042 { 1043 u32 val; 1044 u32 tmp_pix_clks; 1045 int unblank = 0; 1046 1047 if (rinfo->lock_blank) 1048 return 0; 1049 1050 radeon_engine_idle(); 1051 1052 val = INREG(CRTC_EXT_CNTL); 1053 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | 1054 CRTC_VSYNC_DIS); 1055 switch (blank) { 1056 case FB_BLANK_VSYNC_SUSPEND: 1057 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS); 1058 break; 1059 case FB_BLANK_HSYNC_SUSPEND: 1060 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS); 1061 break; 1062 case FB_BLANK_POWERDOWN: 1063 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | 1064 CRTC_HSYNC_DIS); 1065 break; 1066 case FB_BLANK_NORMAL: 1067 val |= CRTC_DISPLAY_DIS; 1068 break; 1069 case FB_BLANK_UNBLANK: 1070 default: 1071 unblank = 1; 1072 } 1073 OUTREG(CRTC_EXT_CNTL, val); 1074 1075 1076 switch (rinfo->mon1_type) { 1077 case MT_DFP: 1078 if (unblank) 1079 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN), 1080 ~(FP_FPON | FP_TMDS_EN)); 1081 else { 1082 if (mode_switch || blank == FB_BLANK_NORMAL) 1083 break; 1084 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN)); 1085 } 1086 break; 1087 case MT_LCD: 1088 del_timer_sync(&rinfo->lvds_timer); 1089 val = INREG(LVDS_GEN_CNTL); 1090 if (unblank) { 1091 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON 1092 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl 1093 & (LVDS_DIGON | LVDS_BL_MOD_EN)); 1094 if ((val ^ target_val) == LVDS_DISPLAY_DIS) 1095 OUTREG(LVDS_GEN_CNTL, target_val); 1096 else if ((val ^ target_val) != 0) { 1097 OUTREG(LVDS_GEN_CNTL, target_val 1098 & ~(LVDS_ON | LVDS_BL_MOD_EN)); 1099 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; 1100 rinfo->init_state.lvds_gen_cntl |= 1101 target_val & LVDS_STATE_MASK; 1102 if (mode_switch) { 1103 radeon_msleep(rinfo->panel_info.pwr_delay); 1104 OUTREG(LVDS_GEN_CNTL, target_val); 1105 } 1106 else { 1107 rinfo->pending_lvds_gen_cntl = target_val; 1108 mod_timer(&rinfo->lvds_timer, 1109 jiffies + 1110 msecs_to_jiffies(rinfo->panel_info.pwr_delay)); 1111 } 1112 } 1113 } else { 1114 val |= LVDS_DISPLAY_DIS; 1115 OUTREG(LVDS_GEN_CNTL, val); 1116 1117 /* We don't do a full switch-off on a simple mode switch */ 1118 if (mode_switch || blank == FB_BLANK_NORMAL) 1119 break; 1120 1121 /* Asic bug, when turning off LVDS_ON, we have to make sure 1122 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off 1123 */ 1124 tmp_pix_clks = INPLL(PIXCLKS_CNTL); 1125 if (rinfo->is_mobility || rinfo->is_IGP) 1126 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb); 1127 val &= ~(LVDS_BL_MOD_EN); 1128 OUTREG(LVDS_GEN_CNTL, val); 1129 udelay(100); 1130 val &= ~(LVDS_ON | LVDS_EN); 1131 OUTREG(LVDS_GEN_CNTL, val); 1132 val &= ~LVDS_DIGON; 1133 rinfo->pending_lvds_gen_cntl = val; 1134 mod_timer(&rinfo->lvds_timer, 1135 jiffies + 1136 msecs_to_jiffies(rinfo->panel_info.pwr_delay)); 1137 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; 1138 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK; 1139 if (rinfo->is_mobility || rinfo->is_IGP) 1140 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks); 1141 } 1142 break; 1143 case MT_CRT: 1144 // todo: powerdown DAC 1145 default: 1146 break; 1147 } 1148 1149 return 0; 1150 } 1151 1152 static int radeonfb_blank (int blank, struct fb_info *info) 1153 { 1154 struct radeonfb_info *rinfo = info->par; 1155 1156 if (rinfo->asleep) 1157 return 0; 1158 1159 return radeon_screen_blank(rinfo, blank, 0); 1160 } 1161 1162 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green, 1163 unsigned blue, unsigned transp, 1164 struct radeonfb_info *rinfo) 1165 { 1166 u32 pindex; 1167 unsigned int i; 1168 1169 1170 if (regno > 255) 1171 return -EINVAL; 1172 1173 red >>= 8; 1174 green >>= 8; 1175 blue >>= 8; 1176 rinfo->palette[regno].red = red; 1177 rinfo->palette[regno].green = green; 1178 rinfo->palette[regno].blue = blue; 1179 1180 /* default */ 1181 pindex = regno; 1182 1183 if (!rinfo->asleep) { 1184 radeon_fifo_wait(9); 1185 1186 if (rinfo->bpp == 16) { 1187 pindex = regno * 8; 1188 1189 if (rinfo->depth == 16 && regno > 63) 1190 return -EINVAL; 1191 if (rinfo->depth == 15 && regno > 31) 1192 return -EINVAL; 1193 1194 /* For 565, the green component is mixed one order 1195 * below 1196 */ 1197 if (rinfo->depth == 16) { 1198 OUTREG(PALETTE_INDEX, pindex>>1); 1199 OUTREG(PALETTE_DATA, 1200 (rinfo->palette[regno>>1].red << 16) | 1201 (green << 8) | 1202 (rinfo->palette[regno>>1].blue)); 1203 green = rinfo->palette[regno<<1].green; 1204 } 1205 } 1206 1207 if (rinfo->depth != 16 || regno < 32) { 1208 OUTREG(PALETTE_INDEX, pindex); 1209 OUTREG(PALETTE_DATA, (red << 16) | 1210 (green << 8) | blue); 1211 } 1212 } 1213 if (regno < 16) { 1214 u32 *pal = rinfo->info->pseudo_palette; 1215 switch (rinfo->depth) { 1216 case 15: 1217 pal[regno] = (regno << 10) | (regno << 5) | regno; 1218 break; 1219 case 16: 1220 pal[regno] = (regno << 11) | (regno << 5) | regno; 1221 break; 1222 case 24: 1223 pal[regno] = (regno << 16) | (regno << 8) | regno; 1224 break; 1225 case 32: 1226 i = (regno << 8) | regno; 1227 pal[regno] = (i << 16) | i; 1228 break; 1229 } 1230 } 1231 return 0; 1232 } 1233 1234 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green, 1235 unsigned blue, unsigned transp, 1236 struct fb_info *info) 1237 { 1238 struct radeonfb_info *rinfo = info->par; 1239 u32 dac_cntl2, vclk_cntl = 0; 1240 int rc; 1241 1242 if (!rinfo->asleep) { 1243 if (rinfo->is_mobility) { 1244 vclk_cntl = INPLL(VCLK_ECP_CNTL); 1245 OUTPLL(VCLK_ECP_CNTL, 1246 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb); 1247 } 1248 1249 /* Make sure we are on first palette */ 1250 if (rinfo->has_CRTC2) { 1251 dac_cntl2 = INREG(DAC_CNTL2); 1252 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL; 1253 OUTREG(DAC_CNTL2, dac_cntl2); 1254 } 1255 } 1256 1257 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo); 1258 1259 if (!rinfo->asleep && rinfo->is_mobility) 1260 OUTPLL(VCLK_ECP_CNTL, vclk_cntl); 1261 1262 return rc; 1263 } 1264 1265 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info) 1266 { 1267 struct radeonfb_info *rinfo = info->par; 1268 u16 *red, *green, *blue, *transp; 1269 u32 dac_cntl2, vclk_cntl = 0; 1270 int i, start, rc = 0; 1271 1272 if (!rinfo->asleep) { 1273 if (rinfo->is_mobility) { 1274 vclk_cntl = INPLL(VCLK_ECP_CNTL); 1275 OUTPLL(VCLK_ECP_CNTL, 1276 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb); 1277 } 1278 1279 /* Make sure we are on first palette */ 1280 if (rinfo->has_CRTC2) { 1281 dac_cntl2 = INREG(DAC_CNTL2); 1282 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL; 1283 OUTREG(DAC_CNTL2, dac_cntl2); 1284 } 1285 } 1286 1287 red = cmap->red; 1288 green = cmap->green; 1289 blue = cmap->blue; 1290 transp = cmap->transp; 1291 start = cmap->start; 1292 1293 for (i = 0; i < cmap->len; i++) { 1294 u_int hred, hgreen, hblue, htransp = 0xffff; 1295 1296 hred = *red++; 1297 hgreen = *green++; 1298 hblue = *blue++; 1299 if (transp) 1300 htransp = *transp++; 1301 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp, 1302 rinfo); 1303 if (rc) 1304 break; 1305 } 1306 1307 if (!rinfo->asleep && rinfo->is_mobility) 1308 OUTPLL(VCLK_ECP_CNTL, vclk_cntl); 1309 1310 return rc; 1311 } 1312 1313 static void radeon_save_state (struct radeonfb_info *rinfo, 1314 struct radeon_regs *save) 1315 { 1316 /* CRTC regs */ 1317 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); 1318 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); 1319 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); 1320 save->dac_cntl = INREG(DAC_CNTL); 1321 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); 1322 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID); 1323 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP); 1324 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID); 1325 save->crtc_pitch = INREG(CRTC_PITCH); 1326 save->surface_cntl = INREG(SURFACE_CNTL); 1327 1328 /* FP regs */ 1329 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP); 1330 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP); 1331 save->fp_gen_cntl = INREG(FP_GEN_CNTL); 1332 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID); 1333 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH); 1334 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID); 1335 save->fp_vert_stretch = INREG(FP_VERT_STRETCH); 1336 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); 1337 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); 1338 save->tmds_crc = INREG(TMDS_CRC); 1339 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); 1340 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL); 1341 1342 /* PLL regs */ 1343 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; 1344 radeon_pll_errata_after_index(rinfo); 1345 save->ppll_div_3 = INPLL(PPLL_DIV_3); 1346 save->ppll_ref_div = INPLL(PPLL_REF_DIV); 1347 } 1348 1349 1350 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) 1351 { 1352 int i; 1353 1354 radeon_fifo_wait(20); 1355 1356 /* Workaround from XFree */ 1357 if (rinfo->is_mobility) { 1358 /* A temporal workaround for the occasional blanking on certain laptop 1359 * panels. This appears to related to the PLL divider registers 1360 * (fail to lock?). It occurs even when all dividers are the same 1361 * with their old settings. In this case we really don't need to 1362 * fiddle with PLL registers. By doing this we can avoid the blanking 1363 * problem with some panels. 1364 */ 1365 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && 1366 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & 1367 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { 1368 /* We still have to force a switch to selected PPLL div thanks to 1369 * an XFree86 driver bug which will switch it away in some cases 1370 * even when using UseFDev */ 1371 OUTREGP(CLOCK_CNTL_INDEX, 1372 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 1373 ~PPLL_DIV_SEL_MASK); 1374 radeon_pll_errata_after_index(rinfo); 1375 radeon_pll_errata_after_data(rinfo); 1376 return; 1377 } 1378 } 1379 1380 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ 1381 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); 1382 1383 /* Reset PPLL & enable atomic update */ 1384 OUTPLLP(PPLL_CNTL, 1385 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, 1386 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 1387 1388 /* Switch to selected PPLL divider */ 1389 OUTREGP(CLOCK_CNTL_INDEX, 1390 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 1391 ~PPLL_DIV_SEL_MASK); 1392 radeon_pll_errata_after_index(rinfo); 1393 radeon_pll_errata_after_data(rinfo); 1394 1395 /* Set PPLL ref. div */ 1396 if (IS_R300_VARIANT(rinfo) || 1397 rinfo->family == CHIP_FAMILY_RS300 || 1398 rinfo->family == CHIP_FAMILY_RS400 || 1399 rinfo->family == CHIP_FAMILY_RS480) { 1400 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 1401 /* When restoring console mode, use saved PPLL_REF_DIV 1402 * setting. 1403 */ 1404 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); 1405 } else { 1406 /* R300 uses ref_div_acc field as real ref divider */ 1407 OUTPLLP(PPLL_REF_DIV, 1408 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 1409 ~R300_PPLL_REF_DIV_ACC_MASK); 1410 } 1411 } else 1412 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); 1413 1414 /* Set PPLL divider 3 & post divider*/ 1415 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); 1416 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); 1417 1418 /* Write update */ 1419 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) 1420 ; 1421 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); 1422 1423 /* Wait read update complete */ 1424 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 1425 the cause yet, but this workaround will mask the problem for now. 1426 Other chips usually will pass at the very first test, so the 1427 workaround shouldn't have any effect on them. */ 1428 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) 1429 ; 1430 1431 OUTPLL(HTOTAL_CNTL, 0); 1432 1433 /* Clear reset & atomic update */ 1434 OUTPLLP(PPLL_CNTL, 0, 1435 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 1436 1437 /* We may want some locking ... oh well */ 1438 radeon_msleep(5); 1439 1440 /* Switch back VCLK source to PPLL */ 1441 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); 1442 } 1443 1444 /* 1445 * Timer function for delayed LVDS panel power up/down 1446 */ 1447 static void radeon_lvds_timer_func(struct timer_list *t) 1448 { 1449 struct radeonfb_info *rinfo = from_timer(rinfo, t, lvds_timer); 1450 1451 radeon_engine_idle(); 1452 1453 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); 1454 } 1455 1456 /* 1457 * Apply a video mode. This will apply the whole register set, including 1458 * the PLL registers, to the card 1459 */ 1460 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, 1461 int regs_only) 1462 { 1463 int i; 1464 int primary_mon = PRIMARY_MONITOR(rinfo); 1465 1466 if (nomodeset) 1467 return; 1468 1469 if (!regs_only) 1470 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); 1471 1472 radeon_fifo_wait(31); 1473 for (i=0; i<10; i++) 1474 OUTREG(common_regs[i].reg, common_regs[i].val); 1475 1476 /* Apply surface registers */ 1477 for (i=0; i<8; i++) { 1478 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]); 1479 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]); 1480 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]); 1481 } 1482 1483 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); 1484 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 1485 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 1486 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl); 1487 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); 1488 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); 1489 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); 1490 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); 1491 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); 1492 OUTREG(CRTC_OFFSET, 0); 1493 OUTREG(CRTC_OFFSET_CNTL, 0); 1494 OUTREG(CRTC_PITCH, mode->crtc_pitch); 1495 OUTREG(SURFACE_CNTL, mode->surface_cntl); 1496 1497 radeon_write_pll_regs(rinfo, mode); 1498 1499 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1500 radeon_fifo_wait(10); 1501 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); 1502 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); 1503 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); 1504 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid); 1505 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch); 1506 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); 1507 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); 1508 OUTREG(TMDS_CRC, mode->tmds_crc); 1509 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); 1510 } 1511 1512 if (!regs_only) 1513 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); 1514 1515 radeon_fifo_wait(2); 1516 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); 1517 1518 return; 1519 } 1520 1521 /* 1522 * Calculate the PLL values for a given mode 1523 */ 1524 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs, 1525 unsigned long freq) 1526 { 1527 static const struct { 1528 int divider; 1529 int bitvalue; 1530 } *post_div, 1531 post_divs[] = { 1532 { 1, 0 }, 1533 { 2, 1 }, 1534 { 4, 2 }, 1535 { 8, 3 }, 1536 { 3, 4 }, 1537 { 16, 5 }, 1538 { 6, 6 }, 1539 { 12, 7 }, 1540 { 0, 0 }, 1541 }; 1542 int fb_div, pll_output_freq = 0; 1543 int uses_dvo = 0; 1544 1545 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm 1546 * not sure which model starts having FP2_GEN_CNTL, I assume anything more 1547 * recent than an r(v)100... 1548 */ 1549 #if 1 1550 /* XXX I had reports of flicker happening with the cinema display 1551 * on TMDS1 that seem to be fixed if I also forbit odd dividers in 1552 * this case. This could just be a bandwidth calculation issue, I 1553 * haven't implemented the bandwidth code yet, but in the meantime, 1554 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects, 1555 * I haven't seen a case were were absolutely needed an odd PLL 1556 * divider. I'll find a better fix once I have more infos on the 1557 * real cause of the problem. 1558 */ 1559 while (rinfo->has_CRTC2) { 1560 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL); 1561 u32 disp_output_cntl; 1562 int source; 1563 1564 /* FP2 path not enabled */ 1565 if ((fp2_gen_cntl & FP2_ON) == 0) 1566 break; 1567 /* Not all chip revs have the same format for this register, 1568 * extract the source selection 1569 */ 1570 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) { 1571 source = (fp2_gen_cntl >> 10) & 0x3; 1572 /* sourced from transform unit, check for transform unit 1573 * own source 1574 */ 1575 if (source == 3) { 1576 disp_output_cntl = INREG(DISP_OUTPUT_CNTL); 1577 source = (disp_output_cntl >> 12) & 0x3; 1578 } 1579 } else 1580 source = (fp2_gen_cntl >> 13) & 0x1; 1581 /* sourced from CRTC2 -> exit */ 1582 if (source == 1) 1583 break; 1584 1585 /* so we end up on CRTC1, let's set uses_dvo to 1 now */ 1586 uses_dvo = 1; 1587 break; 1588 } 1589 #else 1590 uses_dvo = 1; 1591 #endif 1592 if (freq > rinfo->pll.ppll_max) 1593 freq = rinfo->pll.ppll_max; 1594 if (freq*12 < rinfo->pll.ppll_min) 1595 freq = rinfo->pll.ppll_min / 12; 1596 pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n", 1597 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max); 1598 1599 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 1600 pll_output_freq = post_div->divider * freq; 1601 /* If we output to the DVO port (external TMDS), we don't allow an 1602 * odd PLL divider as those aren't supported on this path 1603 */ 1604 if (uses_dvo && (post_div->divider & 1)) 1605 continue; 1606 if (pll_output_freq >= rinfo->pll.ppll_min && 1607 pll_output_freq <= rinfo->pll.ppll_max) 1608 break; 1609 } 1610 1611 /* If we fall through the bottom, try the "default value" 1612 given by the terminal post_div->bitvalue */ 1613 if ( !post_div->divider ) { 1614 post_div = &post_divs[post_div->bitvalue]; 1615 pll_output_freq = post_div->divider * freq; 1616 } 1617 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n", 1618 rinfo->pll.ref_div, rinfo->pll.ref_clk, 1619 pll_output_freq); 1620 1621 /* If we fall through the bottom, try the "default value" 1622 given by the terminal post_div->bitvalue */ 1623 if ( !post_div->divider ) { 1624 post_div = &post_divs[post_div->bitvalue]; 1625 pll_output_freq = post_div->divider * freq; 1626 } 1627 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n", 1628 rinfo->pll.ref_div, rinfo->pll.ref_clk, 1629 pll_output_freq); 1630 1631 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, 1632 rinfo->pll.ref_clk); 1633 regs->ppll_ref_div = rinfo->pll.ref_div; 1634 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); 1635 1636 pr_debug("post div = 0x%x\n", post_div->bitvalue); 1637 pr_debug("fb_div = 0x%x\n", fb_div); 1638 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3); 1639 } 1640 1641 static int radeonfb_set_par(struct fb_info *info) 1642 { 1643 struct radeonfb_info *rinfo = info->par; 1644 struct fb_var_screeninfo *mode = &info->var; 1645 struct radeon_regs *newmode; 1646 int hTotal, vTotal, hSyncStart, hSyncEnd, 1647 vSyncStart, vSyncEnd; 1648 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5}; 1649 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5}; 1650 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock; 1651 int i, freq; 1652 int format = 0; 1653 int nopllcalc = 0; 1654 int hsync_start, hsync_fudge, hsync_wid, vsync_wid; 1655 int primary_mon = PRIMARY_MONITOR(rinfo); 1656 int depth = var_to_depth(mode); 1657 int use_rmx = 0; 1658 1659 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL); 1660 if (!newmode) 1661 return -ENOMEM; 1662 1663 /* We always want engine to be idle on a mode switch, even 1664 * if we won't actually change the mode 1665 */ 1666 radeon_engine_idle(); 1667 1668 hSyncStart = mode->xres + mode->right_margin; 1669 hSyncEnd = hSyncStart + mode->hsync_len; 1670 hTotal = hSyncEnd + mode->left_margin; 1671 1672 vSyncStart = mode->yres + mode->lower_margin; 1673 vSyncEnd = vSyncStart + mode->vsync_len; 1674 vTotal = vSyncEnd + mode->upper_margin; 1675 pixClock = mode->pixclock; 1676 1677 sync = mode->sync; 1678 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 1679 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 1680 1681 if (primary_mon == MT_DFP || primary_mon == MT_LCD) { 1682 if (rinfo->panel_info.xres < mode->xres) 1683 mode->xres = rinfo->panel_info.xres; 1684 if (rinfo->panel_info.yres < mode->yres) 1685 mode->yres = rinfo->panel_info.yres; 1686 1687 hTotal = mode->xres + rinfo->panel_info.hblank; 1688 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus; 1689 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width; 1690 1691 vTotal = mode->yres + rinfo->panel_info.vblank; 1692 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus; 1693 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width; 1694 1695 h_sync_pol = !rinfo->panel_info.hAct_high; 1696 v_sync_pol = !rinfo->panel_info.vAct_high; 1697 1698 pixClock = 100000000 / rinfo->panel_info.clock; 1699 1700 if (rinfo->panel_info.use_bios_dividers) { 1701 nopllcalc = 1; 1702 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider | 1703 (rinfo->panel_info.post_divider << 16); 1704 newmode->ppll_ref_div = rinfo->panel_info.ref_divider; 1705 } 1706 } 1707 dotClock = 1000000000 / pixClock; 1708 freq = dotClock / 10; /* x100 */ 1709 1710 pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n", 1711 hSyncStart, hSyncEnd, hTotal); 1712 pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n", 1713 vSyncStart, vSyncEnd, vTotal); 1714 1715 hsync_wid = (hSyncEnd - hSyncStart) / 8; 1716 vsync_wid = vSyncEnd - vSyncStart; 1717 if (hsync_wid == 0) 1718 hsync_wid = 1; 1719 else if (hsync_wid > 0x3f) /* max */ 1720 hsync_wid = 0x3f; 1721 1722 if (vsync_wid == 0) 1723 vsync_wid = 1; 1724 else if (vsync_wid > 0x1f) /* max */ 1725 vsync_wid = 0x1f; 1726 1727 format = radeon_get_dstbpp(depth); 1728 1729 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) 1730 hsync_fudge = hsync_fudge_fp[format-1]; 1731 else 1732 hsync_fudge = hsync_adj_tab[format-1]; 1733 1734 hsync_start = hSyncStart - 8 + hsync_fudge; 1735 1736 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | 1737 (format << 8); 1738 1739 /* Clear auto-center etc... */ 1740 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl; 1741 newmode->crtc_more_cntl &= 0xfffffff0; 1742 1743 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1744 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN; 1745 if (mirror) 1746 newmode->crtc_ext_cntl |= CRTC_CRT_ON; 1747 1748 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN | 1749 CRTC_INTERLACE_EN); 1750 } else { 1751 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | 1752 CRTC_CRT_ON; 1753 } 1754 1755 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN | 1756 DAC_8BIT_EN; 1757 1758 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) | 1759 (((mode->xres / 8) - 1) << 16)); 1760 1761 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) | 1762 (hsync_wid << 16) | (h_sync_pol << 23)); 1763 1764 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | 1765 ((mode->yres - 1) << 16); 1766 1767 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) | 1768 (vsync_wid << 16) | (v_sync_pol << 23)); 1769 1770 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { 1771 /* We first calculate the engine pitch */ 1772 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f) 1773 & ~(0x3f)) >> 6; 1774 1775 /* Then, re-multiply it to get the CRTC pitch */ 1776 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8); 1777 } else 1778 newmode->crtc_pitch = (mode->xres_virtual >> 3); 1779 1780 newmode->crtc_pitch |= (newmode->crtc_pitch << 16); 1781 1782 /* 1783 * It looks like recent chips have a problem with SURFACE_CNTL, 1784 * setting SURF_TRANSLATION_DIS completely disables the 1785 * swapper as well, so we leave it unset now. 1786 */ 1787 newmode->surface_cntl = 0; 1788 1789 #if defined(__BIG_ENDIAN) 1790 1791 /* Setup swapping on both apertures, though we currently 1792 * only use aperture 0, enabling swapper on aperture 1 1793 * won't harm 1794 */ 1795 switch (mode->bits_per_pixel) { 1796 case 16: 1797 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP; 1798 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP; 1799 break; 1800 case 24: 1801 case 32: 1802 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP; 1803 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP; 1804 break; 1805 } 1806 #endif 1807 1808 /* Clear surface registers */ 1809 for (i=0; i<8; i++) { 1810 newmode->surf_lower_bound[i] = 0; 1811 newmode->surf_upper_bound[i] = 0x1f; 1812 newmode->surf_info[i] = 0; 1813 } 1814 1815 pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n", 1816 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid); 1817 pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n", 1818 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid); 1819 1820 rinfo->bpp = mode->bits_per_pixel; 1821 rinfo->depth = depth; 1822 1823 pr_debug("pixclock = %lu\n", (unsigned long)pixClock); 1824 pr_debug("freq = %lu\n", (unsigned long)freq); 1825 1826 /* We use PPLL_DIV_3 */ 1827 newmode->clk_cntl_index = 0x300; 1828 1829 /* Calculate PPLL value if necessary */ 1830 if (!nopllcalc) 1831 radeon_calc_pll_regs(rinfo, newmode, freq); 1832 1833 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl; 1834 1835 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1836 unsigned int hRatio, vRatio; 1837 1838 if (mode->xres > rinfo->panel_info.xres) 1839 mode->xres = rinfo->panel_info.xres; 1840 if (mode->yres > rinfo->panel_info.yres) 1841 mode->yres = rinfo->panel_info.yres; 1842 1843 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1) 1844 << HORZ_PANEL_SHIFT); 1845 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1) 1846 << VERT_PANEL_SHIFT); 1847 1848 if (mode->xres != rinfo->panel_info.xres) { 1849 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX, 1850 rinfo->panel_info.xres); 1851 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) | 1852 (newmode->fp_horz_stretch & 1853 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH | 1854 HORZ_AUTO_RATIO_INC))); 1855 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND | 1856 HORZ_STRETCH_ENABLE); 1857 use_rmx = 1; 1858 } 1859 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO; 1860 1861 if (mode->yres != rinfo->panel_info.yres) { 1862 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX, 1863 rinfo->panel_info.yres); 1864 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) | 1865 (newmode->fp_vert_stretch & 1866 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED))); 1867 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND | 1868 VERT_STRETCH_ENABLE); 1869 use_rmx = 1; 1870 } 1871 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN; 1872 1873 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32) 1874 ~(FP_SEL_CRTC2 | 1875 FP_RMX_HVSYNC_CONTROL_EN | 1876 FP_DFP_SYNC_SEL | 1877 FP_CRT_SYNC_SEL | 1878 FP_CRTC_LOCK_8DOT | 1879 FP_USE_SHADOW_EN | 1880 FP_CRTC_USE_SHADOW_VEND | 1881 FP_CRT_SYNC_ALT)); 1882 1883 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR | 1884 FP_CRTC_DONT_SHADOW_HEND | 1885 FP_PANEL_FORMAT); 1886 1887 if (IS_R300_VARIANT(rinfo) || 1888 (rinfo->family == CHIP_FAMILY_R200)) { 1889 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 1890 if (use_rmx) 1891 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; 1892 else 1893 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; 1894 } else 1895 newmode->fp_gen_cntl |= FP_SEL_CRTC1; 1896 1897 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl; 1898 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl; 1899 newmode->tmds_crc = rinfo->init_state.tmds_crc; 1900 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl; 1901 1902 if (primary_mon == MT_LCD) { 1903 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON); 1904 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN); 1905 } else { 1906 /* DFP */ 1907 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); 1908 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST); 1909 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */ 1910 if (IS_R300_VARIANT(rinfo) || 1911 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2) 1912 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN; 1913 else 1914 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN; 1915 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON; 1916 } 1917 1918 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) | 1919 (((mode->xres / 8) - 1) << 16)); 1920 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) | 1921 ((mode->yres - 1) << 16); 1922 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) | 1923 (hsync_wid << 16) | (h_sync_pol << 23)); 1924 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) | 1925 (vsync_wid << 16) | (v_sync_pol << 23)); 1926 } 1927 1928 /* do it! */ 1929 if (!rinfo->asleep) { 1930 memcpy(&rinfo->state, newmode, sizeof(*newmode)); 1931 radeon_write_mode (rinfo, newmode, 0); 1932 /* (re)initialize the engine */ 1933 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) 1934 radeonfb_engine_init (rinfo); 1935 } 1936 /* Update fix */ 1937 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) 1938 info->fix.line_length = rinfo->pitch*64; 1939 else 1940 info->fix.line_length = mode->xres_virtual 1941 * ((mode->bits_per_pixel + 1) / 8); 1942 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR 1943 : FB_VISUAL_DIRECTCOLOR; 1944 1945 #ifdef CONFIG_BOOTX_TEXT 1946 /* Update debug text engine */ 1947 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres, 1948 rinfo->depth, info->fix.line_length); 1949 #endif 1950 1951 kfree(newmode); 1952 return 0; 1953 } 1954 1955 1956 static const struct fb_ops radeonfb_ops = { 1957 .owner = THIS_MODULE, 1958 .fb_check_var = radeonfb_check_var, 1959 .fb_set_par = radeonfb_set_par, 1960 .fb_setcolreg = radeonfb_setcolreg, 1961 .fb_setcmap = radeonfb_setcmap, 1962 .fb_pan_display = radeonfb_pan_display, 1963 .fb_blank = radeonfb_blank, 1964 .fb_ioctl = radeonfb_ioctl, 1965 .fb_sync = radeonfb_sync, 1966 .fb_fillrect = radeonfb_fillrect, 1967 .fb_copyarea = radeonfb_copyarea, 1968 .fb_imageblit = radeonfb_imageblit, 1969 }; 1970 1971 1972 static int radeon_set_fbinfo(struct radeonfb_info *rinfo) 1973 { 1974 struct fb_info *info = rinfo->info; 1975 1976 info->par = rinfo; 1977 info->pseudo_palette = rinfo->pseudo_palette; 1978 info->flags = FBINFO_DEFAULT 1979 | FBINFO_HWACCEL_COPYAREA 1980 | FBINFO_HWACCEL_FILLRECT 1981 | FBINFO_HWACCEL_XPAN 1982 | FBINFO_HWACCEL_YPAN; 1983 info->fbops = &radeonfb_ops; 1984 info->screen_base = rinfo->fb_base; 1985 info->screen_size = rinfo->mapped_vram; 1986 /* Fill fix common fields */ 1987 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); 1988 info->fix.smem_start = rinfo->fb_base_phys; 1989 info->fix.smem_len = rinfo->video_ram; 1990 info->fix.type = FB_TYPE_PACKED_PIXELS; 1991 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 1992 info->fix.xpanstep = 8; 1993 info->fix.ypanstep = 1; 1994 info->fix.ywrapstep = 0; 1995 info->fix.type_aux = 0; 1996 info->fix.mmio_start = rinfo->mmio_base_phys; 1997 info->fix.mmio_len = RADEON_REGSIZE; 1998 info->fix.accel = FB_ACCEL_ATI_RADEON; 1999 2000 fb_alloc_cmap(&info->cmap, 256, 0); 2001 2002 if (noaccel) 2003 info->flags |= FBINFO_HWACCEL_DISABLED; 2004 2005 return 0; 2006 } 2007 2008 /* 2009 * This reconfigure the card's internal memory map. In theory, we'd like 2010 * to setup the card's memory at the same address as it's PCI bus address, 2011 * and the AGP aperture right after that so that system RAM on 32 bits 2012 * machines at least, is directly accessible. However, doing so would 2013 * conflict with the current XFree drivers... 2014 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree 2015 * on the proper way to set this up and duplicate this here. In the meantime, 2016 * I put the card's memory at 0 in card space and AGP at some random high 2017 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway 2018 */ 2019 #ifdef CONFIG_PPC 2020 #undef SET_MC_FB_FROM_APERTURE 2021 static void fixup_memory_mappings(struct radeonfb_info *rinfo) 2022 { 2023 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0; 2024 u32 save_crtc_ext_cntl; 2025 u32 aper_base, aper_size; 2026 u32 agp_base; 2027 2028 /* First, we disable display to avoid interfering */ 2029 if (rinfo->has_CRTC2) { 2030 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL); 2031 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B); 2032 } 2033 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL); 2034 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL); 2035 2036 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS); 2037 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B); 2038 mdelay(100); 2039 2040 aper_base = INREG(CNFG_APER_0_BASE); 2041 aper_size = INREG(CNFG_APER_SIZE); 2042 2043 #ifdef SET_MC_FB_FROM_APERTURE 2044 /* Set framebuffer to be at the same address as set in PCI BAR */ 2045 OUTREG(MC_FB_LOCATION, 2046 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16)); 2047 rinfo->fb_local_base = aper_base; 2048 #else 2049 OUTREG(MC_FB_LOCATION, 0x7fff0000); 2050 rinfo->fb_local_base = 0; 2051 #endif 2052 agp_base = aper_base + aper_size; 2053 if (agp_base & 0xf0000000) 2054 agp_base = (aper_base | 0x0fffffff) + 1; 2055 2056 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This 2057 * assumes the FB isn't mapped to 0xf0000000 or above, but this is 2058 * always the case on PPCs afaik. 2059 */ 2060 #ifdef SET_MC_FB_FROM_APERTURE 2061 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16)); 2062 #else 2063 OUTREG(MC_AGP_LOCATION, 0xffffe000); 2064 #endif 2065 2066 /* Fixup the display base addresses & engine offsets while we 2067 * are at it as well 2068 */ 2069 #ifdef SET_MC_FB_FROM_APERTURE 2070 OUTREG(DISPLAY_BASE_ADDR, aper_base); 2071 if (rinfo->has_CRTC2) 2072 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base); 2073 OUTREG(OV0_BASE_ADDR, aper_base); 2074 #else 2075 OUTREG(DISPLAY_BASE_ADDR, 0); 2076 if (rinfo->has_CRTC2) 2077 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0); 2078 OUTREG(OV0_BASE_ADDR, 0); 2079 #endif 2080 mdelay(100); 2081 2082 /* Restore display settings */ 2083 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl); 2084 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl); 2085 if (rinfo->has_CRTC2) 2086 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl); 2087 2088 pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n", 2089 aper_base, 2090 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16), 2091 0xffff0000 | (agp_base >> 16)); 2092 } 2093 #endif /* CONFIG_PPC */ 2094 2095 2096 static void radeon_identify_vram(struct radeonfb_info *rinfo) 2097 { 2098 u32 tmp; 2099 2100 /* framebuffer size */ 2101 if ((rinfo->family == CHIP_FAMILY_RS100) || 2102 (rinfo->family == CHIP_FAMILY_RS200) || 2103 (rinfo->family == CHIP_FAMILY_RS300) || 2104 (rinfo->family == CHIP_FAMILY_RC410) || 2105 (rinfo->family == CHIP_FAMILY_RS400) || 2106 (rinfo->family == CHIP_FAMILY_RS480) ) { 2107 u32 tom = INREG(NB_TOM); 2108 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); 2109 2110 radeon_fifo_wait(6); 2111 OUTREG(MC_FB_LOCATION, tom); 2112 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2113 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2114 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); 2115 2116 /* This is supposed to fix the crtc2 noise problem. */ 2117 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); 2118 2119 if ((rinfo->family == CHIP_FAMILY_RS100) || 2120 (rinfo->family == CHIP_FAMILY_RS200)) { 2121 /* This is to workaround the asic bug for RMX, some versions 2122 of BIOS doesn't have this register initialized correctly. 2123 */ 2124 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, 2125 ~CRTC_H_CUTOFF_ACTIVE_EN); 2126 } 2127 } else { 2128 tmp = INREG(CNFG_MEMSIZE); 2129 } 2130 2131 /* mem size is bits [28:0], mask off the rest */ 2132 rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK; 2133 2134 /* 2135 * Hack to get around some busted production M6's 2136 * reporting no ram 2137 */ 2138 if (rinfo->video_ram == 0) { 2139 switch (rinfo->pdev->device) { 2140 case PCI_CHIP_RADEON_LY: 2141 case PCI_CHIP_RADEON_LZ: 2142 rinfo->video_ram = 8192 * 1024; 2143 break; 2144 default: 2145 break; 2146 } 2147 } 2148 2149 2150 /* 2151 * Now try to identify VRAM type 2152 */ 2153 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) || 2154 (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) 2155 rinfo->vram_ddr = 1; 2156 else 2157 rinfo->vram_ddr = 0; 2158 2159 tmp = INREG(MEM_CNTL); 2160 if (IS_R300_VARIANT(rinfo)) { 2161 tmp &= R300_MEM_NUM_CHANNELS_MASK; 2162 switch (tmp) { 2163 case 0: rinfo->vram_width = 64; break; 2164 case 1: rinfo->vram_width = 128; break; 2165 case 2: rinfo->vram_width = 256; break; 2166 default: rinfo->vram_width = 128; break; 2167 } 2168 } else if ((rinfo->family == CHIP_FAMILY_RV100) || 2169 (rinfo->family == CHIP_FAMILY_RS100) || 2170 (rinfo->family == CHIP_FAMILY_RS200)){ 2171 if (tmp & RV100_MEM_HALF_MODE) 2172 rinfo->vram_width = 32; 2173 else 2174 rinfo->vram_width = 64; 2175 } else { 2176 if (tmp & MEM_NUM_CHANNELS_MASK) 2177 rinfo->vram_width = 128; 2178 else 2179 rinfo->vram_width = 64; 2180 } 2181 2182 /* This may not be correct, as some cards can have half of channel disabled 2183 * ToDo: identify these cases 2184 */ 2185 2186 pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n", 2187 pci_name(rinfo->pdev), 2188 rinfo->video_ram / 1024, 2189 rinfo->vram_ddr ? "DDR" : "SDRAM", 2190 rinfo->vram_width); 2191 } 2192 2193 /* 2194 * Sysfs 2195 */ 2196 2197 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid) 2198 { 2199 return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH); 2200 } 2201 2202 2203 static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj, 2204 struct bin_attribute *bin_attr, 2205 char *buf, loff_t off, size_t count) 2206 { 2207 struct device *dev = container_of(kobj, struct device, kobj); 2208 struct fb_info *info = dev_get_drvdata(dev); 2209 struct radeonfb_info *rinfo = info->par; 2210 2211 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID); 2212 } 2213 2214 2215 static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj, 2216 struct bin_attribute *bin_attr, 2217 char *buf, loff_t off, size_t count) 2218 { 2219 struct device *dev = container_of(kobj, struct device, kobj); 2220 struct fb_info *info = dev_get_drvdata(dev); 2221 struct radeonfb_info *rinfo = info->par; 2222 2223 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID); 2224 } 2225 2226 static const struct bin_attribute edid1_attr = { 2227 .attr = { 2228 .name = "edid1", 2229 .mode = 0444, 2230 }, 2231 .size = EDID_LENGTH, 2232 .read = radeon_show_edid1, 2233 }; 2234 2235 static const struct bin_attribute edid2_attr = { 2236 .attr = { 2237 .name = "edid2", 2238 .mode = 0444, 2239 }, 2240 .size = EDID_LENGTH, 2241 .read = radeon_show_edid2, 2242 }; 2243 2244 static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 2245 { 2246 struct apertures_struct *ap; 2247 2248 ap = alloc_apertures(1); 2249 if (!ap) 2250 return -ENOMEM; 2251 2252 ap->ranges[0].base = pci_resource_start(pdev, 0); 2253 ap->ranges[0].size = pci_resource_len(pdev, 0); 2254 2255 remove_conflicting_framebuffers(ap, KBUILD_MODNAME, false); 2256 2257 kfree(ap); 2258 2259 return 0; 2260 } 2261 2262 static int radeonfb_pci_register(struct pci_dev *pdev, 2263 const struct pci_device_id *ent) 2264 { 2265 struct fb_info *info; 2266 struct radeonfb_info *rinfo; 2267 int ret; 2268 unsigned char c1, c2; 2269 int err = 0; 2270 2271 pr_debug("radeonfb_pci_register BEGIN\n"); 2272 2273 /* Enable device in PCI config */ 2274 ret = pci_enable_device(pdev); 2275 if (ret < 0) { 2276 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n", 2277 pci_name(pdev)); 2278 goto err_out; 2279 } 2280 2281 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev); 2282 if (!info) { 2283 ret = -ENOMEM; 2284 goto err_disable; 2285 } 2286 rinfo = info->par; 2287 rinfo->info = info; 2288 rinfo->pdev = pdev; 2289 2290 spin_lock_init(&rinfo->reg_lock); 2291 timer_setup(&rinfo->lvds_timer, radeon_lvds_timer_func, 0); 2292 2293 c1 = ent->device >> 8; 2294 c2 = ent->device & 0xff; 2295 if (isprint(c1) && isprint(c2)) 2296 snprintf(rinfo->name, sizeof(rinfo->name), 2297 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2); 2298 else 2299 snprintf(rinfo->name, sizeof(rinfo->name), 2300 "ATI Radeon %x", ent->device & 0xffff); 2301 2302 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK; 2303 rinfo->chipset = pdev->device; 2304 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0; 2305 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0; 2306 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0; 2307 2308 /* Set base addrs */ 2309 rinfo->fb_base_phys = pci_resource_start (pdev, 0); 2310 rinfo->mmio_base_phys = pci_resource_start (pdev, 2); 2311 2312 ret = radeon_kick_out_firmware_fb(pdev); 2313 if (ret) 2314 return ret; 2315 2316 /* request the mem regions */ 2317 ret = pci_request_region(pdev, 0, "radeonfb framebuffer"); 2318 if (ret < 0) { 2319 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n", 2320 pci_name(rinfo->pdev)); 2321 goto err_release_fb; 2322 } 2323 2324 ret = pci_request_region(pdev, 2, "radeonfb mmio"); 2325 if (ret < 0) { 2326 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n", 2327 pci_name(rinfo->pdev)); 2328 goto err_release_pci0; 2329 } 2330 2331 /* map the regions */ 2332 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE); 2333 if (!rinfo->mmio_base) { 2334 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n", 2335 pci_name(rinfo->pdev)); 2336 ret = -EIO; 2337 goto err_release_pci2; 2338 } 2339 2340 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; 2341 2342 /* 2343 * Check for errata 2344 */ 2345 rinfo->errata = 0; 2346 if (rinfo->family == CHIP_FAMILY_R300 && 2347 (INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) 2348 == CFG_ATI_REV_A11) 2349 rinfo->errata |= CHIP_ERRATA_R300_CG; 2350 2351 if (rinfo->family == CHIP_FAMILY_RV200 || 2352 rinfo->family == CHIP_FAMILY_RS200) 2353 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2354 2355 if (rinfo->family == CHIP_FAMILY_RV100 || 2356 rinfo->family == CHIP_FAMILY_RS100 || 2357 rinfo->family == CHIP_FAMILY_RS200) 2358 rinfo->errata |= CHIP_ERRATA_PLL_DELAY; 2359 2360 #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) 2361 /* On PPC, we obtain the OF device-node pointer to the firmware 2362 * data for this chip 2363 */ 2364 rinfo->of_node = pci_device_to_OF_node(pdev); 2365 if (rinfo->of_node == NULL) 2366 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n", 2367 pci_name(rinfo->pdev)); 2368 2369 #endif /* CONFIG_PPC || CONFIG_SPARC */ 2370 #ifdef CONFIG_PPC 2371 /* On PPC, the firmware sets up a memory mapping that tends 2372 * to cause lockups when enabling the engine. We reconfigure 2373 * the card internal memory mappings properly 2374 */ 2375 fixup_memory_mappings(rinfo); 2376 #endif /* CONFIG_PPC */ 2377 2378 /* Get VRAM size and type */ 2379 radeon_identify_vram(rinfo); 2380 2381 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram); 2382 2383 do { 2384 rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys, 2385 rinfo->mapped_vram); 2386 } while (rinfo->fb_base == NULL && 2387 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM)); 2388 2389 if (rinfo->fb_base == NULL) { 2390 printk (KERN_ERR "radeonfb (%s): cannot map FB\n", 2391 pci_name(rinfo->pdev)); 2392 ret = -EIO; 2393 goto err_unmap_rom; 2394 } 2395 2396 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev), 2397 rinfo->mapped_vram/1024); 2398 2399 /* 2400 * Map the BIOS ROM if any and retrieve PLL parameters from 2401 * the BIOS. We skip that on mobility chips as the real panel 2402 * values we need aren't in the ROM but in the BIOS image in 2403 * memory. This is definitely not the best meacnism though, 2404 * we really need the arch code to tell us which is the "primary" 2405 * video adapter to use the memory image (or better, the arch 2406 * should provide us a copy of the BIOS image to shield us from 2407 * archs who would store that elsewhere and/or could initialize 2408 * more than one adapter during boot). 2409 */ 2410 if (!rinfo->is_mobility) 2411 radeon_map_ROM(rinfo, pdev); 2412 2413 /* 2414 * On x86, the primary display on laptop may have it's BIOS 2415 * ROM elsewhere, try to locate it at the legacy memory hole. 2416 * We probably need to make sure this is the primary display, 2417 * but that is difficult without some arch support. 2418 */ 2419 #ifdef CONFIG_X86 2420 if (rinfo->bios_seg == NULL) 2421 radeon_find_mem_vbios(rinfo); 2422 #endif 2423 2424 /* If both above failed, try the BIOS ROM again for mobility 2425 * chips 2426 */ 2427 if (rinfo->bios_seg == NULL && rinfo->is_mobility) 2428 radeon_map_ROM(rinfo, pdev); 2429 2430 /* Get informations about the board's PLL */ 2431 radeon_get_pllinfo(rinfo); 2432 2433 #ifdef CONFIG_FB_RADEON_I2C 2434 /* Register I2C bus */ 2435 radeon_create_i2c_busses(rinfo); 2436 #endif 2437 2438 /* set all the vital stuff */ 2439 radeon_set_fbinfo (rinfo); 2440 2441 /* Probe screen types */ 2442 radeon_probe_screens(rinfo, monitor_layout, ignore_edid); 2443 2444 /* Build mode list, check out panel native model */ 2445 radeon_check_modes(rinfo, mode_option); 2446 2447 /* Register some sysfs stuff (should be done better) */ 2448 if (rinfo->mon1_EDID) 2449 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, 2450 &edid1_attr); 2451 if (rinfo->mon2_EDID) 2452 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, 2453 &edid2_attr); 2454 if (err) 2455 pr_warn("%s() Creating sysfs files failed, continuing\n", 2456 __func__); 2457 2458 /* save current mode regs before we switch into the new one 2459 * so we can restore this upon __exit 2460 */ 2461 radeon_save_state (rinfo, &rinfo->init_state); 2462 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs)); 2463 2464 /* Setup Power Management capabilities */ 2465 if (default_dynclk < -1) { 2466 /* -2 is special: means ON on mobility chips and do not 2467 * change on others 2468 */ 2469 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep); 2470 } else 2471 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep); 2472 2473 pci_set_drvdata(pdev, info); 2474 2475 /* Register with fbdev layer */ 2476 ret = register_framebuffer(info); 2477 if (ret < 0) { 2478 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n", 2479 pci_name(rinfo->pdev)); 2480 goto err_unmap_fb; 2481 } 2482 2483 if (!nomtrr) 2484 rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys, 2485 rinfo->video_ram); 2486 2487 if (backlight) 2488 radeonfb_bl_init(rinfo); 2489 2490 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name); 2491 2492 if (rinfo->bios_seg) 2493 radeon_unmap_ROM(rinfo, pdev); 2494 pr_debug("radeonfb_pci_register END\n"); 2495 2496 return 0; 2497 err_unmap_fb: 2498 iounmap(rinfo->fb_base); 2499 err_unmap_rom: 2500 kfree(rinfo->mon1_EDID); 2501 kfree(rinfo->mon2_EDID); 2502 if (rinfo->mon1_modedb) 2503 fb_destroy_modedb(rinfo->mon1_modedb); 2504 fb_dealloc_cmap(&info->cmap); 2505 #ifdef CONFIG_FB_RADEON_I2C 2506 radeon_delete_i2c_busses(rinfo); 2507 #endif 2508 if (rinfo->bios_seg) 2509 radeon_unmap_ROM(rinfo, pdev); 2510 iounmap(rinfo->mmio_base); 2511 err_release_pci2: 2512 pci_release_region(pdev, 2); 2513 err_release_pci0: 2514 pci_release_region(pdev, 0); 2515 err_release_fb: 2516 framebuffer_release(info); 2517 err_disable: 2518 err_out: 2519 return ret; 2520 } 2521 2522 2523 2524 static void radeonfb_pci_unregister(struct pci_dev *pdev) 2525 { 2526 struct fb_info *info = pci_get_drvdata(pdev); 2527 struct radeonfb_info *rinfo = info->par; 2528 2529 if (!rinfo) 2530 return; 2531 2532 radeonfb_pm_exit(rinfo); 2533 2534 if (rinfo->mon1_EDID) 2535 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr); 2536 if (rinfo->mon2_EDID) 2537 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr); 2538 2539 del_timer_sync(&rinfo->lvds_timer); 2540 arch_phys_wc_del(rinfo->wc_cookie); 2541 unregister_framebuffer(info); 2542 2543 radeonfb_bl_exit(rinfo); 2544 2545 iounmap(rinfo->mmio_base); 2546 iounmap(rinfo->fb_base); 2547 2548 pci_release_region(pdev, 2); 2549 pci_release_region(pdev, 0); 2550 2551 kfree(rinfo->mon1_EDID); 2552 kfree(rinfo->mon2_EDID); 2553 if (rinfo->mon1_modedb) 2554 fb_destroy_modedb(rinfo->mon1_modedb); 2555 #ifdef CONFIG_FB_RADEON_I2C 2556 radeon_delete_i2c_busses(rinfo); 2557 #endif 2558 fb_dealloc_cmap(&info->cmap); 2559 framebuffer_release(info); 2560 } 2561 2562 2563 static struct pci_driver radeonfb_driver = { 2564 .name = "radeonfb", 2565 .id_table = radeonfb_pci_table, 2566 .probe = radeonfb_pci_register, 2567 .remove = radeonfb_pci_unregister, 2568 #ifdef CONFIG_PM 2569 .suspend = radeonfb_pci_suspend, 2570 .resume = radeonfb_pci_resume, 2571 #endif /* CONFIG_PM */ 2572 }; 2573 2574 #ifndef MODULE 2575 static int __init radeonfb_setup (char *options) 2576 { 2577 char *this_opt; 2578 2579 if (!options || !*options) 2580 return 0; 2581 2582 while ((this_opt = strsep (&options, ",")) != NULL) { 2583 if (!*this_opt) 2584 continue; 2585 2586 if (!strncmp(this_opt, "noaccel", 7)) { 2587 noaccel = 1; 2588 } else if (!strncmp(this_opt, "mirror", 6)) { 2589 mirror = 1; 2590 } else if (!strncmp(this_opt, "force_dfp", 9)) { 2591 force_dfp = 1; 2592 } else if (!strncmp(this_opt, "panel_yres:", 11)) { 2593 panel_yres = simple_strtoul((this_opt+11), NULL, 0); 2594 } else if (!strncmp(this_opt, "backlight:", 10)) { 2595 backlight = simple_strtoul(this_opt+10, NULL, 0); 2596 } else if (!strncmp(this_opt, "nomtrr", 6)) { 2597 nomtrr = 1; 2598 } else if (!strncmp(this_opt, "nomodeset", 9)) { 2599 nomodeset = 1; 2600 } else if (!strncmp(this_opt, "force_measure_pll", 17)) { 2601 force_measure_pll = 1; 2602 } else if (!strncmp(this_opt, "ignore_edid", 11)) { 2603 ignore_edid = 1; 2604 #if defined(CONFIG_PM) && defined(CONFIG_X86) 2605 } else if (!strncmp(this_opt, "force_sleep", 11)) { 2606 force_sleep = 1; 2607 } else if (!strncmp(this_opt, "ignore_devlist", 14)) { 2608 ignore_devlist = 1; 2609 #endif 2610 } else 2611 mode_option = this_opt; 2612 } 2613 return 0; 2614 } 2615 #endif /* MODULE */ 2616 2617 static int __init radeonfb_init (void) 2618 { 2619 #ifndef MODULE 2620 char *option = NULL; 2621 2622 if (fb_get_options("radeonfb", &option)) 2623 return -ENODEV; 2624 radeonfb_setup(option); 2625 #endif 2626 return pci_register_driver (&radeonfb_driver); 2627 } 2628 2629 2630 static void __exit radeonfb_exit (void) 2631 { 2632 pci_unregister_driver (&radeonfb_driver); 2633 } 2634 2635 module_init(radeonfb_init); 2636 module_exit(radeonfb_exit); 2637 2638 MODULE_AUTHOR("Ani Joshi"); 2639 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset"); 2640 MODULE_LICENSE("GPL"); 2641 module_param(noaccel, bool, 0); 2642 module_param(default_dynclk, int, 0); 2643 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on"); 2644 MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); 2645 module_param(nomodeset, bool, 0); 2646 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode"); 2647 module_param(mirror, bool, 0); 2648 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors"); 2649 module_param(force_dfp, bool, 0); 2650 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp"); 2651 module_param(ignore_edid, bool, 0); 2652 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe"); 2653 module_param(monitor_layout, charp, 0); 2654 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)"); 2655 module_param(force_measure_pll, bool, 0); 2656 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)"); 2657 module_param(nomtrr, bool, 0); 2658 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers"); 2659 module_param(panel_yres, int, 0); 2660 MODULE_PARM_DESC(panel_yres, "int: set panel yres"); 2661 module_param(mode_option, charp, 0); 2662 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); 2663 #if defined(CONFIG_PM) && defined(CONFIG_X86) 2664 module_param(force_sleep, bool, 0); 2665 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware"); 2666 module_param(ignore_devlist, bool, 0); 2667 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops"); 2668 #endif 2669