1 // SPDX-License-Identifier: GPL-2.0
2 
3 /*
4  *  ATI Mach64 CT/VT/GT/LT Support
5  */
6 
7 #include <linux/fb.h>
8 #include <linux/delay.h>
9 #include <asm/io.h>
10 #include <video/mach64.h>
11 #include "atyfb.h"
12 #ifdef CONFIG_PPC
13 #include <asm/machdep.h>
14 #endif
15 
16 #undef DEBUG
17 
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt       (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
22 
23 u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par)
24 {
25 	u8 res;
26 
27 	/* write addr byte */
28 	aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par);
29 	/* read the register value */
30 	res = aty_ld_8(CLOCK_CNTL_DATA, par);
31 	return res;
32 }
33 
34 static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par)
35 {
36 	/* write addr byte */
37 	aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par);
38 	/* write the register value */
39 	aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par);
40 	aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par);
41 }
42 
43 /*
44  * by Daniel Mantione
45  *                                  <daniel.mantione@freepascal.org>
46  *
47  *
48  * ATI Mach64 CT clock synthesis description.
49  *
50  * All clocks on the Mach64 can be calculated using the same principle:
51  *
52  *       XTALIN * x * FB_DIV
53  * CLK = ----------------------
54  *       PLL_REF_DIV * POST_DIV
55  *
56  * XTALIN is a fixed speed clock. Common speeds are 14.31 MHz and 29.50 MHz.
57  * PLL_REF_DIV can be set by the user, but is the same for all clocks.
58  * FB_DIV can be set by the user for each clock individually, it should be set
59  * between 128 and 255, the chip will generate a bad clock signal for too low
60  * values.
61  * x depends on the type of clock; usually it is 2, but for the MCLK it can also
62  * be set to 4.
63  * POST_DIV can be set by the user for each clock individually, Possible values
64  * are 1,2,4,8 and for some clocks other values are available too.
65  * CLK is of course the clock speed that is generated.
66  *
67  * The Mach64 has these clocks:
68  *
69  * MCLK			The clock rate of the chip
70  * XCLK			The clock rate of the on-chip memory
71  * VCLK0		First pixel clock of first CRT controller
72  * VCLK1    Second pixel clock of first CRT controller
73  * VCLK2		Third pixel clock of first CRT controller
74  * VCLK3    Fourth pixel clock of first CRT controller
75  * VCLK			Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
76  * V2CLK		Pixel clock of the second CRT controller.
77  * SCLK			Multi-purpose clock
78  *
79  * - MCLK and XCLK use the same FB_DIV
80  * - VCLK0 .. VCLK3 use the same FB_DIV
81  * - V2CLK is needed when the second CRTC is used (can be used for dualhead);
82  *   i.e. CRT monitor connected to laptop has different resolution than built
83  *   in LCD monitor.
84  * - SCLK is not available on all cards; it is know to exist on the Rage LT-PRO,
85  *   Rage XL and Rage Mobility. It is know not to exist on the Mach64 VT.
86  * - V2CLK is not available on all cards, most likely only the Rage LT-PRO,
87  *   the Rage XL and the Rage Mobility
88  *
89  * SCLK can be used to:
90  * - Clock the chip instead of MCLK
91  * - Replace XTALIN with a user defined frequency
92  * - Generate the pixel clock for the LCD monitor (instead of VCLK)
93  */
94 
95  /*
96   * It can be quite hard to calculate XCLK and MCLK if they don't run at the
97   * same frequency. Luckily, until now all cards that need asynchrone clock
98   * speeds seem to have SCLK.
99   * So this driver uses SCLK to clock the chip and XCLK to clock the memory.
100   */
101 
102 /* ------------------------------------------------------------------------- */
103 
104 /*
105  *  PLL programming (Mach64 CT family)
106  *
107  *
108  * This procedure sets the display fifo. The display fifo is a buffer that
109  * contains data read from the video memory that waits to be processed by
110  * the CRT controller.
111  *
112  * On the more modern Mach64 variants, the chip doesn't calculate the
113  * interval after which the display fifo has to be reloaded from memory
114  * automatically, the driver has to do it instead.
115  */
116 
117 #define Maximum_DSP_PRECISION 7
118 const u8 aty_postdividers[8] = {1,2,4,8,3,5,6,12};
119 
120 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll)
121 {
122 	u32 dsp_off, dsp_on, dsp_xclks;
123 	u32 multiplier, divider, ras_multiplier, ras_divider, tmp;
124 	u8 vshift, xshift;
125 	s8 dsp_precision;
126 
127 	multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real;
128 	divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
129 
130 	ras_multiplier = pll->xclkmaxrasdelay;
131 	ras_divider = 1;
132 
133 	if (bpp>=8)
134 		divider = divider * (bpp >> 2);
135 
136 	vshift = (6 - 2) - pll->xclk_post_div;	/* FIFO is 64 bits wide in accelerator mode ... */
137 
138 	if (bpp == 0)
139 		vshift--;	/* ... but only 32 bits in VGA mode. */
140 
141 #ifdef CONFIG_FB_ATY_GENERIC_LCD
142 	if (pll->xres != 0) {
143 		struct atyfb_par *par = (struct atyfb_par *) info->par;
144 
145 		multiplier = multiplier * par->lcd_width;
146 		divider = divider * pll->xres & ~7;
147 
148 		ras_multiplier = ras_multiplier * par->lcd_width;
149 		ras_divider = ras_divider * pll->xres & ~7;
150 	}
151 #endif
152 	/* If we don't do this, 32 bits for multiplier & divider won't be
153 	enough in certain situations! */
154 	while (((multiplier | divider) & 1) == 0) {
155 		multiplier = multiplier >> 1;
156 		divider = divider >> 1;
157 	}
158 
159 	/* Determine DSP precision first */
160 	tmp = ((multiplier * pll->fifo_size) << vshift) / divider;
161 
162 	for (dsp_precision = -5;  tmp;  dsp_precision++)
163 		tmp >>= 1;
164 	if (dsp_precision < 0)
165 		dsp_precision = 0;
166 	else if (dsp_precision > Maximum_DSP_PRECISION)
167 		dsp_precision = Maximum_DSP_PRECISION;
168 
169 	xshift = 6 - dsp_precision;
170 	vshift += xshift;
171 
172 	/* Move on to dsp_off */
173 	dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider -
174 		(1 << (vshift - xshift));
175 
176 /*    if (bpp == 0)
177         dsp_on = ((multiplier * 20 << vshift) + divider) / divider;
178     else */
179 	{
180 		dsp_on = ((multiplier << vshift) + divider) / divider;
181 		tmp = ((ras_multiplier << xshift) + ras_divider) / ras_divider;
182 		if (dsp_on < tmp)
183 			dsp_on = tmp;
184 		dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift);
185 	}
186 
187 	/* Calculate rounding factor and apply it to dsp_on */
188 	tmp = ((1 << (Maximum_DSP_PRECISION - dsp_precision)) - 1) >> 1;
189 	dsp_on = ((dsp_on + tmp) / (tmp + 1)) * (tmp + 1);
190 
191 	if (dsp_on >= ((dsp_off / (tmp + 1)) * (tmp + 1))) {
192 		dsp_on = dsp_off - (multiplier << vshift) / divider;
193 		dsp_on = (dsp_on / (tmp + 1)) * (tmp + 1);
194 	}
195 
196 	/* Last but not least:  dsp_xclks */
197 	dsp_xclks = ((multiplier << (vshift + 5)) + divider) / divider;
198 
199 	/* Get register values. */
200 	pll->dsp_on_off = (dsp_on << 16) + dsp_off;
201 	pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks;
202 #ifdef DEBUG
203 	printk("atyfb(%s): dsp_config 0x%08x, dsp_on_off 0x%08x\n",
204 		__func__, pll->dsp_config, pll->dsp_on_off);
205 #endif
206 	return 0;
207 }
208 
209 static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll)
210 {
211 	u32 q;
212 	struct atyfb_par *par = (struct atyfb_par *) info->par;
213 	int pllvclk;
214 
215 	/* FIXME: use the VTB/GTB /{3,6,12} post dividers if they're better suited */
216 	q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
217 	if (q < 16*8 || q > 255*8) {
218 		printk(KERN_CRIT "atyfb: vclk out of range\n");
219 		return -EINVAL;
220 	} else {
221 		pll->vclk_post_div  = (q < 128*8);
222 		pll->vclk_post_div += (q <  64*8);
223 		pll->vclk_post_div += (q <  32*8);
224 	}
225 	pll->vclk_post_div_real = aty_postdividers[pll->vclk_post_div];
226 	//    pll->vclk_post_div <<= 6;
227 	pll->vclk_fb_div = q * pll->vclk_post_div_real / 8;
228 	pllvclk = (1000000 * 2 * pll->vclk_fb_div) /
229 		(par->ref_clk_per * pll->pll_ref_div);
230 #ifdef DEBUG
231 	printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n",
232 		__func__, pllvclk, pllvclk / pll->vclk_post_div_real);
233 #endif
234 	pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
235 
236 	/* Set ECP (scaler/overlay clock) divider */
237 	if (par->pll_limits.ecp_max) {
238 		int ecp = pllvclk / pll->vclk_post_div_real;
239 		int ecp_div = 0;
240 
241 		while (ecp > par->pll_limits.ecp_max && ecp_div < 2) {
242 			ecp >>= 1;
243 			ecp_div++;
244 		}
245 		pll->pll_vclk_cntl |= ecp_div << 4;
246 	}
247 
248 	return 0;
249 }
250 
251 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll)
252 {
253 	struct atyfb_par *par = (struct atyfb_par *) info->par;
254 	int err;
255 
256 	if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
257 		return err;
258 	if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
259 		return err;
260 	/*aty_calc_pll_ct(info, &pll->ct);*/
261 	return 0;
262 }
263 
264 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll)
265 {
266 	struct atyfb_par *par = (struct atyfb_par *) info->par;
267 	u32 ret;
268 	ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
269 #ifdef CONFIG_FB_ATY_GENERIC_LCD
270 	if(pll->ct.xres > 0) {
271 		ret *= par->lcd_width;
272 		ret /= pll->ct.xres;
273 	}
274 #endif
275 #ifdef DEBUG
276 	printk("atyfb(%s): calculated 0x%08X(%i)\n", __func__, ret, ret);
277 #endif
278 	return ret;
279 }
280 
281 void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll)
282 {
283 	struct atyfb_par *par = (struct atyfb_par *) info->par;
284 	u32 crtc_gen_cntl;
285 	u8 tmp, tmp2;
286 
287 #ifdef CONFIG_FB_ATY_GENERIC_LCD
288 	u32 lcd_gen_cntrl = 0;
289 #endif
290 
291 #ifdef DEBUG
292 	printk("atyfb(%s): about to program:\n"
293 		"pll_ext_cntl=0x%02x pll_gen_cntl=0x%02x pll_vclk_cntl=0x%02x\n",
294 		__func__,
295 		pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl);
296 
297 	printk("atyfb(%s): setting clock %lu for FeedBackDivider %i, ReferenceDivider %i, PostDivider %i(%i)\n",
298 		__func__,
299 		par->clk_wr_offset, pll->ct.vclk_fb_div,
300 		pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
301 #endif
302 #ifdef CONFIG_FB_ATY_GENERIC_LCD
303 	if (par->lcd_table != 0) {
304 		/* turn off LCD */
305 		lcd_gen_cntrl = aty_ld_lcd(LCD_GEN_CNTL, par);
306 		aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl & ~LCD_ON, par);
307 	}
308 #endif
309 	aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par);
310 
311 	/* Temporarily switch to accelerator mode */
312 	crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
313 	if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN))
314 		aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN, par);
315 
316 	/* Reset VCLK generator */
317 	aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
318 
319 	/* Set post-divider */
320 	tmp2 = par->clk_wr_offset << 1;
321 	tmp = aty_ld_pll_ct(VCLK_POST_DIV, par);
322 	tmp &= ~(0x03U << tmp2);
323 	tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2);
324 	aty_st_pll_ct(VCLK_POST_DIV, tmp, par);
325 
326 	/* Set extended post-divider */
327 	tmp = aty_ld_pll_ct(PLL_EXT_CNTL, par);
328 	tmp &= ~(0x10U << par->clk_wr_offset);
329 	tmp &= 0xF0U;
330 	tmp |= pll->ct.pll_ext_cntl;
331 	aty_st_pll_ct(PLL_EXT_CNTL, tmp, par);
332 
333 	/* Set feedback divider */
334 	tmp = VCLK0_FB_DIV + par->clk_wr_offset;
335 	aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
336 
337 	aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
338 
339 	/* End VCLK generator reset */
340 	aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
341 	mdelay(5);
342 
343 	aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
344 	aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
345 	mdelay(1);
346 
347 	/* Restore mode register */
348 	if (!(crtc_gen_cntl & CRTC_EXT_DISP_EN))
349 		aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl, par);
350 
351 	if (M64_HAS(GTB_DSP)) {
352 		u8 dll_cntl;
353 
354 		if (M64_HAS(XL_DLL))
355 			dll_cntl = 0x80;
356 		else if (par->ram_type >= SDRAM)
357 			dll_cntl = 0xa6;
358 		else
359 			dll_cntl = 0xa0;
360 		aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
361 		aty_st_pll_ct(VFC_CNTL, 0x1b, par);
362 		aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
363 		aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
364 
365 		mdelay(10);
366 		aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
367 		mdelay(10);
368 		aty_st_pll_ct(DLL_CNTL, dll_cntl | 0x40, par);
369 		mdelay(10);
370 		aty_st_pll_ct(DLL_CNTL, dll_cntl & ~0x40, par);
371 	}
372 #ifdef CONFIG_FB_ATY_GENERIC_LCD
373 	if (par->lcd_table != 0) {
374 		/* restore LCD */
375 		aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl, par);
376 	}
377 #endif
378 }
379 
380 static void aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll)
381 {
382 	struct atyfb_par *par = (struct atyfb_par *) info->par;
383 	u8 tmp, clock;
384 
385 	clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
386 	tmp = clock << 1;
387 	pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
388 
389 	pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
390 	pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
391 	pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
392 	pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
393 
394 	pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
395 	pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
396 
397 	if (M64_HAS(GTB_DSP)) {
398 		pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
399 		pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
400 	}
401 }
402 
403 static int aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll)
404 {
405 	struct atyfb_par *par = (struct atyfb_par *) info->par;
406 	u8 mpost_div, xpost_div, sclk_post_div_real;
407 	u32 q, memcntl, trp;
408 	u32 dsp_config;
409 #ifdef DEBUG
410 	int pllmclk, pllsclk;
411 #endif
412 	pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
413 	pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07;
414 	pll->ct.xclk_ref_div = 1;
415 	switch (pll->ct.xclk_post_div) {
416 	case 0:  case 1:  case 2:  case 3:
417 		break;
418 
419 	case 4:
420 		pll->ct.xclk_ref_div = 3;
421 		pll->ct.xclk_post_div = 0;
422 		break;
423 
424 	default:
425 		printk(KERN_CRIT "atyfb: Unsupported xclk source:  %d.\n", pll->ct.xclk_post_div);
426 		return -EINVAL;
427 	}
428 	pll->ct.mclk_fb_mult = 2;
429 	if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) {
430 		pll->ct.mclk_fb_mult = 4;
431 		pll->ct.xclk_post_div -= 1;
432 	}
433 
434 #ifdef DEBUG
435 	printk("atyfb(%s): mclk_fb_mult=%d, xclk_post_div=%d\n",
436 		__func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div);
437 #endif
438 
439 	memcntl = aty_ld_le32(MEM_CNTL, par);
440 	trp = (memcntl & 0x300) >> 8;
441 
442 	pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2;
443 	pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2;
444 
445 	if (M64_HAS(FIFO_32)) {
446 		pll->ct.fifo_size = 32;
447 	} else {
448 		pll->ct.fifo_size = 24;
449 		pll->ct.xclkpagefaultdelay += 2;
450 		pll->ct.xclkmaxrasdelay += 3;
451 	}
452 
453 	switch (par->ram_type) {
454 	case DRAM:
455 		if (info->fix.smem_len<=ONE_MB) {
456 			pll->ct.dsp_loop_latency = 10;
457 		} else {
458 			pll->ct.dsp_loop_latency = 8;
459 			pll->ct.xclkpagefaultdelay += 2;
460 		}
461 		break;
462 	case EDO:
463 	case PSEUDO_EDO:
464 		if (info->fix.smem_len<=ONE_MB) {
465 			pll->ct.dsp_loop_latency = 9;
466 		} else {
467 			pll->ct.dsp_loop_latency = 8;
468 			pll->ct.xclkpagefaultdelay += 1;
469 		}
470 		break;
471 	case SDRAM:
472 		if (info->fix.smem_len<=ONE_MB) {
473 			pll->ct.dsp_loop_latency = 11;
474 		} else {
475 			pll->ct.dsp_loop_latency = 10;
476 			pll->ct.xclkpagefaultdelay += 1;
477 		}
478 		break;
479 	case SGRAM:
480 		pll->ct.dsp_loop_latency = 8;
481 		pll->ct.xclkpagefaultdelay += 3;
482 		break;
483 	default:
484 		pll->ct.dsp_loop_latency = 11;
485 		pll->ct.xclkpagefaultdelay += 3;
486 		break;
487 	}
488 
489 	if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay)
490 		pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1;
491 
492 	/* Allow BIOS to override */
493 	dsp_config = aty_ld_le32(DSP_CONFIG, par);
494 	aty_ld_le32(DSP_ON_OFF, par);
495 	aty_ld_le32(VGA_DSP_CONFIG, par);
496 	aty_ld_le32(VGA_DSP_ON_OFF, par);
497 
498 	if (dsp_config)
499 		pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16;
500 #if 0
501 	FIXME: is it relevant for us?
502 	if ((!dsp_on_off && !M64_HAS(RESET_3D)) ||
503 		((dsp_on_off == vga_dsp_on_off) &&
504 		(!dsp_config || !((dsp_config ^ vga_dsp_config) & DSP_XCLKS_PER_QW)))) {
505 		vga_dsp_on_off &= VGA_DSP_OFF;
506 		vga_dsp_config &= VGA_DSP_XCLKS_PER_QW;
507 		if (ATIDivide(vga_dsp_on_off, vga_dsp_config, 5, 1) > 24)
508 			pll->ct.fifo_size = 32;
509 		else
510 			pll->ct.fifo_size = 24;
511 	}
512 #endif
513 	/* Exit if the user does not want us to tamper with the clock
514 	rates of her chip. */
515 	if (par->mclk_per == 0) {
516 		u8 mclk_fb_div, pll_ext_cntl;
517 		pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
518 		pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
519 		pll->ct.xclk_post_div_real = aty_postdividers[pll_ext_cntl & 0x07];
520 		mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
521 		if (pll_ext_cntl & PLL_MFB_TIMES_4_2B)
522 			mclk_fb_div <<= 1;
523 		pll->ct.mclk_fb_div = mclk_fb_div;
524 		return 0;
525 	}
526 
527 	pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
528 
529 	/* FIXME: use the VTB/GTB /3 post divider if it's better suited */
530 	q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
531 		(pll->ct.mclk_fb_mult * par->xclk_per);
532 
533 	if (q < 16*8 || q > 255*8) {
534 		printk(KERN_CRIT "atxfb: xclk out of range\n");
535 		return -EINVAL;
536 	} else {
537 		xpost_div  = (q < 128*8);
538 		xpost_div += (q <  64*8);
539 		xpost_div += (q <  32*8);
540 	}
541 	pll->ct.xclk_post_div_real = aty_postdividers[xpost_div];
542 	pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8;
543 
544 #ifdef CONFIG_PPC
545 	if (machine_is(powermac)) {
546 		/* Override PLL_EXT_CNTL & 0x07. */
547 		pll->ct.xclk_post_div = xpost_div;
548 		pll->ct.xclk_ref_div = 1;
549 	}
550 #endif
551 
552 #ifdef DEBUG
553 	pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) /
554 			(par->ref_clk_per * pll->ct.pll_ref_div);
555 	printk("atyfb(%s): pllmclk=%d MHz, xclk=%d MHz\n",
556 		__func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real);
557 #endif
558 
559 	if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM))
560 		pll->ct.pll_gen_cntl = OSC_EN;
561 	else
562 		pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */;
563 
564 	if (M64_HAS(MAGIC_POSTDIV))
565 		pll->ct.pll_ext_cntl = 0;
566 	else
567 		pll->ct.pll_ext_cntl = xpost_div;
568 
569 	if (pll->ct.mclk_fb_mult == 4)
570 		pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B;
571 
572 	if (par->mclk_per == par->xclk_per) {
573 		pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */
574 	} else {
575 		/*
576 		* The chip clock is not equal to the memory clock.
577 		* Therefore we will use sclk to clock the chip.
578 		*/
579 		pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */
580 
581 		q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
582 		if (q < 16*8 || q > 255*8) {
583 			printk(KERN_CRIT "atyfb: mclk out of range\n");
584 			return -EINVAL;
585 		} else {
586 			mpost_div  = (q < 128*8);
587 			mpost_div += (q <  64*8);
588 			mpost_div += (q <  32*8);
589 		}
590 		sclk_post_div_real = aty_postdividers[mpost_div];
591 		pll->ct.sclk_fb_div = q * sclk_post_div_real / 8;
592 		pll->ct.spll_cntl2 = mpost_div << 4;
593 #ifdef DEBUG
594 		pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) /
595 			(par->ref_clk_per * pll->ct.pll_ref_div);
596 		printk("atyfb(%s): use sclk, pllsclk=%d MHz, sclk=mclk=%d MHz\n",
597 			__func__, pllsclk, pllsclk / sclk_post_div_real);
598 #endif
599 	}
600 
601 	/* Disable the extra precision pixel clock controls since we do not use them. */
602 	pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par);
603 	pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC);
604 
605 	return 0;
606 }
607 
608 static void aty_resume_pll_ct(const struct fb_info *info,
609 			      union aty_pll *pll)
610 {
611 	struct atyfb_par *par = info->par;
612 
613 	if (par->mclk_per != par->xclk_per) {
614 		/*
615 		* This disables the sclk, crashes the computer as reported:
616 		* aty_st_pll_ct(SPLL_CNTL2, 3, info);
617 		*
618 		* So it seems the sclk must be enabled before it is used;
619 		* so PLL_GEN_CNTL must be programmed *after* the sclk.
620 		*/
621 		aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
622 		aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
623 		/*
624 		 * SCLK has been started. Wait for the PLL to lock. 5 ms
625 		 * should be enough according to mach64 programmer's guide.
626 		 */
627 		mdelay(5);
628 	}
629 
630 	aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
631 	aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
632 	aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
633 	aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
634 	aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par);
635 }
636 
637 static int dummy(void)
638 {
639 	return 0;
640 }
641 
642 const struct aty_dac_ops aty_dac_ct = {
643 	.set_dac	= (void *) dummy,
644 };
645 
646 const struct aty_pll_ops aty_pll_ct = {
647 	.var_to_pll	= aty_var_to_pll_ct,
648 	.pll_to_var	= aty_pll_to_var_ct,
649 	.set_pll	= aty_set_pll_ct,
650 	.get_pll	= aty_get_pll_ct,
651 	.init_pll	= aty_init_pll_ct,
652 	.resume_pll	= aty_resume_pll_ct,
653 };
654