1 // SPDX-License-Identifier: GPL-2.0-only 2 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $ 3 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128 4 * 5 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com> 6 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu> 7 * 8 * Ani Joshi / Jeff Garzik 9 * - Code cleanup 10 * 11 * Michel Danzer <michdaen@iiic.ethz.ch> 12 * - 15/16 bit cleanup 13 * - fix panning 14 * 15 * Benjamin Herrenschmidt 16 * - pmac-specific PM stuff 17 * - various fixes & cleanups 18 * 19 * Andreas Hundt <andi@convergence.de> 20 * - FB_ACTIVATE fixes 21 * 22 * Paul Mackerras <paulus@samba.org> 23 * - Convert to new framebuffer API, 24 * fix colormap setting at 16 bits/pixel (565) 25 * 26 * Paul Mundt 27 * - PCI hotplug 28 * 29 * Jon Smirl <jonsmirl@yahoo.com> 30 * - PCI ID update 31 * - replace ROM BIOS search 32 * 33 * Based off of Geert's atyfb.c and vfb.c. 34 * 35 * TODO: 36 * - monitor sensing (DDC) 37 * - virtual display 38 * - other platform support (only ppc/x86 supported) 39 * - hardware cursor support 40 * 41 * Please cc: your patches to brad@neruo.com. 42 */ 43 44 /* 45 * A special note of gratitude to ATI's devrel for providing documentation, 46 * example code and hardware. Thanks Nitya. -atong and brad 47 */ 48 49 50 #include <linux/module.h> 51 #include <linux/moduleparam.h> 52 #include <linux/kernel.h> 53 #include <linux/errno.h> 54 #include <linux/string.h> 55 #include <linux/mm.h> 56 #include <linux/vmalloc.h> 57 #include <linux/delay.h> 58 #include <linux/interrupt.h> 59 #include <linux/uaccess.h> 60 #include <linux/fb.h> 61 #include <linux/init.h> 62 #include <linux/pci.h> 63 #include <linux/ioport.h> 64 #include <linux/console.h> 65 #include <linux/backlight.h> 66 #include <asm/io.h> 67 68 #ifdef CONFIG_PPC_PMAC 69 #include <asm/machdep.h> 70 #include <asm/pmac_feature.h> 71 #include <asm/prom.h> 72 #include "../macmodes.h" 73 #endif 74 75 #ifdef CONFIG_PMAC_BACKLIGHT 76 #include <asm/backlight.h> 77 #endif 78 79 #ifdef CONFIG_BOOTX_TEXT 80 #include <asm/btext.h> 81 #endif /* CONFIG_BOOTX_TEXT */ 82 83 #include <video/aty128.h> 84 85 /* Debug flag */ 86 #undef DEBUG 87 88 #ifdef DEBUG 89 #define DBG(fmt, args...) \ 90 printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args); 91 #else 92 #define DBG(fmt, args...) 93 #endif 94 95 #ifndef CONFIG_PPC_PMAC 96 /* default mode */ 97 static const struct fb_var_screeninfo default_var = { 98 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */ 99 640, 480, 640, 480, 0, 0, 8, 0, 100 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 101 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2, 102 0, FB_VMODE_NONINTERLACED 103 }; 104 105 #else /* CONFIG_PPC_PMAC */ 106 /* default to 1024x768 at 75Hz on PPC - this will work 107 * on the iMac, the usual 640x480 @ 60Hz doesn't. */ 108 static const struct fb_var_screeninfo default_var = { 109 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */ 110 1024, 768, 1024, 768, 0, 0, 8, 0, 111 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 112 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3, 113 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 114 FB_VMODE_NONINTERLACED 115 }; 116 #endif /* CONFIG_PPC_PMAC */ 117 118 /* default modedb mode */ 119 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */ 120 static const struct fb_videomode defaultmode = { 121 .refresh = 60, 122 .xres = 640, 123 .yres = 480, 124 .pixclock = 39722, 125 .left_margin = 48, 126 .right_margin = 16, 127 .upper_margin = 33, 128 .lower_margin = 10, 129 .hsync_len = 96, 130 .vsync_len = 2, 131 .sync = 0, 132 .vmode = FB_VMODE_NONINTERLACED 133 }; 134 135 /* Chip generations */ 136 enum { 137 rage_128, 138 rage_128_pci, 139 rage_128_pro, 140 rage_128_pro_pci, 141 rage_M3, 142 rage_M3_pci, 143 rage_M4, 144 rage_128_ultra, 145 }; 146 147 /* Must match above enum */ 148 static char * const r128_family[] = { 149 "AGP", 150 "PCI", 151 "PRO AGP", 152 "PRO PCI", 153 "M3 AGP", 154 "M3 PCI", 155 "M4 AGP", 156 "Ultra AGP", 157 }; 158 159 /* 160 * PCI driver prototypes 161 */ 162 static int aty128_probe(struct pci_dev *pdev, 163 const struct pci_device_id *ent); 164 static void aty128_remove(struct pci_dev *pdev); 165 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state); 166 static int aty128_pci_resume(struct pci_dev *pdev); 167 static int aty128_do_resume(struct pci_dev *pdev); 168 169 /* supported Rage128 chipsets */ 170 static const struct pci_device_id aty128_pci_tbl[] = { 171 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE, 172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci }, 173 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF, 174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 }, 175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF, 176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, 177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML, 178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, 179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA, 180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB, 182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC, 184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD, 186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE, 188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF, 190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG, 192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH, 194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI, 196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ, 198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK, 200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL, 202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM, 204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN, 206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO, 208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP, 210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ, 212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR, 214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS, 216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT, 218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU, 220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV, 222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW, 224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX, 226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE, 228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF, 230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG, 232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK, 234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL, 236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE, 238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF, 240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG, 242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH, 244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK, 246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL, 248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM, 250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN, 252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF, 254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL, 256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR, 258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS, 260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT, 262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU, 264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 265 { 0, } 266 }; 267 268 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl); 269 270 static struct pci_driver aty128fb_driver = { 271 .name = "aty128fb", 272 .id_table = aty128_pci_tbl, 273 .probe = aty128_probe, 274 .remove = aty128_remove, 275 .suspend = aty128_pci_suspend, 276 .resume = aty128_pci_resume, 277 }; 278 279 /* packed BIOS settings */ 280 #ifndef CONFIG_PPC 281 typedef struct { 282 u8 clock_chip_type; 283 u8 struct_size; 284 u8 accelerator_entry; 285 u8 VGA_entry; 286 u16 VGA_table_offset; 287 u16 POST_table_offset; 288 u16 XCLK; 289 u16 MCLK; 290 u8 num_PLL_blocks; 291 u8 size_PLL_blocks; 292 u16 PCLK_ref_freq; 293 u16 PCLK_ref_divider; 294 u32 PCLK_min_freq; 295 u32 PCLK_max_freq; 296 u16 MCLK_ref_freq; 297 u16 MCLK_ref_divider; 298 u32 MCLK_min_freq; 299 u32 MCLK_max_freq; 300 u16 XCLK_ref_freq; 301 u16 XCLK_ref_divider; 302 u32 XCLK_min_freq; 303 u32 XCLK_max_freq; 304 } __attribute__ ((packed)) PLL_BLOCK; 305 #endif /* !CONFIG_PPC */ 306 307 /* onboard memory information */ 308 struct aty128_meminfo { 309 u8 ML; 310 u8 MB; 311 u8 Trcd; 312 u8 Trp; 313 u8 Twr; 314 u8 CL; 315 u8 Tr2w; 316 u8 LoopLatency; 317 u8 DspOn; 318 u8 Rloop; 319 const char *name; 320 }; 321 322 /* various memory configurations */ 323 static const struct aty128_meminfo sdr_128 = { 324 .ML = 4, 325 .MB = 4, 326 .Trcd = 3, 327 .Trp = 3, 328 .Twr = 1, 329 .CL = 3, 330 .Tr2w = 1, 331 .LoopLatency = 16, 332 .DspOn = 30, 333 .Rloop = 16, 334 .name = "128-bit SDR SGRAM (1:1)", 335 }; 336 337 static const struct aty128_meminfo sdr_sgram = { 338 .ML = 4, 339 .MB = 4, 340 .Trcd = 1, 341 .Trp = 2, 342 .Twr = 1, 343 .CL = 2, 344 .Tr2w = 1, 345 .LoopLatency = 16, 346 .DspOn = 24, 347 .Rloop = 16, 348 .name = "64-bit SDR SGRAM (2:1)", 349 }; 350 351 static const struct aty128_meminfo ddr_sgram = { 352 .ML = 4, 353 .MB = 4, 354 .Trcd = 3, 355 .Trp = 3, 356 .Twr = 2, 357 .CL = 3, 358 .Tr2w = 1, 359 .LoopLatency = 16, 360 .DspOn = 31, 361 .Rloop = 16, 362 .name = "64-bit DDR SGRAM", 363 }; 364 365 static const struct fb_fix_screeninfo aty128fb_fix = { 366 .id = "ATY Rage128", 367 .type = FB_TYPE_PACKED_PIXELS, 368 .visual = FB_VISUAL_PSEUDOCOLOR, 369 .xpanstep = 8, 370 .ypanstep = 1, 371 .mmio_len = 0x2000, 372 .accel = FB_ACCEL_ATI_RAGE128, 373 }; 374 375 static char *mode_option = NULL; 376 377 #ifdef CONFIG_PPC_PMAC 378 static int default_vmode = VMODE_1024_768_60; 379 static int default_cmode = CMODE_8; 380 #endif 381 382 static int default_crt_on = 0; 383 static int default_lcd_on = 1; 384 static bool mtrr = true; 385 386 #ifdef CONFIG_FB_ATY128_BACKLIGHT 387 static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT); 388 #endif 389 390 /* PLL constants */ 391 struct aty128_constants { 392 u32 ref_clk; 393 u32 ppll_min; 394 u32 ppll_max; 395 u32 ref_divider; 396 u32 xclk; 397 u32 fifo_width; 398 u32 fifo_depth; 399 }; 400 401 struct aty128_crtc { 402 u32 gen_cntl; 403 u32 h_total, h_sync_strt_wid; 404 u32 v_total, v_sync_strt_wid; 405 u32 pitch; 406 u32 offset, offset_cntl; 407 u32 xoffset, yoffset; 408 u32 vxres, vyres; 409 u32 depth, bpp; 410 }; 411 412 struct aty128_pll { 413 u32 post_divider; 414 u32 feedback_divider; 415 u32 vclk; 416 }; 417 418 struct aty128_ddafifo { 419 u32 dda_config; 420 u32 dda_on_off; 421 }; 422 423 /* register values for a specific mode */ 424 struct aty128fb_par { 425 struct aty128_crtc crtc; 426 struct aty128_pll pll; 427 struct aty128_ddafifo fifo_reg; 428 u32 accel_flags; 429 struct aty128_constants constants; /* PLL and others */ 430 void __iomem *regbase; /* remapped mmio */ 431 u32 vram_size; /* onboard video ram */ 432 int chip_gen; 433 const struct aty128_meminfo *mem; /* onboard mem info */ 434 int wc_cookie; 435 int blitter_may_be_busy; 436 int fifo_slots; /* free slots in FIFO (64 max) */ 437 438 int crt_on, lcd_on; 439 struct pci_dev *pdev; 440 struct fb_info *next; 441 int asleep; 442 int lock_blank; 443 444 u8 red[32]; /* see aty128fb_setcolreg */ 445 u8 green[64]; 446 u8 blue[32]; 447 u32 pseudo_palette[16]; /* used for TRUECOLOR */ 448 }; 449 450 451 #define round_div(n, d) ((n+(d/2))/d) 452 453 static int aty128fb_check_var(struct fb_var_screeninfo *var, 454 struct fb_info *info); 455 static int aty128fb_set_par(struct fb_info *info); 456 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 457 u_int transp, struct fb_info *info); 458 static int aty128fb_pan_display(struct fb_var_screeninfo *var, 459 struct fb_info *fb); 460 static int aty128fb_blank(int blank, struct fb_info *fb); 461 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg); 462 static int aty128fb_sync(struct fb_info *info); 463 464 /* 465 * Internal routines 466 */ 467 468 static int aty128_encode_var(struct fb_var_screeninfo *var, 469 const struct aty128fb_par *par); 470 static int aty128_decode_var(struct fb_var_screeninfo *var, 471 struct aty128fb_par *par); 472 static void aty128_timings(struct aty128fb_par *par); 473 static void aty128_init_engine(struct aty128fb_par *par); 474 static void aty128_reset_engine(const struct aty128fb_par *par); 475 static void aty128_flush_pixel_cache(const struct aty128fb_par *par); 476 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par); 477 static void wait_for_fifo(u16 entries, struct aty128fb_par *par); 478 static void wait_for_idle(struct aty128fb_par *par); 479 static u32 depth_to_dst(u32 depth); 480 481 #ifdef CONFIG_FB_ATY128_BACKLIGHT 482 static void aty128_bl_set_power(struct fb_info *info, int power); 483 #endif 484 485 #define BIOS_IN8(v) (readb(bios + (v))) 486 #define BIOS_IN16(v) (readb(bios + (v)) | \ 487 (readb(bios + (v) + 1) << 8)) 488 #define BIOS_IN32(v) (readb(bios + (v)) | \ 489 (readb(bios + (v) + 1) << 8) | \ 490 (readb(bios + (v) + 2) << 16) | \ 491 (readb(bios + (v) + 3) << 24)) 492 493 494 static const struct fb_ops aty128fb_ops = { 495 .owner = THIS_MODULE, 496 .fb_check_var = aty128fb_check_var, 497 .fb_set_par = aty128fb_set_par, 498 .fb_setcolreg = aty128fb_setcolreg, 499 .fb_pan_display = aty128fb_pan_display, 500 .fb_blank = aty128fb_blank, 501 .fb_ioctl = aty128fb_ioctl, 502 .fb_sync = aty128fb_sync, 503 .fb_fillrect = cfb_fillrect, 504 .fb_copyarea = cfb_copyarea, 505 .fb_imageblit = cfb_imageblit, 506 }; 507 508 /* 509 * Functions to read from/write to the mmio registers 510 * - endian conversions may possibly be avoided by 511 * using the other register aperture. TODO. 512 */ 513 static inline u32 _aty_ld_le32(volatile unsigned int regindex, 514 const struct aty128fb_par *par) 515 { 516 return readl (par->regbase + regindex); 517 } 518 519 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, 520 const struct aty128fb_par *par) 521 { 522 writel (val, par->regbase + regindex); 523 } 524 525 static inline u8 _aty_ld_8(unsigned int regindex, 526 const struct aty128fb_par *par) 527 { 528 return readb (par->regbase + regindex); 529 } 530 531 static inline void _aty_st_8(unsigned int regindex, u8 val, 532 const struct aty128fb_par *par) 533 { 534 writeb (val, par->regbase + regindex); 535 } 536 537 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par) 538 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par) 539 #define aty_ld_8(regindex) _aty_ld_8(regindex, par) 540 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par) 541 542 /* 543 * Functions to read from/write to the pll registers 544 */ 545 546 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par) 547 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par) 548 549 550 static u32 _aty_ld_pll(unsigned int pll_index, 551 const struct aty128fb_par *par) 552 { 553 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); 554 return aty_ld_le32(CLOCK_CNTL_DATA); 555 } 556 557 558 static void _aty_st_pll(unsigned int pll_index, u32 val, 559 const struct aty128fb_par *par) 560 { 561 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); 562 aty_st_le32(CLOCK_CNTL_DATA, val); 563 } 564 565 566 /* return true when the PLL has completed an atomic update */ 567 static int aty_pll_readupdate(const struct aty128fb_par *par) 568 { 569 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); 570 } 571 572 573 static void aty_pll_wait_readupdate(const struct aty128fb_par *par) 574 { 575 unsigned long timeout = jiffies + HZ/100; // should be more than enough 576 int reset = 1; 577 578 while (time_before(jiffies, timeout)) 579 if (aty_pll_readupdate(par)) { 580 reset = 0; 581 break; 582 } 583 584 if (reset) /* reset engine?? */ 585 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n"); 586 } 587 588 589 /* tell PLL to update */ 590 static void aty_pll_writeupdate(const struct aty128fb_par *par) 591 { 592 aty_pll_wait_readupdate(par); 593 594 aty_st_pll(PPLL_REF_DIV, 595 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); 596 } 597 598 599 /* write to the scratch register to test r/w functionality */ 600 static int register_test(const struct aty128fb_par *par) 601 { 602 u32 val; 603 int flag = 0; 604 605 val = aty_ld_le32(BIOS_0_SCRATCH); 606 607 aty_st_le32(BIOS_0_SCRATCH, 0x55555555); 608 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) { 609 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); 610 611 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA) 612 flag = 1; 613 } 614 615 aty_st_le32(BIOS_0_SCRATCH, val); // restore value 616 return flag; 617 } 618 619 620 /* 621 * Accelerator engine functions 622 */ 623 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par) 624 { 625 int i; 626 627 for (;;) { 628 for (i = 0; i < 2000000; i++) { 629 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff; 630 if (par->fifo_slots >= entries) 631 return; 632 } 633 aty128_reset_engine(par); 634 } 635 } 636 637 638 static void wait_for_idle(struct aty128fb_par *par) 639 { 640 int i; 641 642 do_wait_for_fifo(64, par); 643 644 for (;;) { 645 for (i = 0; i < 2000000; i++) { 646 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) { 647 aty128_flush_pixel_cache(par); 648 par->blitter_may_be_busy = 0; 649 return; 650 } 651 } 652 aty128_reset_engine(par); 653 } 654 } 655 656 657 static void wait_for_fifo(u16 entries, struct aty128fb_par *par) 658 { 659 if (par->fifo_slots < entries) 660 do_wait_for_fifo(64, par); 661 par->fifo_slots -= entries; 662 } 663 664 665 static void aty128_flush_pixel_cache(const struct aty128fb_par *par) 666 { 667 int i; 668 u32 tmp; 669 670 tmp = aty_ld_le32(PC_NGUI_CTLSTAT); 671 tmp &= ~(0x00ff); 672 tmp |= 0x00ff; 673 aty_st_le32(PC_NGUI_CTLSTAT, tmp); 674 675 for (i = 0; i < 2000000; i++) 676 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY)) 677 break; 678 } 679 680 681 static void aty128_reset_engine(const struct aty128fb_par *par) 682 { 683 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl; 684 685 aty128_flush_pixel_cache(par); 686 687 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX); 688 mclk_cntl = aty_ld_pll(MCLK_CNTL); 689 690 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000); 691 692 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL); 693 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); 694 aty_ld_le32(GEN_RESET_CNTL); 695 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); 696 aty_ld_le32(GEN_RESET_CNTL); 697 698 aty_st_pll(MCLK_CNTL, mclk_cntl); 699 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); 700 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); 701 702 /* use old pio mode */ 703 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); 704 705 DBG("engine reset"); 706 } 707 708 709 static void aty128_init_engine(struct aty128fb_par *par) 710 { 711 u32 pitch_value; 712 713 wait_for_idle(par); 714 715 /* 3D scaler not spoken here */ 716 wait_for_fifo(1, par); 717 aty_st_le32(SCALE_3D_CNTL, 0x00000000); 718 719 aty128_reset_engine(par); 720 721 pitch_value = par->crtc.pitch; 722 if (par->crtc.bpp == 24) { 723 pitch_value = pitch_value * 3; 724 } 725 726 wait_for_fifo(4, par); 727 /* setup engine offset registers */ 728 aty_st_le32(DEFAULT_OFFSET, 0x00000000); 729 730 /* setup engine pitch registers */ 731 aty_st_le32(DEFAULT_PITCH, pitch_value); 732 733 /* set the default scissor register to max dimensions */ 734 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); 735 736 /* set the drawing controls registers */ 737 aty_st_le32(DP_GUI_MASTER_CNTL, 738 GMC_SRC_PITCH_OFFSET_DEFAULT | 739 GMC_DST_PITCH_OFFSET_DEFAULT | 740 GMC_SRC_CLIP_DEFAULT | 741 GMC_DST_CLIP_DEFAULT | 742 GMC_BRUSH_SOLIDCOLOR | 743 (depth_to_dst(par->crtc.depth) << 8) | 744 GMC_SRC_DSTCOLOR | 745 GMC_BYTE_ORDER_MSB_TO_LSB | 746 GMC_DP_CONVERSION_TEMP_6500 | 747 ROP3_PATCOPY | 748 GMC_DP_SRC_RECT | 749 GMC_3D_FCN_EN_CLR | 750 GMC_DST_CLR_CMP_FCN_CLEAR | 751 GMC_AUX_CLIP_CLEAR | 752 GMC_WRITE_MASK_SET); 753 754 wait_for_fifo(8, par); 755 /* clear the line drawing registers */ 756 aty_st_le32(DST_BRES_ERR, 0); 757 aty_st_le32(DST_BRES_INC, 0); 758 aty_st_le32(DST_BRES_DEC, 0); 759 760 /* set brush color registers */ 761 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ 762 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ 763 764 /* set source color registers */ 765 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ 766 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ 767 768 /* default write mask */ 769 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); 770 771 /* Wait for all the writes to be completed before returning */ 772 wait_for_idle(par); 773 } 774 775 776 /* convert depth values to their register representation */ 777 static u32 depth_to_dst(u32 depth) 778 { 779 if (depth <= 8) 780 return DST_8BPP; 781 else if (depth <= 15) 782 return DST_15BPP; 783 else if (depth == 16) 784 return DST_16BPP; 785 else if (depth <= 24) 786 return DST_24BPP; 787 else if (depth <= 32) 788 return DST_32BPP; 789 790 return -EINVAL; 791 } 792 793 /* 794 * PLL informations retreival 795 */ 796 797 798 #ifndef __sparc__ 799 static void __iomem *aty128_map_ROM(const struct aty128fb_par *par, 800 struct pci_dev *dev) 801 { 802 u16 dptr; 803 u8 rom_type; 804 void __iomem *bios; 805 size_t rom_size; 806 807 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */ 808 unsigned int temp; 809 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); 810 temp &= 0x00ffffffu; 811 temp |= 0x04 << 24; 812 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp); 813 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); 814 815 bios = pci_map_rom(dev, &rom_size); 816 817 if (!bios) { 818 printk(KERN_ERR "aty128fb: ROM failed to map\n"); 819 return NULL; 820 } 821 822 /* Very simple test to make sure it appeared */ 823 if (BIOS_IN16(0) != 0xaa55) { 824 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should " 825 " be 0xaa55\n", BIOS_IN16(0)); 826 goto failed; 827 } 828 829 /* Look for the PCI data to check the ROM type */ 830 dptr = BIOS_IN16(0x18); 831 832 /* Check the PCI data signature. If it's wrong, we still assume a normal 833 * x86 ROM for now, until I've verified this works everywhere. 834 * The goal here is more to phase out Open Firmware images. 835 * 836 * Currently, we only look at the first PCI data, we could iteratre and 837 * deal with them all, and we should use fb_bios_start relative to start 838 * of image and not relative start of ROM, but so far, I never found a 839 * dual-image ATI card. 840 * 841 * typedef struct { 842 * u32 signature; + 0x00 843 * u16 vendor; + 0x04 844 * u16 device; + 0x06 845 * u16 reserved_1; + 0x08 846 * u16 dlen; + 0x0a 847 * u8 drevision; + 0x0c 848 * u8 class_hi; + 0x0d 849 * u16 class_lo; + 0x0e 850 * u16 ilen; + 0x10 851 * u16 irevision; + 0x12 852 * u8 type; + 0x14 853 * u8 indicator; + 0x15 854 * u16 reserved_2; + 0x16 855 * } pci_data_t; 856 */ 857 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 858 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n", 859 BIOS_IN32(dptr)); 860 goto anyway; 861 } 862 rom_type = BIOS_IN8(dptr + 0x14); 863 switch(rom_type) { 864 case 0: 865 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n"); 866 break; 867 case 1: 868 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n"); 869 goto failed; 870 case 2: 871 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n"); 872 goto failed; 873 default: 874 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", 875 rom_type); 876 goto failed; 877 } 878 anyway: 879 return bios; 880 881 failed: 882 pci_unmap_rom(dev, bios); 883 return NULL; 884 } 885 886 static void aty128_get_pllinfo(struct aty128fb_par *par, 887 unsigned char __iomem *bios) 888 { 889 unsigned int bios_hdr; 890 unsigned int bios_pll; 891 892 bios_hdr = BIOS_IN16(0x48); 893 bios_pll = BIOS_IN16(bios_hdr + 0x30); 894 895 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16); 896 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12); 897 par->constants.xclk = BIOS_IN16(bios_pll + 0x08); 898 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10); 899 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e); 900 901 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n", 902 par->constants.ppll_max, par->constants.ppll_min, 903 par->constants.xclk, par->constants.ref_divider, 904 par->constants.ref_clk); 905 906 } 907 908 #ifdef CONFIG_X86 909 static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par) 910 { 911 /* I simplified this code as we used to miss the signatures in 912 * a lot of case. It's now closer to XFree, we just don't check 913 * for signatures at all... Something better will have to be done 914 * if we end up having conflicts 915 */ 916 u32 segstart; 917 unsigned char __iomem *rom_base = NULL; 918 919 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { 920 rom_base = ioremap(segstart, 0x10000); 921 if (rom_base == NULL) 922 return NULL; 923 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) 924 break; 925 iounmap(rom_base); 926 rom_base = NULL; 927 } 928 return rom_base; 929 } 930 #endif 931 #endif /* ndef(__sparc__) */ 932 933 /* fill in known card constants if pll_block is not available */ 934 static void aty128_timings(struct aty128fb_par *par) 935 { 936 #ifdef CONFIG_PPC 937 /* instead of a table lookup, assume OF has properly 938 * setup the PLL registers and use their values 939 * to set the XCLK values and reference divider values */ 940 941 u32 x_mpll_ref_fb_div; 942 u32 xclk_cntl; 943 u32 Nx, M; 944 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 }; 945 #endif 946 947 if (!par->constants.ref_clk) 948 par->constants.ref_clk = 2950; 949 950 #ifdef CONFIG_PPC 951 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV); 952 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7; 953 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8; 954 M = x_mpll_ref_fb_div & 0x0000ff; 955 956 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk), 957 (M * PostDivSet[xclk_cntl])); 958 959 par->constants.ref_divider = 960 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; 961 #endif 962 963 if (!par->constants.ref_divider) { 964 par->constants.ref_divider = 0x3b; 965 966 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e); 967 aty_pll_writeupdate(par); 968 } 969 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); 970 aty_pll_writeupdate(par); 971 972 /* from documentation */ 973 if (!par->constants.ppll_min) 974 par->constants.ppll_min = 12500; 975 if (!par->constants.ppll_max) 976 par->constants.ppll_max = 25000; /* 23000 on some cards? */ 977 if (!par->constants.xclk) 978 par->constants.xclk = 0x1d4d; /* same as mclk */ 979 980 par->constants.fifo_width = 128; 981 par->constants.fifo_depth = 32; 982 983 switch (aty_ld_le32(MEM_CNTL) & 0x3) { 984 case 0: 985 par->mem = &sdr_128; 986 break; 987 case 1: 988 par->mem = &sdr_sgram; 989 break; 990 case 2: 991 par->mem = &ddr_sgram; 992 break; 993 default: 994 par->mem = &sdr_sgram; 995 } 996 } 997 998 999 1000 /* 1001 * CRTC programming 1002 */ 1003 1004 /* Program the CRTC registers */ 1005 static void aty128_set_crtc(const struct aty128_crtc *crtc, 1006 const struct aty128fb_par *par) 1007 { 1008 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); 1009 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); 1010 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1011 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); 1012 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1013 aty_st_le32(CRTC_PITCH, crtc->pitch); 1014 aty_st_le32(CRTC_OFFSET, crtc->offset); 1015 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); 1016 /* Disable ATOMIC updating. Is this the right place? */ 1017 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); 1018 } 1019 1020 1021 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var, 1022 struct aty128_crtc *crtc, 1023 const struct aty128fb_par *par) 1024 { 1025 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst; 1026 u32 left, right, upper, lower, hslen, vslen, sync, vmode; 1027 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol; 1028 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1029 u32 depth, bytpp; 1030 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 }; 1031 1032 /* input */ 1033 xres = var->xres; 1034 yres = var->yres; 1035 vxres = var->xres_virtual; 1036 vyres = var->yres_virtual; 1037 xoffset = var->xoffset; 1038 yoffset = var->yoffset; 1039 bpp = var->bits_per_pixel; 1040 left = var->left_margin; 1041 right = var->right_margin; 1042 upper = var->upper_margin; 1043 lower = var->lower_margin; 1044 hslen = var->hsync_len; 1045 vslen = var->vsync_len; 1046 sync = var->sync; 1047 vmode = var->vmode; 1048 1049 if (bpp != 16) 1050 depth = bpp; 1051 else 1052 depth = (var->green.length == 6) ? 16 : 15; 1053 1054 /* check for mode eligibility 1055 * accept only non interlaced modes */ 1056 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 1057 return -EINVAL; 1058 1059 /* convert (and round up) and validate */ 1060 xres = (xres + 7) & ~7; 1061 xoffset = (xoffset + 7) & ~7; 1062 1063 if (vxres < xres + xoffset) 1064 vxres = xres + xoffset; 1065 1066 if (vyres < yres + yoffset) 1067 vyres = yres + yoffset; 1068 1069 /* convert depth into ATI register depth */ 1070 dst = depth_to_dst(depth); 1071 1072 if (dst == -EINVAL) { 1073 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n"); 1074 return -EINVAL; 1075 } 1076 1077 /* convert register depth to bytes per pixel */ 1078 bytpp = mode_bytpp[dst]; 1079 1080 /* make sure there is enough video ram for the mode */ 1081 if ((u32)(vxres * vyres * bytpp) > par->vram_size) { 1082 printk(KERN_ERR "aty128fb: Not enough memory for mode\n"); 1083 return -EINVAL; 1084 } 1085 1086 h_disp = (xres >> 3) - 1; 1087 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL; 1088 1089 v_disp = yres - 1; 1090 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; 1091 1092 /* check to make sure h_total and v_total are in range */ 1093 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { 1094 printk(KERN_ERR "aty128fb: invalid width ranges\n"); 1095 return -EINVAL; 1096 } 1097 1098 h_sync_wid = (hslen + 7) >> 3; 1099 if (h_sync_wid == 0) 1100 h_sync_wid = 1; 1101 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */ 1102 h_sync_wid = 0x3f; 1103 1104 h_sync_strt = (h_disp << 3) + right; 1105 1106 v_sync_wid = vslen; 1107 if (v_sync_wid == 0) 1108 v_sync_wid = 1; 1109 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */ 1110 v_sync_wid = 0x1f; 1111 1112 v_sync_strt = v_disp + lower; 1113 1114 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 1115 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 1116 1117 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; 1118 1119 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8); 1120 1121 crtc->h_total = h_total | (h_disp << 16); 1122 crtc->v_total = v_total | (v_disp << 16); 1123 1124 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) | 1125 (h_sync_pol << 23); 1126 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) | 1127 (v_sync_pol << 23); 1128 1129 crtc->pitch = vxres >> 3; 1130 1131 crtc->offset = 0; 1132 1133 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) 1134 crtc->offset_cntl = 0x00010000; 1135 else 1136 crtc->offset_cntl = 0; 1137 1138 crtc->vxres = vxres; 1139 crtc->vyres = vyres; 1140 crtc->xoffset = xoffset; 1141 crtc->yoffset = yoffset; 1142 crtc->depth = depth; 1143 crtc->bpp = bpp; 1144 1145 return 0; 1146 } 1147 1148 1149 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var) 1150 { 1151 1152 /* fill in pixel info */ 1153 var->red.msb_right = 0; 1154 var->green.msb_right = 0; 1155 var->blue.offset = 0; 1156 var->blue.msb_right = 0; 1157 var->transp.offset = 0; 1158 var->transp.length = 0; 1159 var->transp.msb_right = 0; 1160 switch (pix_width) { 1161 case CRTC_PIX_WIDTH_8BPP: 1162 var->bits_per_pixel = 8; 1163 var->red.offset = 0; 1164 var->red.length = 8; 1165 var->green.offset = 0; 1166 var->green.length = 8; 1167 var->blue.length = 8; 1168 break; 1169 case CRTC_PIX_WIDTH_15BPP: 1170 var->bits_per_pixel = 16; 1171 var->red.offset = 10; 1172 var->red.length = 5; 1173 var->green.offset = 5; 1174 var->green.length = 5; 1175 var->blue.length = 5; 1176 break; 1177 case CRTC_PIX_WIDTH_16BPP: 1178 var->bits_per_pixel = 16; 1179 var->red.offset = 11; 1180 var->red.length = 5; 1181 var->green.offset = 5; 1182 var->green.length = 6; 1183 var->blue.length = 5; 1184 break; 1185 case CRTC_PIX_WIDTH_24BPP: 1186 var->bits_per_pixel = 24; 1187 var->red.offset = 16; 1188 var->red.length = 8; 1189 var->green.offset = 8; 1190 var->green.length = 8; 1191 var->blue.length = 8; 1192 break; 1193 case CRTC_PIX_WIDTH_32BPP: 1194 var->bits_per_pixel = 32; 1195 var->red.offset = 16; 1196 var->red.length = 8; 1197 var->green.offset = 8; 1198 var->green.length = 8; 1199 var->blue.length = 8; 1200 var->transp.offset = 24; 1201 var->transp.length = 8; 1202 break; 1203 default: 1204 printk(KERN_ERR "aty128fb: Invalid pixel width\n"); 1205 return -EINVAL; 1206 } 1207 1208 return 0; 1209 } 1210 1211 1212 static int aty128_crtc_to_var(const struct aty128_crtc *crtc, 1213 struct fb_var_screeninfo *var) 1214 { 1215 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync; 1216 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; 1217 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1218 u32 pix_width; 1219 1220 /* fun with masking */ 1221 h_total = crtc->h_total & 0x1ff; 1222 h_disp = (crtc->h_total >> 16) & 0xff; 1223 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff; 1224 h_sync_dly = crtc->h_sync_strt_wid & 0x7; 1225 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f; 1226 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1; 1227 v_total = crtc->v_total & 0x7ff; 1228 v_disp = (crtc->v_total >> 16) & 0x7ff; 1229 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; 1230 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; 1231 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1; 1232 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; 1233 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; 1234 1235 /* do conversions */ 1236 xres = (h_disp + 1) << 3; 1237 yres = v_disp + 1; 1238 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly; 1239 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly; 1240 hslen = h_sync_wid << 3; 1241 upper = v_total - v_sync_strt - v_sync_wid; 1242 lower = v_sync_strt - v_disp; 1243 vslen = v_sync_wid; 1244 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | 1245 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | 1246 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); 1247 1248 aty128_pix_width_to_var(pix_width, var); 1249 1250 var->xres = xres; 1251 var->yres = yres; 1252 var->xres_virtual = crtc->vxres; 1253 var->yres_virtual = crtc->vyres; 1254 var->xoffset = crtc->xoffset; 1255 var->yoffset = crtc->yoffset; 1256 var->left_margin = left; 1257 var->right_margin = right; 1258 var->upper_margin = upper; 1259 var->lower_margin = lower; 1260 var->hsync_len = hslen; 1261 var->vsync_len = vslen; 1262 var->sync = sync; 1263 var->vmode = FB_VMODE_NONINTERLACED; 1264 1265 return 0; 1266 } 1267 1268 static void aty128_set_crt_enable(struct aty128fb_par *par, int on) 1269 { 1270 if (on) { 1271 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | 1272 CRT_CRTC_ON); 1273 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | 1274 DAC_PALETTE2_SNOOP_EN)); 1275 } else 1276 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & 1277 ~CRT_CRTC_ON); 1278 } 1279 1280 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on) 1281 { 1282 u32 reg; 1283 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1284 struct fb_info *info = pci_get_drvdata(par->pdev); 1285 #endif 1286 1287 if (on) { 1288 reg = aty_ld_le32(LVDS_GEN_CNTL); 1289 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION; 1290 reg &= ~LVDS_DISPLAY_DIS; 1291 aty_st_le32(LVDS_GEN_CNTL, reg); 1292 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1293 aty128_bl_set_power(info, FB_BLANK_UNBLANK); 1294 #endif 1295 } else { 1296 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1297 aty128_bl_set_power(info, FB_BLANK_POWERDOWN); 1298 #endif 1299 reg = aty_ld_le32(LVDS_GEN_CNTL); 1300 reg |= LVDS_DISPLAY_DIS; 1301 aty_st_le32(LVDS_GEN_CNTL, reg); 1302 mdelay(100); 1303 reg &= ~(LVDS_ON /*| LVDS_EN*/); 1304 aty_st_le32(LVDS_GEN_CNTL, reg); 1305 } 1306 } 1307 1308 static void aty128_set_pll(struct aty128_pll *pll, 1309 const struct aty128fb_par *par) 1310 { 1311 u32 div3; 1312 1313 unsigned char post_conv[] = /* register values for post dividers */ 1314 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 }; 1315 1316 /* select PPLL_DIV_3 */ 1317 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); 1318 1319 /* reset PLL */ 1320 aty_st_pll(PPLL_CNTL, 1321 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN); 1322 1323 /* write the reference divider */ 1324 aty_pll_wait_readupdate(par); 1325 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); 1326 aty_pll_writeupdate(par); 1327 1328 div3 = aty_ld_pll(PPLL_DIV_3); 1329 div3 &= ~PPLL_FB3_DIV_MASK; 1330 div3 |= pll->feedback_divider; 1331 div3 &= ~PPLL_POST3_DIV_MASK; 1332 div3 |= post_conv[pll->post_divider] << 16; 1333 1334 /* write feedback and post dividers */ 1335 aty_pll_wait_readupdate(par); 1336 aty_st_pll(PPLL_DIV_3, div3); 1337 aty_pll_writeupdate(par); 1338 1339 aty_pll_wait_readupdate(par); 1340 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ 1341 aty_pll_writeupdate(par); 1342 1343 /* clear the reset, just in case */ 1344 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET); 1345 } 1346 1347 1348 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, 1349 const struct aty128fb_par *par) 1350 { 1351 const struct aty128_constants c = par->constants; 1352 unsigned char post_dividers[] = {1,2,4,8,3,6,12}; 1353 u32 output_freq; 1354 u32 vclk; /* in .01 MHz */ 1355 int i = 0; 1356 u32 n, d; 1357 1358 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ 1359 1360 /* adjust pixel clock if necessary */ 1361 if (vclk > c.ppll_max) 1362 vclk = c.ppll_max; 1363 if (vclk * 12 < c.ppll_min) 1364 vclk = c.ppll_min/12; 1365 1366 /* now, find an acceptable divider */ 1367 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) { 1368 output_freq = post_dividers[i] * vclk; 1369 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) { 1370 pll->post_divider = post_dividers[i]; 1371 break; 1372 } 1373 } 1374 1375 if (i == ARRAY_SIZE(post_dividers)) 1376 return -EINVAL; 1377 1378 /* calculate feedback divider */ 1379 n = c.ref_divider * output_freq; 1380 d = c.ref_clk; 1381 1382 pll->feedback_divider = round_div(n, d); 1383 pll->vclk = vclk; 1384 1385 DBG("post %d feedback %d vlck %d output %d ref_divider %d " 1386 "vclk_per: %d\n", pll->post_divider, 1387 pll->feedback_divider, vclk, output_freq, 1388 c.ref_divider, period_in_ps); 1389 1390 return 0; 1391 } 1392 1393 1394 static int aty128_pll_to_var(const struct aty128_pll *pll, 1395 struct fb_var_screeninfo *var) 1396 { 1397 var->pixclock = 100000000 / pll->vclk; 1398 1399 return 0; 1400 } 1401 1402 1403 static void aty128_set_fifo(const struct aty128_ddafifo *dsp, 1404 const struct aty128fb_par *par) 1405 { 1406 aty_st_le32(DDA_CONFIG, dsp->dda_config); 1407 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); 1408 } 1409 1410 1411 static int aty128_ddafifo(struct aty128_ddafifo *dsp, 1412 const struct aty128_pll *pll, 1413 u32 depth, 1414 const struct aty128fb_par *par) 1415 { 1416 const struct aty128_meminfo *m = par->mem; 1417 u32 xclk = par->constants.xclk; 1418 u32 fifo_width = par->constants.fifo_width; 1419 u32 fifo_depth = par->constants.fifo_depth; 1420 s32 x, b, p, ron, roff; 1421 u32 n, d, bpp; 1422 1423 /* round up to multiple of 8 */ 1424 bpp = (depth+7) & ~7; 1425 1426 n = xclk * fifo_width; 1427 d = pll->vclk * bpp; 1428 x = round_div(n, d); 1429 1430 ron = 4 * m->MB + 1431 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) + 1432 2 * m->Trp + 1433 m->Twr + 1434 m->CL + 1435 m->Tr2w + 1436 x; 1437 1438 DBG("x %x\n", x); 1439 1440 b = 0; 1441 while (x) { 1442 x >>= 1; 1443 b++; 1444 } 1445 p = b + 1; 1446 1447 ron <<= (11 - p); 1448 1449 n <<= (11 - p); 1450 x = round_div(n, d); 1451 roff = x * (fifo_depth - 4); 1452 1453 if ((ron + m->Rloop) >= roff) { 1454 printk(KERN_ERR "aty128fb: Mode out of range!\n"); 1455 return -EINVAL; 1456 } 1457 1458 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n", 1459 p, m->Rloop, x, ron, roff); 1460 1461 dsp->dda_config = p << 16 | m->Rloop << 20 | x; 1462 dsp->dda_on_off = ron << 16 | roff; 1463 1464 return 0; 1465 } 1466 1467 1468 /* 1469 * This actually sets the video mode. 1470 */ 1471 static int aty128fb_set_par(struct fb_info *info) 1472 { 1473 struct aty128fb_par *par = info->par; 1474 u32 config; 1475 int err; 1476 1477 if ((err = aty128_decode_var(&info->var, par)) != 0) 1478 return err; 1479 1480 if (par->blitter_may_be_busy) 1481 wait_for_idle(par); 1482 1483 /* clear all registers that may interfere with mode setting */ 1484 aty_st_le32(OVR_CLR, 0); 1485 aty_st_le32(OVR_WID_LEFT_RIGHT, 0); 1486 aty_st_le32(OVR_WID_TOP_BOTTOM, 0); 1487 aty_st_le32(OV0_SCALE_CNTL, 0); 1488 aty_st_le32(MPP_TB_CONFIG, 0); 1489 aty_st_le32(MPP_GP_CONFIG, 0); 1490 aty_st_le32(SUBPIC_CNTL, 0); 1491 aty_st_le32(VIPH_CONTROL, 0); 1492 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ 1493 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ 1494 aty_st_le32(CAP0_TRIG_CNTL, 0); 1495 aty_st_le32(CAP1_TRIG_CNTL, 0); 1496 1497 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */ 1498 1499 aty128_set_crtc(&par->crtc, par); 1500 aty128_set_pll(&par->pll, par); 1501 aty128_set_fifo(&par->fifo_reg, par); 1502 1503 config = aty_ld_le32(CNFG_CNTL) & ~3; 1504 1505 #if defined(__BIG_ENDIAN) 1506 if (par->crtc.bpp == 32) 1507 config |= 2; /* make aperture do 32 bit swapping */ 1508 else if (par->crtc.bpp == 16) 1509 config |= 1; /* make aperture do 16 bit swapping */ 1510 #endif 1511 1512 aty_st_le32(CNFG_CNTL, config); 1513 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ 1514 1515 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; 1516 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR 1517 : FB_VISUAL_DIRECTCOLOR; 1518 1519 if (par->chip_gen == rage_M3) { 1520 aty128_set_crt_enable(par, par->crt_on); 1521 aty128_set_lcd_enable(par, par->lcd_on); 1522 } 1523 if (par->accel_flags & FB_ACCELF_TEXT) 1524 aty128_init_engine(par); 1525 1526 #ifdef CONFIG_BOOTX_TEXT 1527 btext_update_display(info->fix.smem_start, 1528 (((par->crtc.h_total>>16) & 0xff)+1)*8, 1529 ((par->crtc.v_total>>16) & 0x7ff)+1, 1530 par->crtc.bpp, 1531 par->crtc.vxres*par->crtc.bpp/8); 1532 #endif /* CONFIG_BOOTX_TEXT */ 1533 1534 return 0; 1535 } 1536 1537 /* 1538 * encode/decode the User Defined Part of the Display 1539 */ 1540 1541 static int aty128_decode_var(struct fb_var_screeninfo *var, 1542 struct aty128fb_par *par) 1543 { 1544 int err; 1545 struct aty128_crtc crtc; 1546 struct aty128_pll pll; 1547 struct aty128_ddafifo fifo_reg; 1548 1549 if ((err = aty128_var_to_crtc(var, &crtc, par))) 1550 return err; 1551 1552 if ((err = aty128_var_to_pll(var->pixclock, &pll, par))) 1553 return err; 1554 1555 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par))) 1556 return err; 1557 1558 par->crtc = crtc; 1559 par->pll = pll; 1560 par->fifo_reg = fifo_reg; 1561 par->accel_flags = var->accel_flags; 1562 1563 return 0; 1564 } 1565 1566 1567 static int aty128_encode_var(struct fb_var_screeninfo *var, 1568 const struct aty128fb_par *par) 1569 { 1570 int err; 1571 1572 if ((err = aty128_crtc_to_var(&par->crtc, var))) 1573 return err; 1574 1575 if ((err = aty128_pll_to_var(&par->pll, var))) 1576 return err; 1577 1578 var->nonstd = 0; 1579 var->activate = 0; 1580 1581 var->height = -1; 1582 var->width = -1; 1583 var->accel_flags = par->accel_flags; 1584 1585 return 0; 1586 } 1587 1588 1589 static int aty128fb_check_var(struct fb_var_screeninfo *var, 1590 struct fb_info *info) 1591 { 1592 struct aty128fb_par par; 1593 int err; 1594 1595 par = *(struct aty128fb_par *)info->par; 1596 if ((err = aty128_decode_var(var, &par)) != 0) 1597 return err; 1598 aty128_encode_var(var, &par); 1599 return 0; 1600 } 1601 1602 1603 /* 1604 * Pan or Wrap the Display 1605 */ 1606 static int aty128fb_pan_display(struct fb_var_screeninfo *var, 1607 struct fb_info *fb) 1608 { 1609 struct aty128fb_par *par = fb->par; 1610 u32 xoffset, yoffset; 1611 u32 offset; 1612 u32 xres, yres; 1613 1614 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; 1615 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1; 1616 1617 xoffset = (var->xoffset +7) & ~7; 1618 yoffset = var->yoffset; 1619 1620 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres) 1621 return -EINVAL; 1622 1623 par->crtc.xoffset = xoffset; 1624 par->crtc.yoffset = yoffset; 1625 1626 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3)) 1627 & ~7; 1628 1629 if (par->crtc.bpp == 24) 1630 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */ 1631 1632 aty_st_le32(CRTC_OFFSET, offset); 1633 1634 return 0; 1635 } 1636 1637 1638 /* 1639 * Helper function to store a single palette register 1640 */ 1641 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue, 1642 struct aty128fb_par *par) 1643 { 1644 if (par->chip_gen == rage_M3) { 1645 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & 1646 ~DAC_PALETTE_ACCESS_CNTL); 1647 } 1648 1649 aty_st_8(PALETTE_INDEX, regno); 1650 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); 1651 } 1652 1653 static int aty128fb_sync(struct fb_info *info) 1654 { 1655 struct aty128fb_par *par = info->par; 1656 1657 if (par->blitter_may_be_busy) 1658 wait_for_idle(par); 1659 return 0; 1660 } 1661 1662 #ifndef MODULE 1663 static int aty128fb_setup(char *options) 1664 { 1665 char *this_opt; 1666 1667 if (!options || !*options) 1668 return 0; 1669 1670 while ((this_opt = strsep(&options, ",")) != NULL) { 1671 if (!strncmp(this_opt, "lcd:", 4)) { 1672 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0); 1673 continue; 1674 } else if (!strncmp(this_opt, "crt:", 4)) { 1675 default_crt_on = simple_strtoul(this_opt+4, NULL, 0); 1676 continue; 1677 } else if (!strncmp(this_opt, "backlight:", 10)) { 1678 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1679 backlight = simple_strtoul(this_opt+10, NULL, 0); 1680 #endif 1681 continue; 1682 } 1683 if(!strncmp(this_opt, "nomtrr", 6)) { 1684 mtrr = false; 1685 continue; 1686 } 1687 #ifdef CONFIG_PPC_PMAC 1688 /* vmode and cmode deprecated */ 1689 if (!strncmp(this_opt, "vmode:", 6)) { 1690 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0); 1691 if (vmode > 0 && vmode <= VMODE_MAX) 1692 default_vmode = vmode; 1693 continue; 1694 } else if (!strncmp(this_opt, "cmode:", 6)) { 1695 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0); 1696 switch (cmode) { 1697 case 0: 1698 case 8: 1699 default_cmode = CMODE_8; 1700 break; 1701 case 15: 1702 case 16: 1703 default_cmode = CMODE_16; 1704 break; 1705 case 24: 1706 case 32: 1707 default_cmode = CMODE_32; 1708 break; 1709 } 1710 continue; 1711 } 1712 #endif /* CONFIG_PPC_PMAC */ 1713 mode_option = this_opt; 1714 } 1715 return 0; 1716 } 1717 #endif /* MODULE */ 1718 1719 /* Backlight */ 1720 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1721 #define MAX_LEVEL 0xFF 1722 1723 static int aty128_bl_get_level_brightness(struct aty128fb_par *par, 1724 int level) 1725 { 1726 struct fb_info *info = pci_get_drvdata(par->pdev); 1727 int atylevel; 1728 1729 /* Get and convert the value */ 1730 /* No locking of bl_curve since we read a single value */ 1731 atylevel = MAX_LEVEL - 1732 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL); 1733 1734 if (atylevel < 0) 1735 atylevel = 0; 1736 else if (atylevel > MAX_LEVEL) 1737 atylevel = MAX_LEVEL; 1738 1739 return atylevel; 1740 } 1741 1742 /* We turn off the LCD completely instead of just dimming the backlight. 1743 * This provides greater power saving and the display is useless without 1744 * backlight anyway 1745 */ 1746 #define BACKLIGHT_LVDS_OFF 1747 /* That one prevents proper CRT output with LCD off */ 1748 #undef BACKLIGHT_DAC_OFF 1749 1750 static int aty128_bl_update_status(struct backlight_device *bd) 1751 { 1752 struct aty128fb_par *par = bl_get_data(bd); 1753 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL); 1754 int level; 1755 1756 if (bd->props.power != FB_BLANK_UNBLANK || 1757 bd->props.fb_blank != FB_BLANK_UNBLANK || 1758 !par->lcd_on) 1759 level = 0; 1760 else 1761 level = bd->props.brightness; 1762 1763 reg |= LVDS_BL_MOD_EN | LVDS_BLON; 1764 if (level > 0) { 1765 reg |= LVDS_DIGION; 1766 if (!(reg & LVDS_ON)) { 1767 reg &= ~LVDS_BLON; 1768 aty_st_le32(LVDS_GEN_CNTL, reg); 1769 aty_ld_le32(LVDS_GEN_CNTL); 1770 mdelay(10); 1771 reg |= LVDS_BLON; 1772 aty_st_le32(LVDS_GEN_CNTL, reg); 1773 } 1774 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 1775 reg |= (aty128_bl_get_level_brightness(par, level) << 1776 LVDS_BL_MOD_LEVEL_SHIFT); 1777 #ifdef BACKLIGHT_LVDS_OFF 1778 reg |= LVDS_ON | LVDS_EN; 1779 reg &= ~LVDS_DISPLAY_DIS; 1780 #endif 1781 aty_st_le32(LVDS_GEN_CNTL, reg); 1782 #ifdef BACKLIGHT_DAC_OFF 1783 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); 1784 #endif 1785 } else { 1786 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 1787 reg |= (aty128_bl_get_level_brightness(par, 0) << 1788 LVDS_BL_MOD_LEVEL_SHIFT); 1789 #ifdef BACKLIGHT_LVDS_OFF 1790 reg |= LVDS_DISPLAY_DIS; 1791 aty_st_le32(LVDS_GEN_CNTL, reg); 1792 aty_ld_le32(LVDS_GEN_CNTL); 1793 udelay(10); 1794 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION); 1795 #endif 1796 aty_st_le32(LVDS_GEN_CNTL, reg); 1797 #ifdef BACKLIGHT_DAC_OFF 1798 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); 1799 #endif 1800 } 1801 1802 return 0; 1803 } 1804 1805 static const struct backlight_ops aty128_bl_data = { 1806 .update_status = aty128_bl_update_status, 1807 }; 1808 1809 static void aty128_bl_set_power(struct fb_info *info, int power) 1810 { 1811 if (info->bl_dev) { 1812 info->bl_dev->props.power = power; 1813 backlight_update_status(info->bl_dev); 1814 } 1815 } 1816 1817 static void aty128_bl_init(struct aty128fb_par *par) 1818 { 1819 struct backlight_properties props; 1820 struct fb_info *info = pci_get_drvdata(par->pdev); 1821 struct backlight_device *bd; 1822 char name[12]; 1823 1824 /* Could be extended to Rage128Pro LVDS output too */ 1825 if (par->chip_gen != rage_M3) 1826 return; 1827 1828 #ifdef CONFIG_PMAC_BACKLIGHT 1829 if (!pmac_has_backlight_type("ati")) 1830 return; 1831 #endif 1832 1833 snprintf(name, sizeof(name), "aty128bl%d", info->node); 1834 1835 memset(&props, 0, sizeof(struct backlight_properties)); 1836 props.type = BACKLIGHT_RAW; 1837 props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 1838 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data, 1839 &props); 1840 if (IS_ERR(bd)) { 1841 info->bl_dev = NULL; 1842 printk(KERN_WARNING "aty128: Backlight registration failed\n"); 1843 goto error; 1844 } 1845 1846 info->bl_dev = bd; 1847 fb_bl_default_curve(info, 0, 1848 63 * FB_BACKLIGHT_MAX / MAX_LEVEL, 1849 219 * FB_BACKLIGHT_MAX / MAX_LEVEL); 1850 1851 bd->props.brightness = bd->props.max_brightness; 1852 bd->props.power = FB_BLANK_UNBLANK; 1853 backlight_update_status(bd); 1854 1855 printk("aty128: Backlight initialized (%s)\n", name); 1856 1857 return; 1858 1859 error: 1860 return; 1861 } 1862 1863 static void aty128_bl_exit(struct backlight_device *bd) 1864 { 1865 backlight_device_unregister(bd); 1866 printk("aty128: Backlight unloaded\n"); 1867 } 1868 #endif /* CONFIG_FB_ATY128_BACKLIGHT */ 1869 1870 /* 1871 * Initialisation 1872 */ 1873 1874 #ifdef CONFIG_PPC_PMAC__disabled 1875 static void aty128_early_resume(void *data) 1876 { 1877 struct aty128fb_par *par = data; 1878 1879 if (!console_trylock()) 1880 return; 1881 pci_restore_state(par->pdev); 1882 aty128_do_resume(par->pdev); 1883 console_unlock(); 1884 } 1885 #endif /* CONFIG_PPC_PMAC */ 1886 1887 static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent) 1888 { 1889 struct fb_info *info = pci_get_drvdata(pdev); 1890 struct aty128fb_par *par = info->par; 1891 struct fb_var_screeninfo var; 1892 char video_card[50]; 1893 u8 chip_rev; 1894 u32 dac; 1895 1896 /* Get the chip revision */ 1897 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F; 1898 1899 strcpy(video_card, "Rage128 XX "); 1900 video_card[8] = ent->device >> 8; 1901 video_card[9] = ent->device & 0xFF; 1902 1903 /* range check to make sure */ 1904 if (ent->driver_data < ARRAY_SIZE(r128_family)) 1905 strlcat(video_card, r128_family[ent->driver_data], 1906 sizeof(video_card)); 1907 1908 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev); 1909 1910 if (par->vram_size % (1024 * 1024) == 0) 1911 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name); 1912 else 1913 printk("%dk %s\n", par->vram_size / 1024, par->mem->name); 1914 1915 par->chip_gen = ent->driver_data; 1916 1917 /* fill in info */ 1918 info->fbops = &aty128fb_ops; 1919 info->flags = FBINFO_FLAG_DEFAULT; 1920 1921 par->lcd_on = default_lcd_on; 1922 par->crt_on = default_crt_on; 1923 1924 var = default_var; 1925 #ifdef CONFIG_PPC_PMAC 1926 if (machine_is(powermac)) { 1927 /* Indicate sleep capability */ 1928 if (par->chip_gen == rage_M3) { 1929 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); 1930 #if 0 /* Disable the early video resume hack for now as it's causing problems, 1931 * among others we now rely on the PCI core restoring the config space 1932 * for us, which isn't the case with that hack, and that code path causes 1933 * various things to be called with interrupts off while they shouldn't. 1934 * I'm leaving the code in as it can be useful for debugging purposes 1935 */ 1936 pmac_set_early_video_resume(aty128_early_resume, par); 1937 #endif 1938 } 1939 1940 /* Find default mode */ 1941 if (mode_option) { 1942 if (!mac_find_mode(&var, info, mode_option, 8)) 1943 var = default_var; 1944 } else { 1945 if (default_vmode <= 0 || default_vmode > VMODE_MAX) 1946 default_vmode = VMODE_1024_768_60; 1947 1948 /* iMacs need that resolution 1949 * PowerMac2,1 first r128 iMacs 1950 * PowerMac2,2 summer 2000 iMacs 1951 * PowerMac4,1 january 2001 iMacs "flower power" 1952 */ 1953 if (of_machine_is_compatible("PowerMac2,1") || 1954 of_machine_is_compatible("PowerMac2,2") || 1955 of_machine_is_compatible("PowerMac4,1")) 1956 default_vmode = VMODE_1024_768_75; 1957 1958 /* iBook SE */ 1959 if (of_machine_is_compatible("PowerBook2,2")) 1960 default_vmode = VMODE_800_600_60; 1961 1962 /* PowerBook Firewire (Pismo), iBook Dual USB */ 1963 if (of_machine_is_compatible("PowerBook3,1") || 1964 of_machine_is_compatible("PowerBook4,1")) 1965 default_vmode = VMODE_1024_768_60; 1966 1967 /* PowerBook Titanium */ 1968 if (of_machine_is_compatible("PowerBook3,2")) 1969 default_vmode = VMODE_1152_768_60; 1970 1971 if (default_cmode > 16) 1972 default_cmode = CMODE_32; 1973 else if (default_cmode > 8) 1974 default_cmode = CMODE_16; 1975 else 1976 default_cmode = CMODE_8; 1977 1978 if (mac_vmode_to_var(default_vmode, default_cmode, &var)) 1979 var = default_var; 1980 } 1981 } else 1982 #endif /* CONFIG_PPC_PMAC */ 1983 { 1984 if (mode_option) 1985 if (fb_find_mode(&var, info, mode_option, NULL, 1986 0, &defaultmode, 8) == 0) 1987 var = default_var; 1988 } 1989 1990 var.accel_flags &= ~FB_ACCELF_TEXT; 1991 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */ 1992 1993 if (aty128fb_check_var(&var, info)) { 1994 printk(KERN_ERR "aty128fb: Cannot set default mode.\n"); 1995 return 0; 1996 } 1997 1998 /* setup the DAC the way we like it */ 1999 dac = aty_ld_le32(DAC_CNTL); 2000 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL); 2001 dac |= DAC_MASK; 2002 if (par->chip_gen == rage_M3) 2003 dac |= DAC_PALETTE2_SNOOP_EN; 2004 aty_st_le32(DAC_CNTL, dac); 2005 2006 /* turn off bus mastering, just in case */ 2007 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); 2008 2009 info->var = var; 2010 fb_alloc_cmap(&info->cmap, 256, 0); 2011 2012 var.activate = FB_ACTIVATE_NOW; 2013 2014 aty128_init_engine(par); 2015 2016 par->pdev = pdev; 2017 par->asleep = 0; 2018 par->lock_blank = 0; 2019 2020 #ifdef CONFIG_FB_ATY128_BACKLIGHT 2021 if (backlight) 2022 aty128_bl_init(par); 2023 #endif 2024 2025 if (register_framebuffer(info) < 0) 2026 return 0; 2027 2028 fb_info(info, "%s frame buffer device on %s\n", 2029 info->fix.id, video_card); 2030 2031 return 1; /* success! */ 2032 } 2033 2034 #ifdef CONFIG_PCI 2035 /* register a card ++ajoshi */ 2036 static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2037 { 2038 unsigned long fb_addr, reg_addr; 2039 struct aty128fb_par *par; 2040 struct fb_info *info; 2041 int err; 2042 #ifndef __sparc__ 2043 void __iomem *bios = NULL; 2044 #endif 2045 2046 /* Enable device in PCI config */ 2047 if ((err = pci_enable_device(pdev))) { 2048 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n", 2049 err); 2050 return -ENODEV; 2051 } 2052 2053 fb_addr = pci_resource_start(pdev, 0); 2054 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0), 2055 "aty128fb FB")) { 2056 printk(KERN_ERR "aty128fb: cannot reserve frame " 2057 "buffer memory\n"); 2058 return -ENODEV; 2059 } 2060 2061 reg_addr = pci_resource_start(pdev, 2); 2062 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2), 2063 "aty128fb MMIO")) { 2064 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n"); 2065 goto err_free_fb; 2066 } 2067 2068 /* We have the resources. Now virtualize them */ 2069 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev); 2070 if (!info) 2071 goto err_free_mmio; 2072 2073 par = info->par; 2074 2075 info->pseudo_palette = par->pseudo_palette; 2076 2077 /* Virtualize mmio region */ 2078 info->fix.mmio_start = reg_addr; 2079 par->regbase = pci_ioremap_bar(pdev, 2); 2080 if (!par->regbase) 2081 goto err_free_info; 2082 2083 /* Grab memory size from the card */ 2084 // How does this relate to the resource length from the PCI hardware? 2085 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF; 2086 2087 /* Virtualize the framebuffer */ 2088 info->screen_base = ioremap_wc(fb_addr, par->vram_size); 2089 if (!info->screen_base) 2090 goto err_unmap_out; 2091 2092 /* Set up info->fix */ 2093 info->fix = aty128fb_fix; 2094 info->fix.smem_start = fb_addr; 2095 info->fix.smem_len = par->vram_size; 2096 info->fix.mmio_start = reg_addr; 2097 2098 /* If we can't test scratch registers, something is seriously wrong */ 2099 if (!register_test(par)) { 2100 printk(KERN_ERR "aty128fb: Can't write to video register!\n"); 2101 goto err_out; 2102 } 2103 2104 #ifndef __sparc__ 2105 bios = aty128_map_ROM(par, pdev); 2106 #ifdef CONFIG_X86 2107 if (bios == NULL) 2108 bios = aty128_find_mem_vbios(par); 2109 #endif 2110 if (bios == NULL) 2111 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n"); 2112 else { 2113 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n"); 2114 aty128_get_pllinfo(par, bios); 2115 pci_unmap_rom(pdev, bios); 2116 } 2117 #endif /* __sparc__ */ 2118 2119 aty128_timings(par); 2120 pci_set_drvdata(pdev, info); 2121 2122 if (!aty128_init(pdev, ent)) 2123 goto err_out; 2124 2125 if (mtrr) 2126 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, 2127 par->vram_size); 2128 return 0; 2129 2130 err_out: 2131 iounmap(info->screen_base); 2132 err_unmap_out: 2133 iounmap(par->regbase); 2134 err_free_info: 2135 framebuffer_release(info); 2136 err_free_mmio: 2137 release_mem_region(pci_resource_start(pdev, 2), 2138 pci_resource_len(pdev, 2)); 2139 err_free_fb: 2140 release_mem_region(pci_resource_start(pdev, 0), 2141 pci_resource_len(pdev, 0)); 2142 return -ENODEV; 2143 } 2144 2145 static void aty128_remove(struct pci_dev *pdev) 2146 { 2147 struct fb_info *info = pci_get_drvdata(pdev); 2148 struct aty128fb_par *par; 2149 2150 if (!info) 2151 return; 2152 2153 par = info->par; 2154 2155 unregister_framebuffer(info); 2156 2157 #ifdef CONFIG_FB_ATY128_BACKLIGHT 2158 aty128_bl_exit(info->bl_dev); 2159 #endif 2160 2161 arch_phys_wc_del(par->wc_cookie); 2162 iounmap(par->regbase); 2163 iounmap(info->screen_base); 2164 2165 release_mem_region(pci_resource_start(pdev, 0), 2166 pci_resource_len(pdev, 0)); 2167 release_mem_region(pci_resource_start(pdev, 2), 2168 pci_resource_len(pdev, 2)); 2169 framebuffer_release(info); 2170 } 2171 #endif /* CONFIG_PCI */ 2172 2173 2174 2175 /* 2176 * Blank the display. 2177 */ 2178 static int aty128fb_blank(int blank, struct fb_info *fb) 2179 { 2180 struct aty128fb_par *par = fb->par; 2181 u8 state; 2182 2183 if (par->lock_blank || par->asleep) 2184 return 0; 2185 2186 switch (blank) { 2187 case FB_BLANK_NORMAL: 2188 state = 4; 2189 break; 2190 case FB_BLANK_VSYNC_SUSPEND: 2191 state = 6; 2192 break; 2193 case FB_BLANK_HSYNC_SUSPEND: 2194 state = 5; 2195 break; 2196 case FB_BLANK_POWERDOWN: 2197 state = 7; 2198 break; 2199 case FB_BLANK_UNBLANK: 2200 default: 2201 state = 0; 2202 break; 2203 } 2204 aty_st_8(CRTC_EXT_CNTL+1, state); 2205 2206 if (par->chip_gen == rage_M3) { 2207 aty128_set_crt_enable(par, par->crt_on && !blank); 2208 aty128_set_lcd_enable(par, par->lcd_on && !blank); 2209 } 2210 2211 return 0; 2212 } 2213 2214 /* 2215 * Set a single color register. The values supplied are already 2216 * rounded down to the hardware's capabilities (according to the 2217 * entries in the var structure). Return != 0 for invalid regno. 2218 */ 2219 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 2220 u_int transp, struct fb_info *info) 2221 { 2222 struct aty128fb_par *par = info->par; 2223 2224 if (regno > 255 2225 || (par->crtc.depth == 16 && regno > 63) 2226 || (par->crtc.depth == 15 && regno > 31)) 2227 return 1; 2228 2229 red >>= 8; 2230 green >>= 8; 2231 blue >>= 8; 2232 2233 if (regno < 16) { 2234 int i; 2235 u32 *pal = info->pseudo_palette; 2236 2237 switch (par->crtc.depth) { 2238 case 15: 2239 pal[regno] = (regno << 10) | (regno << 5) | regno; 2240 break; 2241 case 16: 2242 pal[regno] = (regno << 11) | (regno << 6) | regno; 2243 break; 2244 case 24: 2245 pal[regno] = (regno << 16) | (regno << 8) | regno; 2246 break; 2247 case 32: 2248 i = (regno << 8) | regno; 2249 pal[regno] = (i << 16) | i; 2250 break; 2251 } 2252 } 2253 2254 if (par->crtc.depth == 16 && regno > 0) { 2255 /* 2256 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we 2257 * have 32 slots for R and B values but 64 slots for G values. 2258 * Thus the R and B values go in one slot but the G value 2259 * goes in a different slot, and we have to avoid disturbing 2260 * the other fields in the slots we touch. 2261 */ 2262 par->green[regno] = green; 2263 if (regno < 32) { 2264 par->red[regno] = red; 2265 par->blue[regno] = blue; 2266 aty128_st_pal(regno * 8, red, par->green[regno*2], 2267 blue, par); 2268 } 2269 red = par->red[regno/2]; 2270 blue = par->blue[regno/2]; 2271 regno <<= 2; 2272 } else if (par->crtc.bpp == 16) 2273 regno <<= 3; 2274 aty128_st_pal(regno, red, green, blue, par); 2275 2276 return 0; 2277 } 2278 2279 #define ATY_MIRROR_LCD_ON 0x00000001 2280 #define ATY_MIRROR_CRT_ON 0x00000002 2281 2282 /* out param: u32* backlight value: 0 to 15 */ 2283 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32) 2284 /* in param: u32* backlight value: 0 to 15 */ 2285 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32) 2286 2287 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg) 2288 { 2289 struct aty128fb_par *par = info->par; 2290 u32 value; 2291 int rc; 2292 2293 switch (cmd) { 2294 case FBIO_ATY128_SET_MIRROR: 2295 if (par->chip_gen != rage_M3) 2296 return -EINVAL; 2297 rc = get_user(value, (__u32 __user *)arg); 2298 if (rc) 2299 return rc; 2300 par->lcd_on = (value & 0x01) != 0; 2301 par->crt_on = (value & 0x02) != 0; 2302 if (!par->crt_on && !par->lcd_on) 2303 par->lcd_on = 1; 2304 aty128_set_crt_enable(par, par->crt_on); 2305 aty128_set_lcd_enable(par, par->lcd_on); 2306 return 0; 2307 case FBIO_ATY128_GET_MIRROR: 2308 if (par->chip_gen != rage_M3) 2309 return -EINVAL; 2310 value = (par->crt_on << 1) | par->lcd_on; 2311 return put_user(value, (__u32 __user *)arg); 2312 } 2313 return -EINVAL; 2314 } 2315 2316 static void aty128_set_suspend(struct aty128fb_par *par, int suspend) 2317 { 2318 u32 pmgt; 2319 struct pci_dev *pdev = par->pdev; 2320 2321 if (!par->pdev->pm_cap) 2322 return; 2323 2324 /* Set the chip into the appropriate suspend mode (we use D2, 2325 * D3 would require a complete re-initialisation of the chip, 2326 * including PCI config registers, clocks, AGP configuration, ...) 2327 * 2328 * For resume, the core will have already brought us back to D0 2329 */ 2330 if (suspend) { 2331 /* Make sure CRTC2 is reset. Remove that the day we decide to 2332 * actually use CRTC2 and replace it with real code for disabling 2333 * the CRTC2 output during sleep 2334 */ 2335 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & 2336 ~(CRTC2_EN)); 2337 2338 /* Set the power management mode to be PCI based */ 2339 /* Use this magic value for now */ 2340 pmgt = 0x0c005407; 2341 aty_st_pll(POWER_MANAGEMENT, pmgt); 2342 (void)aty_ld_pll(POWER_MANAGEMENT); 2343 aty_st_le32(BUS_CNTL1, 0x00000010); 2344 aty_st_le32(MEM_POWER_MISC, 0x0c830000); 2345 msleep(100); 2346 2347 /* Switch PCI power management to D2 */ 2348 pci_set_power_state(pdev, PCI_D2); 2349 } 2350 } 2351 2352 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state) 2353 { 2354 struct fb_info *info = pci_get_drvdata(pdev); 2355 struct aty128fb_par *par = info->par; 2356 2357 /* Because we may change PCI D state ourselves, we need to 2358 * first save the config space content so the core can 2359 * restore it properly on resume. 2360 */ 2361 pci_save_state(pdev); 2362 2363 /* We don't do anything but D2, for now we return 0, but 2364 * we may want to change that. How do we know if the BIOS 2365 * can properly take care of D3 ? Also, with swsusp, we 2366 * know we'll be rebooted, ... 2367 */ 2368 #ifndef CONFIG_PPC_PMAC 2369 /* HACK ALERT ! Once I find a proper way to say to each driver 2370 * individually what will happen with it's PCI slot, I'll change 2371 * that. On laptops, the AGP slot is just unclocked, so D2 is 2372 * expected, while on desktops, the card is powered off 2373 */ 2374 return 0; 2375 #endif /* CONFIG_PPC_PMAC */ 2376 2377 if (state.event == pdev->dev.power.power_state.event) 2378 return 0; 2379 2380 printk(KERN_DEBUG "aty128fb: suspending...\n"); 2381 2382 console_lock(); 2383 2384 fb_set_suspend(info, 1); 2385 2386 /* Make sure engine is reset */ 2387 wait_for_idle(par); 2388 aty128_reset_engine(par); 2389 wait_for_idle(par); 2390 2391 /* Blank display and LCD */ 2392 aty128fb_blank(FB_BLANK_POWERDOWN, info); 2393 2394 /* Sleep */ 2395 par->asleep = 1; 2396 par->lock_blank = 1; 2397 2398 #ifdef CONFIG_PPC_PMAC 2399 /* On powermac, we have hooks to properly suspend/resume AGP now, 2400 * use them here. We'll ultimately need some generic support here, 2401 * but the generic code isn't quite ready for that yet 2402 */ 2403 pmac_suspend_agp_for_card(pdev); 2404 #endif /* CONFIG_PPC_PMAC */ 2405 2406 /* We need a way to make sure the fbdev layer will _not_ touch the 2407 * framebuffer before we put the chip to suspend state. On 2.4, I 2408 * used dummy fb ops, 2.5 need proper support for this at the 2409 * fbdev level 2410 */ 2411 if (state.event != PM_EVENT_ON) 2412 aty128_set_suspend(par, 1); 2413 2414 console_unlock(); 2415 2416 pdev->dev.power.power_state = state; 2417 2418 return 0; 2419 } 2420 2421 static int aty128_do_resume(struct pci_dev *pdev) 2422 { 2423 struct fb_info *info = pci_get_drvdata(pdev); 2424 struct aty128fb_par *par = info->par; 2425 2426 if (pdev->dev.power.power_state.event == PM_EVENT_ON) 2427 return 0; 2428 2429 /* PCI state will have been restored by the core, so 2430 * we should be in D0 now with our config space fully 2431 * restored 2432 */ 2433 2434 /* Wakeup chip */ 2435 aty128_set_suspend(par, 0); 2436 par->asleep = 0; 2437 2438 /* Restore display & engine */ 2439 aty128_reset_engine(par); 2440 wait_for_idle(par); 2441 aty128fb_set_par(info); 2442 fb_pan_display(info, &info->var); 2443 fb_set_cmap(&info->cmap, info); 2444 2445 /* Refresh */ 2446 fb_set_suspend(info, 0); 2447 2448 /* Unblank */ 2449 par->lock_blank = 0; 2450 aty128fb_blank(0, info); 2451 2452 #ifdef CONFIG_PPC_PMAC 2453 /* On powermac, we have hooks to properly suspend/resume AGP now, 2454 * use them here. We'll ultimately need some generic support here, 2455 * but the generic code isn't quite ready for that yet 2456 */ 2457 pmac_resume_agp_for_card(pdev); 2458 #endif /* CONFIG_PPC_PMAC */ 2459 2460 pdev->dev.power.power_state = PMSG_ON; 2461 2462 printk(KERN_DEBUG "aty128fb: resumed !\n"); 2463 2464 return 0; 2465 } 2466 2467 static int aty128_pci_resume(struct pci_dev *pdev) 2468 { 2469 int rc; 2470 2471 console_lock(); 2472 rc = aty128_do_resume(pdev); 2473 console_unlock(); 2474 2475 return rc; 2476 } 2477 2478 2479 static int aty128fb_init(void) 2480 { 2481 #ifndef MODULE 2482 char *option = NULL; 2483 2484 if (fb_get_options("aty128fb", &option)) 2485 return -ENODEV; 2486 aty128fb_setup(option); 2487 #endif 2488 2489 return pci_register_driver(&aty128fb_driver); 2490 } 2491 2492 static void __exit aty128fb_exit(void) 2493 { 2494 pci_unregister_driver(&aty128fb_driver); 2495 } 2496 2497 module_init(aty128fb_init); 2498 2499 module_exit(aty128fb_exit); 2500 2501 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>"); 2502 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards"); 2503 MODULE_LICENSE("GPL"); 2504 module_param(mode_option, charp, 0); 2505 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); 2506 module_param_named(nomtrr, mtrr, invbool, 0); 2507 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)"); 2508