1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $ 2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128 3 * 4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com> 5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu> 6 * 7 * Ani Joshi / Jeff Garzik 8 * - Code cleanup 9 * 10 * Michel Danzer <michdaen@iiic.ethz.ch> 11 * - 15/16 bit cleanup 12 * - fix panning 13 * 14 * Benjamin Herrenschmidt 15 * - pmac-specific PM stuff 16 * - various fixes & cleanups 17 * 18 * Andreas Hundt <andi@convergence.de> 19 * - FB_ACTIVATE fixes 20 * 21 * Paul Mackerras <paulus@samba.org> 22 * - Convert to new framebuffer API, 23 * fix colormap setting at 16 bits/pixel (565) 24 * 25 * Paul Mundt 26 * - PCI hotplug 27 * 28 * Jon Smirl <jonsmirl@yahoo.com> 29 * - PCI ID update 30 * - replace ROM BIOS search 31 * 32 * Based off of Geert's atyfb.c and vfb.c. 33 * 34 * TODO: 35 * - monitor sensing (DDC) 36 * - virtual display 37 * - other platform support (only ppc/x86 supported) 38 * - hardware cursor support 39 * 40 * Please cc: your patches to brad@neruo.com. 41 */ 42 43 /* 44 * A special note of gratitude to ATI's devrel for providing documentation, 45 * example code and hardware. Thanks Nitya. -atong and brad 46 */ 47 48 49 #include <linux/module.h> 50 #include <linux/moduleparam.h> 51 #include <linux/kernel.h> 52 #include <linux/errno.h> 53 #include <linux/string.h> 54 #include <linux/mm.h> 55 #include <linux/vmalloc.h> 56 #include <linux/delay.h> 57 #include <linux/interrupt.h> 58 #include <linux/uaccess.h> 59 #include <linux/fb.h> 60 #include <linux/init.h> 61 #include <linux/pci.h> 62 #include <linux/ioport.h> 63 #include <linux/console.h> 64 #include <linux/backlight.h> 65 #include <asm/io.h> 66 67 #ifdef CONFIG_PPC_PMAC 68 #include <asm/machdep.h> 69 #include <asm/pmac_feature.h> 70 #include <asm/prom.h> 71 #include "../macmodes.h" 72 #endif 73 74 #ifdef CONFIG_PMAC_BACKLIGHT 75 #include <asm/backlight.h> 76 #endif 77 78 #ifdef CONFIG_BOOTX_TEXT 79 #include <asm/btext.h> 80 #endif /* CONFIG_BOOTX_TEXT */ 81 82 #include <video/aty128.h> 83 84 /* Debug flag */ 85 #undef DEBUG 86 87 #ifdef DEBUG 88 #define DBG(fmt, args...) \ 89 printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args); 90 #else 91 #define DBG(fmt, args...) 92 #endif 93 94 #ifndef CONFIG_PPC_PMAC 95 /* default mode */ 96 static struct fb_var_screeninfo default_var = { 97 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */ 98 640, 480, 640, 480, 0, 0, 8, 0, 99 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 100 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2, 101 0, FB_VMODE_NONINTERLACED 102 }; 103 104 #else /* CONFIG_PPC_PMAC */ 105 /* default to 1024x768 at 75Hz on PPC - this will work 106 * on the iMac, the usual 640x480 @ 60Hz doesn't. */ 107 static struct fb_var_screeninfo default_var = { 108 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */ 109 1024, 768, 1024, 768, 0, 0, 8, 0, 110 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 111 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3, 112 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 113 FB_VMODE_NONINTERLACED 114 }; 115 #endif /* CONFIG_PPC_PMAC */ 116 117 /* default modedb mode */ 118 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */ 119 static struct fb_videomode defaultmode = { 120 .refresh = 60, 121 .xres = 640, 122 .yres = 480, 123 .pixclock = 39722, 124 .left_margin = 48, 125 .right_margin = 16, 126 .upper_margin = 33, 127 .lower_margin = 10, 128 .hsync_len = 96, 129 .vsync_len = 2, 130 .sync = 0, 131 .vmode = FB_VMODE_NONINTERLACED 132 }; 133 134 /* Chip generations */ 135 enum { 136 rage_128, 137 rage_128_pci, 138 rage_128_pro, 139 rage_128_pro_pci, 140 rage_M3, 141 rage_M3_pci, 142 rage_M4, 143 rage_128_ultra, 144 }; 145 146 /* Must match above enum */ 147 static char * const r128_family[] = { 148 "AGP", 149 "PCI", 150 "PRO AGP", 151 "PRO PCI", 152 "M3 AGP", 153 "M3 PCI", 154 "M4 AGP", 155 "Ultra AGP", 156 }; 157 158 /* 159 * PCI driver prototypes 160 */ 161 static int aty128_probe(struct pci_dev *pdev, 162 const struct pci_device_id *ent); 163 static void aty128_remove(struct pci_dev *pdev); 164 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state); 165 static int aty128_pci_resume(struct pci_dev *pdev); 166 static int aty128_do_resume(struct pci_dev *pdev); 167 168 /* supported Rage128 chipsets */ 169 static struct pci_device_id aty128_pci_tbl[] = { 170 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE, 171 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci }, 172 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF, 173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 }, 174 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF, 175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, 176 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML, 177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 }, 178 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA, 179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 180 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB, 181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 182 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC, 183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 184 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD, 185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 186 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE, 187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 188 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF, 189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 190 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG, 191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 192 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH, 193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 194 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI, 195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 196 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ, 197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 198 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK, 199 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 200 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL, 201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 202 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM, 203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 204 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN, 205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 206 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO, 207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 208 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP, 209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 210 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ, 211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 212 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR, 213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci }, 214 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS, 215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 216 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT, 217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 218 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU, 219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 220 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV, 221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 222 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW, 223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 224 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX, 225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro }, 226 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE, 227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 228 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF, 229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 230 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG, 231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 232 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK, 233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 234 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL, 235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 236 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE, 237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 238 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF, 239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci }, 240 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG, 241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 242 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH, 243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 244 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK, 245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 246 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL, 247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 248 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM, 249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 250 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN, 251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 }, 252 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF, 253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 254 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL, 255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 256 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR, 257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 258 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS, 259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 260 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT, 261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 262 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU, 263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra }, 264 { 0, } 265 }; 266 267 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl); 268 269 static struct pci_driver aty128fb_driver = { 270 .name = "aty128fb", 271 .id_table = aty128_pci_tbl, 272 .probe = aty128_probe, 273 .remove = aty128_remove, 274 .suspend = aty128_pci_suspend, 275 .resume = aty128_pci_resume, 276 }; 277 278 /* packed BIOS settings */ 279 #ifndef CONFIG_PPC 280 typedef struct { 281 u8 clock_chip_type; 282 u8 struct_size; 283 u8 accelerator_entry; 284 u8 VGA_entry; 285 u16 VGA_table_offset; 286 u16 POST_table_offset; 287 u16 XCLK; 288 u16 MCLK; 289 u8 num_PLL_blocks; 290 u8 size_PLL_blocks; 291 u16 PCLK_ref_freq; 292 u16 PCLK_ref_divider; 293 u32 PCLK_min_freq; 294 u32 PCLK_max_freq; 295 u16 MCLK_ref_freq; 296 u16 MCLK_ref_divider; 297 u32 MCLK_min_freq; 298 u32 MCLK_max_freq; 299 u16 XCLK_ref_freq; 300 u16 XCLK_ref_divider; 301 u32 XCLK_min_freq; 302 u32 XCLK_max_freq; 303 } __attribute__ ((packed)) PLL_BLOCK; 304 #endif /* !CONFIG_PPC */ 305 306 /* onboard memory information */ 307 struct aty128_meminfo { 308 u8 ML; 309 u8 MB; 310 u8 Trcd; 311 u8 Trp; 312 u8 Twr; 313 u8 CL; 314 u8 Tr2w; 315 u8 LoopLatency; 316 u8 DspOn; 317 u8 Rloop; 318 const char *name; 319 }; 320 321 /* various memory configurations */ 322 static const struct aty128_meminfo sdr_128 = { 323 .ML = 4, 324 .MB = 4, 325 .Trcd = 3, 326 .Trp = 3, 327 .Twr = 1, 328 .CL = 3, 329 .Tr2w = 1, 330 .LoopLatency = 16, 331 .DspOn = 30, 332 .Rloop = 16, 333 .name = "128-bit SDR SGRAM (1:1)", 334 }; 335 336 static const struct aty128_meminfo sdr_64 = { 337 .ML = 4, 338 .MB = 8, 339 .Trcd = 3, 340 .Trp = 3, 341 .Twr = 1, 342 .CL = 3, 343 .Tr2w = 1, 344 .LoopLatency = 17, 345 .DspOn = 46, 346 .Rloop = 17, 347 .name = "64-bit SDR SGRAM (1:1)", 348 }; 349 350 static const struct aty128_meminfo sdr_sgram = { 351 .ML = 4, 352 .MB = 4, 353 .Trcd = 1, 354 .Trp = 2, 355 .Twr = 1, 356 .CL = 2, 357 .Tr2w = 1, 358 .LoopLatency = 16, 359 .DspOn = 24, 360 .Rloop = 16, 361 .name = "64-bit SDR SGRAM (2:1)", 362 }; 363 364 static const struct aty128_meminfo ddr_sgram = { 365 .ML = 4, 366 .MB = 4, 367 .Trcd = 3, 368 .Trp = 3, 369 .Twr = 2, 370 .CL = 3, 371 .Tr2w = 1, 372 .LoopLatency = 16, 373 .DspOn = 31, 374 .Rloop = 16, 375 .name = "64-bit DDR SGRAM", 376 }; 377 378 static struct fb_fix_screeninfo aty128fb_fix = { 379 .id = "ATY Rage128", 380 .type = FB_TYPE_PACKED_PIXELS, 381 .visual = FB_VISUAL_PSEUDOCOLOR, 382 .xpanstep = 8, 383 .ypanstep = 1, 384 .mmio_len = 0x2000, 385 .accel = FB_ACCEL_ATI_RAGE128, 386 }; 387 388 static char *mode_option = NULL; 389 390 #ifdef CONFIG_PPC_PMAC 391 static int default_vmode = VMODE_1024_768_60; 392 static int default_cmode = CMODE_8; 393 #endif 394 395 static int default_crt_on = 0; 396 static int default_lcd_on = 1; 397 static bool mtrr = true; 398 399 #ifdef CONFIG_FB_ATY128_BACKLIGHT 400 #ifdef CONFIG_PMAC_BACKLIGHT 401 static int backlight = 1; 402 #else 403 static int backlight = 0; 404 #endif 405 #endif 406 407 /* PLL constants */ 408 struct aty128_constants { 409 u32 ref_clk; 410 u32 ppll_min; 411 u32 ppll_max; 412 u32 ref_divider; 413 u32 xclk; 414 u32 fifo_width; 415 u32 fifo_depth; 416 }; 417 418 struct aty128_crtc { 419 u32 gen_cntl; 420 u32 h_total, h_sync_strt_wid; 421 u32 v_total, v_sync_strt_wid; 422 u32 pitch; 423 u32 offset, offset_cntl; 424 u32 xoffset, yoffset; 425 u32 vxres, vyres; 426 u32 depth, bpp; 427 }; 428 429 struct aty128_pll { 430 u32 post_divider; 431 u32 feedback_divider; 432 u32 vclk; 433 }; 434 435 struct aty128_ddafifo { 436 u32 dda_config; 437 u32 dda_on_off; 438 }; 439 440 /* register values for a specific mode */ 441 struct aty128fb_par { 442 struct aty128_crtc crtc; 443 struct aty128_pll pll; 444 struct aty128_ddafifo fifo_reg; 445 u32 accel_flags; 446 struct aty128_constants constants; /* PLL and others */ 447 void __iomem *regbase; /* remapped mmio */ 448 u32 vram_size; /* onboard video ram */ 449 int chip_gen; 450 const struct aty128_meminfo *mem; /* onboard mem info */ 451 int wc_cookie; 452 int blitter_may_be_busy; 453 int fifo_slots; /* free slots in FIFO (64 max) */ 454 455 int crt_on, lcd_on; 456 struct pci_dev *pdev; 457 struct fb_info *next; 458 int asleep; 459 int lock_blank; 460 461 u8 red[32]; /* see aty128fb_setcolreg */ 462 u8 green[64]; 463 u8 blue[32]; 464 u32 pseudo_palette[16]; /* used for TRUECOLOR */ 465 }; 466 467 468 #define round_div(n, d) ((n+(d/2))/d) 469 470 static int aty128fb_check_var(struct fb_var_screeninfo *var, 471 struct fb_info *info); 472 static int aty128fb_set_par(struct fb_info *info); 473 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 474 u_int transp, struct fb_info *info); 475 static int aty128fb_pan_display(struct fb_var_screeninfo *var, 476 struct fb_info *fb); 477 static int aty128fb_blank(int blank, struct fb_info *fb); 478 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg); 479 static int aty128fb_sync(struct fb_info *info); 480 481 /* 482 * Internal routines 483 */ 484 485 static int aty128_encode_var(struct fb_var_screeninfo *var, 486 const struct aty128fb_par *par); 487 static int aty128_decode_var(struct fb_var_screeninfo *var, 488 struct aty128fb_par *par); 489 #if 0 490 static void aty128_get_pllinfo(struct aty128fb_par *par, void __iomem *bios); 491 static void __iomem *aty128_map_ROM(struct pci_dev *pdev, 492 const struct aty128fb_par *par); 493 #endif 494 static void aty128_timings(struct aty128fb_par *par); 495 static void aty128_init_engine(struct aty128fb_par *par); 496 static void aty128_reset_engine(const struct aty128fb_par *par); 497 static void aty128_flush_pixel_cache(const struct aty128fb_par *par); 498 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par); 499 static void wait_for_fifo(u16 entries, struct aty128fb_par *par); 500 static void wait_for_idle(struct aty128fb_par *par); 501 static u32 depth_to_dst(u32 depth); 502 503 #ifdef CONFIG_FB_ATY128_BACKLIGHT 504 static void aty128_bl_set_power(struct fb_info *info, int power); 505 #endif 506 507 #define BIOS_IN8(v) (readb(bios + (v))) 508 #define BIOS_IN16(v) (readb(bios + (v)) | \ 509 (readb(bios + (v) + 1) << 8)) 510 #define BIOS_IN32(v) (readb(bios + (v)) | \ 511 (readb(bios + (v) + 1) << 8) | \ 512 (readb(bios + (v) + 2) << 16) | \ 513 (readb(bios + (v) + 3) << 24)) 514 515 516 static struct fb_ops aty128fb_ops = { 517 .owner = THIS_MODULE, 518 .fb_check_var = aty128fb_check_var, 519 .fb_set_par = aty128fb_set_par, 520 .fb_setcolreg = aty128fb_setcolreg, 521 .fb_pan_display = aty128fb_pan_display, 522 .fb_blank = aty128fb_blank, 523 .fb_ioctl = aty128fb_ioctl, 524 .fb_sync = aty128fb_sync, 525 .fb_fillrect = cfb_fillrect, 526 .fb_copyarea = cfb_copyarea, 527 .fb_imageblit = cfb_imageblit, 528 }; 529 530 /* 531 * Functions to read from/write to the mmio registers 532 * - endian conversions may possibly be avoided by 533 * using the other register aperture. TODO. 534 */ 535 static inline u32 _aty_ld_le32(volatile unsigned int regindex, 536 const struct aty128fb_par *par) 537 { 538 return readl (par->regbase + regindex); 539 } 540 541 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val, 542 const struct aty128fb_par *par) 543 { 544 writel (val, par->regbase + regindex); 545 } 546 547 static inline u8 _aty_ld_8(unsigned int regindex, 548 const struct aty128fb_par *par) 549 { 550 return readb (par->regbase + regindex); 551 } 552 553 static inline void _aty_st_8(unsigned int regindex, u8 val, 554 const struct aty128fb_par *par) 555 { 556 writeb (val, par->regbase + regindex); 557 } 558 559 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par) 560 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par) 561 #define aty_ld_8(regindex) _aty_ld_8(regindex, par) 562 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par) 563 564 /* 565 * Functions to read from/write to the pll registers 566 */ 567 568 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par) 569 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par) 570 571 572 static u32 _aty_ld_pll(unsigned int pll_index, 573 const struct aty128fb_par *par) 574 { 575 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); 576 return aty_ld_le32(CLOCK_CNTL_DATA); 577 } 578 579 580 static void _aty_st_pll(unsigned int pll_index, u32 val, 581 const struct aty128fb_par *par) 582 { 583 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); 584 aty_st_le32(CLOCK_CNTL_DATA, val); 585 } 586 587 588 /* return true when the PLL has completed an atomic update */ 589 static int aty_pll_readupdate(const struct aty128fb_par *par) 590 { 591 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); 592 } 593 594 595 static void aty_pll_wait_readupdate(const struct aty128fb_par *par) 596 { 597 unsigned long timeout = jiffies + HZ/100; // should be more than enough 598 int reset = 1; 599 600 while (time_before(jiffies, timeout)) 601 if (aty_pll_readupdate(par)) { 602 reset = 0; 603 break; 604 } 605 606 if (reset) /* reset engine?? */ 607 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n"); 608 } 609 610 611 /* tell PLL to update */ 612 static void aty_pll_writeupdate(const struct aty128fb_par *par) 613 { 614 aty_pll_wait_readupdate(par); 615 616 aty_st_pll(PPLL_REF_DIV, 617 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); 618 } 619 620 621 /* write to the scratch register to test r/w functionality */ 622 static int register_test(const struct aty128fb_par *par) 623 { 624 u32 val; 625 int flag = 0; 626 627 val = aty_ld_le32(BIOS_0_SCRATCH); 628 629 aty_st_le32(BIOS_0_SCRATCH, 0x55555555); 630 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) { 631 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); 632 633 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA) 634 flag = 1; 635 } 636 637 aty_st_le32(BIOS_0_SCRATCH, val); // restore value 638 return flag; 639 } 640 641 642 /* 643 * Accelerator engine functions 644 */ 645 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par) 646 { 647 int i; 648 649 for (;;) { 650 for (i = 0; i < 2000000; i++) { 651 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff; 652 if (par->fifo_slots >= entries) 653 return; 654 } 655 aty128_reset_engine(par); 656 } 657 } 658 659 660 static void wait_for_idle(struct aty128fb_par *par) 661 { 662 int i; 663 664 do_wait_for_fifo(64, par); 665 666 for (;;) { 667 for (i = 0; i < 2000000; i++) { 668 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) { 669 aty128_flush_pixel_cache(par); 670 par->blitter_may_be_busy = 0; 671 return; 672 } 673 } 674 aty128_reset_engine(par); 675 } 676 } 677 678 679 static void wait_for_fifo(u16 entries, struct aty128fb_par *par) 680 { 681 if (par->fifo_slots < entries) 682 do_wait_for_fifo(64, par); 683 par->fifo_slots -= entries; 684 } 685 686 687 static void aty128_flush_pixel_cache(const struct aty128fb_par *par) 688 { 689 int i; 690 u32 tmp; 691 692 tmp = aty_ld_le32(PC_NGUI_CTLSTAT); 693 tmp &= ~(0x00ff); 694 tmp |= 0x00ff; 695 aty_st_le32(PC_NGUI_CTLSTAT, tmp); 696 697 for (i = 0; i < 2000000; i++) 698 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY)) 699 break; 700 } 701 702 703 static void aty128_reset_engine(const struct aty128fb_par *par) 704 { 705 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl; 706 707 aty128_flush_pixel_cache(par); 708 709 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX); 710 mclk_cntl = aty_ld_pll(MCLK_CNTL); 711 712 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000); 713 714 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL); 715 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); 716 aty_ld_le32(GEN_RESET_CNTL); 717 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); 718 aty_ld_le32(GEN_RESET_CNTL); 719 720 aty_st_pll(MCLK_CNTL, mclk_cntl); 721 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); 722 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); 723 724 /* use old pio mode */ 725 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); 726 727 DBG("engine reset"); 728 } 729 730 731 static void aty128_init_engine(struct aty128fb_par *par) 732 { 733 u32 pitch_value; 734 735 wait_for_idle(par); 736 737 /* 3D scaler not spoken here */ 738 wait_for_fifo(1, par); 739 aty_st_le32(SCALE_3D_CNTL, 0x00000000); 740 741 aty128_reset_engine(par); 742 743 pitch_value = par->crtc.pitch; 744 if (par->crtc.bpp == 24) { 745 pitch_value = pitch_value * 3; 746 } 747 748 wait_for_fifo(4, par); 749 /* setup engine offset registers */ 750 aty_st_le32(DEFAULT_OFFSET, 0x00000000); 751 752 /* setup engine pitch registers */ 753 aty_st_le32(DEFAULT_PITCH, pitch_value); 754 755 /* set the default scissor register to max dimensions */ 756 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); 757 758 /* set the drawing controls registers */ 759 aty_st_le32(DP_GUI_MASTER_CNTL, 760 GMC_SRC_PITCH_OFFSET_DEFAULT | 761 GMC_DST_PITCH_OFFSET_DEFAULT | 762 GMC_SRC_CLIP_DEFAULT | 763 GMC_DST_CLIP_DEFAULT | 764 GMC_BRUSH_SOLIDCOLOR | 765 (depth_to_dst(par->crtc.depth) << 8) | 766 GMC_SRC_DSTCOLOR | 767 GMC_BYTE_ORDER_MSB_TO_LSB | 768 GMC_DP_CONVERSION_TEMP_6500 | 769 ROP3_PATCOPY | 770 GMC_DP_SRC_RECT | 771 GMC_3D_FCN_EN_CLR | 772 GMC_DST_CLR_CMP_FCN_CLEAR | 773 GMC_AUX_CLIP_CLEAR | 774 GMC_WRITE_MASK_SET); 775 776 wait_for_fifo(8, par); 777 /* clear the line drawing registers */ 778 aty_st_le32(DST_BRES_ERR, 0); 779 aty_st_le32(DST_BRES_INC, 0); 780 aty_st_le32(DST_BRES_DEC, 0); 781 782 /* set brush color registers */ 783 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ 784 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ 785 786 /* set source color registers */ 787 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ 788 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ 789 790 /* default write mask */ 791 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); 792 793 /* Wait for all the writes to be completed before returning */ 794 wait_for_idle(par); 795 } 796 797 798 /* convert depth values to their register representation */ 799 static u32 depth_to_dst(u32 depth) 800 { 801 if (depth <= 8) 802 return DST_8BPP; 803 else if (depth <= 15) 804 return DST_15BPP; 805 else if (depth == 16) 806 return DST_16BPP; 807 else if (depth <= 24) 808 return DST_24BPP; 809 else if (depth <= 32) 810 return DST_32BPP; 811 812 return -EINVAL; 813 } 814 815 /* 816 * PLL informations retreival 817 */ 818 819 820 #ifndef __sparc__ 821 static void __iomem *aty128_map_ROM(const struct aty128fb_par *par, 822 struct pci_dev *dev) 823 { 824 u16 dptr; 825 u8 rom_type; 826 void __iomem *bios; 827 size_t rom_size; 828 829 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */ 830 unsigned int temp; 831 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); 832 temp &= 0x00ffffffu; 833 temp |= 0x04 << 24; 834 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp); 835 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG); 836 837 bios = pci_map_rom(dev, &rom_size); 838 839 if (!bios) { 840 printk(KERN_ERR "aty128fb: ROM failed to map\n"); 841 return NULL; 842 } 843 844 /* Very simple test to make sure it appeared */ 845 if (BIOS_IN16(0) != 0xaa55) { 846 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should " 847 " be 0xaa55\n", BIOS_IN16(0)); 848 goto failed; 849 } 850 851 /* Look for the PCI data to check the ROM type */ 852 dptr = BIOS_IN16(0x18); 853 854 /* Check the PCI data signature. If it's wrong, we still assume a normal 855 * x86 ROM for now, until I've verified this works everywhere. 856 * The goal here is more to phase out Open Firmware images. 857 * 858 * Currently, we only look at the first PCI data, we could iteratre and 859 * deal with them all, and we should use fb_bios_start relative to start 860 * of image and not relative start of ROM, but so far, I never found a 861 * dual-image ATI card. 862 * 863 * typedef struct { 864 * u32 signature; + 0x00 865 * u16 vendor; + 0x04 866 * u16 device; + 0x06 867 * u16 reserved_1; + 0x08 868 * u16 dlen; + 0x0a 869 * u8 drevision; + 0x0c 870 * u8 class_hi; + 0x0d 871 * u16 class_lo; + 0x0e 872 * u16 ilen; + 0x10 873 * u16 irevision; + 0x12 874 * u8 type; + 0x14 875 * u8 indicator; + 0x15 876 * u16 reserved_2; + 0x16 877 * } pci_data_t; 878 */ 879 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { 880 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n", 881 BIOS_IN32(dptr)); 882 goto anyway; 883 } 884 rom_type = BIOS_IN8(dptr + 0x14); 885 switch(rom_type) { 886 case 0: 887 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n"); 888 break; 889 case 1: 890 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n"); 891 goto failed; 892 case 2: 893 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n"); 894 goto failed; 895 default: 896 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", 897 rom_type); 898 goto failed; 899 } 900 anyway: 901 return bios; 902 903 failed: 904 pci_unmap_rom(dev, bios); 905 return NULL; 906 } 907 908 static void aty128_get_pllinfo(struct aty128fb_par *par, 909 unsigned char __iomem *bios) 910 { 911 unsigned int bios_hdr; 912 unsigned int bios_pll; 913 914 bios_hdr = BIOS_IN16(0x48); 915 bios_pll = BIOS_IN16(bios_hdr + 0x30); 916 917 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16); 918 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12); 919 par->constants.xclk = BIOS_IN16(bios_pll + 0x08); 920 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10); 921 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e); 922 923 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n", 924 par->constants.ppll_max, par->constants.ppll_min, 925 par->constants.xclk, par->constants.ref_divider, 926 par->constants.ref_clk); 927 928 } 929 930 #ifdef CONFIG_X86 931 static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par) 932 { 933 /* I simplified this code as we used to miss the signatures in 934 * a lot of case. It's now closer to XFree, we just don't check 935 * for signatures at all... Something better will have to be done 936 * if we end up having conflicts 937 */ 938 u32 segstart; 939 unsigned char __iomem *rom_base = NULL; 940 941 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { 942 rom_base = ioremap(segstart, 0x10000); 943 if (rom_base == NULL) 944 return NULL; 945 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) 946 break; 947 iounmap(rom_base); 948 rom_base = NULL; 949 } 950 return rom_base; 951 } 952 #endif 953 #endif /* ndef(__sparc__) */ 954 955 /* fill in known card constants if pll_block is not available */ 956 static void aty128_timings(struct aty128fb_par *par) 957 { 958 #ifdef CONFIG_PPC 959 /* instead of a table lookup, assume OF has properly 960 * setup the PLL registers and use their values 961 * to set the XCLK values and reference divider values */ 962 963 u32 x_mpll_ref_fb_div; 964 u32 xclk_cntl; 965 u32 Nx, M; 966 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 }; 967 #endif 968 969 if (!par->constants.ref_clk) 970 par->constants.ref_clk = 2950; 971 972 #ifdef CONFIG_PPC 973 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV); 974 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7; 975 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8; 976 M = x_mpll_ref_fb_div & 0x0000ff; 977 978 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk), 979 (M * PostDivSet[xclk_cntl])); 980 981 par->constants.ref_divider = 982 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; 983 #endif 984 985 if (!par->constants.ref_divider) { 986 par->constants.ref_divider = 0x3b; 987 988 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e); 989 aty_pll_writeupdate(par); 990 } 991 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider); 992 aty_pll_writeupdate(par); 993 994 /* from documentation */ 995 if (!par->constants.ppll_min) 996 par->constants.ppll_min = 12500; 997 if (!par->constants.ppll_max) 998 par->constants.ppll_max = 25000; /* 23000 on some cards? */ 999 if (!par->constants.xclk) 1000 par->constants.xclk = 0x1d4d; /* same as mclk */ 1001 1002 par->constants.fifo_width = 128; 1003 par->constants.fifo_depth = 32; 1004 1005 switch (aty_ld_le32(MEM_CNTL) & 0x3) { 1006 case 0: 1007 par->mem = &sdr_128; 1008 break; 1009 case 1: 1010 par->mem = &sdr_sgram; 1011 break; 1012 case 2: 1013 par->mem = &ddr_sgram; 1014 break; 1015 default: 1016 par->mem = &sdr_sgram; 1017 } 1018 } 1019 1020 1021 1022 /* 1023 * CRTC programming 1024 */ 1025 1026 /* Program the CRTC registers */ 1027 static void aty128_set_crtc(const struct aty128_crtc *crtc, 1028 const struct aty128fb_par *par) 1029 { 1030 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); 1031 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); 1032 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 1033 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); 1034 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 1035 aty_st_le32(CRTC_PITCH, crtc->pitch); 1036 aty_st_le32(CRTC_OFFSET, crtc->offset); 1037 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); 1038 /* Disable ATOMIC updating. Is this the right place? */ 1039 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); 1040 } 1041 1042 1043 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var, 1044 struct aty128_crtc *crtc, 1045 const struct aty128fb_par *par) 1046 { 1047 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst; 1048 u32 left, right, upper, lower, hslen, vslen, sync, vmode; 1049 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol; 1050 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1051 u32 depth, bytpp; 1052 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 }; 1053 1054 /* input */ 1055 xres = var->xres; 1056 yres = var->yres; 1057 vxres = var->xres_virtual; 1058 vyres = var->yres_virtual; 1059 xoffset = var->xoffset; 1060 yoffset = var->yoffset; 1061 bpp = var->bits_per_pixel; 1062 left = var->left_margin; 1063 right = var->right_margin; 1064 upper = var->upper_margin; 1065 lower = var->lower_margin; 1066 hslen = var->hsync_len; 1067 vslen = var->vsync_len; 1068 sync = var->sync; 1069 vmode = var->vmode; 1070 1071 if (bpp != 16) 1072 depth = bpp; 1073 else 1074 depth = (var->green.length == 6) ? 16 : 15; 1075 1076 /* check for mode eligibility 1077 * accept only non interlaced modes */ 1078 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 1079 return -EINVAL; 1080 1081 /* convert (and round up) and validate */ 1082 xres = (xres + 7) & ~7; 1083 xoffset = (xoffset + 7) & ~7; 1084 1085 if (vxres < xres + xoffset) 1086 vxres = xres + xoffset; 1087 1088 if (vyres < yres + yoffset) 1089 vyres = yres + yoffset; 1090 1091 /* convert depth into ATI register depth */ 1092 dst = depth_to_dst(depth); 1093 1094 if (dst == -EINVAL) { 1095 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n"); 1096 return -EINVAL; 1097 } 1098 1099 /* convert register depth to bytes per pixel */ 1100 bytpp = mode_bytpp[dst]; 1101 1102 /* make sure there is enough video ram for the mode */ 1103 if ((u32)(vxres * vyres * bytpp) > par->vram_size) { 1104 printk(KERN_ERR "aty128fb: Not enough memory for mode\n"); 1105 return -EINVAL; 1106 } 1107 1108 h_disp = (xres >> 3) - 1; 1109 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL; 1110 1111 v_disp = yres - 1; 1112 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; 1113 1114 /* check to make sure h_total and v_total are in range */ 1115 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { 1116 printk(KERN_ERR "aty128fb: invalid width ranges\n"); 1117 return -EINVAL; 1118 } 1119 1120 h_sync_wid = (hslen + 7) >> 3; 1121 if (h_sync_wid == 0) 1122 h_sync_wid = 1; 1123 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */ 1124 h_sync_wid = 0x3f; 1125 1126 h_sync_strt = (h_disp << 3) + right; 1127 1128 v_sync_wid = vslen; 1129 if (v_sync_wid == 0) 1130 v_sync_wid = 1; 1131 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */ 1132 v_sync_wid = 0x1f; 1133 1134 v_sync_strt = v_disp + lower; 1135 1136 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 1137 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 1138 1139 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; 1140 1141 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8); 1142 1143 crtc->h_total = h_total | (h_disp << 16); 1144 crtc->v_total = v_total | (v_disp << 16); 1145 1146 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) | 1147 (h_sync_pol << 23); 1148 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) | 1149 (v_sync_pol << 23); 1150 1151 crtc->pitch = vxres >> 3; 1152 1153 crtc->offset = 0; 1154 1155 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) 1156 crtc->offset_cntl = 0x00010000; 1157 else 1158 crtc->offset_cntl = 0; 1159 1160 crtc->vxres = vxres; 1161 crtc->vyres = vyres; 1162 crtc->xoffset = xoffset; 1163 crtc->yoffset = yoffset; 1164 crtc->depth = depth; 1165 crtc->bpp = bpp; 1166 1167 return 0; 1168 } 1169 1170 1171 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var) 1172 { 1173 1174 /* fill in pixel info */ 1175 var->red.msb_right = 0; 1176 var->green.msb_right = 0; 1177 var->blue.offset = 0; 1178 var->blue.msb_right = 0; 1179 var->transp.offset = 0; 1180 var->transp.length = 0; 1181 var->transp.msb_right = 0; 1182 switch (pix_width) { 1183 case CRTC_PIX_WIDTH_8BPP: 1184 var->bits_per_pixel = 8; 1185 var->red.offset = 0; 1186 var->red.length = 8; 1187 var->green.offset = 0; 1188 var->green.length = 8; 1189 var->blue.length = 8; 1190 break; 1191 case CRTC_PIX_WIDTH_15BPP: 1192 var->bits_per_pixel = 16; 1193 var->red.offset = 10; 1194 var->red.length = 5; 1195 var->green.offset = 5; 1196 var->green.length = 5; 1197 var->blue.length = 5; 1198 break; 1199 case CRTC_PIX_WIDTH_16BPP: 1200 var->bits_per_pixel = 16; 1201 var->red.offset = 11; 1202 var->red.length = 5; 1203 var->green.offset = 5; 1204 var->green.length = 6; 1205 var->blue.length = 5; 1206 break; 1207 case CRTC_PIX_WIDTH_24BPP: 1208 var->bits_per_pixel = 24; 1209 var->red.offset = 16; 1210 var->red.length = 8; 1211 var->green.offset = 8; 1212 var->green.length = 8; 1213 var->blue.length = 8; 1214 break; 1215 case CRTC_PIX_WIDTH_32BPP: 1216 var->bits_per_pixel = 32; 1217 var->red.offset = 16; 1218 var->red.length = 8; 1219 var->green.offset = 8; 1220 var->green.length = 8; 1221 var->blue.length = 8; 1222 var->transp.offset = 24; 1223 var->transp.length = 8; 1224 break; 1225 default: 1226 printk(KERN_ERR "aty128fb: Invalid pixel width\n"); 1227 return -EINVAL; 1228 } 1229 1230 return 0; 1231 } 1232 1233 1234 static int aty128_crtc_to_var(const struct aty128_crtc *crtc, 1235 struct fb_var_screeninfo *var) 1236 { 1237 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync; 1238 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; 1239 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1240 u32 pix_width; 1241 1242 /* fun with masking */ 1243 h_total = crtc->h_total & 0x1ff; 1244 h_disp = (crtc->h_total >> 16) & 0xff; 1245 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff; 1246 h_sync_dly = crtc->h_sync_strt_wid & 0x7; 1247 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f; 1248 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1; 1249 v_total = crtc->v_total & 0x7ff; 1250 v_disp = (crtc->v_total >> 16) & 0x7ff; 1251 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; 1252 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; 1253 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1; 1254 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; 1255 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; 1256 1257 /* do conversions */ 1258 xres = (h_disp + 1) << 3; 1259 yres = v_disp + 1; 1260 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly; 1261 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly; 1262 hslen = h_sync_wid << 3; 1263 upper = v_total - v_sync_strt - v_sync_wid; 1264 lower = v_sync_strt - v_disp; 1265 vslen = v_sync_wid; 1266 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | 1267 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | 1268 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); 1269 1270 aty128_pix_width_to_var(pix_width, var); 1271 1272 var->xres = xres; 1273 var->yres = yres; 1274 var->xres_virtual = crtc->vxres; 1275 var->yres_virtual = crtc->vyres; 1276 var->xoffset = crtc->xoffset; 1277 var->yoffset = crtc->yoffset; 1278 var->left_margin = left; 1279 var->right_margin = right; 1280 var->upper_margin = upper; 1281 var->lower_margin = lower; 1282 var->hsync_len = hslen; 1283 var->vsync_len = vslen; 1284 var->sync = sync; 1285 var->vmode = FB_VMODE_NONINTERLACED; 1286 1287 return 0; 1288 } 1289 1290 static void aty128_set_crt_enable(struct aty128fb_par *par, int on) 1291 { 1292 if (on) { 1293 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | 1294 CRT_CRTC_ON); 1295 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | 1296 DAC_PALETTE2_SNOOP_EN)); 1297 } else 1298 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & 1299 ~CRT_CRTC_ON); 1300 } 1301 1302 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on) 1303 { 1304 u32 reg; 1305 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1306 struct fb_info *info = pci_get_drvdata(par->pdev); 1307 #endif 1308 1309 if (on) { 1310 reg = aty_ld_le32(LVDS_GEN_CNTL); 1311 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION; 1312 reg &= ~LVDS_DISPLAY_DIS; 1313 aty_st_le32(LVDS_GEN_CNTL, reg); 1314 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1315 aty128_bl_set_power(info, FB_BLANK_UNBLANK); 1316 #endif 1317 } else { 1318 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1319 aty128_bl_set_power(info, FB_BLANK_POWERDOWN); 1320 #endif 1321 reg = aty_ld_le32(LVDS_GEN_CNTL); 1322 reg |= LVDS_DISPLAY_DIS; 1323 aty_st_le32(LVDS_GEN_CNTL, reg); 1324 mdelay(100); 1325 reg &= ~(LVDS_ON /*| LVDS_EN*/); 1326 aty_st_le32(LVDS_GEN_CNTL, reg); 1327 } 1328 } 1329 1330 static void aty128_set_pll(struct aty128_pll *pll, 1331 const struct aty128fb_par *par) 1332 { 1333 u32 div3; 1334 1335 unsigned char post_conv[] = /* register values for post dividers */ 1336 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 }; 1337 1338 /* select PPLL_DIV_3 */ 1339 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); 1340 1341 /* reset PLL */ 1342 aty_st_pll(PPLL_CNTL, 1343 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN); 1344 1345 /* write the reference divider */ 1346 aty_pll_wait_readupdate(par); 1347 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff); 1348 aty_pll_writeupdate(par); 1349 1350 div3 = aty_ld_pll(PPLL_DIV_3); 1351 div3 &= ~PPLL_FB3_DIV_MASK; 1352 div3 |= pll->feedback_divider; 1353 div3 &= ~PPLL_POST3_DIV_MASK; 1354 div3 |= post_conv[pll->post_divider] << 16; 1355 1356 /* write feedback and post dividers */ 1357 aty_pll_wait_readupdate(par); 1358 aty_st_pll(PPLL_DIV_3, div3); 1359 aty_pll_writeupdate(par); 1360 1361 aty_pll_wait_readupdate(par); 1362 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ 1363 aty_pll_writeupdate(par); 1364 1365 /* clear the reset, just in case */ 1366 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET); 1367 } 1368 1369 1370 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, 1371 const struct aty128fb_par *par) 1372 { 1373 const struct aty128_constants c = par->constants; 1374 unsigned char post_dividers[] = {1,2,4,8,3,6,12}; 1375 u32 output_freq; 1376 u32 vclk; /* in .01 MHz */ 1377 int i = 0; 1378 u32 n, d; 1379 1380 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ 1381 1382 /* adjust pixel clock if necessary */ 1383 if (vclk > c.ppll_max) 1384 vclk = c.ppll_max; 1385 if (vclk * 12 < c.ppll_min) 1386 vclk = c.ppll_min/12; 1387 1388 /* now, find an acceptable divider */ 1389 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) { 1390 output_freq = post_dividers[i] * vclk; 1391 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) { 1392 pll->post_divider = post_dividers[i]; 1393 break; 1394 } 1395 } 1396 1397 if (i == ARRAY_SIZE(post_dividers)) 1398 return -EINVAL; 1399 1400 /* calculate feedback divider */ 1401 n = c.ref_divider * output_freq; 1402 d = c.ref_clk; 1403 1404 pll->feedback_divider = round_div(n, d); 1405 pll->vclk = vclk; 1406 1407 DBG("post %d feedback %d vlck %d output %d ref_divider %d " 1408 "vclk_per: %d\n", pll->post_divider, 1409 pll->feedback_divider, vclk, output_freq, 1410 c.ref_divider, period_in_ps); 1411 1412 return 0; 1413 } 1414 1415 1416 static int aty128_pll_to_var(const struct aty128_pll *pll, 1417 struct fb_var_screeninfo *var) 1418 { 1419 var->pixclock = 100000000 / pll->vclk; 1420 1421 return 0; 1422 } 1423 1424 1425 static void aty128_set_fifo(const struct aty128_ddafifo *dsp, 1426 const struct aty128fb_par *par) 1427 { 1428 aty_st_le32(DDA_CONFIG, dsp->dda_config); 1429 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); 1430 } 1431 1432 1433 static int aty128_ddafifo(struct aty128_ddafifo *dsp, 1434 const struct aty128_pll *pll, 1435 u32 depth, 1436 const struct aty128fb_par *par) 1437 { 1438 const struct aty128_meminfo *m = par->mem; 1439 u32 xclk = par->constants.xclk; 1440 u32 fifo_width = par->constants.fifo_width; 1441 u32 fifo_depth = par->constants.fifo_depth; 1442 s32 x, b, p, ron, roff; 1443 u32 n, d, bpp; 1444 1445 /* round up to multiple of 8 */ 1446 bpp = (depth+7) & ~7; 1447 1448 n = xclk * fifo_width; 1449 d = pll->vclk * bpp; 1450 x = round_div(n, d); 1451 1452 ron = 4 * m->MB + 1453 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) + 1454 2 * m->Trp + 1455 m->Twr + 1456 m->CL + 1457 m->Tr2w + 1458 x; 1459 1460 DBG("x %x\n", x); 1461 1462 b = 0; 1463 while (x) { 1464 x >>= 1; 1465 b++; 1466 } 1467 p = b + 1; 1468 1469 ron <<= (11 - p); 1470 1471 n <<= (11 - p); 1472 x = round_div(n, d); 1473 roff = x * (fifo_depth - 4); 1474 1475 if ((ron + m->Rloop) >= roff) { 1476 printk(KERN_ERR "aty128fb: Mode out of range!\n"); 1477 return -EINVAL; 1478 } 1479 1480 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n", 1481 p, m->Rloop, x, ron, roff); 1482 1483 dsp->dda_config = p << 16 | m->Rloop << 20 | x; 1484 dsp->dda_on_off = ron << 16 | roff; 1485 1486 return 0; 1487 } 1488 1489 1490 /* 1491 * This actually sets the video mode. 1492 */ 1493 static int aty128fb_set_par(struct fb_info *info) 1494 { 1495 struct aty128fb_par *par = info->par; 1496 u32 config; 1497 int err; 1498 1499 if ((err = aty128_decode_var(&info->var, par)) != 0) 1500 return err; 1501 1502 if (par->blitter_may_be_busy) 1503 wait_for_idle(par); 1504 1505 /* clear all registers that may interfere with mode setting */ 1506 aty_st_le32(OVR_CLR, 0); 1507 aty_st_le32(OVR_WID_LEFT_RIGHT, 0); 1508 aty_st_le32(OVR_WID_TOP_BOTTOM, 0); 1509 aty_st_le32(OV0_SCALE_CNTL, 0); 1510 aty_st_le32(MPP_TB_CONFIG, 0); 1511 aty_st_le32(MPP_GP_CONFIG, 0); 1512 aty_st_le32(SUBPIC_CNTL, 0); 1513 aty_st_le32(VIPH_CONTROL, 0); 1514 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ 1515 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ 1516 aty_st_le32(CAP0_TRIG_CNTL, 0); 1517 aty_st_le32(CAP1_TRIG_CNTL, 0); 1518 1519 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */ 1520 1521 aty128_set_crtc(&par->crtc, par); 1522 aty128_set_pll(&par->pll, par); 1523 aty128_set_fifo(&par->fifo_reg, par); 1524 1525 config = aty_ld_le32(CNFG_CNTL) & ~3; 1526 1527 #if defined(__BIG_ENDIAN) 1528 if (par->crtc.bpp == 32) 1529 config |= 2; /* make aperture do 32 bit swapping */ 1530 else if (par->crtc.bpp == 16) 1531 config |= 1; /* make aperture do 16 bit swapping */ 1532 #endif 1533 1534 aty_st_le32(CNFG_CNTL, config); 1535 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ 1536 1537 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; 1538 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR 1539 : FB_VISUAL_DIRECTCOLOR; 1540 1541 if (par->chip_gen == rage_M3) { 1542 aty128_set_crt_enable(par, par->crt_on); 1543 aty128_set_lcd_enable(par, par->lcd_on); 1544 } 1545 if (par->accel_flags & FB_ACCELF_TEXT) 1546 aty128_init_engine(par); 1547 1548 #ifdef CONFIG_BOOTX_TEXT 1549 btext_update_display(info->fix.smem_start, 1550 (((par->crtc.h_total>>16) & 0xff)+1)*8, 1551 ((par->crtc.v_total>>16) & 0x7ff)+1, 1552 par->crtc.bpp, 1553 par->crtc.vxres*par->crtc.bpp/8); 1554 #endif /* CONFIG_BOOTX_TEXT */ 1555 1556 return 0; 1557 } 1558 1559 /* 1560 * encode/decode the User Defined Part of the Display 1561 */ 1562 1563 static int aty128_decode_var(struct fb_var_screeninfo *var, 1564 struct aty128fb_par *par) 1565 { 1566 int err; 1567 struct aty128_crtc crtc; 1568 struct aty128_pll pll; 1569 struct aty128_ddafifo fifo_reg; 1570 1571 if ((err = aty128_var_to_crtc(var, &crtc, par))) 1572 return err; 1573 1574 if ((err = aty128_var_to_pll(var->pixclock, &pll, par))) 1575 return err; 1576 1577 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par))) 1578 return err; 1579 1580 par->crtc = crtc; 1581 par->pll = pll; 1582 par->fifo_reg = fifo_reg; 1583 par->accel_flags = var->accel_flags; 1584 1585 return 0; 1586 } 1587 1588 1589 static int aty128_encode_var(struct fb_var_screeninfo *var, 1590 const struct aty128fb_par *par) 1591 { 1592 int err; 1593 1594 if ((err = aty128_crtc_to_var(&par->crtc, var))) 1595 return err; 1596 1597 if ((err = aty128_pll_to_var(&par->pll, var))) 1598 return err; 1599 1600 var->nonstd = 0; 1601 var->activate = 0; 1602 1603 var->height = -1; 1604 var->width = -1; 1605 var->accel_flags = par->accel_flags; 1606 1607 return 0; 1608 } 1609 1610 1611 static int aty128fb_check_var(struct fb_var_screeninfo *var, 1612 struct fb_info *info) 1613 { 1614 struct aty128fb_par par; 1615 int err; 1616 1617 par = *(struct aty128fb_par *)info->par; 1618 if ((err = aty128_decode_var(var, &par)) != 0) 1619 return err; 1620 aty128_encode_var(var, &par); 1621 return 0; 1622 } 1623 1624 1625 /* 1626 * Pan or Wrap the Display 1627 */ 1628 static int aty128fb_pan_display(struct fb_var_screeninfo *var, 1629 struct fb_info *fb) 1630 { 1631 struct aty128fb_par *par = fb->par; 1632 u32 xoffset, yoffset; 1633 u32 offset; 1634 u32 xres, yres; 1635 1636 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; 1637 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1; 1638 1639 xoffset = (var->xoffset +7) & ~7; 1640 yoffset = var->yoffset; 1641 1642 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres) 1643 return -EINVAL; 1644 1645 par->crtc.xoffset = xoffset; 1646 par->crtc.yoffset = yoffset; 1647 1648 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3)) 1649 & ~7; 1650 1651 if (par->crtc.bpp == 24) 1652 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */ 1653 1654 aty_st_le32(CRTC_OFFSET, offset); 1655 1656 return 0; 1657 } 1658 1659 1660 /* 1661 * Helper function to store a single palette register 1662 */ 1663 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue, 1664 struct aty128fb_par *par) 1665 { 1666 if (par->chip_gen == rage_M3) { 1667 #if 0 1668 /* Note: For now, on M3, we set palette on both heads, which may 1669 * be useless. Can someone with a M3 check this ? 1670 * 1671 * This code would still be useful if using the second CRTC to 1672 * do mirroring 1673 */ 1674 1675 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | 1676 DAC_PALETTE_ACCESS_CNTL); 1677 aty_st_8(PALETTE_INDEX, regno); 1678 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); 1679 #endif 1680 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & 1681 ~DAC_PALETTE_ACCESS_CNTL); 1682 } 1683 1684 aty_st_8(PALETTE_INDEX, regno); 1685 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); 1686 } 1687 1688 static int aty128fb_sync(struct fb_info *info) 1689 { 1690 struct aty128fb_par *par = info->par; 1691 1692 if (par->blitter_may_be_busy) 1693 wait_for_idle(par); 1694 return 0; 1695 } 1696 1697 #ifndef MODULE 1698 static int aty128fb_setup(char *options) 1699 { 1700 char *this_opt; 1701 1702 if (!options || !*options) 1703 return 0; 1704 1705 while ((this_opt = strsep(&options, ",")) != NULL) { 1706 if (!strncmp(this_opt, "lcd:", 4)) { 1707 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0); 1708 continue; 1709 } else if (!strncmp(this_opt, "crt:", 4)) { 1710 default_crt_on = simple_strtoul(this_opt+4, NULL, 0); 1711 continue; 1712 } else if (!strncmp(this_opt, "backlight:", 10)) { 1713 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1714 backlight = simple_strtoul(this_opt+10, NULL, 0); 1715 #endif 1716 continue; 1717 } 1718 if(!strncmp(this_opt, "nomtrr", 6)) { 1719 mtrr = 0; 1720 continue; 1721 } 1722 #ifdef CONFIG_PPC_PMAC 1723 /* vmode and cmode deprecated */ 1724 if (!strncmp(this_opt, "vmode:", 6)) { 1725 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0); 1726 if (vmode > 0 && vmode <= VMODE_MAX) 1727 default_vmode = vmode; 1728 continue; 1729 } else if (!strncmp(this_opt, "cmode:", 6)) { 1730 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0); 1731 switch (cmode) { 1732 case 0: 1733 case 8: 1734 default_cmode = CMODE_8; 1735 break; 1736 case 15: 1737 case 16: 1738 default_cmode = CMODE_16; 1739 break; 1740 case 24: 1741 case 32: 1742 default_cmode = CMODE_32; 1743 break; 1744 } 1745 continue; 1746 } 1747 #endif /* CONFIG_PPC_PMAC */ 1748 mode_option = this_opt; 1749 } 1750 return 0; 1751 } 1752 #endif /* MODULE */ 1753 1754 /* Backlight */ 1755 #ifdef CONFIG_FB_ATY128_BACKLIGHT 1756 #define MAX_LEVEL 0xFF 1757 1758 static int aty128_bl_get_level_brightness(struct aty128fb_par *par, 1759 int level) 1760 { 1761 struct fb_info *info = pci_get_drvdata(par->pdev); 1762 int atylevel; 1763 1764 /* Get and convert the value */ 1765 /* No locking of bl_curve since we read a single value */ 1766 atylevel = MAX_LEVEL - 1767 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL); 1768 1769 if (atylevel < 0) 1770 atylevel = 0; 1771 else if (atylevel > MAX_LEVEL) 1772 atylevel = MAX_LEVEL; 1773 1774 return atylevel; 1775 } 1776 1777 /* We turn off the LCD completely instead of just dimming the backlight. 1778 * This provides greater power saving and the display is useless without 1779 * backlight anyway 1780 */ 1781 #define BACKLIGHT_LVDS_OFF 1782 /* That one prevents proper CRT output with LCD off */ 1783 #undef BACKLIGHT_DAC_OFF 1784 1785 static int aty128_bl_update_status(struct backlight_device *bd) 1786 { 1787 struct aty128fb_par *par = bl_get_data(bd); 1788 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL); 1789 int level; 1790 1791 if (bd->props.power != FB_BLANK_UNBLANK || 1792 bd->props.fb_blank != FB_BLANK_UNBLANK || 1793 !par->lcd_on) 1794 level = 0; 1795 else 1796 level = bd->props.brightness; 1797 1798 reg |= LVDS_BL_MOD_EN | LVDS_BLON; 1799 if (level > 0) { 1800 reg |= LVDS_DIGION; 1801 if (!(reg & LVDS_ON)) { 1802 reg &= ~LVDS_BLON; 1803 aty_st_le32(LVDS_GEN_CNTL, reg); 1804 aty_ld_le32(LVDS_GEN_CNTL); 1805 mdelay(10); 1806 reg |= LVDS_BLON; 1807 aty_st_le32(LVDS_GEN_CNTL, reg); 1808 } 1809 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 1810 reg |= (aty128_bl_get_level_brightness(par, level) << 1811 LVDS_BL_MOD_LEVEL_SHIFT); 1812 #ifdef BACKLIGHT_LVDS_OFF 1813 reg |= LVDS_ON | LVDS_EN; 1814 reg &= ~LVDS_DISPLAY_DIS; 1815 #endif 1816 aty_st_le32(LVDS_GEN_CNTL, reg); 1817 #ifdef BACKLIGHT_DAC_OFF 1818 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); 1819 #endif 1820 } else { 1821 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 1822 reg |= (aty128_bl_get_level_brightness(par, 0) << 1823 LVDS_BL_MOD_LEVEL_SHIFT); 1824 #ifdef BACKLIGHT_LVDS_OFF 1825 reg |= LVDS_DISPLAY_DIS; 1826 aty_st_le32(LVDS_GEN_CNTL, reg); 1827 aty_ld_le32(LVDS_GEN_CNTL); 1828 udelay(10); 1829 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION); 1830 #endif 1831 aty_st_le32(LVDS_GEN_CNTL, reg); 1832 #ifdef BACKLIGHT_DAC_OFF 1833 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); 1834 #endif 1835 } 1836 1837 return 0; 1838 } 1839 1840 static const struct backlight_ops aty128_bl_data = { 1841 .update_status = aty128_bl_update_status, 1842 }; 1843 1844 static void aty128_bl_set_power(struct fb_info *info, int power) 1845 { 1846 if (info->bl_dev) { 1847 info->bl_dev->props.power = power; 1848 backlight_update_status(info->bl_dev); 1849 } 1850 } 1851 1852 static void aty128_bl_init(struct aty128fb_par *par) 1853 { 1854 struct backlight_properties props; 1855 struct fb_info *info = pci_get_drvdata(par->pdev); 1856 struct backlight_device *bd; 1857 char name[12]; 1858 1859 /* Could be extended to Rage128Pro LVDS output too */ 1860 if (par->chip_gen != rage_M3) 1861 return; 1862 1863 #ifdef CONFIG_PMAC_BACKLIGHT 1864 if (!pmac_has_backlight_type("ati")) 1865 return; 1866 #endif 1867 1868 snprintf(name, sizeof(name), "aty128bl%d", info->node); 1869 1870 memset(&props, 0, sizeof(struct backlight_properties)); 1871 props.type = BACKLIGHT_RAW; 1872 props.max_brightness = FB_BACKLIGHT_LEVELS - 1; 1873 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data, 1874 &props); 1875 if (IS_ERR(bd)) { 1876 info->bl_dev = NULL; 1877 printk(KERN_WARNING "aty128: Backlight registration failed\n"); 1878 goto error; 1879 } 1880 1881 info->bl_dev = bd; 1882 fb_bl_default_curve(info, 0, 1883 63 * FB_BACKLIGHT_MAX / MAX_LEVEL, 1884 219 * FB_BACKLIGHT_MAX / MAX_LEVEL); 1885 1886 bd->props.brightness = bd->props.max_brightness; 1887 bd->props.power = FB_BLANK_UNBLANK; 1888 backlight_update_status(bd); 1889 1890 printk("aty128: Backlight initialized (%s)\n", name); 1891 1892 return; 1893 1894 error: 1895 return; 1896 } 1897 1898 static void aty128_bl_exit(struct backlight_device *bd) 1899 { 1900 backlight_device_unregister(bd); 1901 printk("aty128: Backlight unloaded\n"); 1902 } 1903 #endif /* CONFIG_FB_ATY128_BACKLIGHT */ 1904 1905 /* 1906 * Initialisation 1907 */ 1908 1909 #ifdef CONFIG_PPC_PMAC__disabled 1910 static void aty128_early_resume(void *data) 1911 { 1912 struct aty128fb_par *par = data; 1913 1914 if (!console_trylock()) 1915 return; 1916 pci_restore_state(par->pdev); 1917 aty128_do_resume(par->pdev); 1918 console_unlock(); 1919 } 1920 #endif /* CONFIG_PPC_PMAC */ 1921 1922 static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent) 1923 { 1924 struct fb_info *info = pci_get_drvdata(pdev); 1925 struct aty128fb_par *par = info->par; 1926 struct fb_var_screeninfo var; 1927 char video_card[50]; 1928 u8 chip_rev; 1929 u32 dac; 1930 1931 /* Get the chip revision */ 1932 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F; 1933 1934 strcpy(video_card, "Rage128 XX "); 1935 video_card[8] = ent->device >> 8; 1936 video_card[9] = ent->device & 0xFF; 1937 1938 /* range check to make sure */ 1939 if (ent->driver_data < ARRAY_SIZE(r128_family)) 1940 strlcat(video_card, r128_family[ent->driver_data], 1941 sizeof(video_card)); 1942 1943 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev); 1944 1945 if (par->vram_size % (1024 * 1024) == 0) 1946 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name); 1947 else 1948 printk("%dk %s\n", par->vram_size / 1024, par->mem->name); 1949 1950 par->chip_gen = ent->driver_data; 1951 1952 /* fill in info */ 1953 info->fbops = &aty128fb_ops; 1954 info->flags = FBINFO_FLAG_DEFAULT; 1955 1956 par->lcd_on = default_lcd_on; 1957 par->crt_on = default_crt_on; 1958 1959 var = default_var; 1960 #ifdef CONFIG_PPC_PMAC 1961 if (machine_is(powermac)) { 1962 /* Indicate sleep capability */ 1963 if (par->chip_gen == rage_M3) { 1964 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); 1965 #if 0 /* Disable the early video resume hack for now as it's causing problems, 1966 * among others we now rely on the PCI core restoring the config space 1967 * for us, which isn't the case with that hack, and that code path causes 1968 * various things to be called with interrupts off while they shouldn't. 1969 * I'm leaving the code in as it can be useful for debugging purposes 1970 */ 1971 pmac_set_early_video_resume(aty128_early_resume, par); 1972 #endif 1973 } 1974 1975 /* Find default mode */ 1976 if (mode_option) { 1977 if (!mac_find_mode(&var, info, mode_option, 8)) 1978 var = default_var; 1979 } else { 1980 if (default_vmode <= 0 || default_vmode > VMODE_MAX) 1981 default_vmode = VMODE_1024_768_60; 1982 1983 /* iMacs need that resolution 1984 * PowerMac2,1 first r128 iMacs 1985 * PowerMac2,2 summer 2000 iMacs 1986 * PowerMac4,1 january 2001 iMacs "flower power" 1987 */ 1988 if (of_machine_is_compatible("PowerMac2,1") || 1989 of_machine_is_compatible("PowerMac2,2") || 1990 of_machine_is_compatible("PowerMac4,1")) 1991 default_vmode = VMODE_1024_768_75; 1992 1993 /* iBook SE */ 1994 if (of_machine_is_compatible("PowerBook2,2")) 1995 default_vmode = VMODE_800_600_60; 1996 1997 /* PowerBook Firewire (Pismo), iBook Dual USB */ 1998 if (of_machine_is_compatible("PowerBook3,1") || 1999 of_machine_is_compatible("PowerBook4,1")) 2000 default_vmode = VMODE_1024_768_60; 2001 2002 /* PowerBook Titanium */ 2003 if (of_machine_is_compatible("PowerBook3,2")) 2004 default_vmode = VMODE_1152_768_60; 2005 2006 if (default_cmode > 16) 2007 default_cmode = CMODE_32; 2008 else if (default_cmode > 8) 2009 default_cmode = CMODE_16; 2010 else 2011 default_cmode = CMODE_8; 2012 2013 if (mac_vmode_to_var(default_vmode, default_cmode, &var)) 2014 var = default_var; 2015 } 2016 } else 2017 #endif /* CONFIG_PPC_PMAC */ 2018 { 2019 if (mode_option) 2020 if (fb_find_mode(&var, info, mode_option, NULL, 2021 0, &defaultmode, 8) == 0) 2022 var = default_var; 2023 } 2024 2025 var.accel_flags &= ~FB_ACCELF_TEXT; 2026 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */ 2027 2028 if (aty128fb_check_var(&var, info)) { 2029 printk(KERN_ERR "aty128fb: Cannot set default mode.\n"); 2030 return 0; 2031 } 2032 2033 /* setup the DAC the way we like it */ 2034 dac = aty_ld_le32(DAC_CNTL); 2035 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL); 2036 dac |= DAC_MASK; 2037 if (par->chip_gen == rage_M3) 2038 dac |= DAC_PALETTE2_SNOOP_EN; 2039 aty_st_le32(DAC_CNTL, dac); 2040 2041 /* turn off bus mastering, just in case */ 2042 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); 2043 2044 info->var = var; 2045 fb_alloc_cmap(&info->cmap, 256, 0); 2046 2047 var.activate = FB_ACTIVATE_NOW; 2048 2049 aty128_init_engine(par); 2050 2051 par->pdev = pdev; 2052 par->asleep = 0; 2053 par->lock_blank = 0; 2054 2055 #ifdef CONFIG_FB_ATY128_BACKLIGHT 2056 if (backlight) 2057 aty128_bl_init(par); 2058 #endif 2059 2060 if (register_framebuffer(info) < 0) 2061 return 0; 2062 2063 fb_info(info, "%s frame buffer device on %s\n", 2064 info->fix.id, video_card); 2065 2066 return 1; /* success! */ 2067 } 2068 2069 #ifdef CONFIG_PCI 2070 /* register a card ++ajoshi */ 2071 static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2072 { 2073 unsigned long fb_addr, reg_addr; 2074 struct aty128fb_par *par; 2075 struct fb_info *info; 2076 int err; 2077 #ifndef __sparc__ 2078 void __iomem *bios = NULL; 2079 #endif 2080 2081 /* Enable device in PCI config */ 2082 if ((err = pci_enable_device(pdev))) { 2083 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n", 2084 err); 2085 return -ENODEV; 2086 } 2087 2088 fb_addr = pci_resource_start(pdev, 0); 2089 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0), 2090 "aty128fb FB")) { 2091 printk(KERN_ERR "aty128fb: cannot reserve frame " 2092 "buffer memory\n"); 2093 return -ENODEV; 2094 } 2095 2096 reg_addr = pci_resource_start(pdev, 2); 2097 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2), 2098 "aty128fb MMIO")) { 2099 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n"); 2100 goto err_free_fb; 2101 } 2102 2103 /* We have the resources. Now virtualize them */ 2104 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev); 2105 if (info == NULL) { 2106 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n"); 2107 goto err_free_mmio; 2108 } 2109 par = info->par; 2110 2111 info->pseudo_palette = par->pseudo_palette; 2112 2113 /* Virtualize mmio region */ 2114 info->fix.mmio_start = reg_addr; 2115 par->regbase = pci_ioremap_bar(pdev, 2); 2116 if (!par->regbase) 2117 goto err_free_info; 2118 2119 /* Grab memory size from the card */ 2120 // How does this relate to the resource length from the PCI hardware? 2121 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF; 2122 2123 /* Virtualize the framebuffer */ 2124 info->screen_base = ioremap_wc(fb_addr, par->vram_size); 2125 if (!info->screen_base) 2126 goto err_unmap_out; 2127 2128 /* Set up info->fix */ 2129 info->fix = aty128fb_fix; 2130 info->fix.smem_start = fb_addr; 2131 info->fix.smem_len = par->vram_size; 2132 info->fix.mmio_start = reg_addr; 2133 2134 /* If we can't test scratch registers, something is seriously wrong */ 2135 if (!register_test(par)) { 2136 printk(KERN_ERR "aty128fb: Can't write to video register!\n"); 2137 goto err_out; 2138 } 2139 2140 #ifndef __sparc__ 2141 bios = aty128_map_ROM(par, pdev); 2142 #ifdef CONFIG_X86 2143 if (bios == NULL) 2144 bios = aty128_find_mem_vbios(par); 2145 #endif 2146 if (bios == NULL) 2147 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n"); 2148 else { 2149 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n"); 2150 aty128_get_pllinfo(par, bios); 2151 pci_unmap_rom(pdev, bios); 2152 } 2153 #endif /* __sparc__ */ 2154 2155 aty128_timings(par); 2156 pci_set_drvdata(pdev, info); 2157 2158 if (!aty128_init(pdev, ent)) 2159 goto err_out; 2160 2161 if (mtrr) 2162 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, 2163 par->vram_size); 2164 return 0; 2165 2166 err_out: 2167 iounmap(info->screen_base); 2168 err_unmap_out: 2169 iounmap(par->regbase); 2170 err_free_info: 2171 framebuffer_release(info); 2172 err_free_mmio: 2173 release_mem_region(pci_resource_start(pdev, 2), 2174 pci_resource_len(pdev, 2)); 2175 err_free_fb: 2176 release_mem_region(pci_resource_start(pdev, 0), 2177 pci_resource_len(pdev, 0)); 2178 return -ENODEV; 2179 } 2180 2181 static void aty128_remove(struct pci_dev *pdev) 2182 { 2183 struct fb_info *info = pci_get_drvdata(pdev); 2184 struct aty128fb_par *par; 2185 2186 if (!info) 2187 return; 2188 2189 par = info->par; 2190 2191 unregister_framebuffer(info); 2192 2193 #ifdef CONFIG_FB_ATY128_BACKLIGHT 2194 aty128_bl_exit(info->bl_dev); 2195 #endif 2196 2197 arch_phys_wc_del(par->wc_cookie); 2198 iounmap(par->regbase); 2199 iounmap(info->screen_base); 2200 2201 release_mem_region(pci_resource_start(pdev, 0), 2202 pci_resource_len(pdev, 0)); 2203 release_mem_region(pci_resource_start(pdev, 2), 2204 pci_resource_len(pdev, 2)); 2205 framebuffer_release(info); 2206 } 2207 #endif /* CONFIG_PCI */ 2208 2209 2210 2211 /* 2212 * Blank the display. 2213 */ 2214 static int aty128fb_blank(int blank, struct fb_info *fb) 2215 { 2216 struct aty128fb_par *par = fb->par; 2217 u8 state; 2218 2219 if (par->lock_blank || par->asleep) 2220 return 0; 2221 2222 switch (blank) { 2223 case FB_BLANK_NORMAL: 2224 state = 4; 2225 break; 2226 case FB_BLANK_VSYNC_SUSPEND: 2227 state = 6; 2228 break; 2229 case FB_BLANK_HSYNC_SUSPEND: 2230 state = 5; 2231 break; 2232 case FB_BLANK_POWERDOWN: 2233 state = 7; 2234 break; 2235 case FB_BLANK_UNBLANK: 2236 default: 2237 state = 0; 2238 break; 2239 } 2240 aty_st_8(CRTC_EXT_CNTL+1, state); 2241 2242 if (par->chip_gen == rage_M3) { 2243 aty128_set_crt_enable(par, par->crt_on && !blank); 2244 aty128_set_lcd_enable(par, par->lcd_on && !blank); 2245 } 2246 2247 return 0; 2248 } 2249 2250 /* 2251 * Set a single color register. The values supplied are already 2252 * rounded down to the hardware's capabilities (according to the 2253 * entries in the var structure). Return != 0 for invalid regno. 2254 */ 2255 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 2256 u_int transp, struct fb_info *info) 2257 { 2258 struct aty128fb_par *par = info->par; 2259 2260 if (regno > 255 2261 || (par->crtc.depth == 16 && regno > 63) 2262 || (par->crtc.depth == 15 && regno > 31)) 2263 return 1; 2264 2265 red >>= 8; 2266 green >>= 8; 2267 blue >>= 8; 2268 2269 if (regno < 16) { 2270 int i; 2271 u32 *pal = info->pseudo_palette; 2272 2273 switch (par->crtc.depth) { 2274 case 15: 2275 pal[regno] = (regno << 10) | (regno << 5) | regno; 2276 break; 2277 case 16: 2278 pal[regno] = (regno << 11) | (regno << 6) | regno; 2279 break; 2280 case 24: 2281 pal[regno] = (regno << 16) | (regno << 8) | regno; 2282 break; 2283 case 32: 2284 i = (regno << 8) | regno; 2285 pal[regno] = (i << 16) | i; 2286 break; 2287 } 2288 } 2289 2290 if (par->crtc.depth == 16 && regno > 0) { 2291 /* 2292 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we 2293 * have 32 slots for R and B values but 64 slots for G values. 2294 * Thus the R and B values go in one slot but the G value 2295 * goes in a different slot, and we have to avoid disturbing 2296 * the other fields in the slots we touch. 2297 */ 2298 par->green[regno] = green; 2299 if (regno < 32) { 2300 par->red[regno] = red; 2301 par->blue[regno] = blue; 2302 aty128_st_pal(regno * 8, red, par->green[regno*2], 2303 blue, par); 2304 } 2305 red = par->red[regno/2]; 2306 blue = par->blue[regno/2]; 2307 regno <<= 2; 2308 } else if (par->crtc.bpp == 16) 2309 regno <<= 3; 2310 aty128_st_pal(regno, red, green, blue, par); 2311 2312 return 0; 2313 } 2314 2315 #define ATY_MIRROR_LCD_ON 0x00000001 2316 #define ATY_MIRROR_CRT_ON 0x00000002 2317 2318 /* out param: u32* backlight value: 0 to 15 */ 2319 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32) 2320 /* in param: u32* backlight value: 0 to 15 */ 2321 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32) 2322 2323 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg) 2324 { 2325 struct aty128fb_par *par = info->par; 2326 u32 value; 2327 int rc; 2328 2329 switch (cmd) { 2330 case FBIO_ATY128_SET_MIRROR: 2331 if (par->chip_gen != rage_M3) 2332 return -EINVAL; 2333 rc = get_user(value, (__u32 __user *)arg); 2334 if (rc) 2335 return rc; 2336 par->lcd_on = (value & 0x01) != 0; 2337 par->crt_on = (value & 0x02) != 0; 2338 if (!par->crt_on && !par->lcd_on) 2339 par->lcd_on = 1; 2340 aty128_set_crt_enable(par, par->crt_on); 2341 aty128_set_lcd_enable(par, par->lcd_on); 2342 return 0; 2343 case FBIO_ATY128_GET_MIRROR: 2344 if (par->chip_gen != rage_M3) 2345 return -EINVAL; 2346 value = (par->crt_on << 1) | par->lcd_on; 2347 return put_user(value, (__u32 __user *)arg); 2348 } 2349 return -EINVAL; 2350 } 2351 2352 #if 0 2353 /* 2354 * Accelerated functions 2355 */ 2356 2357 static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty, 2358 u_int width, u_int height, 2359 struct fb_info_aty128 *par) 2360 { 2361 u32 save_dp_datatype, save_dp_cntl, dstval; 2362 2363 if (!width || !height) 2364 return; 2365 2366 dstval = depth_to_dst(par->current_par.crtc.depth); 2367 if (dstval == DST_24BPP) { 2368 srcx *= 3; 2369 dstx *= 3; 2370 width *= 3; 2371 } else if (dstval == -EINVAL) { 2372 printk("aty128fb: invalid depth or RGBA\n"); 2373 return; 2374 } 2375 2376 wait_for_fifo(2, par); 2377 save_dp_datatype = aty_ld_le32(DP_DATATYPE); 2378 save_dp_cntl = aty_ld_le32(DP_CNTL); 2379 2380 wait_for_fifo(6, par); 2381 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx); 2382 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT); 2383 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 2384 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR); 2385 2386 aty_st_le32(DST_Y_X, (dsty << 16) | dstx); 2387 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width); 2388 2389 par->blitter_may_be_busy = 1; 2390 2391 wait_for_fifo(2, par); 2392 aty_st_le32(DP_DATATYPE, save_dp_datatype); 2393 aty_st_le32(DP_CNTL, save_dp_cntl); 2394 } 2395 2396 2397 /* 2398 * Text mode accelerated functions 2399 */ 2400 2401 static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, 2402 int dx, int height, int width) 2403 { 2404 sx *= fontwidth(p); 2405 sy *= fontheight(p); 2406 dx *= fontwidth(p); 2407 dy *= fontheight(p); 2408 width *= fontwidth(p); 2409 height *= fontheight(p); 2410 2411 aty128_rectcopy(sx, sy, dx, dy, width, height, 2412 (struct fb_info_aty128 *)p->fb_info); 2413 } 2414 #endif /* 0 */ 2415 2416 static void aty128_set_suspend(struct aty128fb_par *par, int suspend) 2417 { 2418 u32 pmgt; 2419 struct pci_dev *pdev = par->pdev; 2420 2421 if (!par->pdev->pm_cap) 2422 return; 2423 2424 /* Set the chip into the appropriate suspend mode (we use D2, 2425 * D3 would require a complete re-initialisation of the chip, 2426 * including PCI config registers, clocks, AGP configuration, ...) 2427 * 2428 * For resume, the core will have already brought us back to D0 2429 */ 2430 if (suspend) { 2431 /* Make sure CRTC2 is reset. Remove that the day we decide to 2432 * actually use CRTC2 and replace it with real code for disabling 2433 * the CRTC2 output during sleep 2434 */ 2435 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & 2436 ~(CRTC2_EN)); 2437 2438 /* Set the power management mode to be PCI based */ 2439 /* Use this magic value for now */ 2440 pmgt = 0x0c005407; 2441 aty_st_pll(POWER_MANAGEMENT, pmgt); 2442 (void)aty_ld_pll(POWER_MANAGEMENT); 2443 aty_st_le32(BUS_CNTL1, 0x00000010); 2444 aty_st_le32(MEM_POWER_MISC, 0x0c830000); 2445 mdelay(100); 2446 2447 /* Switch PCI power management to D2 */ 2448 pci_set_power_state(pdev, PCI_D2); 2449 } 2450 } 2451 2452 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state) 2453 { 2454 struct fb_info *info = pci_get_drvdata(pdev); 2455 struct aty128fb_par *par = info->par; 2456 2457 /* Because we may change PCI D state ourselves, we need to 2458 * first save the config space content so the core can 2459 * restore it properly on resume. 2460 */ 2461 pci_save_state(pdev); 2462 2463 /* We don't do anything but D2, for now we return 0, but 2464 * we may want to change that. How do we know if the BIOS 2465 * can properly take care of D3 ? Also, with swsusp, we 2466 * know we'll be rebooted, ... 2467 */ 2468 #ifndef CONFIG_PPC_PMAC 2469 /* HACK ALERT ! Once I find a proper way to say to each driver 2470 * individually what will happen with it's PCI slot, I'll change 2471 * that. On laptops, the AGP slot is just unclocked, so D2 is 2472 * expected, while on desktops, the card is powered off 2473 */ 2474 return 0; 2475 #endif /* CONFIG_PPC_PMAC */ 2476 2477 if (state.event == pdev->dev.power.power_state.event) 2478 return 0; 2479 2480 printk(KERN_DEBUG "aty128fb: suspending...\n"); 2481 2482 console_lock(); 2483 2484 fb_set_suspend(info, 1); 2485 2486 /* Make sure engine is reset */ 2487 wait_for_idle(par); 2488 aty128_reset_engine(par); 2489 wait_for_idle(par); 2490 2491 /* Blank display and LCD */ 2492 aty128fb_blank(FB_BLANK_POWERDOWN, info); 2493 2494 /* Sleep */ 2495 par->asleep = 1; 2496 par->lock_blank = 1; 2497 2498 #ifdef CONFIG_PPC_PMAC 2499 /* On powermac, we have hooks to properly suspend/resume AGP now, 2500 * use them here. We'll ultimately need some generic support here, 2501 * but the generic code isn't quite ready for that yet 2502 */ 2503 pmac_suspend_agp_for_card(pdev); 2504 #endif /* CONFIG_PPC_PMAC */ 2505 2506 /* We need a way to make sure the fbdev layer will _not_ touch the 2507 * framebuffer before we put the chip to suspend state. On 2.4, I 2508 * used dummy fb ops, 2.5 need proper support for this at the 2509 * fbdev level 2510 */ 2511 if (state.event != PM_EVENT_ON) 2512 aty128_set_suspend(par, 1); 2513 2514 console_unlock(); 2515 2516 pdev->dev.power.power_state = state; 2517 2518 return 0; 2519 } 2520 2521 static int aty128_do_resume(struct pci_dev *pdev) 2522 { 2523 struct fb_info *info = pci_get_drvdata(pdev); 2524 struct aty128fb_par *par = info->par; 2525 2526 if (pdev->dev.power.power_state.event == PM_EVENT_ON) 2527 return 0; 2528 2529 /* PCI state will have been restored by the core, so 2530 * we should be in D0 now with our config space fully 2531 * restored 2532 */ 2533 2534 /* Wakeup chip */ 2535 aty128_set_suspend(par, 0); 2536 par->asleep = 0; 2537 2538 /* Restore display & engine */ 2539 aty128_reset_engine(par); 2540 wait_for_idle(par); 2541 aty128fb_set_par(info); 2542 fb_pan_display(info, &info->var); 2543 fb_set_cmap(&info->cmap, info); 2544 2545 /* Refresh */ 2546 fb_set_suspend(info, 0); 2547 2548 /* Unblank */ 2549 par->lock_blank = 0; 2550 aty128fb_blank(0, info); 2551 2552 #ifdef CONFIG_PPC_PMAC 2553 /* On powermac, we have hooks to properly suspend/resume AGP now, 2554 * use them here. We'll ultimately need some generic support here, 2555 * but the generic code isn't quite ready for that yet 2556 */ 2557 pmac_resume_agp_for_card(pdev); 2558 #endif /* CONFIG_PPC_PMAC */ 2559 2560 pdev->dev.power.power_state = PMSG_ON; 2561 2562 printk(KERN_DEBUG "aty128fb: resumed !\n"); 2563 2564 return 0; 2565 } 2566 2567 static int aty128_pci_resume(struct pci_dev *pdev) 2568 { 2569 int rc; 2570 2571 console_lock(); 2572 rc = aty128_do_resume(pdev); 2573 console_unlock(); 2574 2575 return rc; 2576 } 2577 2578 2579 static int aty128fb_init(void) 2580 { 2581 #ifndef MODULE 2582 char *option = NULL; 2583 2584 if (fb_get_options("aty128fb", &option)) 2585 return -ENODEV; 2586 aty128fb_setup(option); 2587 #endif 2588 2589 return pci_register_driver(&aty128fb_driver); 2590 } 2591 2592 static void __exit aty128fb_exit(void) 2593 { 2594 pci_unregister_driver(&aty128fb_driver); 2595 } 2596 2597 module_init(aty128fb_init); 2598 2599 module_exit(aty128fb_exit); 2600 2601 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>"); 2602 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards"); 2603 MODULE_LICENSE("GPL"); 2604 module_param(mode_option, charp, 0); 2605 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); 2606 module_param_named(nomtrr, mtrr, invbool, 0); 2607 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)"); 2608