1 /* 2 * drivers/video/asiliantfb.c 3 * frame buffer driver for Asiliant 69000 chip 4 * Copyright (C) 2001-2003 Saito.K & Jeanne 5 * 6 * from driver/video/chipsfb.c and, 7 * 8 * drivers/video/asiliantfb.c -- frame buffer device for 9 * Asiliant 69030 chip (formerly Intel, formerly Chips & Technologies) 10 * Author: apc@agelectronics.co.uk 11 * Copyright (C) 2000 AG Electronics 12 * Note: the data sheets don't seem to be available from Asiliant. 13 * They are available by searching developer.intel.com, but are not otherwise 14 * linked to. 15 * 16 * This driver should be portable with minimal effort to the 69000 display 17 * chip, and to the twin-display mode of the 69030. 18 * Contains code from Thomas Hhenleitner <th@visuelle-maschinen.de> (thanks) 19 * 20 * Derived from the CT65550 driver chipsfb.c: 21 * Copyright (C) 1998 Paul Mackerras 22 * ...which was derived from the Powermac "chips" driver: 23 * Copyright (C) 1997 Fabio Riccardi. 24 * And from the frame buffer device for Open Firmware-initialized devices: 25 * Copyright (C) 1997 Geert Uytterhoeven. 26 * 27 * This file is subject to the terms and conditions of the GNU General Public 28 * License. See the file COPYING in the main directory of this archive for 29 * more details. 30 */ 31 32 #include <linux/aperture.h> 33 #include <linux/module.h> 34 #include <linux/kernel.h> 35 #include <linux/errno.h> 36 #include <linux/string.h> 37 #include <linux/mm.h> 38 #include <linux/vmalloc.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/fb.h> 42 #include <linux/init.h> 43 #include <linux/pci.h> 44 #include <asm/io.h> 45 46 /* Built in clock of the 69030 */ 47 static const unsigned Fref = 14318180; 48 49 #define mmio_base (p->screen_base + 0x400000) 50 51 #define mm_write_ind(num, val, ap, dp) do { \ 52 writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \ 53 } while (0) 54 55 static void mm_write_xr(struct fb_info *p, u8 reg, u8 data) 56 { 57 mm_write_ind(reg, data, 0x7ac, 0x7ad); 58 } 59 #define write_xr(num, val) mm_write_xr(p, num, val) 60 61 static void mm_write_fr(struct fb_info *p, u8 reg, u8 data) 62 { 63 mm_write_ind(reg, data, 0x7a0, 0x7a1); 64 } 65 #define write_fr(num, val) mm_write_fr(p, num, val) 66 67 static void mm_write_cr(struct fb_info *p, u8 reg, u8 data) 68 { 69 mm_write_ind(reg, data, 0x7a8, 0x7a9); 70 } 71 #define write_cr(num, val) mm_write_cr(p, num, val) 72 73 static void mm_write_gr(struct fb_info *p, u8 reg, u8 data) 74 { 75 mm_write_ind(reg, data, 0x79c, 0x79d); 76 } 77 #define write_gr(num, val) mm_write_gr(p, num, val) 78 79 static void mm_write_sr(struct fb_info *p, u8 reg, u8 data) 80 { 81 mm_write_ind(reg, data, 0x788, 0x789); 82 } 83 #define write_sr(num, val) mm_write_sr(p, num, val) 84 85 static void mm_write_ar(struct fb_info *p, u8 reg, u8 data) 86 { 87 readb(mmio_base + 0x7b4); 88 mm_write_ind(reg, data, 0x780, 0x780); 89 } 90 #define write_ar(num, val) mm_write_ar(p, num, val) 91 92 static int asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *); 93 static int asiliantfb_check_var(struct fb_var_screeninfo *var, 94 struct fb_info *info); 95 static int asiliantfb_set_par(struct fb_info *info); 96 static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 97 u_int transp, struct fb_info *info); 98 99 static const struct fb_ops asiliantfb_ops = { 100 .owner = THIS_MODULE, 101 .fb_check_var = asiliantfb_check_var, 102 .fb_set_par = asiliantfb_set_par, 103 .fb_setcolreg = asiliantfb_setcolreg, 104 .fb_fillrect = cfb_fillrect, 105 .fb_copyarea = cfb_copyarea, 106 .fb_imageblit = cfb_imageblit, 107 }; 108 109 /* Calculate the ratios for the dot clocks without using a single long long 110 * value */ 111 static void asiliant_calc_dclk2(u32 *ppixclock, u8 *dclk2_m, u8 *dclk2_n, u8 *dclk2_div) 112 { 113 unsigned pixclock = *ppixclock; 114 unsigned Ftarget; 115 unsigned n; 116 unsigned best_error = 0xffffffff; 117 unsigned best_m = 0xffffffff, 118 best_n = 0xffffffff; 119 unsigned ratio; 120 unsigned remainder; 121 unsigned char divisor = 0; 122 123 /* Calculate the frequency required. This is hard enough. */ 124 ratio = 1000000 / pixclock; 125 remainder = 1000000 % pixclock; 126 Ftarget = 1000000 * ratio + (1000000 * remainder) / pixclock; 127 128 while (Ftarget < 100000000) { 129 divisor += 0x10; 130 Ftarget <<= 1; 131 } 132 133 ratio = Ftarget / Fref; 134 remainder = Ftarget % Fref; 135 136 /* This expresses the constraint that 150kHz <= Fref/n <= 5Mhz, 137 * together with 3 <= n <= 257. */ 138 for (n = 3; n <= 257; n++) { 139 unsigned m = n * ratio + (n * remainder) / Fref; 140 141 /* 3 <= m <= 257 */ 142 if (m >= 3 && m <= 257) { 143 unsigned new_error = Ftarget * n >= Fref * m ? 144 ((Ftarget * n) - (Fref * m)) : ((Fref * m) - (Ftarget * n)); 145 if (new_error < best_error) { 146 best_n = n; 147 best_m = m; 148 best_error = new_error; 149 } 150 } 151 /* But if VLD = 4, then 4m <= 1028 */ 152 else if (m <= 1028) { 153 /* remember there are still only 8-bits of precision in m, so 154 * avoid over-optimistic error calculations */ 155 unsigned new_error = Ftarget * n >= Fref * (m & ~3) ? 156 ((Ftarget * n) - (Fref * (m & ~3))) : ((Fref * (m & ~3)) - (Ftarget * n)); 157 if (new_error < best_error) { 158 best_n = n; 159 best_m = m; 160 best_error = new_error; 161 } 162 } 163 } 164 if (best_m > 257) 165 best_m >>= 2; /* divide m by 4, and leave VCO loop divide at 4 */ 166 else 167 divisor |= 4; /* or set VCO loop divide to 1 */ 168 *dclk2_m = best_m - 2; 169 *dclk2_n = best_n - 2; 170 *dclk2_div = divisor; 171 *ppixclock = pixclock; 172 return; 173 } 174 175 static void asiliant_set_timing(struct fb_info *p) 176 { 177 unsigned hd = p->var.xres / 8; 178 unsigned hs = (p->var.xres + p->var.right_margin) / 8; 179 unsigned he = (p->var.xres + p->var.right_margin + p->var.hsync_len) / 8; 180 unsigned ht = (p->var.left_margin + p->var.xres + p->var.right_margin + p->var.hsync_len) / 8; 181 unsigned vd = p->var.yres; 182 unsigned vs = p->var.yres + p->var.lower_margin; 183 unsigned ve = p->var.yres + p->var.lower_margin + p->var.vsync_len; 184 unsigned vt = p->var.upper_margin + p->var.yres + p->var.lower_margin + p->var.vsync_len; 185 unsigned wd = (p->var.xres_virtual * ((p->var.bits_per_pixel+7)/8)) / 8; 186 187 if ((p->var.xres == 640) && (p->var.yres == 480) && (p->var.pixclock == 39722)) { 188 write_fr(0x01, 0x02); /* LCD */ 189 } else { 190 write_fr(0x01, 0x01); /* CRT */ 191 } 192 193 write_cr(0x11, (ve - 1) & 0x0f); 194 write_cr(0x00, (ht - 5) & 0xff); 195 write_cr(0x01, hd - 1); 196 write_cr(0x02, hd); 197 write_cr(0x03, ((ht - 1) & 0x1f) | 0x80); 198 write_cr(0x04, hs); 199 write_cr(0x05, (((ht - 1) & 0x20) <<2) | (he & 0x1f)); 200 write_cr(0x3c, (ht - 1) & 0xc0); 201 write_cr(0x06, (vt - 2) & 0xff); 202 write_cr(0x30, (vt - 2) >> 8); 203 write_cr(0x07, 0x00); 204 write_cr(0x08, 0x00); 205 write_cr(0x09, 0x00); 206 write_cr(0x10, (vs - 1) & 0xff); 207 write_cr(0x32, ((vs - 1) >> 8) & 0xf); 208 write_cr(0x11, ((ve - 1) & 0x0f) | 0x80); 209 write_cr(0x12, (vd - 1) & 0xff); 210 write_cr(0x31, ((vd - 1) & 0xf00) >> 8); 211 write_cr(0x13, wd & 0xff); 212 write_cr(0x41, (wd & 0xf00) >> 8); 213 write_cr(0x15, (vs - 1) & 0xff); 214 write_cr(0x33, ((vs - 1) >> 8) & 0xf); 215 write_cr(0x38, ((ht - 5) & 0x100) >> 8); 216 write_cr(0x16, (vt - 1) & 0xff); 217 write_cr(0x18, 0x00); 218 219 if (p->var.xres == 640) { 220 writeb(0xc7, mmio_base + 0x784); /* set misc output reg */ 221 } else { 222 writeb(0x07, mmio_base + 0x784); /* set misc output reg */ 223 } 224 } 225 226 static int asiliantfb_check_var(struct fb_var_screeninfo *var, 227 struct fb_info *p) 228 { 229 unsigned long Ftarget, ratio, remainder; 230 231 if (!var->pixclock) 232 return -EINVAL; 233 234 ratio = 1000000 / var->pixclock; 235 remainder = 1000000 % var->pixclock; 236 Ftarget = 1000000 * ratio + (1000000 * remainder) / var->pixclock; 237 238 /* First check the constraint that the maximum post-VCO divisor is 32, 239 * and the maximum Fvco is 220MHz */ 240 if (Ftarget > 220000000 || Ftarget < 3125000) { 241 printk(KERN_ERR "asiliantfb dotclock must be between 3.125 and 220MHz\n"); 242 return -ENXIO; 243 } 244 var->xres_virtual = var->xres; 245 var->yres_virtual = var->yres; 246 247 if (var->bits_per_pixel == 24) { 248 var->red.offset = 16; 249 var->green.offset = 8; 250 var->blue.offset = 0; 251 var->red.length = var->blue.length = var->green.length = 8; 252 } else if (var->bits_per_pixel == 16) { 253 switch (var->red.offset) { 254 case 11: 255 var->green.length = 6; 256 break; 257 case 10: 258 var->green.length = 5; 259 break; 260 default: 261 return -EINVAL; 262 } 263 var->green.offset = 5; 264 var->blue.offset = 0; 265 var->red.length = var->blue.length = 5; 266 } else if (var->bits_per_pixel == 8) { 267 var->red.offset = var->green.offset = var->blue.offset = 0; 268 var->red.length = var->green.length = var->blue.length = 8; 269 } 270 return 0; 271 } 272 273 static int asiliantfb_set_par(struct fb_info *p) 274 { 275 u8 dclk2_m; /* Holds m-2 value for register */ 276 u8 dclk2_n; /* Holds n-2 value for register */ 277 u8 dclk2_div; /* Holds divisor bitmask */ 278 279 /* Set pixclock */ 280 asiliant_calc_dclk2(&p->var.pixclock, &dclk2_m, &dclk2_n, &dclk2_div); 281 282 /* Set color depth */ 283 if (p->var.bits_per_pixel == 24) { 284 write_xr(0x81, 0x16); /* 24 bit packed color mode */ 285 write_xr(0x82, 0x00); /* Disable palettes */ 286 write_xr(0x20, 0x20); /* 24 bit blitter mode */ 287 } else if (p->var.bits_per_pixel == 16) { 288 if (p->var.red.offset == 11) 289 write_xr(0x81, 0x15); /* 16 bit color mode */ 290 else 291 write_xr(0x81, 0x14); /* 15 bit color mode */ 292 write_xr(0x82, 0x00); /* Disable palettes */ 293 write_xr(0x20, 0x10); /* 16 bit blitter mode */ 294 } else if (p->var.bits_per_pixel == 8) { 295 write_xr(0x0a, 0x02); /* Linear */ 296 write_xr(0x81, 0x12); /* 8 bit color mode */ 297 write_xr(0x82, 0x00); /* Graphics gamma enable */ 298 write_xr(0x20, 0x00); /* 8 bit blitter mode */ 299 } 300 p->fix.line_length = p->var.xres * (p->var.bits_per_pixel >> 3); 301 p->fix.visual = (p->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; 302 write_xr(0xc4, dclk2_m); 303 write_xr(0xc5, dclk2_n); 304 write_xr(0xc7, dclk2_div); 305 /* Set up the CR registers */ 306 asiliant_set_timing(p); 307 return 0; 308 } 309 310 static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 311 u_int transp, struct fb_info *p) 312 { 313 if (regno > 255) 314 return 1; 315 red >>= 8; 316 green >>= 8; 317 blue >>= 8; 318 319 /* Set hardware palete */ 320 writeb(regno, mmio_base + 0x790); 321 udelay(1); 322 writeb(red, mmio_base + 0x791); 323 writeb(green, mmio_base + 0x791); 324 writeb(blue, mmio_base + 0x791); 325 326 if (regno < 16) { 327 switch(p->var.red.offset) { 328 case 10: /* RGB 555 */ 329 ((u32 *)(p->pseudo_palette))[regno] = 330 ((red & 0xf8) << 7) | 331 ((green & 0xf8) << 2) | 332 ((blue & 0xf8) >> 3); 333 break; 334 case 11: /* RGB 565 */ 335 ((u32 *)(p->pseudo_palette))[regno] = 336 ((red & 0xf8) << 8) | 337 ((green & 0xfc) << 3) | 338 ((blue & 0xf8) >> 3); 339 break; 340 case 16: /* RGB 888 */ 341 ((u32 *)(p->pseudo_palette))[regno] = 342 (red << 16) | 343 (green << 8) | 344 (blue); 345 break; 346 } 347 } 348 349 return 0; 350 } 351 352 struct chips_init_reg { 353 unsigned char addr; 354 unsigned char data; 355 }; 356 357 static struct chips_init_reg chips_init_sr[] = 358 { 359 {0x00, 0x03}, /* Reset register */ 360 {0x01, 0x01}, /* Clocking mode */ 361 {0x02, 0x0f}, /* Plane mask */ 362 {0x04, 0x0e} /* Memory mode */ 363 }; 364 365 static struct chips_init_reg chips_init_gr[] = 366 { 367 {0x03, 0x00}, /* Data rotate */ 368 {0x05, 0x00}, /* Graphics mode */ 369 {0x06, 0x01}, /* Miscellaneous */ 370 {0x08, 0x00} /* Bit mask */ 371 }; 372 373 static struct chips_init_reg chips_init_ar[] = 374 { 375 {0x10, 0x01}, /* Mode control */ 376 {0x11, 0x00}, /* Overscan */ 377 {0x12, 0x0f}, /* Memory plane enable */ 378 {0x13, 0x00} /* Horizontal pixel panning */ 379 }; 380 381 static struct chips_init_reg chips_init_cr[] = 382 { 383 {0x0c, 0x00}, /* Start address high */ 384 {0x0d, 0x00}, /* Start address low */ 385 {0x40, 0x00}, /* Extended Start Address */ 386 {0x41, 0x00}, /* Extended Start Address */ 387 {0x14, 0x00}, /* Underline location */ 388 {0x17, 0xe3}, /* CRT mode control */ 389 {0x70, 0x00} /* Interlace control */ 390 }; 391 392 393 static struct chips_init_reg chips_init_fr[] = 394 { 395 {0x01, 0x02}, 396 {0x03, 0x08}, 397 {0x08, 0xcc}, 398 {0x0a, 0x08}, 399 {0x18, 0x00}, 400 {0x1e, 0x80}, 401 {0x40, 0x83}, 402 {0x41, 0x00}, 403 {0x48, 0x13}, 404 {0x4d, 0x60}, 405 {0x4e, 0x0f}, 406 407 {0x0b, 0x01}, 408 409 {0x21, 0x51}, 410 {0x22, 0x1d}, 411 {0x23, 0x5f}, 412 {0x20, 0x4f}, 413 {0x34, 0x00}, 414 {0x24, 0x51}, 415 {0x25, 0x00}, 416 {0x27, 0x0b}, 417 {0x26, 0x00}, 418 {0x37, 0x80}, 419 {0x33, 0x0b}, 420 {0x35, 0x11}, 421 {0x36, 0x02}, 422 {0x31, 0xea}, 423 {0x32, 0x0c}, 424 {0x30, 0xdf}, 425 {0x10, 0x0c}, 426 {0x11, 0xe0}, 427 {0x12, 0x50}, 428 {0x13, 0x00}, 429 {0x16, 0x03}, 430 {0x17, 0xbd}, 431 {0x1a, 0x00}, 432 }; 433 434 435 static struct chips_init_reg chips_init_xr[] = 436 { 437 {0xce, 0x00}, /* set default memory clock */ 438 {0xcc, 200 }, /* MCLK ratio M */ 439 {0xcd, 18 }, /* MCLK ratio N */ 440 {0xce, 0x90}, /* MCLK divisor = 2 */ 441 442 {0xc4, 209 }, 443 {0xc5, 118 }, 444 {0xc7, 32 }, 445 {0xcf, 0x06}, 446 {0x09, 0x01}, /* IO Control - CRT controller extensions */ 447 {0x0a, 0x02}, /* Frame buffer mapping */ 448 {0x0b, 0x01}, /* PCI burst write */ 449 {0x40, 0x03}, /* Memory access control */ 450 {0x80, 0x82}, /* Pixel pipeline configuration 0 */ 451 {0x81, 0x12}, /* Pixel pipeline configuration 1 */ 452 {0x82, 0x08}, /* Pixel pipeline configuration 2 */ 453 454 {0xd0, 0x0f}, 455 {0xd1, 0x01}, 456 }; 457 458 static void chips_hw_init(struct fb_info *p) 459 { 460 int i; 461 462 for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i) 463 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data); 464 write_xr(0x81, 0x12); 465 write_xr(0x82, 0x08); 466 write_xr(0x20, 0x00); 467 for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i) 468 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data); 469 for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i) 470 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data); 471 for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i) 472 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data); 473 /* Enable video output in attribute index register */ 474 writeb(0x20, mmio_base + 0x780); 475 for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i) 476 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data); 477 for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i) 478 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data); 479 } 480 481 static const struct fb_fix_screeninfo asiliantfb_fix = { 482 .id = "Asiliant 69000", 483 .type = FB_TYPE_PACKED_PIXELS, 484 .visual = FB_VISUAL_PSEUDOCOLOR, 485 .accel = FB_ACCEL_NONE, 486 .line_length = 640, 487 .smem_len = 0x200000, /* 2MB */ 488 }; 489 490 static const struct fb_var_screeninfo asiliantfb_var = { 491 .xres = 640, 492 .yres = 480, 493 .xres_virtual = 640, 494 .yres_virtual = 480, 495 .bits_per_pixel = 8, 496 .red = { .length = 8 }, 497 .green = { .length = 8 }, 498 .blue = { .length = 8 }, 499 .height = -1, 500 .width = -1, 501 .vmode = FB_VMODE_NONINTERLACED, 502 .pixclock = 39722, 503 .left_margin = 48, 504 .right_margin = 16, 505 .upper_margin = 33, 506 .lower_margin = 10, 507 .hsync_len = 96, 508 .vsync_len = 2, 509 }; 510 511 static int init_asiliant(struct fb_info *p, unsigned long addr) 512 { 513 int err; 514 515 p->fix = asiliantfb_fix; 516 p->fix.smem_start = addr; 517 p->var = asiliantfb_var; 518 p->fbops = &asiliantfb_ops; 519 p->flags = FBINFO_DEFAULT; 520 521 err = fb_alloc_cmap(&p->cmap, 256, 0); 522 if (err) { 523 printk(KERN_ERR "C&T 69000 fb failed to alloc cmap memory\n"); 524 return err; 525 } 526 527 err = register_framebuffer(p); 528 if (err < 0) { 529 printk(KERN_ERR "C&T 69000 framebuffer failed to register\n"); 530 fb_dealloc_cmap(&p->cmap); 531 return err; 532 } 533 534 fb_info(p, "Asiliant 69000 frame buffer (%dK RAM detected)\n", 535 p->fix.smem_len / 1024); 536 537 writeb(0xff, mmio_base + 0x78c); 538 chips_hw_init(p); 539 return 0; 540 } 541 542 static int asiliantfb_pci_init(struct pci_dev *dp, 543 const struct pci_device_id *ent) 544 { 545 unsigned long addr, size; 546 struct fb_info *p; 547 int err; 548 549 err = aperture_remove_conflicting_pci_devices(dp, "asiliantfb"); 550 if (err) 551 return err; 552 553 if ((dp->resource[0].flags & IORESOURCE_MEM) == 0) 554 return -ENODEV; 555 addr = pci_resource_start(dp, 0); 556 size = pci_resource_len(dp, 0); 557 if (addr == 0) 558 return -ENODEV; 559 if (!request_mem_region(addr, size, "asiliantfb")) 560 return -EBUSY; 561 562 p = framebuffer_alloc(sizeof(u32) * 16, &dp->dev); 563 if (!p) { 564 release_mem_region(addr, size); 565 return -ENOMEM; 566 } 567 p->pseudo_palette = p->par; 568 p->par = NULL; 569 570 p->screen_base = ioremap(addr, 0x800000); 571 if (p->screen_base == NULL) { 572 release_mem_region(addr, size); 573 framebuffer_release(p); 574 return -ENOMEM; 575 } 576 577 pci_write_config_dword(dp, 4, 0x02800083); 578 writeb(3, p->screen_base + 0x400784); 579 580 err = init_asiliant(p, addr); 581 if (err) { 582 iounmap(p->screen_base); 583 release_mem_region(addr, size); 584 framebuffer_release(p); 585 return err; 586 } 587 588 pci_set_drvdata(dp, p); 589 return 0; 590 } 591 592 static void asiliantfb_remove(struct pci_dev *dp) 593 { 594 struct fb_info *p = pci_get_drvdata(dp); 595 596 unregister_framebuffer(p); 597 fb_dealloc_cmap(&p->cmap); 598 iounmap(p->screen_base); 599 release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0)); 600 framebuffer_release(p); 601 } 602 603 static const struct pci_device_id asiliantfb_pci_tbl[] = { 604 { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000, PCI_ANY_ID, PCI_ANY_ID }, 605 { 0 } 606 }; 607 608 MODULE_DEVICE_TABLE(pci, asiliantfb_pci_tbl); 609 610 static struct pci_driver asiliantfb_driver = { 611 .name = "asiliantfb", 612 .id_table = asiliantfb_pci_tbl, 613 .probe = asiliantfb_pci_init, 614 .remove = asiliantfb_remove, 615 }; 616 617 static int __init asiliantfb_init(void) 618 { 619 if (fb_modesetting_disabled("asiliantfb")) 620 return -ENODEV; 621 622 if (fb_get_options("asiliantfb", NULL)) 623 return -ENODEV; 624 625 return pci_register_driver(&asiliantfb_driver); 626 } 627 628 module_init(asiliantfb_init); 629 630 static void __exit asiliantfb_exit(void) 631 { 632 pci_unregister_driver(&asiliantfb_driver); 633 } 634 635 MODULE_LICENSE("GPL"); 636