1 /* 2 * linux/drivers/video/arkfb.c -- Frame buffer device driver for ARK 2000PV 3 * with ICS 5342 dac (it is easy to add support for different dacs). 4 * 5 * Copyright (c) 2007 Ondrej Zajicek <santiago@crfreenet.org> 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file COPYING in the main directory of this archive for 9 * more details. 10 * 11 * Code is based on s3fb 12 */ 13 14 #include <linux/aperture.h> 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/errno.h> 18 #include <linux/string.h> 19 #include <linux/mm.h> 20 #include <linux/tty.h> 21 #include <linux/slab.h> 22 #include <linux/delay.h> 23 #include <linux/fb.h> 24 #include <linux/svga.h> 25 #include <linux/init.h> 26 #include <linux/pci.h> 27 #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */ 28 #include <video/vga.h> 29 30 struct arkfb_info { 31 int mclk_freq; 32 int wc_cookie; 33 34 struct dac_info *dac; 35 struct vgastate state; 36 struct mutex open_lock; 37 unsigned int ref_count; 38 u32 pseudo_palette[16]; 39 }; 40 41 42 /* ------------------------------------------------------------------------- */ 43 44 45 static const struct svga_fb_format arkfb_formats[] = { 46 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 47 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 8}, 48 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 49 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 50 { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1, 51 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16}, 52 { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, 53 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8}, 54 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, 55 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4}, 56 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, 57 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4}, 58 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 59 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 8, 8}, 60 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, 61 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2}, 62 SVGA_FORMAT_END 63 }; 64 65 66 /* CRT timing register sets */ 67 68 static const struct vga_regset ark_h_total_regs[] = {{0x00, 0, 7}, {0x41, 7, 7}, VGA_REGSET_END}; 69 static const struct vga_regset ark_h_display_regs[] = {{0x01, 0, 7}, {0x41, 6, 6}, VGA_REGSET_END}; 70 static const struct vga_regset ark_h_blank_start_regs[] = {{0x02, 0, 7}, {0x41, 5, 5}, VGA_REGSET_END}; 71 static const struct vga_regset ark_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7 }, VGA_REGSET_END}; 72 static const struct vga_regset ark_h_sync_start_regs[] = {{0x04, 0, 7}, {0x41, 4, 4}, VGA_REGSET_END}; 73 static const struct vga_regset ark_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; 74 75 static const struct vga_regset ark_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x40, 7, 7}, VGA_REGSET_END}; 76 static const struct vga_regset ark_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x40, 6, 6}, VGA_REGSET_END}; 77 static const struct vga_regset ark_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x40, 5, 5}, VGA_REGSET_END}; 78 // const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 6}, VGA_REGSET_END}; 79 static const struct vga_regset ark_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; 80 static const struct vga_regset ark_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x40, 4, 4}, VGA_REGSET_END}; 81 static const struct vga_regset ark_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; 82 83 static const struct vga_regset ark_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, VGA_REGSET_END}; 84 static const struct vga_regset ark_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x40, 0, 2}, VGA_REGSET_END}; 85 static const struct vga_regset ark_offset_regs[] = {{0x13, 0, 7}, {0x41, 3, 3}, VGA_REGSET_END}; 86 87 static const struct svga_timing_regs ark_timing_regs = { 88 ark_h_total_regs, ark_h_display_regs, ark_h_blank_start_regs, 89 ark_h_blank_end_regs, ark_h_sync_start_regs, ark_h_sync_end_regs, 90 ark_v_total_regs, ark_v_display_regs, ark_v_blank_start_regs, 91 ark_v_blank_end_regs, ark_v_sync_start_regs, ark_v_sync_end_regs, 92 }; 93 94 95 /* ------------------------------------------------------------------------- */ 96 97 98 /* Module parameters */ 99 100 static char *mode_option = "640x480-8@60"; 101 102 MODULE_AUTHOR("(c) 2007 Ondrej Zajicek <santiago@crfreenet.org>"); 103 MODULE_LICENSE("GPL"); 104 MODULE_DESCRIPTION("fbdev driver for ARK 2000PV"); 105 106 module_param(mode_option, charp, 0444); 107 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)"); 108 module_param_named(mode, mode_option, charp, 0444); 109 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)"); 110 111 static int threshold = 4; 112 113 module_param(threshold, int, 0644); 114 MODULE_PARM_DESC(threshold, "FIFO threshold"); 115 116 117 /* ------------------------------------------------------------------------- */ 118 119 120 static void arkfb_settile(struct fb_info *info, struct fb_tilemap *map) 121 { 122 const u8 *font = map->data; 123 u8 __iomem *fb = (u8 __iomem *)info->screen_base; 124 int i, c; 125 126 if ((map->width != 8) || (map->height != 16) || 127 (map->depth != 1) || (map->length != 256)) { 128 fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n", 129 map->width, map->height, map->depth, map->length); 130 return; 131 } 132 133 fb += 2; 134 for (c = 0; c < map->length; c++) { 135 for (i = 0; i < map->height; i++) { 136 fb_writeb(font[i], &fb[i * 4]); 137 fb_writeb(font[i], &fb[i * 4 + (128 * 8)]); 138 } 139 fb += 128; 140 141 if ((c % 8) == 7) 142 fb += 128*8; 143 144 font += map->height; 145 } 146 } 147 148 static void arkfb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor) 149 { 150 struct arkfb_info *par = info->par; 151 152 svga_tilecursor(par->state.vgabase, info, cursor); 153 } 154 155 static struct fb_tile_ops arkfb_tile_ops = { 156 .fb_settile = arkfb_settile, 157 .fb_tilecopy = svga_tilecopy, 158 .fb_tilefill = svga_tilefill, 159 .fb_tileblit = svga_tileblit, 160 .fb_tilecursor = arkfb_tilecursor, 161 .fb_get_tilemax = svga_get_tilemax, 162 }; 163 164 165 /* ------------------------------------------------------------------------- */ 166 167 168 /* image data is MSB-first, fb structure is MSB-first too */ 169 static inline u32 expand_color(u32 c) 170 { 171 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; 172 } 173 174 /* arkfb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ 175 static void arkfb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) 176 { 177 u32 fg = expand_color(image->fg_color); 178 u32 bg = expand_color(image->bg_color); 179 const u8 *src1, *src; 180 u8 __iomem *dst1; 181 u32 __iomem *dst; 182 u32 val; 183 int x, y; 184 185 src1 = image->data; 186 dst1 = info->screen_base + (image->dy * info->fix.line_length) 187 + ((image->dx / 8) * 4); 188 189 for (y = 0; y < image->height; y++) { 190 src = src1; 191 dst = (u32 __iomem *) dst1; 192 for (x = 0; x < image->width; x += 8) { 193 val = *(src++) * 0x01010101; 194 val = (val & fg) | (~val & bg); 195 fb_writel(val, dst++); 196 } 197 src1 += image->width / 8; 198 dst1 += info->fix.line_length; 199 } 200 201 } 202 203 /* arkfb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ 204 static void arkfb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 205 { 206 u32 fg = expand_color(rect->color); 207 u8 __iomem *dst1; 208 u32 __iomem *dst; 209 int x, y; 210 211 dst1 = info->screen_base + (rect->dy * info->fix.line_length) 212 + ((rect->dx / 8) * 4); 213 214 for (y = 0; y < rect->height; y++) { 215 dst = (u32 __iomem *) dst1; 216 for (x = 0; x < rect->width; x += 8) { 217 fb_writel(fg, dst++); 218 } 219 dst1 += info->fix.line_length; 220 } 221 222 } 223 224 225 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ 226 static inline u32 expand_pixel(u32 c) 227 { 228 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | 229 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; 230 } 231 232 /* arkfb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ 233 static void arkfb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) 234 { 235 u32 fg = image->fg_color * 0x11111111; 236 u32 bg = image->bg_color * 0x11111111; 237 const u8 *src1, *src; 238 u8 __iomem *dst1; 239 u32 __iomem *dst; 240 u32 val; 241 int x, y; 242 243 src1 = image->data; 244 dst1 = info->screen_base + (image->dy * info->fix.line_length) 245 + ((image->dx / 8) * 4); 246 247 for (y = 0; y < image->height; y++) { 248 src = src1; 249 dst = (u32 __iomem *) dst1; 250 for (x = 0; x < image->width; x += 8) { 251 val = expand_pixel(*(src++)); 252 val = (val & fg) | (~val & bg); 253 fb_writel(val, dst++); 254 } 255 src1 += image->width / 8; 256 dst1 += info->fix.line_length; 257 } 258 259 } 260 261 static void arkfb_imageblit(struct fb_info *info, const struct fb_image *image) 262 { 263 if ((info->var.bits_per_pixel == 4) && (image->depth == 1) 264 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { 265 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) 266 arkfb_iplan_imageblit(info, image); 267 else 268 arkfb_cfb4_imageblit(info, image); 269 } else 270 cfb_imageblit(info, image); 271 } 272 273 static void arkfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 274 { 275 if ((info->var.bits_per_pixel == 4) 276 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) 277 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) 278 arkfb_iplan_fillrect(info, rect); 279 else 280 cfb_fillrect(info, rect); 281 } 282 283 284 /* ------------------------------------------------------------------------- */ 285 286 287 enum 288 { 289 DAC_PSEUDO8_8, 290 DAC_RGB1555_8, 291 DAC_RGB0565_8, 292 DAC_RGB0888_8, 293 DAC_RGB8888_8, 294 DAC_PSEUDO8_16, 295 DAC_RGB1555_16, 296 DAC_RGB0565_16, 297 DAC_RGB0888_16, 298 DAC_RGB8888_16, 299 DAC_MAX 300 }; 301 302 struct dac_ops { 303 int (*dac_get_mode)(struct dac_info *info); 304 int (*dac_set_mode)(struct dac_info *info, int mode); 305 int (*dac_get_freq)(struct dac_info *info, int channel); 306 int (*dac_set_freq)(struct dac_info *info, int channel, u32 freq); 307 void (*dac_release)(struct dac_info *info); 308 }; 309 310 typedef void (*dac_read_regs_t)(void *data, u8 *code, int count); 311 typedef void (*dac_write_regs_t)(void *data, u8 *code, int count); 312 313 struct dac_info 314 { 315 struct dac_ops *dacops; 316 dac_read_regs_t dac_read_regs; 317 dac_write_regs_t dac_write_regs; 318 void *data; 319 }; 320 321 322 static inline u8 dac_read_reg(struct dac_info *info, u8 reg) 323 { 324 u8 code[2] = {reg, 0}; 325 info->dac_read_regs(info->data, code, 1); 326 return code[1]; 327 } 328 329 static inline void dac_read_regs(struct dac_info *info, u8 *code, int count) 330 { 331 info->dac_read_regs(info->data, code, count); 332 } 333 334 static inline void dac_write_reg(struct dac_info *info, u8 reg, u8 val) 335 { 336 u8 code[2] = {reg, val}; 337 info->dac_write_regs(info->data, code, 1); 338 } 339 340 static inline void dac_write_regs(struct dac_info *info, u8 *code, int count) 341 { 342 info->dac_write_regs(info->data, code, count); 343 } 344 345 static inline int dac_set_mode(struct dac_info *info, int mode) 346 { 347 return info->dacops->dac_set_mode(info, mode); 348 } 349 350 static inline int dac_set_freq(struct dac_info *info, int channel, u32 freq) 351 { 352 return info->dacops->dac_set_freq(info, channel, freq); 353 } 354 355 static inline void dac_release(struct dac_info *info) 356 { 357 info->dacops->dac_release(info); 358 } 359 360 361 /* ------------------------------------------------------------------------- */ 362 363 364 /* ICS5342 DAC */ 365 366 struct ics5342_info 367 { 368 struct dac_info dac; 369 u8 mode; 370 }; 371 372 #define DAC_PAR(info) ((struct ics5342_info *) info) 373 374 /* LSB is set to distinguish unused slots */ 375 static const u8 ics5342_mode_table[DAC_MAX] = { 376 [DAC_PSEUDO8_8] = 0x01, [DAC_RGB1555_8] = 0x21, [DAC_RGB0565_8] = 0x61, 377 [DAC_RGB0888_8] = 0x41, [DAC_PSEUDO8_16] = 0x11, [DAC_RGB1555_16] = 0x31, 378 [DAC_RGB0565_16] = 0x51, [DAC_RGB0888_16] = 0x91, [DAC_RGB8888_16] = 0x71 379 }; 380 381 static int ics5342_set_mode(struct dac_info *info, int mode) 382 { 383 u8 code; 384 385 if (mode >= DAC_MAX) 386 return -EINVAL; 387 388 code = ics5342_mode_table[mode]; 389 390 if (! code) 391 return -EINVAL; 392 393 dac_write_reg(info, 6, code & 0xF0); 394 DAC_PAR(info)->mode = mode; 395 396 return 0; 397 } 398 399 static const struct svga_pll ics5342_pll = {3, 129, 3, 33, 0, 3, 400 60000, 250000, 14318}; 401 402 /* pd4 - allow only posdivider 4 (r=2) */ 403 static const struct svga_pll ics5342_pll_pd4 = {3, 129, 3, 33, 2, 2, 404 60000, 335000, 14318}; 405 406 /* 270 MHz should be upper bound for VCO clock according to specs, 407 but that is too restrictive in pd4 case */ 408 409 static int ics5342_set_freq(struct dac_info *info, int channel, u32 freq) 410 { 411 u16 m, n, r; 412 413 /* only postdivider 4 (r=2) is valid in mode DAC_PSEUDO8_16 */ 414 int rv = svga_compute_pll((DAC_PAR(info)->mode == DAC_PSEUDO8_16) 415 ? &ics5342_pll_pd4 : &ics5342_pll, 416 freq, &m, &n, &r, 0); 417 418 if (rv < 0) { 419 return -EINVAL; 420 } else { 421 u8 code[6] = {4, 3, 5, m-2, 5, (n-2) | (r << 5)}; 422 dac_write_regs(info, code, 3); 423 return 0; 424 } 425 } 426 427 static void ics5342_release(struct dac_info *info) 428 { 429 ics5342_set_mode(info, DAC_PSEUDO8_8); 430 kfree(info); 431 } 432 433 static struct dac_ops ics5342_ops = { 434 .dac_set_mode = ics5342_set_mode, 435 .dac_set_freq = ics5342_set_freq, 436 .dac_release = ics5342_release 437 }; 438 439 440 static struct dac_info * ics5342_init(dac_read_regs_t drr, dac_write_regs_t dwr, void *data) 441 { 442 struct dac_info *info = kzalloc(sizeof(struct ics5342_info), GFP_KERNEL); 443 444 if (! info) 445 return NULL; 446 447 info->dacops = &ics5342_ops; 448 info->dac_read_regs = drr; 449 info->dac_write_regs = dwr; 450 info->data = data; 451 DAC_PAR(info)->mode = DAC_PSEUDO8_8; /* estimation */ 452 return info; 453 } 454 455 456 /* ------------------------------------------------------------------------- */ 457 458 459 static unsigned short dac_regs[4] = {0x3c8, 0x3c9, 0x3c6, 0x3c7}; 460 461 static void ark_dac_read_regs(void *data, u8 *code, int count) 462 { 463 struct fb_info *info = data; 464 struct arkfb_info *par; 465 u8 regval; 466 467 par = info->par; 468 regval = vga_rseq(par->state.vgabase, 0x1C); 469 while (count != 0) 470 { 471 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); 472 code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]); 473 count--; 474 code += 2; 475 } 476 477 vga_wseq(par->state.vgabase, 0x1C, regval); 478 } 479 480 static void ark_dac_write_regs(void *data, u8 *code, int count) 481 { 482 struct fb_info *info = data; 483 struct arkfb_info *par; 484 u8 regval; 485 486 par = info->par; 487 regval = vga_rseq(par->state.vgabase, 0x1C); 488 while (count != 0) 489 { 490 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0)); 491 vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]); 492 count--; 493 code += 2; 494 } 495 496 vga_wseq(par->state.vgabase, 0x1C, regval); 497 } 498 499 500 static void ark_set_pixclock(struct fb_info *info, u32 pixclock) 501 { 502 struct arkfb_info *par = info->par; 503 u8 regval; 504 505 int rv = dac_set_freq(par->dac, 0, 1000000000 / pixclock); 506 if (rv < 0) { 507 fb_err(info, "cannot set requested pixclock, keeping old value\n"); 508 return; 509 } 510 511 /* Set VGA misc register */ 512 regval = vga_r(par->state.vgabase, VGA_MIS_R); 513 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); 514 } 515 516 517 /* Open framebuffer */ 518 519 static int arkfb_open(struct fb_info *info, int user) 520 { 521 struct arkfb_info *par = info->par; 522 523 mutex_lock(&(par->open_lock)); 524 if (par->ref_count == 0) { 525 void __iomem *vgabase = par->state.vgabase; 526 527 memset(&(par->state), 0, sizeof(struct vgastate)); 528 par->state.vgabase = vgabase; 529 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; 530 par->state.num_crtc = 0x60; 531 par->state.num_seq = 0x30; 532 save_vga(&(par->state)); 533 } 534 535 par->ref_count++; 536 mutex_unlock(&(par->open_lock)); 537 538 return 0; 539 } 540 541 /* Close framebuffer */ 542 543 static int arkfb_release(struct fb_info *info, int user) 544 { 545 struct arkfb_info *par = info->par; 546 547 mutex_lock(&(par->open_lock)); 548 if (par->ref_count == 0) { 549 mutex_unlock(&(par->open_lock)); 550 return -EINVAL; 551 } 552 553 if (par->ref_count == 1) { 554 restore_vga(&(par->state)); 555 dac_set_mode(par->dac, DAC_PSEUDO8_8); 556 } 557 558 par->ref_count--; 559 mutex_unlock(&(par->open_lock)); 560 561 return 0; 562 } 563 564 /* Validate passed in var */ 565 566 static int arkfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 567 { 568 int rv, mem, step; 569 570 if (!var->pixclock) 571 return -EINVAL; 572 573 /* Find appropriate format */ 574 rv = svga_match_format (arkfb_formats, var, NULL); 575 if (rv < 0) 576 { 577 fb_err(info, "unsupported mode requested\n"); 578 return rv; 579 } 580 581 /* Do not allow to have real resoulution larger than virtual */ 582 if (var->xres > var->xres_virtual) 583 var->xres_virtual = var->xres; 584 585 if (var->yres > var->yres_virtual) 586 var->yres_virtual = var->yres; 587 588 /* Round up xres_virtual to have proper alignment of lines */ 589 step = arkfb_formats[rv].xresstep - 1; 590 var->xres_virtual = (var->xres_virtual+step) & ~step; 591 592 593 /* Check whether have enough memory */ 594 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; 595 if (mem > info->screen_size) 596 { 597 fb_err(info, "not enough framebuffer memory (%d kB requested, %d kB available)\n", 598 mem >> 10, (unsigned int) (info->screen_size >> 10)); 599 return -EINVAL; 600 } 601 602 rv = svga_check_timings (&ark_timing_regs, var, info->node); 603 if (rv < 0) 604 { 605 fb_err(info, "invalid timings requested\n"); 606 return rv; 607 } 608 609 /* Interlaced mode is broken */ 610 if (var->vmode & FB_VMODE_INTERLACED) 611 return -EINVAL; 612 613 return 0; 614 } 615 616 /* Set video mode from par */ 617 618 static int arkfb_set_par(struct fb_info *info) 619 { 620 struct arkfb_info *par = info->par; 621 u32 value, mode, hmul, hdiv, offset_value, screen_size; 622 u32 bpp = info->var.bits_per_pixel; 623 u8 regval; 624 625 if (bpp != 0) { 626 info->fix.ypanstep = 1; 627 info->fix.line_length = (info->var.xres_virtual * bpp) / 8; 628 629 info->flags &= ~FBINFO_MISC_TILEBLITTING; 630 info->tileops = NULL; 631 632 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ 633 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); 634 info->pixmap.blit_y = ~(u32)0; 635 636 offset_value = (info->var.xres_virtual * bpp) / 64; 637 screen_size = info->var.yres_virtual * info->fix.line_length; 638 } else { 639 info->fix.ypanstep = 16; 640 info->fix.line_length = 0; 641 642 info->flags |= FBINFO_MISC_TILEBLITTING; 643 info->tileops = &arkfb_tile_ops; 644 645 /* supports 8x16 tiles only */ 646 info->pixmap.blit_x = 1 << (8 - 1); 647 info->pixmap.blit_y = 1 << (16 - 1); 648 649 offset_value = info->var.xres_virtual / 16; 650 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; 651 } 652 653 info->var.xoffset = 0; 654 info->var.yoffset = 0; 655 info->var.activate = FB_ACTIVATE_NOW; 656 657 /* Unlock registers */ 658 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); 659 660 /* Blank screen and turn off sync */ 661 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 662 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); 663 664 /* Set default values */ 665 svga_set_default_gfx_regs(par->state.vgabase); 666 svga_set_default_atc_regs(par->state.vgabase); 667 svga_set_default_seq_regs(par->state.vgabase); 668 svga_set_default_crt_regs(par->state.vgabase); 669 svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF); 670 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0); 671 672 /* ARK specific initialization */ 673 svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */ 674 svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */ 675 676 vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16); 677 vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24); 678 vga_wseq(par->state.vgabase, 0x15, 0); 679 vga_wseq(par->state.vgabase, 0x16, 0); 680 681 /* Set the FIFO threshold register */ 682 /* It is fascinating way to store 5-bit value in 8-bit register */ 683 regval = 0x10 | ((threshold & 0x0E) >> 1) | (threshold & 0x01) << 7 | (threshold & 0x10) << 1; 684 vga_wseq(par->state.vgabase, 0x18, regval); 685 686 /* Set the offset register */ 687 fb_dbg(info, "offset register : %d\n", offset_value); 688 svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value); 689 690 /* fix for hi-res textmode */ 691 svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); 692 693 if (info->var.vmode & FB_VMODE_DOUBLE) 694 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); 695 else 696 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); 697 698 if (info->var.vmode & FB_VMODE_INTERLACED) 699 svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04); 700 else 701 svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04); 702 703 hmul = 1; 704 hdiv = 1; 705 mode = svga_match_format(arkfb_formats, &(info->var), &(info->fix)); 706 707 /* Set mode-specific register values */ 708 switch (mode) { 709 case 0: 710 fb_dbg(info, "text mode\n"); 711 svga_set_textmode_vga_regs(par->state.vgabase); 712 713 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ 714 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ 715 dac_set_mode(par->dac, DAC_PSEUDO8_8); 716 717 break; 718 case 1: 719 fb_dbg(info, "4 bit pseudocolor\n"); 720 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); 721 722 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ 723 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ 724 dac_set_mode(par->dac, DAC_PSEUDO8_8); 725 break; 726 case 2: 727 fb_dbg(info, "4 bit pseudocolor, planar\n"); 728 729 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */ 730 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ 731 dac_set_mode(par->dac, DAC_PSEUDO8_8); 732 break; 733 case 3: 734 fb_dbg(info, "8 bit pseudocolor\n"); 735 736 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */ 737 738 if (info->var.pixclock > 20000) { 739 fb_dbg(info, "not using multiplex\n"); 740 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */ 741 dac_set_mode(par->dac, DAC_PSEUDO8_8); 742 } else { 743 fb_dbg(info, "using multiplex\n"); 744 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ 745 dac_set_mode(par->dac, DAC_PSEUDO8_16); 746 hdiv = 2; 747 } 748 break; 749 case 4: 750 fb_dbg(info, "5/5/5 truecolor\n"); 751 752 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ 753 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ 754 dac_set_mode(par->dac, DAC_RGB1555_16); 755 break; 756 case 5: 757 fb_dbg(info, "5/6/5 truecolor\n"); 758 759 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ 760 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ 761 dac_set_mode(par->dac, DAC_RGB0565_16); 762 break; 763 case 6: 764 fb_dbg(info, "8/8/8 truecolor\n"); 765 766 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */ 767 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ 768 dac_set_mode(par->dac, DAC_RGB0888_16); 769 hmul = 3; 770 hdiv = 2; 771 break; 772 case 7: 773 fb_dbg(info, "8/8/8/8 truecolor\n"); 774 775 vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */ 776 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */ 777 dac_set_mode(par->dac, DAC_RGB8888_16); 778 hmul = 2; 779 break; 780 default: 781 fb_err(info, "unsupported mode - bug\n"); 782 return -EINVAL; 783 } 784 785 ark_set_pixclock(info, (hdiv * info->var.pixclock) / hmul); 786 svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv, 787 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 788 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1, 789 hmul, info->node); 790 791 /* Set interlaced mode start/end register */ 792 value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len; 793 value = ((value * hmul / hdiv) / 8) - 5; 794 vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2); 795 796 memset_io(info->screen_base, 0x00, screen_size); 797 /* Device and screen back on */ 798 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); 799 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); 800 801 return 0; 802 } 803 804 /* Set a colour register */ 805 806 static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 807 u_int transp, struct fb_info *fb) 808 { 809 switch (fb->var.bits_per_pixel) { 810 case 0: 811 case 4: 812 if (regno >= 16) 813 return -EINVAL; 814 815 if ((fb->var.bits_per_pixel == 4) && 816 (fb->var.nonstd == 0)) { 817 outb(0xF0, VGA_PEL_MSK); 818 outb(regno*16, VGA_PEL_IW); 819 } else { 820 outb(0x0F, VGA_PEL_MSK); 821 outb(regno, VGA_PEL_IW); 822 } 823 outb(red >> 10, VGA_PEL_D); 824 outb(green >> 10, VGA_PEL_D); 825 outb(blue >> 10, VGA_PEL_D); 826 break; 827 case 8: 828 if (regno >= 256) 829 return -EINVAL; 830 831 outb(0xFF, VGA_PEL_MSK); 832 outb(regno, VGA_PEL_IW); 833 outb(red >> 10, VGA_PEL_D); 834 outb(green >> 10, VGA_PEL_D); 835 outb(blue >> 10, VGA_PEL_D); 836 break; 837 case 16: 838 if (regno >= 16) 839 return 0; 840 841 if (fb->var.green.length == 5) 842 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | 843 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); 844 else if (fb->var.green.length == 6) 845 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | 846 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); 847 else 848 return -EINVAL; 849 break; 850 case 24: 851 case 32: 852 if (regno >= 16) 853 return 0; 854 855 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | 856 (green & 0xFF00) | ((blue & 0xFF00) >> 8); 857 break; 858 default: 859 return -EINVAL; 860 } 861 862 return 0; 863 } 864 865 /* Set the display blanking state */ 866 867 static int arkfb_blank(int blank_mode, struct fb_info *info) 868 { 869 struct arkfb_info *par = info->par; 870 871 switch (blank_mode) { 872 case FB_BLANK_UNBLANK: 873 fb_dbg(info, "unblank\n"); 874 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); 875 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); 876 break; 877 case FB_BLANK_NORMAL: 878 fb_dbg(info, "blank\n"); 879 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 880 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); 881 break; 882 case FB_BLANK_POWERDOWN: 883 case FB_BLANK_HSYNC_SUSPEND: 884 case FB_BLANK_VSYNC_SUSPEND: 885 fb_dbg(info, "sync down\n"); 886 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); 887 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); 888 break; 889 } 890 return 0; 891 } 892 893 894 /* Pan the display */ 895 896 static int arkfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 897 { 898 struct arkfb_info *par = info->par; 899 unsigned int offset; 900 901 /* Calculate the offset */ 902 if (info->var.bits_per_pixel == 0) { 903 offset = (var->yoffset / 16) * (info->var.xres_virtual / 2) 904 + (var->xoffset / 2); 905 offset = offset >> 2; 906 } else { 907 offset = (var->yoffset * info->fix.line_length) + 908 (var->xoffset * info->var.bits_per_pixel / 8); 909 offset = offset >> ((info->var.bits_per_pixel == 4) ? 2 : 3); 910 } 911 912 /* Set the offset */ 913 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset); 914 915 return 0; 916 } 917 918 919 /* ------------------------------------------------------------------------- */ 920 921 922 /* Frame buffer operations */ 923 924 static const struct fb_ops arkfb_ops = { 925 .owner = THIS_MODULE, 926 .fb_open = arkfb_open, 927 .fb_release = arkfb_release, 928 .fb_check_var = arkfb_check_var, 929 .fb_set_par = arkfb_set_par, 930 .fb_setcolreg = arkfb_setcolreg, 931 .fb_blank = arkfb_blank, 932 .fb_pan_display = arkfb_pan_display, 933 .fb_fillrect = arkfb_fillrect, 934 .fb_copyarea = cfb_copyarea, 935 .fb_imageblit = arkfb_imageblit, 936 .fb_get_caps = svga_get_caps, 937 }; 938 939 940 /* ------------------------------------------------------------------------- */ 941 942 943 /* PCI probe */ 944 static int ark_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) 945 { 946 struct pci_bus_region bus_reg; 947 struct resource vga_res; 948 struct fb_info *info; 949 struct arkfb_info *par; 950 int rc; 951 u8 regval; 952 953 rc = aperture_remove_conflicting_pci_devices(dev, "arkfb"); 954 if (rc < 0) 955 return rc; 956 957 /* Ignore secondary VGA device because there is no VGA arbitration */ 958 if (! svga_primary_device(dev)) { 959 dev_info(&(dev->dev), "ignoring secondary device\n"); 960 return -ENODEV; 961 } 962 963 /* Allocate and fill driver data structure */ 964 info = framebuffer_alloc(sizeof(struct arkfb_info), &(dev->dev)); 965 if (!info) 966 return -ENOMEM; 967 968 par = info->par; 969 mutex_init(&par->open_lock); 970 971 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; 972 info->fbops = &arkfb_ops; 973 974 /* Prepare PCI device */ 975 rc = pci_enable_device(dev); 976 if (rc < 0) { 977 dev_err(info->device, "cannot enable PCI device\n"); 978 goto err_enable_device; 979 } 980 981 rc = pci_request_regions(dev, "arkfb"); 982 if (rc < 0) { 983 dev_err(info->device, "cannot reserve framebuffer region\n"); 984 goto err_request_regions; 985 } 986 987 par->dac = ics5342_init(ark_dac_read_regs, ark_dac_write_regs, info); 988 if (! par->dac) { 989 rc = -ENOMEM; 990 dev_err(info->device, "RAMDAC initialization failed\n"); 991 goto err_dac; 992 } 993 994 info->fix.smem_start = pci_resource_start(dev, 0); 995 info->fix.smem_len = pci_resource_len(dev, 0); 996 997 /* Map physical IO memory address into kernel space */ 998 info->screen_base = pci_iomap_wc(dev, 0, 0); 999 if (! info->screen_base) { 1000 rc = -ENOMEM; 1001 dev_err(info->device, "iomap for framebuffer failed\n"); 1002 goto err_iomap; 1003 } 1004 1005 bus_reg.start = 0; 1006 bus_reg.end = 64 * 1024; 1007 1008 vga_res.flags = IORESOURCE_IO; 1009 1010 pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg); 1011 1012 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start; 1013 1014 /* FIXME get memsize */ 1015 regval = vga_rseq(par->state.vgabase, 0x10); 1016 info->screen_size = (1 << (regval >> 6)) << 20; 1017 info->fix.smem_len = info->screen_size; 1018 1019 strcpy(info->fix.id, "ARK 2000PV"); 1020 info->fix.mmio_start = 0; 1021 info->fix.mmio_len = 0; 1022 info->fix.type = FB_TYPE_PACKED_PIXELS; 1023 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 1024 info->fix.ypanstep = 0; 1025 info->fix.accel = FB_ACCEL_NONE; 1026 info->pseudo_palette = (void*) (par->pseudo_palette); 1027 1028 /* Prepare startup mode */ 1029 rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8); 1030 if (! ((rc == 1) || (rc == 2))) { 1031 rc = -EINVAL; 1032 dev_err(info->device, "mode %s not found\n", mode_option); 1033 goto err_find_mode; 1034 } 1035 1036 rc = fb_alloc_cmap(&info->cmap, 256, 0); 1037 if (rc < 0) { 1038 dev_err(info->device, "cannot allocate colormap\n"); 1039 goto err_alloc_cmap; 1040 } 1041 1042 rc = register_framebuffer(info); 1043 if (rc < 0) { 1044 dev_err(info->device, "cannot register framebuffer\n"); 1045 goto err_reg_fb; 1046 } 1047 1048 fb_info(info, "%s on %s, %d MB RAM\n", 1049 info->fix.id, pci_name(dev), info->fix.smem_len >> 20); 1050 1051 /* Record a reference to the driver data */ 1052 pci_set_drvdata(dev, info); 1053 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, 1054 info->fix.smem_len); 1055 return 0; 1056 1057 /* Error handling */ 1058 err_reg_fb: 1059 fb_dealloc_cmap(&info->cmap); 1060 err_alloc_cmap: 1061 err_find_mode: 1062 pci_iounmap(dev, info->screen_base); 1063 err_iomap: 1064 dac_release(par->dac); 1065 err_dac: 1066 pci_release_regions(dev); 1067 err_request_regions: 1068 /* pci_disable_device(dev); */ 1069 err_enable_device: 1070 framebuffer_release(info); 1071 return rc; 1072 } 1073 1074 /* PCI remove */ 1075 1076 static void ark_pci_remove(struct pci_dev *dev) 1077 { 1078 struct fb_info *info = pci_get_drvdata(dev); 1079 1080 if (info) { 1081 struct arkfb_info *par = info->par; 1082 arch_phys_wc_del(par->wc_cookie); 1083 dac_release(par->dac); 1084 unregister_framebuffer(info); 1085 fb_dealloc_cmap(&info->cmap); 1086 1087 pci_iounmap(dev, info->screen_base); 1088 pci_release_regions(dev); 1089 /* pci_disable_device(dev); */ 1090 1091 framebuffer_release(info); 1092 } 1093 } 1094 1095 1096 /* PCI suspend */ 1097 1098 static int __maybe_unused ark_pci_suspend(struct device *dev) 1099 { 1100 struct fb_info *info = dev_get_drvdata(dev); 1101 struct arkfb_info *par = info->par; 1102 1103 dev_info(info->device, "suspend\n"); 1104 1105 console_lock(); 1106 mutex_lock(&(par->open_lock)); 1107 1108 if (par->ref_count == 0) { 1109 mutex_unlock(&(par->open_lock)); 1110 console_unlock(); 1111 return 0; 1112 } 1113 1114 fb_set_suspend(info, 1); 1115 1116 mutex_unlock(&(par->open_lock)); 1117 console_unlock(); 1118 1119 return 0; 1120 } 1121 1122 1123 /* PCI resume */ 1124 1125 static int __maybe_unused ark_pci_resume(struct device *dev) 1126 { 1127 struct fb_info *info = dev_get_drvdata(dev); 1128 struct arkfb_info *par = info->par; 1129 1130 dev_info(info->device, "resume\n"); 1131 1132 console_lock(); 1133 mutex_lock(&(par->open_lock)); 1134 1135 if (par->ref_count == 0) 1136 goto fail; 1137 1138 arkfb_set_par(info); 1139 fb_set_suspend(info, 0); 1140 1141 fail: 1142 mutex_unlock(&(par->open_lock)); 1143 console_unlock(); 1144 return 0; 1145 } 1146 1147 static const struct dev_pm_ops ark_pci_pm_ops = { 1148 #ifdef CONFIG_PM_SLEEP 1149 .suspend = ark_pci_suspend, 1150 .resume = ark_pci_resume, 1151 .freeze = NULL, 1152 .thaw = ark_pci_resume, 1153 .poweroff = ark_pci_suspend, 1154 .restore = ark_pci_resume, 1155 #endif 1156 }; 1157 1158 /* List of boards that we are trying to support */ 1159 1160 static const struct pci_device_id ark_devices[] = { 1161 {PCI_DEVICE(0xEDD8, 0xA099)}, 1162 {0, 0, 0, 0, 0, 0, 0} 1163 }; 1164 1165 1166 MODULE_DEVICE_TABLE(pci, ark_devices); 1167 1168 static struct pci_driver arkfb_pci_driver = { 1169 .name = "arkfb", 1170 .id_table = ark_devices, 1171 .probe = ark_pci_probe, 1172 .remove = ark_pci_remove, 1173 .driver.pm = &ark_pci_pm_ops, 1174 }; 1175 1176 /* Cleanup */ 1177 1178 static void __exit arkfb_cleanup(void) 1179 { 1180 pr_debug("arkfb: cleaning up\n"); 1181 pci_unregister_driver(&arkfb_pci_driver); 1182 } 1183 1184 /* Driver Initialisation */ 1185 1186 static int __init arkfb_init(void) 1187 { 1188 1189 #ifndef MODULE 1190 char *option = NULL; 1191 1192 if (fb_get_options("arkfb", &option)) 1193 return -ENODEV; 1194 1195 if (option && *option) 1196 mode_option = option; 1197 #endif 1198 1199 pr_debug("arkfb: initializing\n"); 1200 return pci_register_driver(&arkfb_pci_driver); 1201 } 1202 1203 module_init(arkfb_init); 1204 module_exit(arkfb_cleanup); 1205