1 /* 2 * linux/drivers/video/amba-clcd.c 3 * 4 * Copyright (C) 2001 ARM Limited, by David A Rusling 5 * Updated to 2.5, Deep Blue Solutions Ltd. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file COPYING in the main directory of this archive 9 * for more details. 10 * 11 * ARM PrimeCell PL110 Color LCD Controller 12 */ 13 #include <linux/amba/bus.h> 14 #include <linux/amba/clcd.h> 15 #include <linux/backlight.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/fb.h> 20 #include <linux/init.h> 21 #include <linux/ioport.h> 22 #include <linux/list.h> 23 #include <linux/mm.h> 24 #include <linux/module.h> 25 #include <linux/of_address.h> 26 #include <linux/of_graph.h> 27 #include <linux/slab.h> 28 #include <linux/string.h> 29 #include <video/display_timing.h> 30 #include <video/of_display_timing.h> 31 #include <video/videomode.h> 32 33 #include "amba-clcd-nomadik.h" 34 #include "amba-clcd-versatile.h" 35 36 #define to_clcd(info) container_of(info, struct clcd_fb, fb) 37 38 /* This is limited to 16 characters when displayed by X startup */ 39 static const char *clcd_name = "CLCD FB"; 40 41 /* 42 * Unfortunately, the enable/disable functions may be called either from 43 * process or IRQ context, and we _need_ to delay. This is _not_ good. 44 */ 45 static inline void clcdfb_sleep(unsigned int ms) 46 { 47 if (in_atomic()) { 48 mdelay(ms); 49 } else { 50 msleep(ms); 51 } 52 } 53 54 static inline void clcdfb_set_start(struct clcd_fb *fb) 55 { 56 unsigned long ustart = fb->fb.fix.smem_start; 57 unsigned long lstart; 58 59 ustart += fb->fb.var.yoffset * fb->fb.fix.line_length; 60 lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2; 61 62 writel(ustart, fb->regs + CLCD_UBAS); 63 writel(lstart, fb->regs + CLCD_LBAS); 64 } 65 66 static void clcdfb_disable(struct clcd_fb *fb) 67 { 68 u32 val; 69 70 if (fb->board->disable) 71 fb->board->disable(fb); 72 73 if (fb->panel->backlight) { 74 fb->panel->backlight->props.power = FB_BLANK_POWERDOWN; 75 backlight_update_status(fb->panel->backlight); 76 } 77 78 val = readl(fb->regs + fb->off_cntl); 79 if (val & CNTL_LCDPWR) { 80 val &= ~CNTL_LCDPWR; 81 writel(val, fb->regs + fb->off_cntl); 82 83 clcdfb_sleep(20); 84 } 85 if (val & CNTL_LCDEN) { 86 val &= ~CNTL_LCDEN; 87 writel(val, fb->regs + fb->off_cntl); 88 } 89 90 /* 91 * Disable CLCD clock source. 92 */ 93 if (fb->clk_enabled) { 94 fb->clk_enabled = false; 95 clk_disable(fb->clk); 96 } 97 } 98 99 static void clcdfb_enable(struct clcd_fb *fb, u32 cntl) 100 { 101 /* 102 * Enable the CLCD clock source. 103 */ 104 if (!fb->clk_enabled) { 105 fb->clk_enabled = true; 106 clk_enable(fb->clk); 107 } 108 109 /* 110 * Bring up by first enabling.. 111 */ 112 cntl |= CNTL_LCDEN; 113 writel(cntl, fb->regs + fb->off_cntl); 114 115 clcdfb_sleep(20); 116 117 /* 118 * and now apply power. 119 */ 120 cntl |= CNTL_LCDPWR; 121 writel(cntl, fb->regs + fb->off_cntl); 122 123 /* 124 * Turn on backlight 125 */ 126 if (fb->panel->backlight) { 127 fb->panel->backlight->props.power = FB_BLANK_UNBLANK; 128 backlight_update_status(fb->panel->backlight); 129 } 130 131 /* 132 * finally, enable the interface. 133 */ 134 if (fb->board->enable) 135 fb->board->enable(fb); 136 } 137 138 static int 139 clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var) 140 { 141 u32 caps; 142 int ret = 0; 143 144 if (fb->panel->caps && fb->board->caps) 145 caps = fb->panel->caps & fb->board->caps; 146 else { 147 /* Old way of specifying what can be used */ 148 caps = fb->panel->cntl & CNTL_BGR ? 149 CLCD_CAP_BGR : CLCD_CAP_RGB; 150 /* But mask out 444 modes as they weren't supported */ 151 caps &= ~CLCD_CAP_444; 152 } 153 154 /* Only TFT panels can do RGB888/BGR888 */ 155 if (!(fb->panel->cntl & CNTL_LCDTFT)) 156 caps &= ~CLCD_CAP_888; 157 158 memset(&var->transp, 0, sizeof(var->transp)); 159 160 var->red.msb_right = 0; 161 var->green.msb_right = 0; 162 var->blue.msb_right = 0; 163 164 switch (var->bits_per_pixel) { 165 case 1: 166 case 2: 167 case 4: 168 case 8: 169 /* If we can't do 5551, reject */ 170 caps &= CLCD_CAP_5551; 171 if (!caps) { 172 ret = -EINVAL; 173 break; 174 } 175 176 var->red.length = var->bits_per_pixel; 177 var->red.offset = 0; 178 var->green.length = var->bits_per_pixel; 179 var->green.offset = 0; 180 var->blue.length = var->bits_per_pixel; 181 var->blue.offset = 0; 182 break; 183 184 case 16: 185 /* If we can't do 444, 5551 or 565, reject */ 186 if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) { 187 ret = -EINVAL; 188 break; 189 } 190 191 /* 192 * Green length can be 4, 5 or 6 depending whether 193 * we're operating in 444, 5551 or 565 mode. 194 */ 195 if (var->green.length == 4 && caps & CLCD_CAP_444) 196 caps &= CLCD_CAP_444; 197 if (var->green.length == 5 && caps & CLCD_CAP_5551) 198 caps &= CLCD_CAP_5551; 199 else if (var->green.length == 6 && caps & CLCD_CAP_565) 200 caps &= CLCD_CAP_565; 201 else { 202 /* 203 * PL110 officially only supports RGB555, 204 * but may be wired up to allow RGB565. 205 */ 206 if (caps & CLCD_CAP_565) { 207 var->green.length = 6; 208 caps &= CLCD_CAP_565; 209 } else if (caps & CLCD_CAP_5551) { 210 var->green.length = 5; 211 caps &= CLCD_CAP_5551; 212 } else { 213 var->green.length = 4; 214 caps &= CLCD_CAP_444; 215 } 216 } 217 218 if (var->green.length >= 5) { 219 var->red.length = 5; 220 var->blue.length = 5; 221 } else { 222 var->red.length = 4; 223 var->blue.length = 4; 224 } 225 break; 226 case 24: 227 if (fb->vendor->packed_24_bit_pixels) { 228 var->red.length = 8; 229 var->green.length = 8; 230 var->blue.length = 8; 231 } else { 232 ret = -EINVAL; 233 } 234 break; 235 case 32: 236 /* If we can't do 888, reject */ 237 caps &= CLCD_CAP_888; 238 if (!caps) { 239 ret = -EINVAL; 240 break; 241 } 242 243 var->red.length = 8; 244 var->green.length = 8; 245 var->blue.length = 8; 246 break; 247 default: 248 ret = -EINVAL; 249 break; 250 } 251 252 /* 253 * >= 16bpp displays have separate colour component bitfields 254 * encoded in the pixel data. Calculate their position from 255 * the bitfield length defined above. 256 */ 257 if (ret == 0 && var->bits_per_pixel >= 16) { 258 bool bgr, rgb; 259 260 bgr = caps & CLCD_CAP_BGR && var->blue.offset == 0; 261 rgb = caps & CLCD_CAP_RGB && var->red.offset == 0; 262 263 if (!bgr && !rgb) 264 /* 265 * The requested format was not possible, try just 266 * our capabilities. One of BGR or RGB must be 267 * supported. 268 */ 269 bgr = caps & CLCD_CAP_BGR; 270 271 if (bgr) { 272 var->blue.offset = 0; 273 var->green.offset = var->blue.offset + var->blue.length; 274 var->red.offset = var->green.offset + var->green.length; 275 } else { 276 var->red.offset = 0; 277 var->green.offset = var->red.offset + var->red.length; 278 var->blue.offset = var->green.offset + var->green.length; 279 } 280 } 281 282 return ret; 283 } 284 285 static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) 286 { 287 struct clcd_fb *fb = to_clcd(info); 288 int ret = -EINVAL; 289 290 if (fb->board->check) 291 ret = fb->board->check(fb, var); 292 293 if (ret == 0 && 294 var->xres_virtual * var->bits_per_pixel / 8 * 295 var->yres_virtual > fb->fb.fix.smem_len) 296 ret = -EINVAL; 297 298 if (ret == 0) 299 ret = clcdfb_set_bitfields(fb, var); 300 301 return ret; 302 } 303 304 static int clcdfb_set_par(struct fb_info *info) 305 { 306 struct clcd_fb *fb = to_clcd(info); 307 struct clcd_regs regs; 308 309 fb->fb.fix.line_length = fb->fb.var.xres_virtual * 310 fb->fb.var.bits_per_pixel / 8; 311 312 if (fb->fb.var.bits_per_pixel <= 8) 313 fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; 314 else 315 fb->fb.fix.visual = FB_VISUAL_TRUECOLOR; 316 317 fb->board->decode(fb, ®s); 318 319 clcdfb_disable(fb); 320 321 /* Some variants must be clocked here */ 322 if (fb->vendor->clock_timregs && !fb->clk_enabled) { 323 fb->clk_enabled = true; 324 clk_enable(fb->clk); 325 } 326 327 writel(regs.tim0, fb->regs + CLCD_TIM0); 328 writel(regs.tim1, fb->regs + CLCD_TIM1); 329 writel(regs.tim2, fb->regs + CLCD_TIM2); 330 writel(regs.tim3, fb->regs + CLCD_TIM3); 331 332 clcdfb_set_start(fb); 333 334 clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000); 335 336 fb->clcd_cntl = regs.cntl; 337 338 clcdfb_enable(fb, regs.cntl); 339 340 #ifdef DEBUG 341 printk(KERN_INFO 342 "CLCD: Registers set to\n" 343 " %08x %08x %08x %08x\n" 344 " %08x %08x %08x %08x\n", 345 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1), 346 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3), 347 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS), 348 readl(fb->regs + fb->off_ienb), readl(fb->regs + fb->off_cntl)); 349 #endif 350 351 return 0; 352 } 353 354 static inline u32 convert_bitfield(int val, struct fb_bitfield *bf) 355 { 356 unsigned int mask = (1 << bf->length) - 1; 357 358 return (val >> (16 - bf->length) & mask) << bf->offset; 359 } 360 361 /* 362 * Set a single color register. The values supplied have a 16 bit 363 * magnitude. Return != 0 for invalid regno. 364 */ 365 static int 366 clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, 367 unsigned int blue, unsigned int transp, struct fb_info *info) 368 { 369 struct clcd_fb *fb = to_clcd(info); 370 371 if (regno < 16) 372 fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) | 373 convert_bitfield(blue, &fb->fb.var.blue) | 374 convert_bitfield(green, &fb->fb.var.green) | 375 convert_bitfield(red, &fb->fb.var.red); 376 377 if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) { 378 int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3); 379 u32 val, mask, newval; 380 381 newval = (red >> 11) & 0x001f; 382 newval |= (green >> 6) & 0x03e0; 383 newval |= (blue >> 1) & 0x7c00; 384 385 /* 386 * 3.2.11: if we're configured for big endian 387 * byte order, the palette entries are swapped. 388 */ 389 if (fb->clcd_cntl & CNTL_BEBO) 390 regno ^= 1; 391 392 if (regno & 1) { 393 newval <<= 16; 394 mask = 0x0000ffff; 395 } else { 396 mask = 0xffff0000; 397 } 398 399 val = readl(fb->regs + hw_reg) & mask; 400 writel(val | newval, fb->regs + hw_reg); 401 } 402 403 return regno > 255; 404 } 405 406 /* 407 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL 408 * then the caller blanks by setting the CLUT (Color Look Up Table) to all 409 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due 410 * to e.g. a video mode which doesn't support it. Implements VESA suspend 411 * and powerdown modes on hardware that supports disabling hsync/vsync: 412 * blank_mode == 2: suspend vsync 413 * blank_mode == 3: suspend hsync 414 * blank_mode == 4: powerdown 415 */ 416 static int clcdfb_blank(int blank_mode, struct fb_info *info) 417 { 418 struct clcd_fb *fb = to_clcd(info); 419 420 if (blank_mode != 0) { 421 clcdfb_disable(fb); 422 } else { 423 clcdfb_enable(fb, fb->clcd_cntl); 424 } 425 return 0; 426 } 427 428 static int clcdfb_mmap(struct fb_info *info, 429 struct vm_area_struct *vma) 430 { 431 struct clcd_fb *fb = to_clcd(info); 432 unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT; 433 int ret = -EINVAL; 434 435 len = info->fix.smem_len; 436 437 if (off <= len && vma->vm_end - vma->vm_start <= len - off && 438 fb->board->mmap) 439 ret = fb->board->mmap(fb, vma); 440 441 return ret; 442 } 443 444 static struct fb_ops clcdfb_ops = { 445 .owner = THIS_MODULE, 446 .fb_check_var = clcdfb_check_var, 447 .fb_set_par = clcdfb_set_par, 448 .fb_setcolreg = clcdfb_setcolreg, 449 .fb_blank = clcdfb_blank, 450 .fb_fillrect = cfb_fillrect, 451 .fb_copyarea = cfb_copyarea, 452 .fb_imageblit = cfb_imageblit, 453 .fb_mmap = clcdfb_mmap, 454 }; 455 456 static int clcdfb_register(struct clcd_fb *fb) 457 { 458 int ret; 459 460 /* 461 * ARM PL111 always has IENB at 0x1c; it's only PL110 462 * which is reversed on some platforms. 463 */ 464 if (amba_manf(fb->dev) == 0x41 && amba_part(fb->dev) == 0x111) { 465 fb->off_ienb = CLCD_PL111_IENB; 466 fb->off_cntl = CLCD_PL111_CNTL; 467 } else { 468 if (of_machine_is_compatible("arm,versatile-ab") || 469 of_machine_is_compatible("arm,versatile-pb")) { 470 fb->off_ienb = CLCD_PL111_IENB; 471 fb->off_cntl = CLCD_PL111_CNTL; 472 } else { 473 fb->off_ienb = CLCD_PL110_IENB; 474 fb->off_cntl = CLCD_PL110_CNTL; 475 } 476 } 477 478 fb->clk = clk_get(&fb->dev->dev, NULL); 479 if (IS_ERR(fb->clk)) { 480 ret = PTR_ERR(fb->clk); 481 goto out; 482 } 483 484 ret = clk_prepare(fb->clk); 485 if (ret) 486 goto free_clk; 487 488 fb->fb.device = &fb->dev->dev; 489 490 fb->fb.fix.mmio_start = fb->dev->res.start; 491 fb->fb.fix.mmio_len = resource_size(&fb->dev->res); 492 493 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len); 494 if (!fb->regs) { 495 printk(KERN_ERR "CLCD: unable to remap registers\n"); 496 ret = -ENOMEM; 497 goto clk_unprep; 498 } 499 500 fb->fb.fbops = &clcdfb_ops; 501 fb->fb.flags = FBINFO_FLAG_DEFAULT; 502 fb->fb.pseudo_palette = fb->cmap; 503 504 strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id)); 505 fb->fb.fix.type = FB_TYPE_PACKED_PIXELS; 506 fb->fb.fix.type_aux = 0; 507 fb->fb.fix.xpanstep = 0; 508 fb->fb.fix.ypanstep = 0; 509 fb->fb.fix.ywrapstep = 0; 510 fb->fb.fix.accel = FB_ACCEL_NONE; 511 512 fb->fb.var.xres = fb->panel->mode.xres; 513 fb->fb.var.yres = fb->panel->mode.yres; 514 fb->fb.var.xres_virtual = fb->panel->mode.xres; 515 fb->fb.var.yres_virtual = fb->panel->mode.yres; 516 fb->fb.var.bits_per_pixel = fb->panel->bpp; 517 fb->fb.var.grayscale = fb->panel->grayscale; 518 fb->fb.var.pixclock = fb->panel->mode.pixclock; 519 fb->fb.var.left_margin = fb->panel->mode.left_margin; 520 fb->fb.var.right_margin = fb->panel->mode.right_margin; 521 fb->fb.var.upper_margin = fb->panel->mode.upper_margin; 522 fb->fb.var.lower_margin = fb->panel->mode.lower_margin; 523 fb->fb.var.hsync_len = fb->panel->mode.hsync_len; 524 fb->fb.var.vsync_len = fb->panel->mode.vsync_len; 525 fb->fb.var.sync = fb->panel->mode.sync; 526 fb->fb.var.vmode = fb->panel->mode.vmode; 527 fb->fb.var.activate = FB_ACTIVATE_NOW; 528 fb->fb.var.nonstd = 0; 529 fb->fb.var.height = fb->panel->height; 530 fb->fb.var.width = fb->panel->width; 531 fb->fb.var.accel_flags = 0; 532 533 fb->fb.monspecs.hfmin = 0; 534 fb->fb.monspecs.hfmax = 100000; 535 fb->fb.monspecs.vfmin = 0; 536 fb->fb.monspecs.vfmax = 400; 537 fb->fb.monspecs.dclkmin = 1000000; 538 fb->fb.monspecs.dclkmax = 100000000; 539 540 /* 541 * Make sure that the bitfields are set appropriately. 542 */ 543 clcdfb_set_bitfields(fb, &fb->fb.var); 544 545 /* 546 * Allocate colourmap. 547 */ 548 ret = fb_alloc_cmap(&fb->fb.cmap, 256, 0); 549 if (ret) 550 goto unmap; 551 552 /* 553 * Ensure interrupts are disabled. 554 */ 555 writel(0, fb->regs + fb->off_ienb); 556 557 fb_set_var(&fb->fb, &fb->fb.var); 558 559 dev_info(&fb->dev->dev, "%s hardware, %s display\n", 560 fb->board->name, fb->panel->mode.name); 561 562 ret = register_framebuffer(&fb->fb); 563 if (ret == 0) 564 goto out; 565 566 printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret); 567 568 fb_dealloc_cmap(&fb->fb.cmap); 569 unmap: 570 iounmap(fb->regs); 571 clk_unprep: 572 clk_unprepare(fb->clk); 573 free_clk: 574 clk_put(fb->clk); 575 out: 576 return ret; 577 } 578 579 #ifdef CONFIG_OF 580 static int clcdfb_of_get_dpi_panel_mode(struct device_node *node, 581 struct clcd_panel *clcd_panel) 582 { 583 int err; 584 struct display_timing timing; 585 struct videomode video; 586 587 err = of_get_display_timing(node, "panel-timing", &timing); 588 if (err) 589 return err; 590 591 videomode_from_timing(&timing, &video); 592 593 err = fb_videomode_from_videomode(&video, &clcd_panel->mode); 594 if (err) 595 return err; 596 597 /* Set up some inversion flags */ 598 if (timing.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 599 clcd_panel->tim2 |= TIM2_IPC; 600 else if (!(timing.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)) 601 /* 602 * To preserve backwards compatibility, the IPC (inverted 603 * pixel clock) flag needs to be set on any display that 604 * doesn't explicitly specify that the pixel clock is 605 * active on the negative or positive edge. 606 */ 607 clcd_panel->tim2 |= TIM2_IPC; 608 609 if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW) 610 clcd_panel->tim2 |= TIM2_IHS; 611 612 if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW) 613 clcd_panel->tim2 |= TIM2_IVS; 614 615 if (timing.flags & DISPLAY_FLAGS_DE_LOW) 616 clcd_panel->tim2 |= TIM2_IOE; 617 618 return 0; 619 } 620 621 static int clcdfb_snprintf_mode(char *buf, int size, struct fb_videomode *mode) 622 { 623 return snprintf(buf, size, "%ux%u@%u", mode->xres, mode->yres, 624 mode->refresh); 625 } 626 627 static int clcdfb_of_get_backlight(struct device_node *panel, 628 struct clcd_panel *clcd_panel) 629 { 630 struct device_node *backlight; 631 632 /* Look up the optional backlight phandle */ 633 backlight = of_parse_phandle(panel, "backlight", 0); 634 if (backlight) { 635 clcd_panel->backlight = of_find_backlight_by_node(backlight); 636 of_node_put(backlight); 637 638 if (!clcd_panel->backlight) 639 return -EPROBE_DEFER; 640 } 641 return 0; 642 } 643 644 static int clcdfb_of_get_mode(struct device *dev, struct device_node *panel, 645 struct clcd_panel *clcd_panel) 646 { 647 int err; 648 struct fb_videomode *mode; 649 char *name; 650 int len; 651 652 /* Only directly connected DPI panels supported for now */ 653 if (of_device_is_compatible(panel, "panel-dpi")) 654 err = clcdfb_of_get_dpi_panel_mode(panel, clcd_panel); 655 else 656 err = -ENOENT; 657 if (err) 658 return err; 659 mode = &clcd_panel->mode; 660 661 len = clcdfb_snprintf_mode(NULL, 0, mode); 662 name = devm_kzalloc(dev, len + 1, GFP_KERNEL); 663 if (!name) 664 return -ENOMEM; 665 666 clcdfb_snprintf_mode(name, len + 1, mode); 667 mode->name = name; 668 669 return 0; 670 } 671 672 static int clcdfb_of_init_tft_panel(struct clcd_fb *fb, u32 r0, u32 g0, u32 b0) 673 { 674 static struct { 675 unsigned int part; 676 u32 r0, g0, b0; 677 u32 caps; 678 } panels[] = { 679 { 0x110, 1, 7, 13, CLCD_CAP_5551 }, 680 { 0x110, 0, 8, 16, CLCD_CAP_888 }, 681 { 0x110, 16, 8, 0, CLCD_CAP_888 }, 682 { 0x111, 4, 14, 20, CLCD_CAP_444 }, 683 { 0x111, 3, 11, 19, CLCD_CAP_444 | CLCD_CAP_5551 }, 684 { 0x111, 3, 10, 19, CLCD_CAP_444 | CLCD_CAP_5551 | 685 CLCD_CAP_565 }, 686 { 0x111, 0, 8, 16, CLCD_CAP_444 | CLCD_CAP_5551 | 687 CLCD_CAP_565 | CLCD_CAP_888 }, 688 }; 689 int i; 690 691 /* Bypass pixel clock divider */ 692 fb->panel->tim2 |= TIM2_BCD; 693 694 /* TFT display, vert. comp. interrupt at the start of the back porch */ 695 fb->panel->cntl |= CNTL_LCDTFT | CNTL_LCDVCOMP(1); 696 697 fb->panel->caps = 0; 698 699 /* Match the setup with known variants */ 700 for (i = 0; i < ARRAY_SIZE(panels) && !fb->panel->caps; i++) { 701 if (amba_part(fb->dev) != panels[i].part) 702 continue; 703 if (g0 != panels[i].g0) 704 continue; 705 if (r0 == panels[i].r0 && b0 == panels[i].b0) 706 fb->panel->caps = panels[i].caps; 707 } 708 709 /* 710 * If we actually physically connected the R lines to B and 711 * vice versa 712 */ 713 if (r0 != 0 && b0 == 0) 714 fb->panel->bgr_connection = true; 715 716 if (fb->panel->caps && fb->vendor->st_bitmux_control) { 717 /* 718 * Set up the special bits for the Nomadik control register 719 * (other platforms tend to do this through an external 720 * register). 721 */ 722 723 /* Offset of the highest used color */ 724 int maxoff = max3(r0, g0, b0); 725 /* Most significant bit out, highest used bit */ 726 int msb = 0; 727 728 if (fb->panel->caps & CLCD_CAP_888) { 729 msb = maxoff + 8 - 1; 730 } else if (fb->panel->caps & CLCD_CAP_565) { 731 msb = maxoff + 5 - 1; 732 fb->panel->cntl |= CNTL_ST_1XBPP_565; 733 } else if (fb->panel->caps & CLCD_CAP_5551) { 734 msb = maxoff + 5 - 1; 735 fb->panel->cntl |= CNTL_ST_1XBPP_5551; 736 } else if (fb->panel->caps & CLCD_CAP_444) { 737 msb = maxoff + 4 - 1; 738 fb->panel->cntl |= CNTL_ST_1XBPP_444; 739 } 740 741 /* Send out as many bits as we need */ 742 if (msb > 17) 743 fb->panel->cntl |= CNTL_ST_CDWID_24; 744 else if (msb > 15) 745 fb->panel->cntl |= CNTL_ST_CDWID_18; 746 else if (msb > 11) 747 fb->panel->cntl |= CNTL_ST_CDWID_16; 748 else 749 fb->panel->cntl |= CNTL_ST_CDWID_12; 750 } 751 752 return fb->panel->caps ? 0 : -EINVAL; 753 } 754 755 static int clcdfb_of_init_display(struct clcd_fb *fb) 756 { 757 struct device_node *endpoint, *panel; 758 int err; 759 unsigned int bpp; 760 u32 max_bandwidth; 761 u32 tft_r0b0g0[3]; 762 763 fb->panel = devm_kzalloc(&fb->dev->dev, sizeof(*fb->panel), GFP_KERNEL); 764 if (!fb->panel) 765 return -ENOMEM; 766 767 /* 768 * Fetch the panel endpoint. 769 */ 770 endpoint = of_graph_get_next_endpoint(fb->dev->dev.of_node, NULL); 771 if (!endpoint) 772 return -ENODEV; 773 774 panel = of_graph_get_remote_port_parent(endpoint); 775 if (!panel) 776 return -ENODEV; 777 778 if (fb->vendor->init_panel) { 779 err = fb->vendor->init_panel(fb, panel); 780 if (err) 781 return err; 782 } 783 784 err = clcdfb_of_get_backlight(panel, fb->panel); 785 if (err) 786 return err; 787 788 err = clcdfb_of_get_mode(&fb->dev->dev, panel, fb->panel); 789 if (err) 790 return err; 791 792 err = of_property_read_u32(fb->dev->dev.of_node, "max-memory-bandwidth", 793 &max_bandwidth); 794 if (!err) { 795 /* 796 * max_bandwidth is in bytes per second and pixclock in 797 * pico-seconds, so the maximum allowed bits per pixel is 798 * 8 * max_bandwidth / (PICOS2KHZ(pixclock) * 1000) 799 * Rearrange this calculation to avoid overflow and then ensure 800 * result is a valid format. 801 */ 802 bpp = max_bandwidth / (1000 / 8) 803 / PICOS2KHZ(fb->panel->mode.pixclock); 804 bpp = rounddown_pow_of_two(bpp); 805 if (bpp > 32) 806 bpp = 32; 807 } else 808 bpp = 32; 809 fb->panel->bpp = bpp; 810 811 #ifdef CONFIG_CPU_BIG_ENDIAN 812 fb->panel->cntl |= CNTL_BEBO; 813 #endif 814 fb->panel->width = -1; 815 fb->panel->height = -1; 816 817 if (of_property_read_u32_array(endpoint, 818 "arm,pl11x,tft-r0g0b0-pads", 819 tft_r0b0g0, ARRAY_SIZE(tft_r0b0g0)) != 0) 820 return -ENOENT; 821 822 return clcdfb_of_init_tft_panel(fb, tft_r0b0g0[0], 823 tft_r0b0g0[1], tft_r0b0g0[2]); 824 } 825 826 static int clcdfb_of_vram_setup(struct clcd_fb *fb) 827 { 828 int err; 829 struct device_node *memory; 830 u64 size; 831 832 err = clcdfb_of_init_display(fb); 833 if (err) 834 return err; 835 836 memory = of_parse_phandle(fb->dev->dev.of_node, "memory-region", 0); 837 if (!memory) 838 return -ENODEV; 839 840 fb->fb.screen_base = of_iomap(memory, 0); 841 if (!fb->fb.screen_base) 842 return -ENOMEM; 843 844 fb->fb.fix.smem_start = of_translate_address(memory, 845 of_get_address(memory, 0, &size, NULL)); 846 fb->fb.fix.smem_len = size; 847 848 return 0; 849 } 850 851 static int clcdfb_of_vram_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) 852 { 853 unsigned long off, user_size, kernel_size; 854 855 856 off = vma->vm_pgoff << PAGE_SHIFT; 857 user_size = vma->vm_end - vma->vm_start; 858 kernel_size = fb->fb.fix.smem_len; 859 860 if (off >= kernel_size || user_size > (kernel_size - off)) 861 return -ENXIO; 862 863 return remap_pfn_range(vma, vma->vm_start, 864 __phys_to_pfn(fb->fb.fix.smem_start) + vma->vm_pgoff, 865 user_size, 866 pgprot_writecombine(vma->vm_page_prot)); 867 } 868 869 static void clcdfb_of_vram_remove(struct clcd_fb *fb) 870 { 871 iounmap(fb->fb.screen_base); 872 } 873 874 static int clcdfb_of_dma_setup(struct clcd_fb *fb) 875 { 876 unsigned long framesize; 877 dma_addr_t dma; 878 int err; 879 880 err = clcdfb_of_init_display(fb); 881 if (err) 882 return err; 883 884 framesize = PAGE_ALIGN(fb->panel->mode.xres * fb->panel->mode.yres * 885 fb->panel->bpp / 8); 886 fb->fb.screen_base = dma_alloc_coherent(&fb->dev->dev, framesize, 887 &dma, GFP_KERNEL); 888 if (!fb->fb.screen_base) 889 return -ENOMEM; 890 891 fb->fb.fix.smem_start = dma; 892 fb->fb.fix.smem_len = framesize; 893 894 return 0; 895 } 896 897 static int clcdfb_of_dma_mmap(struct clcd_fb *fb, struct vm_area_struct *vma) 898 { 899 return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base, 900 fb->fb.fix.smem_start, fb->fb.fix.smem_len); 901 } 902 903 static void clcdfb_of_dma_remove(struct clcd_fb *fb) 904 { 905 dma_free_coherent(&fb->dev->dev, fb->fb.fix.smem_len, 906 fb->fb.screen_base, fb->fb.fix.smem_start); 907 } 908 909 static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev) 910 { 911 struct clcd_board *board = devm_kzalloc(&dev->dev, sizeof(*board), 912 GFP_KERNEL); 913 struct device_node *node = dev->dev.of_node; 914 915 if (!board) 916 return NULL; 917 918 board->name = of_node_full_name(node); 919 board->caps = CLCD_CAP_ALL; 920 board->check = clcdfb_check; 921 board->decode = clcdfb_decode; 922 if (of_find_property(node, "memory-region", NULL)) { 923 board->setup = clcdfb_of_vram_setup; 924 board->mmap = clcdfb_of_vram_mmap; 925 board->remove = clcdfb_of_vram_remove; 926 } else { 927 board->setup = clcdfb_of_dma_setup; 928 board->mmap = clcdfb_of_dma_mmap; 929 board->remove = clcdfb_of_dma_remove; 930 } 931 932 return board; 933 } 934 #else 935 static struct clcd_board *clcdfb_of_get_board(struct amba_device *dev) 936 { 937 return NULL; 938 } 939 #endif 940 941 static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id) 942 { 943 struct clcd_board *board = dev_get_platdata(&dev->dev); 944 struct clcd_vendor_data *vendor = id->data; 945 struct clcd_fb *fb; 946 int ret; 947 948 if (!board) 949 board = clcdfb_of_get_board(dev); 950 951 if (!board) 952 return -EINVAL; 953 954 if (vendor->init_board) { 955 ret = vendor->init_board(dev, board); 956 if (ret) 957 return ret; 958 } 959 960 ret = dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32)); 961 if (ret) 962 goto out; 963 964 ret = amba_request_regions(dev, NULL); 965 if (ret) { 966 printk(KERN_ERR "CLCD: unable to reserve regs region\n"); 967 goto out; 968 } 969 970 fb = kzalloc(sizeof(struct clcd_fb), GFP_KERNEL); 971 if (!fb) { 972 printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n"); 973 ret = -ENOMEM; 974 goto free_region; 975 } 976 977 fb->dev = dev; 978 fb->vendor = vendor; 979 fb->board = board; 980 981 dev_info(&fb->dev->dev, "PL%03x designer %02x rev%u at 0x%08llx\n", 982 amba_part(dev), amba_manf(dev), amba_rev(dev), 983 (unsigned long long)dev->res.start); 984 985 ret = fb->board->setup(fb); 986 if (ret) 987 goto free_fb; 988 989 ret = clcdfb_register(fb); 990 if (ret == 0) { 991 amba_set_drvdata(dev, fb); 992 goto out; 993 } 994 995 fb->board->remove(fb); 996 free_fb: 997 kfree(fb); 998 free_region: 999 amba_release_regions(dev); 1000 out: 1001 return ret; 1002 } 1003 1004 static int clcdfb_remove(struct amba_device *dev) 1005 { 1006 struct clcd_fb *fb = amba_get_drvdata(dev); 1007 1008 clcdfb_disable(fb); 1009 unregister_framebuffer(&fb->fb); 1010 if (fb->fb.cmap.len) 1011 fb_dealloc_cmap(&fb->fb.cmap); 1012 iounmap(fb->regs); 1013 clk_unprepare(fb->clk); 1014 clk_put(fb->clk); 1015 1016 fb->board->remove(fb); 1017 1018 kfree(fb); 1019 1020 amba_release_regions(dev); 1021 1022 return 0; 1023 } 1024 1025 static struct clcd_vendor_data vendor_arm = { 1026 /* Sets up the versatile board displays */ 1027 .init_panel = versatile_clcd_init_panel, 1028 }; 1029 1030 static struct clcd_vendor_data vendor_nomadik = { 1031 .clock_timregs = true, 1032 .packed_24_bit_pixels = true, 1033 .st_bitmux_control = true, 1034 .init_board = nomadik_clcd_init_board, 1035 .init_panel = nomadik_clcd_init_panel, 1036 }; 1037 1038 static const struct amba_id clcdfb_id_table[] = { 1039 { 1040 .id = 0x00041110, 1041 .mask = 0x000ffffe, 1042 .data = &vendor_arm, 1043 }, 1044 /* ST Electronics Nomadik variant */ 1045 { 1046 .id = 0x00180110, 1047 .mask = 0x00fffffe, 1048 .data = &vendor_nomadik, 1049 }, 1050 { 0, 0 }, 1051 }; 1052 1053 MODULE_DEVICE_TABLE(amba, clcdfb_id_table); 1054 1055 static struct amba_driver clcd_driver = { 1056 .drv = { 1057 .name = "clcd-pl11x", 1058 }, 1059 .probe = clcdfb_probe, 1060 .remove = clcdfb_remove, 1061 .id_table = clcdfb_id_table, 1062 }; 1063 1064 static int __init amba_clcdfb_init(void) 1065 { 1066 if (fb_get_options("ambafb", NULL)) 1067 return -ENODEV; 1068 1069 return amba_driver_register(&clcd_driver); 1070 } 1071 1072 module_init(amba_clcdfb_init); 1073 1074 static void __exit amba_clcdfb_exit(void) 1075 { 1076 amba_driver_unregister(&clcd_driver); 1077 } 1078 1079 module_exit(amba_clcdfb_exit); 1080 1081 MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver"); 1082 MODULE_LICENSE("GPL"); 1083