1 /* 2 * VFIO PCI config space virtualization 3 * 4 * Copyright (C) 2012 Red Hat, Inc. All rights reserved. 5 * Author: Alex Williamson <alex.williamson@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Derived from original vfio: 12 * Copyright 2010 Cisco Systems, Inc. All rights reserved. 13 * Author: Tom Lyon, pugs@cisco.com 14 */ 15 16 /* 17 * This code handles reading and writing of PCI configuration registers. 18 * This is hairy because we want to allow a lot of flexibility to the 19 * user driver, but cannot trust it with all of the config fields. 20 * Tables determine which fields can be read and written, as well as 21 * which fields are 'virtualized' - special actions and translations to 22 * make it appear to the user that he has control, when in fact things 23 * must be negotiated with the underlying OS. 24 */ 25 26 #include <linux/fs.h> 27 #include <linux/pci.h> 28 #include <linux/uaccess.h> 29 #include <linux/vfio.h> 30 31 #include "vfio_pci_private.h" 32 33 #define PCI_CFG_SPACE_SIZE 256 34 35 /* Useful "pseudo" capabilities */ 36 #define PCI_CAP_ID_BASIC 0 37 #define PCI_CAP_ID_INVALID 0xFF 38 39 #define is_bar(offset) \ 40 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \ 41 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4)) 42 43 /* 44 * Lengths of PCI Config Capabilities 45 * 0: Removed from the user visible capability list 46 * FF: Variable length 47 */ 48 static u8 pci_cap_length[] = { 49 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */ 50 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF, 51 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF, 52 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF, 53 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */ 54 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */ 55 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */ 56 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */ 57 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */ 58 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */ 59 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */ 60 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */ 61 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */ 62 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */ 63 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */ 64 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */ 65 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */ 66 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF, 67 [PCI_CAP_ID_SATA] = 0xFF, 68 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF, 69 }; 70 71 /* 72 * Lengths of PCIe/PCI-X Extended Config Capabilities 73 * 0: Removed or masked from the user visible capabilty list 74 * FF: Variable length 75 */ 76 static u16 pci_ext_cap_length[] = { 77 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND, 78 [PCI_EXT_CAP_ID_VC] = 0xFF, 79 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF, 80 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF, 81 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */ 82 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */ 83 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */ 84 [PCI_EXT_CAP_ID_MFVC] = 0xFF, 85 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */ 86 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */ 87 [PCI_EXT_CAP_ID_VNDR] = 0xFF, 88 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */ 89 [PCI_EXT_CAP_ID_ACS] = 0xFF, 90 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF, 91 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF, 92 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF, 93 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */ 94 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF, 95 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF, 96 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */ 97 [PCI_EXT_CAP_ID_REBAR] = 0xFF, 98 [PCI_EXT_CAP_ID_DPA] = 0xFF, 99 [PCI_EXT_CAP_ID_TPH] = 0xFF, 100 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF, 101 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */ 102 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */ 103 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */ 104 }; 105 106 /* 107 * Read/Write Permission Bits - one bit for each bit in capability 108 * Any field can be read if it exists, but what is read depends on 109 * whether the field is 'virtualized', or just pass thru to the 110 * hardware. Any virtualized field is also virtualized for writes. 111 * Writes are only permitted if they have a 1 bit here. 112 */ 113 struct perm_bits { 114 u8 *virt; /* read/write virtual data, not hw */ 115 u8 *write; /* writeable bits */ 116 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count, 117 struct perm_bits *perm, int offset, __le32 *val); 118 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count, 119 struct perm_bits *perm, int offset, __le32 val); 120 }; 121 122 #define NO_VIRT 0 123 #define ALL_VIRT 0xFFFFFFFFU 124 #define NO_WRITE 0 125 #define ALL_WRITE 0xFFFFFFFFU 126 127 static int vfio_user_config_read(struct pci_dev *pdev, int offset, 128 __le32 *val, int count) 129 { 130 int ret = -EINVAL; 131 u32 tmp_val = 0; 132 133 switch (count) { 134 case 1: 135 { 136 u8 tmp; 137 ret = pci_user_read_config_byte(pdev, offset, &tmp); 138 tmp_val = tmp; 139 break; 140 } 141 case 2: 142 { 143 u16 tmp; 144 ret = pci_user_read_config_word(pdev, offset, &tmp); 145 tmp_val = tmp; 146 break; 147 } 148 case 4: 149 ret = pci_user_read_config_dword(pdev, offset, &tmp_val); 150 break; 151 } 152 153 *val = cpu_to_le32(tmp_val); 154 155 return pcibios_err_to_errno(ret); 156 } 157 158 static int vfio_user_config_write(struct pci_dev *pdev, int offset, 159 __le32 val, int count) 160 { 161 int ret = -EINVAL; 162 u32 tmp_val = le32_to_cpu(val); 163 164 switch (count) { 165 case 1: 166 ret = pci_user_write_config_byte(pdev, offset, tmp_val); 167 break; 168 case 2: 169 ret = pci_user_write_config_word(pdev, offset, tmp_val); 170 break; 171 case 4: 172 ret = pci_user_write_config_dword(pdev, offset, tmp_val); 173 break; 174 } 175 176 return pcibios_err_to_errno(ret); 177 } 178 179 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos, 180 int count, struct perm_bits *perm, 181 int offset, __le32 *val) 182 { 183 __le32 virt = 0; 184 185 memcpy(val, vdev->vconfig + pos, count); 186 187 memcpy(&virt, perm->virt + offset, count); 188 189 /* Any non-virtualized bits? */ 190 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) { 191 struct pci_dev *pdev = vdev->pdev; 192 __le32 phys_val = 0; 193 int ret; 194 195 ret = vfio_user_config_read(pdev, pos, &phys_val, count); 196 if (ret) 197 return ret; 198 199 *val = (phys_val & ~virt) | (*val & virt); 200 } 201 202 return count; 203 } 204 205 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos, 206 int count, struct perm_bits *perm, 207 int offset, __le32 val) 208 { 209 __le32 virt = 0, write = 0; 210 211 memcpy(&write, perm->write + offset, count); 212 213 if (!write) 214 return count; /* drop, no writable bits */ 215 216 memcpy(&virt, perm->virt + offset, count); 217 218 /* Virtualized and writable bits go to vconfig */ 219 if (write & virt) { 220 __le32 virt_val = 0; 221 222 memcpy(&virt_val, vdev->vconfig + pos, count); 223 224 virt_val &= ~(write & virt); 225 virt_val |= (val & (write & virt)); 226 227 memcpy(vdev->vconfig + pos, &virt_val, count); 228 } 229 230 /* Non-virtualzed and writable bits go to hardware */ 231 if (write & ~virt) { 232 struct pci_dev *pdev = vdev->pdev; 233 __le32 phys_val = 0; 234 int ret; 235 236 ret = vfio_user_config_read(pdev, pos, &phys_val, count); 237 if (ret) 238 return ret; 239 240 phys_val &= ~(write & ~virt); 241 phys_val |= (val & (write & ~virt)); 242 243 ret = vfio_user_config_write(pdev, pos, phys_val, count); 244 if (ret) 245 return ret; 246 } 247 248 return count; 249 } 250 251 /* Allow direct read from hardware, except for capability next pointer */ 252 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos, 253 int count, struct perm_bits *perm, 254 int offset, __le32 *val) 255 { 256 int ret; 257 258 ret = vfio_user_config_read(vdev->pdev, pos, val, count); 259 if (ret) 260 return pcibios_err_to_errno(ret); 261 262 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */ 263 if (offset < 4) 264 memcpy(val, vdev->vconfig + pos, count); 265 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */ 266 if (offset == PCI_CAP_LIST_ID && count > 1) 267 memcpy(val, vdev->vconfig + pos, 268 min(PCI_CAP_FLAGS, count)); 269 else if (offset == PCI_CAP_LIST_NEXT) 270 memcpy(val, vdev->vconfig + pos, 1); 271 } 272 273 return count; 274 } 275 276 static int vfio_direct_config_write(struct vfio_pci_device *vdev, int pos, 277 int count, struct perm_bits *perm, 278 int offset, __le32 val) 279 { 280 int ret; 281 282 ret = vfio_user_config_write(vdev->pdev, pos, val, count); 283 if (ret) 284 return ret; 285 286 return count; 287 } 288 289 /* Default all regions to read-only, no-virtualization */ 290 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = { 291 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } 292 }; 293 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = { 294 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } 295 }; 296 297 static void free_perm_bits(struct perm_bits *perm) 298 { 299 kfree(perm->virt); 300 kfree(perm->write); 301 perm->virt = NULL; 302 perm->write = NULL; 303 } 304 305 static int alloc_perm_bits(struct perm_bits *perm, int size) 306 { 307 /* 308 * Round up all permission bits to the next dword, this lets us 309 * ignore whether a read/write exceeds the defined capability 310 * structure. We can do this because: 311 * - Standard config space is already dword aligned 312 * - Capabilities are all dword alinged (bits 0:1 of next reserved) 313 * - Express capabilities defined as dword aligned 314 */ 315 size = round_up(size, 4); 316 317 /* 318 * Zero state is 319 * - All Readable, None Writeable, None Virtualized 320 */ 321 perm->virt = kzalloc(size, GFP_KERNEL); 322 perm->write = kzalloc(size, GFP_KERNEL); 323 if (!perm->virt || !perm->write) { 324 free_perm_bits(perm); 325 return -ENOMEM; 326 } 327 328 perm->readfn = vfio_default_config_read; 329 perm->writefn = vfio_default_config_write; 330 331 return 0; 332 } 333 334 /* 335 * Helper functions for filling in permission tables 336 */ 337 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write) 338 { 339 p->virt[off] = virt; 340 p->write[off] = write; 341 } 342 343 /* Handle endian-ness - pci and tables are little-endian */ 344 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write) 345 { 346 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt); 347 *(__le16 *)(&p->write[off]) = cpu_to_le16(write); 348 } 349 350 /* Handle endian-ness - pci and tables are little-endian */ 351 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write) 352 { 353 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt); 354 *(__le32 *)(&p->write[off]) = cpu_to_le32(write); 355 } 356 357 /* 358 * Restore the *real* BARs after we detect a FLR or backdoor reset. 359 * (backdoor = some device specific technique that we didn't catch) 360 */ 361 static void vfio_bar_restore(struct vfio_pci_device *vdev) 362 { 363 struct pci_dev *pdev = vdev->pdev; 364 u32 *rbar = vdev->rbar; 365 int i; 366 367 if (pdev->is_virtfn) 368 return; 369 370 pr_info("%s: %s reset recovery - restoring bars\n", 371 __func__, dev_name(&pdev->dev)); 372 373 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++) 374 pci_user_write_config_dword(pdev, i, *rbar); 375 376 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar); 377 } 378 379 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar) 380 { 381 unsigned long flags = pci_resource_flags(pdev, bar); 382 u32 val; 383 384 if (flags & IORESOURCE_IO) 385 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO); 386 387 val = PCI_BASE_ADDRESS_SPACE_MEMORY; 388 389 if (flags & IORESOURCE_PREFETCH) 390 val |= PCI_BASE_ADDRESS_MEM_PREFETCH; 391 392 if (flags & IORESOURCE_MEM_64) 393 val |= PCI_BASE_ADDRESS_MEM_TYPE_64; 394 395 return cpu_to_le32(val); 396 } 397 398 /* 399 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs 400 * to reflect the hardware capabilities. This implements BAR sizing. 401 */ 402 static void vfio_bar_fixup(struct vfio_pci_device *vdev) 403 { 404 struct pci_dev *pdev = vdev->pdev; 405 int i; 406 __le32 *bar; 407 u64 mask; 408 409 bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0]; 410 411 for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) { 412 if (!pci_resource_start(pdev, i)) { 413 *bar = 0; /* Unmapped by host = unimplemented to user */ 414 continue; 415 } 416 417 mask = ~(pci_resource_len(pdev, i) - 1); 418 419 *bar &= cpu_to_le32((u32)mask); 420 *bar |= vfio_generate_bar_flags(pdev, i); 421 422 if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) { 423 bar++; 424 *bar &= cpu_to_le32((u32)(mask >> 32)); 425 i++; 426 } 427 } 428 429 bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS]; 430 431 /* 432 * NB. we expose the actual BAR size here, regardless of whether 433 * we can read it. When we report the REGION_INFO for the ROM 434 * we report what PCI tells us is the actual ROM size. 435 */ 436 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) { 437 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1); 438 mask |= PCI_ROM_ADDRESS_ENABLE; 439 *bar &= cpu_to_le32((u32)mask); 440 } else 441 *bar = 0; 442 443 vdev->bardirty = false; 444 } 445 446 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos, 447 int count, struct perm_bits *perm, 448 int offset, __le32 *val) 449 { 450 if (is_bar(offset)) /* pos == offset for basic config */ 451 vfio_bar_fixup(vdev); 452 453 count = vfio_default_config_read(vdev, pos, count, perm, offset, val); 454 455 /* Mask in virtual memory enable for SR-IOV devices */ 456 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) { 457 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]); 458 u32 tmp_val = le32_to_cpu(*val); 459 460 tmp_val |= cmd & PCI_COMMAND_MEMORY; 461 *val = cpu_to_le32(tmp_val); 462 } 463 464 return count; 465 } 466 467 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos, 468 int count, struct perm_bits *perm, 469 int offset, __le32 val) 470 { 471 struct pci_dev *pdev = vdev->pdev; 472 __le16 *virt_cmd; 473 u16 new_cmd = 0; 474 int ret; 475 476 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND]; 477 478 if (offset == PCI_COMMAND) { 479 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io; 480 u16 phys_cmd; 481 482 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd); 483 if (ret) 484 return ret; 485 486 new_cmd = le32_to_cpu(val); 487 488 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY); 489 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY); 490 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY); 491 492 phys_io = !!(phys_cmd & PCI_COMMAND_IO); 493 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO); 494 new_io = !!(new_cmd & PCI_COMMAND_IO); 495 496 /* 497 * If the user is writing mem/io enable (new_mem/io) and we 498 * think it's already enabled (virt_mem/io), but the hardware 499 * shows it disabled (phys_mem/io, then the device has 500 * undergone some kind of backdoor reset and needs to be 501 * restored before we allow it to enable the bars. 502 * SR-IOV devices will trigger this, but we catch them later 503 */ 504 if ((new_mem && virt_mem && !phys_mem) || 505 (new_io && virt_io && !phys_io)) 506 vfio_bar_restore(vdev); 507 } 508 509 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 510 if (count < 0) 511 return count; 512 513 /* 514 * Save current memory/io enable bits in vconfig to allow for 515 * the test above next time. 516 */ 517 if (offset == PCI_COMMAND) { 518 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO; 519 520 *virt_cmd &= cpu_to_le16(~mask); 521 *virt_cmd |= cpu_to_le16(new_cmd & mask); 522 } 523 524 /* Emulate INTx disable */ 525 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) { 526 bool virt_intx_disable; 527 528 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) & 529 PCI_COMMAND_INTX_DISABLE); 530 531 if (virt_intx_disable && !vdev->virq_disabled) { 532 vdev->virq_disabled = true; 533 vfio_pci_intx_mask(vdev); 534 } else if (!virt_intx_disable && vdev->virq_disabled) { 535 vdev->virq_disabled = false; 536 vfio_pci_intx_unmask(vdev); 537 } 538 } 539 540 if (is_bar(offset)) 541 vdev->bardirty = true; 542 543 return count; 544 } 545 546 /* Permissions for the Basic PCI Header */ 547 static int __init init_pci_cap_basic_perm(struct perm_bits *perm) 548 { 549 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF)) 550 return -ENOMEM; 551 552 perm->readfn = vfio_basic_config_read; 553 perm->writefn = vfio_basic_config_write; 554 555 /* Virtualized for SR-IOV functions, which just have FFFF */ 556 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE); 557 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE); 558 559 /* 560 * Virtualize INTx disable, we use it internally for interrupt 561 * control and can emulate it for non-PCI 2.3 devices. 562 */ 563 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE); 564 565 /* Virtualize capability list, we might want to skip/disable */ 566 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE); 567 568 /* No harm to write */ 569 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE); 570 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE); 571 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE); 572 573 /* Virtualize all bars, can't touch the real ones */ 574 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE); 575 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE); 576 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE); 577 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE); 578 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE); 579 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE); 580 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE); 581 582 /* Allow us to adjust capability chain */ 583 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE); 584 585 /* Sometimes used by sw, just virtualize */ 586 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE); 587 return 0; 588 } 589 590 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos, 591 int count, struct perm_bits *perm, 592 int offset, __le32 val) 593 { 594 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 595 if (count < 0) 596 return count; 597 598 if (offset == PCI_PM_CTRL) { 599 pci_power_t state; 600 601 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) { 602 case 0: 603 state = PCI_D0; 604 break; 605 case 1: 606 state = PCI_D1; 607 break; 608 case 2: 609 state = PCI_D2; 610 break; 611 case 3: 612 state = PCI_D3hot; 613 break; 614 } 615 616 pci_set_power_state(vdev->pdev, state); 617 } 618 619 return count; 620 } 621 622 /* Permissions for the Power Management capability */ 623 static int __init init_pci_cap_pm_perm(struct perm_bits *perm) 624 { 625 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM])) 626 return -ENOMEM; 627 628 perm->writefn = vfio_pm_config_write; 629 630 /* 631 * We always virtualize the next field so we can remove 632 * capabilities from the chain if we want to. 633 */ 634 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 635 636 /* 637 * Power management is defined *per function*, so we can let 638 * the user change power state, but we trap and initiate the 639 * change ourselves, so the state bits are read-only. 640 */ 641 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK); 642 return 0; 643 } 644 645 /* Permissions for PCI-X capability */ 646 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm) 647 { 648 /* Alloc 24, but only 8 are used in v0 */ 649 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2)) 650 return -ENOMEM; 651 652 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 653 654 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE); 655 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE); 656 return 0; 657 } 658 659 /* Permissions for PCI Express capability */ 660 static int __init init_pci_cap_exp_perm(struct perm_bits *perm) 661 { 662 /* Alloc larger of two possible sizes */ 663 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2)) 664 return -ENOMEM; 665 666 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 667 668 /* 669 * Allow writes to device control fields (includes FLR!) 670 * but not to devctl_phantom which could confuse IOMMU 671 * or to the ARI bit in devctl2 which is set at probe time 672 */ 673 p_setw(perm, PCI_EXP_DEVCTL, NO_VIRT, ~PCI_EXP_DEVCTL_PHANTOM); 674 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI); 675 return 0; 676 } 677 678 /* Permissions for Advanced Function capability */ 679 static int __init init_pci_cap_af_perm(struct perm_bits *perm) 680 { 681 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF])) 682 return -ENOMEM; 683 684 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 685 p_setb(perm, PCI_AF_CTRL, NO_VIRT, PCI_AF_CTRL_FLR); 686 return 0; 687 } 688 689 /* Permissions for Advanced Error Reporting extended capability */ 690 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm) 691 { 692 u32 mask; 693 694 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR])) 695 return -ENOMEM; 696 697 /* 698 * Virtualize the first dword of all express capabilities 699 * because it includes the next pointer. This lets us later 700 * remove capabilities from the chain if we need to. 701 */ 702 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 703 704 /* Writable bits mask */ 705 mask = PCI_ERR_UNC_TRAIN | /* Training */ 706 PCI_ERR_UNC_DLP | /* Data Link Protocol */ 707 PCI_ERR_UNC_SURPDN | /* Surprise Down */ 708 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */ 709 PCI_ERR_UNC_FCP | /* Flow Control Protocol */ 710 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */ 711 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */ 712 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */ 713 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */ 714 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */ 715 PCI_ERR_UNC_ECRC | /* ECRC Error Status */ 716 PCI_ERR_UNC_UNSUP | /* Unsupported Request */ 717 PCI_ERR_UNC_ACSV | /* ACS Violation */ 718 PCI_ERR_UNC_INTN | /* internal error */ 719 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */ 720 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */ 721 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */ 722 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask); 723 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask); 724 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask); 725 726 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */ 727 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */ 728 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */ 729 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */ 730 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */ 731 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */ 732 PCI_ERR_COR_INTERNAL | /* Corrected Internal */ 733 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */ 734 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask); 735 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask); 736 737 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */ 738 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */ 739 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask); 740 return 0; 741 } 742 743 /* Permissions for Power Budgeting extended capability */ 744 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm) 745 { 746 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR])) 747 return -ENOMEM; 748 749 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 750 751 /* Writing the data selector is OK, the info is still read-only */ 752 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE); 753 return 0; 754 } 755 756 /* 757 * Initialize the shared permission tables 758 */ 759 void vfio_pci_uninit_perm_bits(void) 760 { 761 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]); 762 763 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]); 764 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]); 765 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]); 766 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]); 767 768 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]); 769 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]); 770 } 771 772 int __init vfio_pci_init_perm_bits(void) 773 { 774 int ret; 775 776 /* Basic config space */ 777 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]); 778 779 /* Capabilities */ 780 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]); 781 cap_perms[PCI_CAP_ID_VPD].writefn = vfio_direct_config_write; 782 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]); 783 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_direct_config_write; 784 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]); 785 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]); 786 787 /* Extended capabilities */ 788 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]); 789 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]); 790 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_direct_config_write; 791 792 if (ret) 793 vfio_pci_uninit_perm_bits(); 794 795 return ret; 796 } 797 798 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos) 799 { 800 u8 cap; 801 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE : 802 PCI_STD_HEADER_SIZEOF; 803 base /= 4; 804 pos /= 4; 805 806 cap = vdev->pci_config_map[pos]; 807 808 if (cap == PCI_CAP_ID_BASIC) 809 return 0; 810 811 /* XXX Can we have to abutting capabilities of the same type? */ 812 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap) 813 pos--; 814 815 return pos * 4; 816 } 817 818 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos, 819 int count, struct perm_bits *perm, 820 int offset, __le32 *val) 821 { 822 /* Update max available queue size from msi_qmax */ 823 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) { 824 __le16 *flags; 825 int start; 826 827 start = vfio_find_cap_start(vdev, pos); 828 829 flags = (__le16 *)&vdev->vconfig[start]; 830 831 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK); 832 *flags |= cpu_to_le16(vdev->msi_qmax << 1); 833 } 834 835 return vfio_default_config_read(vdev, pos, count, perm, offset, val); 836 } 837 838 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos, 839 int count, struct perm_bits *perm, 840 int offset, __le32 val) 841 { 842 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 843 if (count < 0) 844 return count; 845 846 /* Fixup and write configured queue size and enable to hardware */ 847 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) { 848 __le16 *pflags; 849 u16 flags; 850 int start, ret; 851 852 start = vfio_find_cap_start(vdev, pos); 853 854 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS]; 855 856 flags = le16_to_cpu(*pflags); 857 858 /* MSI is enabled via ioctl */ 859 if (!is_msi(vdev)) 860 flags &= ~PCI_MSI_FLAGS_ENABLE; 861 862 /* Check queue size */ 863 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) { 864 flags &= ~PCI_MSI_FLAGS_QSIZE; 865 flags |= vdev->msi_qmax << 4; 866 } 867 868 /* Write back to virt and to hardware */ 869 *pflags = cpu_to_le16(flags); 870 ret = pci_user_write_config_word(vdev->pdev, 871 start + PCI_MSI_FLAGS, 872 flags); 873 if (ret) 874 return pcibios_err_to_errno(ret); 875 } 876 877 return count; 878 } 879 880 /* 881 * MSI determination is per-device, so this routine gets used beyond 882 * initialization time. Don't add __init 883 */ 884 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags) 885 { 886 if (alloc_perm_bits(perm, len)) 887 return -ENOMEM; 888 889 perm->readfn = vfio_msi_config_read; 890 perm->writefn = vfio_msi_config_write; 891 892 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 893 894 /* 895 * The upper byte of the control register is reserved, 896 * just setup the lower byte. 897 */ 898 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE); 899 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE); 900 if (flags & PCI_MSI_FLAGS_64BIT) { 901 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE); 902 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE); 903 if (flags & PCI_MSI_FLAGS_MASKBIT) { 904 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE); 905 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE); 906 } 907 } else { 908 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE); 909 if (flags & PCI_MSI_FLAGS_MASKBIT) { 910 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE); 911 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE); 912 } 913 } 914 return 0; 915 } 916 917 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */ 918 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos) 919 { 920 struct pci_dev *pdev = vdev->pdev; 921 int len, ret; 922 u16 flags; 923 924 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags); 925 if (ret) 926 return pcibios_err_to_errno(ret); 927 928 len = 10; /* Minimum size */ 929 if (flags & PCI_MSI_FLAGS_64BIT) 930 len += 4; 931 if (flags & PCI_MSI_FLAGS_MASKBIT) 932 len += 10; 933 934 if (vdev->msi_perm) 935 return len; 936 937 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL); 938 if (!vdev->msi_perm) 939 return -ENOMEM; 940 941 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags); 942 if (ret) 943 return ret; 944 945 return len; 946 } 947 948 /* Determine extended capability length for VC (2 & 9) and MFVC */ 949 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos) 950 { 951 struct pci_dev *pdev = vdev->pdev; 952 u32 tmp; 953 int ret, evcc, phases, vc_arb; 954 int len = PCI_CAP_VC_BASE_SIZEOF; 955 956 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_REG1, &tmp); 957 if (ret) 958 return pcibios_err_to_errno(ret); 959 960 evcc = tmp & PCI_VC_REG1_EVCC; /* extended vc count */ 961 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_REG2, &tmp); 962 if (ret) 963 return pcibios_err_to_errno(ret); 964 965 if (tmp & PCI_VC_REG2_128_PHASE) 966 phases = 128; 967 else if (tmp & PCI_VC_REG2_64_PHASE) 968 phases = 64; 969 else if (tmp & PCI_VC_REG2_32_PHASE) 970 phases = 32; 971 else 972 phases = 0; 973 974 vc_arb = phases * 4; 975 976 /* 977 * Port arbitration tables are root & switch only; 978 * function arbitration tables are function 0 only. 979 * In either case, we'll never let user write them so 980 * we don't care how big they are 981 */ 982 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF; 983 if (vc_arb) { 984 len = round_up(len, 16); 985 len += vc_arb / 8; 986 } 987 return len; 988 } 989 990 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos) 991 { 992 struct pci_dev *pdev = vdev->pdev; 993 u16 word; 994 u8 byte; 995 int ret; 996 997 switch (cap) { 998 case PCI_CAP_ID_MSI: 999 return vfio_msi_cap_len(vdev, pos); 1000 case PCI_CAP_ID_PCIX: 1001 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word); 1002 if (ret) 1003 return pcibios_err_to_errno(ret); 1004 1005 if (PCI_X_CMD_VERSION(word)) { 1006 vdev->extended_caps = true; 1007 return PCI_CAP_PCIX_SIZEOF_V2; 1008 } else 1009 return PCI_CAP_PCIX_SIZEOF_V0; 1010 case PCI_CAP_ID_VNDR: 1011 /* length follows next field */ 1012 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte); 1013 if (ret) 1014 return pcibios_err_to_errno(ret); 1015 1016 return byte; 1017 case PCI_CAP_ID_EXP: 1018 /* length based on version */ 1019 ret = pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &word); 1020 if (ret) 1021 return pcibios_err_to_errno(ret); 1022 1023 vdev->extended_caps = true; 1024 1025 if ((word & PCI_EXP_FLAGS_VERS) == 1) 1026 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1; 1027 else 1028 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2; 1029 case PCI_CAP_ID_HT: 1030 ret = pci_read_config_byte(pdev, pos + 3, &byte); 1031 if (ret) 1032 return pcibios_err_to_errno(ret); 1033 1034 return (byte & HT_3BIT_CAP_MASK) ? 1035 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG; 1036 case PCI_CAP_ID_SATA: 1037 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte); 1038 if (ret) 1039 return pcibios_err_to_errno(ret); 1040 1041 byte &= PCI_SATA_REGS_MASK; 1042 if (byte == PCI_SATA_REGS_INLINE) 1043 return PCI_SATA_SIZEOF_LONG; 1044 else 1045 return PCI_SATA_SIZEOF_SHORT; 1046 default: 1047 pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n", 1048 dev_name(&pdev->dev), __func__, cap, pos); 1049 } 1050 1051 return 0; 1052 } 1053 1054 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos) 1055 { 1056 struct pci_dev *pdev = vdev->pdev; 1057 u8 byte; 1058 u32 dword; 1059 int ret; 1060 1061 switch (ecap) { 1062 case PCI_EXT_CAP_ID_VNDR: 1063 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword); 1064 if (ret) 1065 return pcibios_err_to_errno(ret); 1066 1067 return dword >> PCI_VSEC_HDR_LEN_SHIFT; 1068 case PCI_EXT_CAP_ID_VC: 1069 case PCI_EXT_CAP_ID_VC9: 1070 case PCI_EXT_CAP_ID_MFVC: 1071 return vfio_vc_cap_len(vdev, epos); 1072 case PCI_EXT_CAP_ID_ACS: 1073 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte); 1074 if (ret) 1075 return pcibios_err_to_errno(ret); 1076 1077 if (byte & PCI_ACS_EC) { 1078 int bits; 1079 1080 ret = pci_read_config_byte(pdev, 1081 epos + PCI_ACS_EGRESS_BITS, 1082 &byte); 1083 if (ret) 1084 return pcibios_err_to_errno(ret); 1085 1086 bits = byte ? round_up(byte, 32) : 256; 1087 return 8 + (bits / 8); 1088 } 1089 return 8; 1090 1091 case PCI_EXT_CAP_ID_REBAR: 1092 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte); 1093 if (ret) 1094 return pcibios_err_to_errno(ret); 1095 1096 byte &= PCI_REBAR_CTRL_NBAR_MASK; 1097 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT; 1098 1099 return 4 + (byte * 8); 1100 case PCI_EXT_CAP_ID_DPA: 1101 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte); 1102 if (ret) 1103 return pcibios_err_to_errno(ret); 1104 1105 byte &= PCI_DPA_CAP_SUBSTATE_MASK; 1106 byte = round_up(byte + 1, 4); 1107 return PCI_DPA_BASE_SIZEOF + byte; 1108 case PCI_EXT_CAP_ID_TPH: 1109 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword); 1110 if (ret) 1111 return pcibios_err_to_errno(ret); 1112 1113 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) { 1114 int sts; 1115 1116 sts = byte & PCI_TPH_CAP_ST_MASK; 1117 sts >>= PCI_TPH_CAP_ST_SHIFT; 1118 return PCI_TPH_BASE_SIZEOF + round_up(sts * 2, 4); 1119 } 1120 return PCI_TPH_BASE_SIZEOF; 1121 default: 1122 pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n", 1123 dev_name(&pdev->dev), __func__, ecap, epos); 1124 } 1125 1126 return 0; 1127 } 1128 1129 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev, 1130 int offset, int size) 1131 { 1132 struct pci_dev *pdev = vdev->pdev; 1133 int ret = 0; 1134 1135 /* 1136 * We try to read physical config space in the largest chunks 1137 * we can, assuming that all of the fields support dword access. 1138 * pci_save_state() makes this same assumption and seems to do ok. 1139 */ 1140 while (size) { 1141 int filled; 1142 1143 if (size >= 4 && !(offset % 4)) { 1144 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset]; 1145 u32 dword; 1146 1147 ret = pci_read_config_dword(pdev, offset, &dword); 1148 if (ret) 1149 return ret; 1150 *dwordp = cpu_to_le32(dword); 1151 filled = 4; 1152 } else if (size >= 2 && !(offset % 2)) { 1153 __le16 *wordp = (__le16 *)&vdev->vconfig[offset]; 1154 u16 word; 1155 1156 ret = pci_read_config_word(pdev, offset, &word); 1157 if (ret) 1158 return ret; 1159 *wordp = cpu_to_le16(word); 1160 filled = 2; 1161 } else { 1162 u8 *byte = &vdev->vconfig[offset]; 1163 ret = pci_read_config_byte(pdev, offset, byte); 1164 if (ret) 1165 return ret; 1166 filled = 1; 1167 } 1168 1169 offset += filled; 1170 size -= filled; 1171 } 1172 1173 return ret; 1174 } 1175 1176 static int vfio_cap_init(struct vfio_pci_device *vdev) 1177 { 1178 struct pci_dev *pdev = vdev->pdev; 1179 u8 *map = vdev->pci_config_map; 1180 u16 status; 1181 u8 pos, *prev, cap; 1182 int loops, ret, caps = 0; 1183 1184 /* Any capabilities? */ 1185 ret = pci_read_config_word(pdev, PCI_STATUS, &status); 1186 if (ret) 1187 return ret; 1188 1189 if (!(status & PCI_STATUS_CAP_LIST)) 1190 return 0; /* Done */ 1191 1192 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos); 1193 if (ret) 1194 return ret; 1195 1196 /* Mark the previous position in case we want to skip a capability */ 1197 prev = &vdev->vconfig[PCI_CAPABILITY_LIST]; 1198 1199 /* We can bound our loop, capabilities are dword aligned */ 1200 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF; 1201 while (pos && loops--) { 1202 u8 next; 1203 int i, len = 0; 1204 1205 ret = pci_read_config_byte(pdev, pos, &cap); 1206 if (ret) 1207 return ret; 1208 1209 ret = pci_read_config_byte(pdev, 1210 pos + PCI_CAP_LIST_NEXT, &next); 1211 if (ret) 1212 return ret; 1213 1214 if (cap <= PCI_CAP_ID_MAX) { 1215 len = pci_cap_length[cap]; 1216 if (len == 0xFF) { /* Variable length */ 1217 len = vfio_cap_len(vdev, cap, pos); 1218 if (len < 0) 1219 return len; 1220 } 1221 } 1222 1223 if (!len) { 1224 pr_info("%s: %s hiding cap 0x%x\n", 1225 __func__, dev_name(&pdev->dev), cap); 1226 *prev = next; 1227 pos = next; 1228 continue; 1229 } 1230 1231 /* Sanity check, do we overlap other capabilities? */ 1232 for (i = 0; i < len; i += 4) { 1233 if (likely(map[(pos + i) / 4] == PCI_CAP_ID_INVALID)) 1234 continue; 1235 1236 pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n", 1237 __func__, dev_name(&pdev->dev), 1238 pos + i, map[pos + i], cap); 1239 } 1240 1241 memset(map + (pos / 4), cap, len / 4); 1242 ret = vfio_fill_vconfig_bytes(vdev, pos, len); 1243 if (ret) 1244 return ret; 1245 1246 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT]; 1247 pos = next; 1248 caps++; 1249 } 1250 1251 /* If we didn't fill any capabilities, clear the status flag */ 1252 if (!caps) { 1253 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS]; 1254 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST); 1255 } 1256 1257 return 0; 1258 } 1259 1260 static int vfio_ecap_init(struct vfio_pci_device *vdev) 1261 { 1262 struct pci_dev *pdev = vdev->pdev; 1263 u8 *map = vdev->pci_config_map; 1264 u16 epos; 1265 __le32 *prev = NULL; 1266 int loops, ret, ecaps = 0; 1267 1268 if (!vdev->extended_caps) 1269 return 0; 1270 1271 epos = PCI_CFG_SPACE_SIZE; 1272 1273 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF; 1274 1275 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) { 1276 u32 header; 1277 u16 ecap; 1278 int i, len = 0; 1279 bool hidden = false; 1280 1281 ret = pci_read_config_dword(pdev, epos, &header); 1282 if (ret) 1283 return ret; 1284 1285 ecap = PCI_EXT_CAP_ID(header); 1286 1287 if (ecap <= PCI_EXT_CAP_ID_MAX) { 1288 len = pci_ext_cap_length[ecap]; 1289 if (len == 0xFF) { 1290 len = vfio_ext_cap_len(vdev, ecap, epos); 1291 if (len < 0) 1292 return ret; 1293 } 1294 } 1295 1296 if (!len) { 1297 pr_info("%s: %s hiding ecap 0x%x@0x%x\n", 1298 __func__, dev_name(&pdev->dev), ecap, epos); 1299 1300 /* If not the first in the chain, we can skip over it */ 1301 if (prev) { 1302 u32 val = epos = PCI_EXT_CAP_NEXT(header); 1303 *prev &= cpu_to_le32(~(0xffcU << 20)); 1304 *prev |= cpu_to_le32(val << 20); 1305 continue; 1306 } 1307 1308 /* 1309 * Otherwise, fill in a placeholder, the direct 1310 * readfn will virtualize this automatically 1311 */ 1312 len = PCI_CAP_SIZEOF; 1313 hidden = true; 1314 } 1315 1316 for (i = 0; i < len; i += 4) { 1317 if (likely(map[(epos + i) / 4] == PCI_CAP_ID_INVALID)) 1318 continue; 1319 1320 pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n", 1321 __func__, dev_name(&pdev->dev), 1322 epos + i, map[epos + i], ecap); 1323 } 1324 1325 /* 1326 * Even though ecap is 2 bytes, we're currently a long way 1327 * from exceeding 1 byte capabilities. If we ever make it 1328 * up to 0xFF we'll need to up this to a two-byte, byte map. 1329 */ 1330 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID); 1331 1332 memset(map + (epos / 4), ecap, len / 4); 1333 ret = vfio_fill_vconfig_bytes(vdev, epos, len); 1334 if (ret) 1335 return ret; 1336 1337 /* 1338 * If we're just using this capability to anchor the list, 1339 * hide the real ID. Only count real ecaps. XXX PCI spec 1340 * indicates to use cap id = 0, version = 0, next = 0 if 1341 * ecaps are absent, hope users check all the way to next. 1342 */ 1343 if (hidden) 1344 *(__le32 *)&vdev->vconfig[epos] &= 1345 cpu_to_le32((0xffcU << 20)); 1346 else 1347 ecaps++; 1348 1349 prev = (__le32 *)&vdev->vconfig[epos]; 1350 epos = PCI_EXT_CAP_NEXT(header); 1351 } 1352 1353 if (!ecaps) 1354 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0; 1355 1356 return 0; 1357 } 1358 1359 /* 1360 * For each device we allocate a pci_config_map that indicates the 1361 * capability occupying each dword and thus the struct perm_bits we 1362 * use for read and write. We also allocate a virtualized config 1363 * space which tracks reads and writes to bits that we emulate for 1364 * the user. Initial values filled from device. 1365 * 1366 * Using shared stuct perm_bits between all vfio-pci devices saves 1367 * us from allocating cfg_size buffers for virt and write for every 1368 * device. We could remove vconfig and allocate individual buffers 1369 * for each area requring emulated bits, but the array of pointers 1370 * would be comparable in size (at least for standard config space). 1371 */ 1372 int vfio_config_init(struct vfio_pci_device *vdev) 1373 { 1374 struct pci_dev *pdev = vdev->pdev; 1375 u8 *map, *vconfig; 1376 int ret; 1377 1378 /* 1379 * Config space, caps and ecaps are all dword aligned, so we can 1380 * use one byte per dword to record the type. 1381 */ 1382 map = kmalloc(pdev->cfg_size / 4, GFP_KERNEL); 1383 if (!map) 1384 return -ENOMEM; 1385 1386 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL); 1387 if (!vconfig) { 1388 kfree(map); 1389 return -ENOMEM; 1390 } 1391 1392 vdev->pci_config_map = map; 1393 vdev->vconfig = vconfig; 1394 1395 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF / 4); 1396 memset(map + (PCI_STD_HEADER_SIZEOF / 4), PCI_CAP_ID_INVALID, 1397 (pdev->cfg_size - PCI_STD_HEADER_SIZEOF) / 4); 1398 1399 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF); 1400 if (ret) 1401 goto out; 1402 1403 vdev->bardirty = true; 1404 1405 /* 1406 * XXX can we just pci_load_saved_state/pci_restore_state? 1407 * may need to rebuild vconfig after that 1408 */ 1409 1410 /* For restore after reset */ 1411 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]); 1412 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]); 1413 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]); 1414 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]); 1415 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]); 1416 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]); 1417 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]); 1418 1419 if (pdev->is_virtfn) { 1420 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor); 1421 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device); 1422 } 1423 1424 ret = vfio_cap_init(vdev); 1425 if (ret) 1426 goto out; 1427 1428 ret = vfio_ecap_init(vdev); 1429 if (ret) 1430 goto out; 1431 1432 return 0; 1433 1434 out: 1435 kfree(map); 1436 vdev->pci_config_map = NULL; 1437 kfree(vconfig); 1438 vdev->vconfig = NULL; 1439 return pcibios_err_to_errno(ret); 1440 } 1441 1442 void vfio_config_free(struct vfio_pci_device *vdev) 1443 { 1444 kfree(vdev->vconfig); 1445 vdev->vconfig = NULL; 1446 kfree(vdev->pci_config_map); 1447 vdev->pci_config_map = NULL; 1448 kfree(vdev->msi_perm); 1449 vdev->msi_perm = NULL; 1450 } 1451 1452 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf, 1453 size_t count, loff_t *ppos, bool iswrite) 1454 { 1455 struct pci_dev *pdev = vdev->pdev; 1456 struct perm_bits *perm; 1457 __le32 val = 0; 1458 int cap_start = 0, offset; 1459 u8 cap_id; 1460 ssize_t ret = count; 1461 1462 if (*ppos < 0 || *ppos + count > pdev->cfg_size) 1463 return -EFAULT; 1464 1465 /* 1466 * gcc can't seem to figure out we're a static function, only called 1467 * with count of 1/2/4 and hits copy_from_user_overflow without this. 1468 */ 1469 if (count > sizeof(val)) 1470 return -EINVAL; 1471 1472 cap_id = vdev->pci_config_map[*ppos / 4]; 1473 1474 if (cap_id == PCI_CAP_ID_INVALID) { 1475 if (iswrite) 1476 return ret; /* drop */ 1477 1478 /* 1479 * Per PCI spec 3.0, section 6.1, reads from reserved and 1480 * unimplemented registers return 0 1481 */ 1482 if (copy_to_user(buf, &val, count)) 1483 return -EFAULT; 1484 1485 return ret; 1486 } 1487 1488 /* 1489 * All capabilities are minimum 4 bytes and aligned on dword 1490 * boundaries. Since we don't support unaligned accesses, we're 1491 * only ever accessing a single capability. 1492 */ 1493 if (*ppos >= PCI_CFG_SPACE_SIZE) { 1494 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX); 1495 1496 perm = &ecap_perms[cap_id]; 1497 cap_start = vfio_find_cap_start(vdev, *ppos); 1498 1499 } else { 1500 WARN_ON(cap_id > PCI_CAP_ID_MAX); 1501 1502 perm = &cap_perms[cap_id]; 1503 1504 if (cap_id == PCI_CAP_ID_MSI) 1505 perm = vdev->msi_perm; 1506 1507 if (cap_id > PCI_CAP_ID_BASIC) 1508 cap_start = vfio_find_cap_start(vdev, *ppos); 1509 } 1510 1511 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC); 1512 WARN_ON(cap_start > *ppos); 1513 1514 offset = *ppos - cap_start; 1515 1516 if (iswrite) { 1517 if (!perm->writefn) 1518 return ret; 1519 1520 if (copy_from_user(&val, buf, count)) 1521 return -EFAULT; 1522 1523 ret = perm->writefn(vdev, *ppos, count, perm, offset, val); 1524 } else { 1525 if (perm->readfn) { 1526 ret = perm->readfn(vdev, *ppos, count, 1527 perm, offset, &val); 1528 if (ret < 0) 1529 return ret; 1530 } 1531 1532 if (copy_to_user(buf, &val, count)) 1533 return -EFAULT; 1534 } 1535 1536 return ret; 1537 } 1538 1539 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf, 1540 size_t count, loff_t *ppos, bool iswrite) 1541 { 1542 size_t done = 0; 1543 int ret = 0; 1544 loff_t pos = *ppos; 1545 1546 pos &= VFIO_PCI_OFFSET_MASK; 1547 1548 /* 1549 * We want to both keep the access size the caller users as well as 1550 * support reading large chunks of config space in a single call. 1551 * PCI doesn't support unaligned accesses, so we can safely break 1552 * those apart. 1553 */ 1554 while (count) { 1555 if (count >= 4 && !(pos % 4)) 1556 ret = vfio_config_do_rw(vdev, buf, 4, &pos, iswrite); 1557 else if (count >= 2 && !(pos % 2)) 1558 ret = vfio_config_do_rw(vdev, buf, 2, &pos, iswrite); 1559 else 1560 ret = vfio_config_do_rw(vdev, buf, 1, &pos, iswrite); 1561 1562 if (ret < 0) 1563 return ret; 1564 1565 count -= ret; 1566 done += ret; 1567 buf += ret; 1568 pos += ret; 1569 } 1570 1571 *ppos += done; 1572 1573 return done; 1574 } 1575