1 /*
2  * VFIO PCI config space virtualization
3  *
4  * Copyright (C) 2012 Red Hat, Inc.  All rights reserved.
5  *     Author: Alex Williamson <alex.williamson@redhat.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  * Derived from original vfio:
12  * Copyright 2010 Cisco Systems, Inc.  All rights reserved.
13  * Author: Tom Lyon, pugs@cisco.com
14  */
15 
16 /*
17  * This code handles reading and writing of PCI configuration registers.
18  * This is hairy because we want to allow a lot of flexibility to the
19  * user driver, but cannot trust it with all of the config fields.
20  * Tables determine which fields can be read and written, as well as
21  * which fields are 'virtualized' - special actions and translations to
22  * make it appear to the user that he has control, when in fact things
23  * must be negotiated with the underlying OS.
24  */
25 
26 #include <linux/fs.h>
27 #include <linux/pci.h>
28 #include <linux/uaccess.h>
29 #include <linux/vfio.h>
30 #include <linux/slab.h>
31 
32 #include "vfio_pci_private.h"
33 
34 /* Fake capability ID for standard config space */
35 #define PCI_CAP_ID_BASIC	0
36 
37 #define is_bar(offset)	\
38 	((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
39 	 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
40 
41 /*
42  * Lengths of PCI Config Capabilities
43  *   0: Removed from the user visible capability list
44  *   FF: Variable length
45  */
46 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = {
47 	[PCI_CAP_ID_BASIC]	= PCI_STD_HEADER_SIZEOF, /* pci config header */
48 	[PCI_CAP_ID_PM]		= PCI_PM_SIZEOF,
49 	[PCI_CAP_ID_AGP]	= PCI_AGP_SIZEOF,
50 	[PCI_CAP_ID_VPD]	= PCI_CAP_VPD_SIZEOF,
51 	[PCI_CAP_ID_SLOTID]	= 0,		/* bridge - don't care */
52 	[PCI_CAP_ID_MSI]	= 0xFF,		/* 10, 14, 20, or 24 */
53 	[PCI_CAP_ID_CHSWP]	= 0,		/* cpci - not yet */
54 	[PCI_CAP_ID_PCIX]	= 0xFF,		/* 8 or 24 */
55 	[PCI_CAP_ID_HT]		= 0xFF,		/* hypertransport */
56 	[PCI_CAP_ID_VNDR]	= 0xFF,		/* variable */
57 	[PCI_CAP_ID_DBG]	= 0,		/* debug - don't care */
58 	[PCI_CAP_ID_CCRC]	= 0,		/* cpci - not yet */
59 	[PCI_CAP_ID_SHPC]	= 0,		/* hotswap - not yet */
60 	[PCI_CAP_ID_SSVID]	= 0,		/* bridge - don't care */
61 	[PCI_CAP_ID_AGP3]	= 0,		/* AGP8x - not yet */
62 	[PCI_CAP_ID_SECDEV]	= 0,		/* secure device not yet */
63 	[PCI_CAP_ID_EXP]	= 0xFF,		/* 20 or 44 */
64 	[PCI_CAP_ID_MSIX]	= PCI_CAP_MSIX_SIZEOF,
65 	[PCI_CAP_ID_SATA]	= 0xFF,
66 	[PCI_CAP_ID_AF]		= PCI_CAP_AF_SIZEOF,
67 };
68 
69 /*
70  * Lengths of PCIe/PCI-X Extended Config Capabilities
71  *   0: Removed or masked from the user visible capability list
72  *   FF: Variable length
73  */
74 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = {
75 	[PCI_EXT_CAP_ID_ERR]	=	PCI_ERR_ROOT_COMMAND,
76 	[PCI_EXT_CAP_ID_VC]	=	0xFF,
77 	[PCI_EXT_CAP_ID_DSN]	=	PCI_EXT_CAP_DSN_SIZEOF,
78 	[PCI_EXT_CAP_ID_PWR]	=	PCI_EXT_CAP_PWR_SIZEOF,
79 	[PCI_EXT_CAP_ID_RCLD]	=	0,	/* root only - don't care */
80 	[PCI_EXT_CAP_ID_RCILC]	=	0,	/* root only - don't care */
81 	[PCI_EXT_CAP_ID_RCEC]	=	0,	/* root only - don't care */
82 	[PCI_EXT_CAP_ID_MFVC]	=	0xFF,
83 	[PCI_EXT_CAP_ID_VC9]	=	0xFF,	/* same as CAP_ID_VC */
84 	[PCI_EXT_CAP_ID_RCRB]	=	0,	/* root only - don't care */
85 	[PCI_EXT_CAP_ID_VNDR]	=	0xFF,
86 	[PCI_EXT_CAP_ID_CAC]	=	0,	/* obsolete */
87 	[PCI_EXT_CAP_ID_ACS]	=	0xFF,
88 	[PCI_EXT_CAP_ID_ARI]	=	PCI_EXT_CAP_ARI_SIZEOF,
89 	[PCI_EXT_CAP_ID_ATS]	=	PCI_EXT_CAP_ATS_SIZEOF,
90 	[PCI_EXT_CAP_ID_SRIOV]	=	PCI_EXT_CAP_SRIOV_SIZEOF,
91 	[PCI_EXT_CAP_ID_MRIOV]	=	0,	/* not yet */
92 	[PCI_EXT_CAP_ID_MCAST]	=	PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF,
93 	[PCI_EXT_CAP_ID_PRI]	=	PCI_EXT_CAP_PRI_SIZEOF,
94 	[PCI_EXT_CAP_ID_AMD_XXX] =	0,	/* not yet */
95 	[PCI_EXT_CAP_ID_REBAR]	=	0xFF,
96 	[PCI_EXT_CAP_ID_DPA]	=	0xFF,
97 	[PCI_EXT_CAP_ID_TPH]	=	0xFF,
98 	[PCI_EXT_CAP_ID_LTR]	=	PCI_EXT_CAP_LTR_SIZEOF,
99 	[PCI_EXT_CAP_ID_SECPCI]	=	0,	/* not yet */
100 	[PCI_EXT_CAP_ID_PMUX]	=	0,	/* not yet */
101 	[PCI_EXT_CAP_ID_PASID]	=	0,	/* not yet */
102 };
103 
104 /*
105  * Read/Write Permission Bits - one bit for each bit in capability
106  * Any field can be read if it exists, but what is read depends on
107  * whether the field is 'virtualized', or just pass thru to the
108  * hardware.  Any virtualized field is also virtualized for writes.
109  * Writes are only permitted if they have a 1 bit here.
110  */
111 struct perm_bits {
112 	u8	*virt;		/* read/write virtual data, not hw */
113 	u8	*write;		/* writeable bits */
114 	int	(*readfn)(struct vfio_pci_device *vdev, int pos, int count,
115 			  struct perm_bits *perm, int offset, __le32 *val);
116 	int	(*writefn)(struct vfio_pci_device *vdev, int pos, int count,
117 			   struct perm_bits *perm, int offset, __le32 val);
118 };
119 
120 #define	NO_VIRT		0
121 #define	ALL_VIRT	0xFFFFFFFFU
122 #define	NO_WRITE	0
123 #define	ALL_WRITE	0xFFFFFFFFU
124 
125 static int vfio_user_config_read(struct pci_dev *pdev, int offset,
126 				 __le32 *val, int count)
127 {
128 	int ret = -EINVAL;
129 	u32 tmp_val = 0;
130 
131 	switch (count) {
132 	case 1:
133 	{
134 		u8 tmp;
135 		ret = pci_user_read_config_byte(pdev, offset, &tmp);
136 		tmp_val = tmp;
137 		break;
138 	}
139 	case 2:
140 	{
141 		u16 tmp;
142 		ret = pci_user_read_config_word(pdev, offset, &tmp);
143 		tmp_val = tmp;
144 		break;
145 	}
146 	case 4:
147 		ret = pci_user_read_config_dword(pdev, offset, &tmp_val);
148 		break;
149 	}
150 
151 	*val = cpu_to_le32(tmp_val);
152 
153 	return ret;
154 }
155 
156 static int vfio_user_config_write(struct pci_dev *pdev, int offset,
157 				  __le32 val, int count)
158 {
159 	int ret = -EINVAL;
160 	u32 tmp_val = le32_to_cpu(val);
161 
162 	switch (count) {
163 	case 1:
164 		ret = pci_user_write_config_byte(pdev, offset, tmp_val);
165 		break;
166 	case 2:
167 		ret = pci_user_write_config_word(pdev, offset, tmp_val);
168 		break;
169 	case 4:
170 		ret = pci_user_write_config_dword(pdev, offset, tmp_val);
171 		break;
172 	}
173 
174 	return ret;
175 }
176 
177 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos,
178 				    int count, struct perm_bits *perm,
179 				    int offset, __le32 *val)
180 {
181 	__le32 virt = 0;
182 
183 	memcpy(val, vdev->vconfig + pos, count);
184 
185 	memcpy(&virt, perm->virt + offset, count);
186 
187 	/* Any non-virtualized bits? */
188 	if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) {
189 		struct pci_dev *pdev = vdev->pdev;
190 		__le32 phys_val = 0;
191 		int ret;
192 
193 		ret = vfio_user_config_read(pdev, pos, &phys_val, count);
194 		if (ret)
195 			return ret;
196 
197 		*val = (phys_val & ~virt) | (*val & virt);
198 	}
199 
200 	return count;
201 }
202 
203 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos,
204 				     int count, struct perm_bits *perm,
205 				     int offset, __le32 val)
206 {
207 	__le32 virt = 0, write = 0;
208 
209 	memcpy(&write, perm->write + offset, count);
210 
211 	if (!write)
212 		return count; /* drop, no writable bits */
213 
214 	memcpy(&virt, perm->virt + offset, count);
215 
216 	/* Virtualized and writable bits go to vconfig */
217 	if (write & virt) {
218 		__le32 virt_val = 0;
219 
220 		memcpy(&virt_val, vdev->vconfig + pos, count);
221 
222 		virt_val &= ~(write & virt);
223 		virt_val |= (val & (write & virt));
224 
225 		memcpy(vdev->vconfig + pos, &virt_val, count);
226 	}
227 
228 	/* Non-virtualzed and writable bits go to hardware */
229 	if (write & ~virt) {
230 		struct pci_dev *pdev = vdev->pdev;
231 		__le32 phys_val = 0;
232 		int ret;
233 
234 		ret = vfio_user_config_read(pdev, pos, &phys_val, count);
235 		if (ret)
236 			return ret;
237 
238 		phys_val &= ~(write & ~virt);
239 		phys_val |= (val & (write & ~virt));
240 
241 		ret = vfio_user_config_write(pdev, pos, phys_val, count);
242 		if (ret)
243 			return ret;
244 	}
245 
246 	return count;
247 }
248 
249 /* Allow direct read from hardware, except for capability next pointer */
250 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos,
251 				   int count, struct perm_bits *perm,
252 				   int offset, __le32 *val)
253 {
254 	int ret;
255 
256 	ret = vfio_user_config_read(vdev->pdev, pos, val, count);
257 	if (ret)
258 		return ret;
259 
260 	if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */
261 		if (offset < 4)
262 			memcpy(val, vdev->vconfig + pos, count);
263 	} else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */
264 		if (offset == PCI_CAP_LIST_ID && count > 1)
265 			memcpy(val, vdev->vconfig + pos,
266 			       min(PCI_CAP_FLAGS, count));
267 		else if (offset == PCI_CAP_LIST_NEXT)
268 			memcpy(val, vdev->vconfig + pos, 1);
269 	}
270 
271 	return count;
272 }
273 
274 /* Raw access skips any kind of virtualization */
275 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos,
276 				 int count, struct perm_bits *perm,
277 				 int offset, __le32 val)
278 {
279 	int ret;
280 
281 	ret = vfio_user_config_write(vdev->pdev, pos, val, count);
282 	if (ret)
283 		return ret;
284 
285 	return count;
286 }
287 
288 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos,
289 				int count, struct perm_bits *perm,
290 				int offset, __le32 *val)
291 {
292 	int ret;
293 
294 	ret = vfio_user_config_read(vdev->pdev, pos, val, count);
295 	if (ret)
296 		return ret;
297 
298 	return count;
299 }
300 
301 /* Virt access uses only virtualization */
302 static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos,
303 				  int count, struct perm_bits *perm,
304 				  int offset, __le32 val)
305 {
306 	memcpy(vdev->vconfig + pos, &val, count);
307 	return count;
308 }
309 
310 static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos,
311 				 int count, struct perm_bits *perm,
312 				 int offset, __le32 *val)
313 {
314 	memcpy(val, vdev->vconfig + pos, count);
315 	return count;
316 }
317 
318 /* Default capability regions to read-only, no-virtualization */
319 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = {
320 	[0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
321 };
322 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = {
323 	[0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read }
324 };
325 /*
326  * Default unassigned regions to raw read-write access.  Some devices
327  * require this to function as they hide registers between the gaps in
328  * config space (be2net).  Like MMIO and I/O port registers, we have
329  * to trust the hardware isolation.
330  */
331 static struct perm_bits unassigned_perms = {
332 	.readfn = vfio_raw_config_read,
333 	.writefn = vfio_raw_config_write
334 };
335 
336 static struct perm_bits virt_perms = {
337 	.readfn = vfio_virt_config_read,
338 	.writefn = vfio_virt_config_write
339 };
340 
341 static void free_perm_bits(struct perm_bits *perm)
342 {
343 	kfree(perm->virt);
344 	kfree(perm->write);
345 	perm->virt = NULL;
346 	perm->write = NULL;
347 }
348 
349 static int alloc_perm_bits(struct perm_bits *perm, int size)
350 {
351 	/*
352 	 * Round up all permission bits to the next dword, this lets us
353 	 * ignore whether a read/write exceeds the defined capability
354 	 * structure.  We can do this because:
355 	 *  - Standard config space is already dword aligned
356 	 *  - Capabilities are all dword aligned (bits 0:1 of next reserved)
357 	 *  - Express capabilities defined as dword aligned
358 	 */
359 	size = round_up(size, 4);
360 
361 	/*
362 	 * Zero state is
363 	 * - All Readable, None Writeable, None Virtualized
364 	 */
365 	perm->virt = kzalloc(size, GFP_KERNEL);
366 	perm->write = kzalloc(size, GFP_KERNEL);
367 	if (!perm->virt || !perm->write) {
368 		free_perm_bits(perm);
369 		return -ENOMEM;
370 	}
371 
372 	perm->readfn = vfio_default_config_read;
373 	perm->writefn = vfio_default_config_write;
374 
375 	return 0;
376 }
377 
378 /*
379  * Helper functions for filling in permission tables
380  */
381 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write)
382 {
383 	p->virt[off] = virt;
384 	p->write[off] = write;
385 }
386 
387 /* Handle endian-ness - pci and tables are little-endian */
388 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write)
389 {
390 	*(__le16 *)(&p->virt[off]) = cpu_to_le16(virt);
391 	*(__le16 *)(&p->write[off]) = cpu_to_le16(write);
392 }
393 
394 /* Handle endian-ness - pci and tables are little-endian */
395 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write)
396 {
397 	*(__le32 *)(&p->virt[off]) = cpu_to_le32(virt);
398 	*(__le32 *)(&p->write[off]) = cpu_to_le32(write);
399 }
400 
401 /*
402  * Restore the *real* BARs after we detect a FLR or backdoor reset.
403  * (backdoor = some device specific technique that we didn't catch)
404  */
405 static void vfio_bar_restore(struct vfio_pci_device *vdev)
406 {
407 	struct pci_dev *pdev = vdev->pdev;
408 	u32 *rbar = vdev->rbar;
409 	u16 cmd;
410 	int i;
411 
412 	if (pdev->is_virtfn)
413 		return;
414 
415 	pr_info("%s: %s reset recovery - restoring bars\n",
416 		__func__, dev_name(&pdev->dev));
417 
418 	for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++)
419 		pci_user_write_config_dword(pdev, i, *rbar);
420 
421 	pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
422 
423 	if (vdev->nointx) {
424 		pci_user_read_config_word(pdev, PCI_COMMAND, &cmd);
425 		cmd |= PCI_COMMAND_INTX_DISABLE;
426 		pci_user_write_config_word(pdev, PCI_COMMAND, cmd);
427 	}
428 }
429 
430 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
431 {
432 	unsigned long flags = pci_resource_flags(pdev, bar);
433 	u32 val;
434 
435 	if (flags & IORESOURCE_IO)
436 		return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO);
437 
438 	val = PCI_BASE_ADDRESS_SPACE_MEMORY;
439 
440 	if (flags & IORESOURCE_PREFETCH)
441 		val |= PCI_BASE_ADDRESS_MEM_PREFETCH;
442 
443 	if (flags & IORESOURCE_MEM_64)
444 		val |= PCI_BASE_ADDRESS_MEM_TYPE_64;
445 
446 	return cpu_to_le32(val);
447 }
448 
449 /*
450  * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
451  * to reflect the hardware capabilities.  This implements BAR sizing.
452  */
453 static void vfio_bar_fixup(struct vfio_pci_device *vdev)
454 {
455 	struct pci_dev *pdev = vdev->pdev;
456 	int i;
457 	__le32 *bar;
458 	u64 mask;
459 
460 	bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0];
461 
462 	for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) {
463 		if (!pci_resource_start(pdev, i)) {
464 			*bar = 0; /* Unmapped by host = unimplemented to user */
465 			continue;
466 		}
467 
468 		mask = ~(pci_resource_len(pdev, i) - 1);
469 
470 		*bar &= cpu_to_le32((u32)mask);
471 		*bar |= vfio_generate_bar_flags(pdev, i);
472 
473 		if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) {
474 			bar++;
475 			*bar &= cpu_to_le32((u32)(mask >> 32));
476 			i++;
477 		}
478 	}
479 
480 	bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS];
481 
482 	/*
483 	 * NB. REGION_INFO will have reported zero size if we weren't able
484 	 * to read the ROM, but we still return the actual BAR size here if
485 	 * it exists (or the shadow ROM space).
486 	 */
487 	if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) {
488 		mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1);
489 		mask |= PCI_ROM_ADDRESS_ENABLE;
490 		*bar &= cpu_to_le32((u32)mask);
491 	} else if (pdev->resource[PCI_ROM_RESOURCE].flags &
492 					IORESOURCE_ROM_SHADOW) {
493 		mask = ~(0x20000 - 1);
494 		mask |= PCI_ROM_ADDRESS_ENABLE;
495 		*bar &= cpu_to_le32((u32)mask);
496 	} else
497 		*bar = 0;
498 
499 	vdev->bardirty = false;
500 }
501 
502 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,
503 				  int count, struct perm_bits *perm,
504 				  int offset, __le32 *val)
505 {
506 	if (is_bar(offset)) /* pos == offset for basic config */
507 		vfio_bar_fixup(vdev);
508 
509 	count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
510 
511 	/* Mask in virtual memory enable for SR-IOV devices */
512 	if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) {
513 		u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]);
514 		u32 tmp_val = le32_to_cpu(*val);
515 
516 		tmp_val |= cmd & PCI_COMMAND_MEMORY;
517 		*val = cpu_to_le32(tmp_val);
518 	}
519 
520 	return count;
521 }
522 
523 /* Test whether BARs match the value we think they should contain */
524 static bool vfio_need_bar_restore(struct vfio_pci_device *vdev)
525 {
526 	int i = 0, pos = PCI_BASE_ADDRESS_0, ret;
527 	u32 bar;
528 
529 	for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) {
530 		if (vdev->rbar[i]) {
531 			ret = pci_user_read_config_dword(vdev->pdev, pos, &bar);
532 			if (ret || vdev->rbar[i] != bar)
533 				return true;
534 		}
535 	}
536 
537 	return false;
538 }
539 
540 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
541 				   int count, struct perm_bits *perm,
542 				   int offset, __le32 val)
543 {
544 	struct pci_dev *pdev = vdev->pdev;
545 	__le16 *virt_cmd;
546 	u16 new_cmd = 0;
547 	int ret;
548 
549 	virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND];
550 
551 	if (offset == PCI_COMMAND) {
552 		bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io;
553 		u16 phys_cmd;
554 
555 		ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd);
556 		if (ret)
557 			return ret;
558 
559 		new_cmd = le32_to_cpu(val);
560 
561 		phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY);
562 		virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY);
563 		new_mem = !!(new_cmd & PCI_COMMAND_MEMORY);
564 
565 		phys_io = !!(phys_cmd & PCI_COMMAND_IO);
566 		virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO);
567 		new_io = !!(new_cmd & PCI_COMMAND_IO);
568 
569 		/*
570 		 * If the user is writing mem/io enable (new_mem/io) and we
571 		 * think it's already enabled (virt_mem/io), but the hardware
572 		 * shows it disabled (phys_mem/io, then the device has
573 		 * undergone some kind of backdoor reset and needs to be
574 		 * restored before we allow it to enable the bars.
575 		 * SR-IOV devices will trigger this, but we catch them later
576 		 */
577 		if ((new_mem && virt_mem && !phys_mem) ||
578 		    (new_io && virt_io && !phys_io) ||
579 		    vfio_need_bar_restore(vdev))
580 			vfio_bar_restore(vdev);
581 	}
582 
583 	count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
584 	if (count < 0)
585 		return count;
586 
587 	/*
588 	 * Save current memory/io enable bits in vconfig to allow for
589 	 * the test above next time.
590 	 */
591 	if (offset == PCI_COMMAND) {
592 		u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
593 
594 		*virt_cmd &= cpu_to_le16(~mask);
595 		*virt_cmd |= cpu_to_le16(new_cmd & mask);
596 	}
597 
598 	/* Emulate INTx disable */
599 	if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) {
600 		bool virt_intx_disable;
601 
602 		virt_intx_disable = !!(le16_to_cpu(*virt_cmd) &
603 				       PCI_COMMAND_INTX_DISABLE);
604 
605 		if (virt_intx_disable && !vdev->virq_disabled) {
606 			vdev->virq_disabled = true;
607 			vfio_pci_intx_mask(vdev);
608 		} else if (!virt_intx_disable && vdev->virq_disabled) {
609 			vdev->virq_disabled = false;
610 			vfio_pci_intx_unmask(vdev);
611 		}
612 	}
613 
614 	if (is_bar(offset))
615 		vdev->bardirty = true;
616 
617 	return count;
618 }
619 
620 /* Permissions for the Basic PCI Header */
621 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
622 {
623 	if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
624 		return -ENOMEM;
625 
626 	perm->readfn = vfio_basic_config_read;
627 	perm->writefn = vfio_basic_config_write;
628 
629 	/* Virtualized for SR-IOV functions, which just have FFFF */
630 	p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
631 	p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
632 
633 	/*
634 	 * Virtualize INTx disable, we use it internally for interrupt
635 	 * control and can emulate it for non-PCI 2.3 devices.
636 	 */
637 	p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
638 
639 	/* Virtualize capability list, we might want to skip/disable */
640 	p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
641 
642 	/* No harm to write */
643 	p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
644 	p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
645 	p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
646 
647 	/* Virtualize all bars, can't touch the real ones */
648 	p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
649 	p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
650 	p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
651 	p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
652 	p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
653 	p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
654 	p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
655 
656 	/* Allow us to adjust capability chain */
657 	p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
658 
659 	/* Sometimes used by sw, just virtualize */
660 	p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
661 
662 	/* Virtualize interrupt pin to allow hiding INTx */
663 	p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
664 
665 	return 0;
666 }
667 
668 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos,
669 				int count, struct perm_bits *perm,
670 				int offset, __le32 val)
671 {
672 	count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
673 	if (count < 0)
674 		return count;
675 
676 	if (offset == PCI_PM_CTRL) {
677 		pci_power_t state;
678 
679 		switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) {
680 		case 0:
681 			state = PCI_D0;
682 			break;
683 		case 1:
684 			state = PCI_D1;
685 			break;
686 		case 2:
687 			state = PCI_D2;
688 			break;
689 		case 3:
690 			state = PCI_D3hot;
691 			break;
692 		}
693 
694 		pci_set_power_state(vdev->pdev, state);
695 	}
696 
697 	return count;
698 }
699 
700 /* Permissions for the Power Management capability */
701 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
702 {
703 	if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
704 		return -ENOMEM;
705 
706 	perm->writefn = vfio_pm_config_write;
707 
708 	/*
709 	 * We always virtualize the next field so we can remove
710 	 * capabilities from the chain if we want to.
711 	 */
712 	p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
713 
714 	/*
715 	 * Power management is defined *per function*, so we can let
716 	 * the user change power state, but we trap and initiate the
717 	 * change ourselves, so the state bits are read-only.
718 	 */
719 	p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);
720 	return 0;
721 }
722 
723 static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos,
724 				 int count, struct perm_bits *perm,
725 				 int offset, __le32 val)
726 {
727 	struct pci_dev *pdev = vdev->pdev;
728 	__le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR);
729 	__le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA);
730 	u16 addr;
731 	u32 data;
732 
733 	/*
734 	 * Write through to emulation.  If the write includes the upper byte
735 	 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we
736 	 * have work to do.
737 	 */
738 	count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
739 	if (count < 0 || offset > PCI_VPD_ADDR + 1 ||
740 	    offset + count <= PCI_VPD_ADDR + 1)
741 		return count;
742 
743 	addr = le16_to_cpu(*paddr);
744 
745 	if (addr & PCI_VPD_ADDR_F) {
746 		data = le32_to_cpu(*pdata);
747 		if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4)
748 			return count;
749 	} else {
750 		data = 0;
751 		if (pci_read_vpd(pdev, addr, 4, &data) < 0)
752 			return count;
753 		*pdata = cpu_to_le32(data);
754 	}
755 
756 	/*
757 	 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to
758 	 * signal completion.  If an error occurs above, we assume that not
759 	 * toggling this bit will induce a driver timeout.
760 	 */
761 	addr ^= PCI_VPD_ADDR_F;
762 	*paddr = cpu_to_le16(addr);
763 
764 	return count;
765 }
766 
767 /* Permissions for Vital Product Data capability */
768 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
769 {
770 	if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
771 		return -ENOMEM;
772 
773 	perm->writefn = vfio_vpd_config_write;
774 
775 	/*
776 	 * We always virtualize the next field so we can remove
777 	 * capabilities from the chain if we want to.
778 	 */
779 	p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
780 
781 	/*
782 	 * Both the address and data registers are virtualized to
783 	 * enable access through the pci_vpd_read/write functions
784 	 */
785 	p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
786 	p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
787 
788 	return 0;
789 }
790 
791 /* Permissions for PCI-X capability */
792 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
793 {
794 	/* Alloc 24, but only 8 are used in v0 */
795 	if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
796 		return -ENOMEM;
797 
798 	p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
799 
800 	p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
801 	p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
802 	return 0;
803 }
804 
805 static int vfio_exp_config_write(struct vfio_pci_device *vdev, int pos,
806 				 int count, struct perm_bits *perm,
807 				 int offset, __le32 val)
808 {
809 	__le16 *ctrl = (__le16 *)(vdev->vconfig + pos -
810 				  offset + PCI_EXP_DEVCTL);
811 
812 	count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
813 	if (count < 0)
814 		return count;
815 
816 	/*
817 	 * The FLR bit is virtualized, if set and the device supports PCIe
818 	 * FLR, issue a reset_function.  Regardless, clear the bit, the spec
819 	 * requires it to be always read as zero.  NB, reset_function might
820 	 * not use a PCIe FLR, we don't have that level of granularity.
821 	 */
822 	if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) {
823 		u32 cap;
824 		int ret;
825 
826 		*ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR);
827 
828 		ret = pci_user_read_config_dword(vdev->pdev,
829 						 pos - offset + PCI_EXP_DEVCAP,
830 						 &cap);
831 
832 		if (!ret && (cap & PCI_EXP_DEVCAP_FLR))
833 			pci_try_reset_function(vdev->pdev);
834 	}
835 
836 	return count;
837 }
838 
839 /* Permissions for PCI Express capability */
840 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
841 {
842 	/* Alloc largest of possible sizes */
843 	if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
844 		return -ENOMEM;
845 
846 	perm->writefn = vfio_exp_config_write;
847 
848 	p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
849 
850 	/*
851 	 * Allow writes to device control fields, except devctl_phantom,
852 	 * which could confuse IOMMU, and the ARI bit in devctl2, which
853 	 * is set at probe time.  FLR gets virtualized via our writefn.
854 	 */
855 	p_setw(perm, PCI_EXP_DEVCTL,
856 	       PCI_EXP_DEVCTL_BCR_FLR, ~PCI_EXP_DEVCTL_PHANTOM);
857 	p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
858 	return 0;
859 }
860 
861 static int vfio_af_config_write(struct vfio_pci_device *vdev, int pos,
862 				int count, struct perm_bits *perm,
863 				int offset, __le32 val)
864 {
865 	u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL;
866 
867 	count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
868 	if (count < 0)
869 		return count;
870 
871 	/*
872 	 * The FLR bit is virtualized, if set and the device supports AF
873 	 * FLR, issue a reset_function.  Regardless, clear the bit, the spec
874 	 * requires it to be always read as zero.  NB, reset_function might
875 	 * not use an AF FLR, we don't have that level of granularity.
876 	 */
877 	if (*ctrl & PCI_AF_CTRL_FLR) {
878 		u8 cap;
879 		int ret;
880 
881 		*ctrl &= ~PCI_AF_CTRL_FLR;
882 
883 		ret = pci_user_read_config_byte(vdev->pdev,
884 						pos - offset + PCI_AF_CAP,
885 						&cap);
886 
887 		if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP))
888 			pci_try_reset_function(vdev->pdev);
889 	}
890 
891 	return count;
892 }
893 
894 /* Permissions for Advanced Function capability */
895 static int __init init_pci_cap_af_perm(struct perm_bits *perm)
896 {
897 	if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
898 		return -ENOMEM;
899 
900 	perm->writefn = vfio_af_config_write;
901 
902 	p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
903 	p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
904 	return 0;
905 }
906 
907 /* Permissions for Advanced Error Reporting extended capability */
908 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
909 {
910 	u32 mask;
911 
912 	if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
913 		return -ENOMEM;
914 
915 	/*
916 	 * Virtualize the first dword of all express capabilities
917 	 * because it includes the next pointer.  This lets us later
918 	 * remove capabilities from the chain if we need to.
919 	 */
920 	p_setd(perm, 0, ALL_VIRT, NO_WRITE);
921 
922 	/* Writable bits mask */
923 	mask =	PCI_ERR_UNC_UND |		/* Undefined */
924 		PCI_ERR_UNC_DLP |		/* Data Link Protocol */
925 		PCI_ERR_UNC_SURPDN |		/* Surprise Down */
926 		PCI_ERR_UNC_POISON_TLP |	/* Poisoned TLP */
927 		PCI_ERR_UNC_FCP |		/* Flow Control Protocol */
928 		PCI_ERR_UNC_COMP_TIME |		/* Completion Timeout */
929 		PCI_ERR_UNC_COMP_ABORT |	/* Completer Abort */
930 		PCI_ERR_UNC_UNX_COMP |		/* Unexpected Completion */
931 		PCI_ERR_UNC_RX_OVER |		/* Receiver Overflow */
932 		PCI_ERR_UNC_MALF_TLP |		/* Malformed TLP */
933 		PCI_ERR_UNC_ECRC |		/* ECRC Error Status */
934 		PCI_ERR_UNC_UNSUP |		/* Unsupported Request */
935 		PCI_ERR_UNC_ACSV |		/* ACS Violation */
936 		PCI_ERR_UNC_INTN |		/* internal error */
937 		PCI_ERR_UNC_MCBTLP |		/* MC blocked TLP */
938 		PCI_ERR_UNC_ATOMEG |		/* Atomic egress blocked */
939 		PCI_ERR_UNC_TLPPRE;		/* TLP prefix blocked */
940 	p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
941 	p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
942 	p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
943 
944 	mask =	PCI_ERR_COR_RCVR |		/* Receiver Error Status */
945 		PCI_ERR_COR_BAD_TLP |		/* Bad TLP Status */
946 		PCI_ERR_COR_BAD_DLLP |		/* Bad DLLP Status */
947 		PCI_ERR_COR_REP_ROLL |		/* REPLAY_NUM Rollover */
948 		PCI_ERR_COR_REP_TIMER |		/* Replay Timer Timeout */
949 		PCI_ERR_COR_ADV_NFAT |		/* Advisory Non-Fatal */
950 		PCI_ERR_COR_INTERNAL |		/* Corrected Internal */
951 		PCI_ERR_COR_LOG_OVER;		/* Header Log Overflow */
952 	p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
953 	p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
954 
955 	mask =	PCI_ERR_CAP_ECRC_GENE |		/* ECRC Generation Enable */
956 		PCI_ERR_CAP_ECRC_CHKE;		/* ECRC Check Enable */
957 	p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
958 	return 0;
959 }
960 
961 /* Permissions for Power Budgeting extended capability */
962 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
963 {
964 	if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
965 		return -ENOMEM;
966 
967 	p_setd(perm, 0, ALL_VIRT, NO_WRITE);
968 
969 	/* Writing the data selector is OK, the info is still read-only */
970 	p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
971 	return 0;
972 }
973 
974 /*
975  * Initialize the shared permission tables
976  */
977 void vfio_pci_uninit_perm_bits(void)
978 {
979 	free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]);
980 
981 	free_perm_bits(&cap_perms[PCI_CAP_ID_PM]);
982 	free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]);
983 	free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]);
984 	free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]);
985 	free_perm_bits(&cap_perms[PCI_CAP_ID_AF]);
986 
987 	free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
988 	free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
989 }
990 
991 int __init vfio_pci_init_perm_bits(void)
992 {
993 	int ret;
994 
995 	/* Basic config space */
996 	ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]);
997 
998 	/* Capabilities */
999 	ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]);
1000 	ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]);
1001 	ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]);
1002 	cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1003 	ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]);
1004 	ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]);
1005 
1006 	/* Extended capabilities */
1007 	ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]);
1008 	ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]);
1009 	ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write;
1010 
1011 	if (ret)
1012 		vfio_pci_uninit_perm_bits();
1013 
1014 	return ret;
1015 }
1016 
1017 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos)
1018 {
1019 	u8 cap;
1020 	int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE :
1021 						 PCI_STD_HEADER_SIZEOF;
1022 	cap = vdev->pci_config_map[pos];
1023 
1024 	if (cap == PCI_CAP_ID_BASIC)
1025 		return 0;
1026 
1027 	/* XXX Can we have to abutting capabilities of the same type? */
1028 	while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap)
1029 		pos--;
1030 
1031 	return pos;
1032 }
1033 
1034 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos,
1035 				int count, struct perm_bits *perm,
1036 				int offset, __le32 *val)
1037 {
1038 	/* Update max available queue size from msi_qmax */
1039 	if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1040 		__le16 *flags;
1041 		int start;
1042 
1043 		start = vfio_find_cap_start(vdev, pos);
1044 
1045 		flags = (__le16 *)&vdev->vconfig[start];
1046 
1047 		*flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK);
1048 		*flags |= cpu_to_le16(vdev->msi_qmax << 1);
1049 	}
1050 
1051 	return vfio_default_config_read(vdev, pos, count, perm, offset, val);
1052 }
1053 
1054 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos,
1055 				 int count, struct perm_bits *perm,
1056 				 int offset, __le32 val)
1057 {
1058 	count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
1059 	if (count < 0)
1060 		return count;
1061 
1062 	/* Fixup and write configured queue size and enable to hardware */
1063 	if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) {
1064 		__le16 *pflags;
1065 		u16 flags;
1066 		int start, ret;
1067 
1068 		start = vfio_find_cap_start(vdev, pos);
1069 
1070 		pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS];
1071 
1072 		flags = le16_to_cpu(*pflags);
1073 
1074 		/* MSI is enabled via ioctl */
1075 		if  (!is_msi(vdev))
1076 			flags &= ~PCI_MSI_FLAGS_ENABLE;
1077 
1078 		/* Check queue size */
1079 		if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) {
1080 			flags &= ~PCI_MSI_FLAGS_QSIZE;
1081 			flags |= vdev->msi_qmax << 4;
1082 		}
1083 
1084 		/* Write back to virt and to hardware */
1085 		*pflags = cpu_to_le16(flags);
1086 		ret = pci_user_write_config_word(vdev->pdev,
1087 						 start + PCI_MSI_FLAGS,
1088 						 flags);
1089 		if (ret)
1090 			return ret;
1091 	}
1092 
1093 	return count;
1094 }
1095 
1096 /*
1097  * MSI determination is per-device, so this routine gets used beyond
1098  * initialization time. Don't add __init
1099  */
1100 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
1101 {
1102 	if (alloc_perm_bits(perm, len))
1103 		return -ENOMEM;
1104 
1105 	perm->readfn = vfio_msi_config_read;
1106 	perm->writefn = vfio_msi_config_write;
1107 
1108 	p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
1109 
1110 	/*
1111 	 * The upper byte of the control register is reserved,
1112 	 * just setup the lower byte.
1113 	 */
1114 	p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
1115 	p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
1116 	if (flags & PCI_MSI_FLAGS_64BIT) {
1117 		p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
1118 		p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
1119 		if (flags & PCI_MSI_FLAGS_MASKBIT) {
1120 			p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
1121 			p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
1122 		}
1123 	} else {
1124 		p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
1125 		if (flags & PCI_MSI_FLAGS_MASKBIT) {
1126 			p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
1127 			p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
1128 		}
1129 	}
1130 	return 0;
1131 }
1132 
1133 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
1134 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos)
1135 {
1136 	struct pci_dev *pdev = vdev->pdev;
1137 	int len, ret;
1138 	u16 flags;
1139 
1140 	ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags);
1141 	if (ret)
1142 		return pcibios_err_to_errno(ret);
1143 
1144 	len = 10; /* Minimum size */
1145 	if (flags & PCI_MSI_FLAGS_64BIT)
1146 		len += 4;
1147 	if (flags & PCI_MSI_FLAGS_MASKBIT)
1148 		len += 10;
1149 
1150 	if (vdev->msi_perm)
1151 		return len;
1152 
1153 	vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL);
1154 	if (!vdev->msi_perm)
1155 		return -ENOMEM;
1156 
1157 	ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags);
1158 	if (ret)
1159 		return ret;
1160 
1161 	return len;
1162 }
1163 
1164 /* Determine extended capability length for VC (2 & 9) and MFVC */
1165 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos)
1166 {
1167 	struct pci_dev *pdev = vdev->pdev;
1168 	u32 tmp;
1169 	int ret, evcc, phases, vc_arb;
1170 	int len = PCI_CAP_VC_BASE_SIZEOF;
1171 
1172 	ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp);
1173 	if (ret)
1174 		return pcibios_err_to_errno(ret);
1175 
1176 	evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */
1177 	ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp);
1178 	if (ret)
1179 		return pcibios_err_to_errno(ret);
1180 
1181 	if (tmp & PCI_VC_CAP2_128_PHASE)
1182 		phases = 128;
1183 	else if (tmp & PCI_VC_CAP2_64_PHASE)
1184 		phases = 64;
1185 	else if (tmp & PCI_VC_CAP2_32_PHASE)
1186 		phases = 32;
1187 	else
1188 		phases = 0;
1189 
1190 	vc_arb = phases * 4;
1191 
1192 	/*
1193 	 * Port arbitration tables are root & switch only;
1194 	 * function arbitration tables are function 0 only.
1195 	 * In either case, we'll never let user write them so
1196 	 * we don't care how big they are
1197 	 */
1198 	len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF;
1199 	if (vc_arb) {
1200 		len = round_up(len, 16);
1201 		len += vc_arb / 8;
1202 	}
1203 	return len;
1204 }
1205 
1206 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
1207 {
1208 	struct pci_dev *pdev = vdev->pdev;
1209 	u32 dword;
1210 	u16 word;
1211 	u8 byte;
1212 	int ret;
1213 
1214 	switch (cap) {
1215 	case PCI_CAP_ID_MSI:
1216 		return vfio_msi_cap_len(vdev, pos);
1217 	case PCI_CAP_ID_PCIX:
1218 		ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word);
1219 		if (ret)
1220 			return pcibios_err_to_errno(ret);
1221 
1222 		if (PCI_X_CMD_VERSION(word)) {
1223 			if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1224 				/* Test for extended capabilities */
1225 				pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE,
1226 						      &dword);
1227 				vdev->extended_caps = (dword != 0);
1228 			}
1229 			return PCI_CAP_PCIX_SIZEOF_V2;
1230 		} else
1231 			return PCI_CAP_PCIX_SIZEOF_V0;
1232 	case PCI_CAP_ID_VNDR:
1233 		/* length follows next field */
1234 		ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte);
1235 		if (ret)
1236 			return pcibios_err_to_errno(ret);
1237 
1238 		return byte;
1239 	case PCI_CAP_ID_EXP:
1240 		if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
1241 			/* Test for extended capabilities */
1242 			pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
1243 			vdev->extended_caps = (dword != 0);
1244 		}
1245 
1246 		/* length based on version and type */
1247 		if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) {
1248 			if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
1249 				return 0xc; /* "All Devices" only, no link */
1250 			return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1;
1251 		} else {
1252 			if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END)
1253 				return 0x2c; /* No link */
1254 			return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2;
1255 		}
1256 	case PCI_CAP_ID_HT:
1257 		ret = pci_read_config_byte(pdev, pos + 3, &byte);
1258 		if (ret)
1259 			return pcibios_err_to_errno(ret);
1260 
1261 		return (byte & HT_3BIT_CAP_MASK) ?
1262 			HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG;
1263 	case PCI_CAP_ID_SATA:
1264 		ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte);
1265 		if (ret)
1266 			return pcibios_err_to_errno(ret);
1267 
1268 		byte &= PCI_SATA_REGS_MASK;
1269 		if (byte == PCI_SATA_REGS_INLINE)
1270 			return PCI_SATA_SIZEOF_LONG;
1271 		else
1272 			return PCI_SATA_SIZEOF_SHORT;
1273 	default:
1274 		pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n",
1275 			dev_name(&pdev->dev), __func__, cap, pos);
1276 	}
1277 
1278 	return 0;
1279 }
1280 
1281 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos)
1282 {
1283 	struct pci_dev *pdev = vdev->pdev;
1284 	u8 byte;
1285 	u32 dword;
1286 	int ret;
1287 
1288 	switch (ecap) {
1289 	case PCI_EXT_CAP_ID_VNDR:
1290 		ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword);
1291 		if (ret)
1292 			return pcibios_err_to_errno(ret);
1293 
1294 		return dword >> PCI_VSEC_HDR_LEN_SHIFT;
1295 	case PCI_EXT_CAP_ID_VC:
1296 	case PCI_EXT_CAP_ID_VC9:
1297 	case PCI_EXT_CAP_ID_MFVC:
1298 		return vfio_vc_cap_len(vdev, epos);
1299 	case PCI_EXT_CAP_ID_ACS:
1300 		ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte);
1301 		if (ret)
1302 			return pcibios_err_to_errno(ret);
1303 
1304 		if (byte & PCI_ACS_EC) {
1305 			int bits;
1306 
1307 			ret = pci_read_config_byte(pdev,
1308 						   epos + PCI_ACS_EGRESS_BITS,
1309 						   &byte);
1310 			if (ret)
1311 				return pcibios_err_to_errno(ret);
1312 
1313 			bits = byte ? round_up(byte, 32) : 256;
1314 			return 8 + (bits / 8);
1315 		}
1316 		return 8;
1317 
1318 	case PCI_EXT_CAP_ID_REBAR:
1319 		ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte);
1320 		if (ret)
1321 			return pcibios_err_to_errno(ret);
1322 
1323 		byte &= PCI_REBAR_CTRL_NBAR_MASK;
1324 		byte >>= PCI_REBAR_CTRL_NBAR_SHIFT;
1325 
1326 		return 4 + (byte * 8);
1327 	case PCI_EXT_CAP_ID_DPA:
1328 		ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte);
1329 		if (ret)
1330 			return pcibios_err_to_errno(ret);
1331 
1332 		byte &= PCI_DPA_CAP_SUBSTATE_MASK;
1333 		return PCI_DPA_BASE_SIZEOF + byte + 1;
1334 	case PCI_EXT_CAP_ID_TPH:
1335 		ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword);
1336 		if (ret)
1337 			return pcibios_err_to_errno(ret);
1338 
1339 		if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) {
1340 			int sts;
1341 
1342 			sts = dword & PCI_TPH_CAP_ST_MASK;
1343 			sts >>= PCI_TPH_CAP_ST_SHIFT;
1344 			return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2;
1345 		}
1346 		return PCI_TPH_BASE_SIZEOF;
1347 	default:
1348 		pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n",
1349 			dev_name(&pdev->dev), __func__, ecap, epos);
1350 	}
1351 
1352 	return 0;
1353 }
1354 
1355 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev,
1356 				   int offset, int size)
1357 {
1358 	struct pci_dev *pdev = vdev->pdev;
1359 	int ret = 0;
1360 
1361 	/*
1362 	 * We try to read physical config space in the largest chunks
1363 	 * we can, assuming that all of the fields support dword access.
1364 	 * pci_save_state() makes this same assumption and seems to do ok.
1365 	 */
1366 	while (size) {
1367 		int filled;
1368 
1369 		if (size >= 4 && !(offset % 4)) {
1370 			__le32 *dwordp = (__le32 *)&vdev->vconfig[offset];
1371 			u32 dword;
1372 
1373 			ret = pci_read_config_dword(pdev, offset, &dword);
1374 			if (ret)
1375 				return ret;
1376 			*dwordp = cpu_to_le32(dword);
1377 			filled = 4;
1378 		} else if (size >= 2 && !(offset % 2)) {
1379 			__le16 *wordp = (__le16 *)&vdev->vconfig[offset];
1380 			u16 word;
1381 
1382 			ret = pci_read_config_word(pdev, offset, &word);
1383 			if (ret)
1384 				return ret;
1385 			*wordp = cpu_to_le16(word);
1386 			filled = 2;
1387 		} else {
1388 			u8 *byte = &vdev->vconfig[offset];
1389 			ret = pci_read_config_byte(pdev, offset, byte);
1390 			if (ret)
1391 				return ret;
1392 			filled = 1;
1393 		}
1394 
1395 		offset += filled;
1396 		size -= filled;
1397 	}
1398 
1399 	return ret;
1400 }
1401 
1402 static int vfio_cap_init(struct vfio_pci_device *vdev)
1403 {
1404 	struct pci_dev *pdev = vdev->pdev;
1405 	u8 *map = vdev->pci_config_map;
1406 	u16 status;
1407 	u8 pos, *prev, cap;
1408 	int loops, ret, caps = 0;
1409 
1410 	/* Any capabilities? */
1411 	ret = pci_read_config_word(pdev, PCI_STATUS, &status);
1412 	if (ret)
1413 		return ret;
1414 
1415 	if (!(status & PCI_STATUS_CAP_LIST))
1416 		return 0; /* Done */
1417 
1418 	ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
1419 	if (ret)
1420 		return ret;
1421 
1422 	/* Mark the previous position in case we want to skip a capability */
1423 	prev = &vdev->vconfig[PCI_CAPABILITY_LIST];
1424 
1425 	/* We can bound our loop, capabilities are dword aligned */
1426 	loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF;
1427 	while (pos && loops--) {
1428 		u8 next;
1429 		int i, len = 0;
1430 
1431 		ret = pci_read_config_byte(pdev, pos, &cap);
1432 		if (ret)
1433 			return ret;
1434 
1435 		ret = pci_read_config_byte(pdev,
1436 					   pos + PCI_CAP_LIST_NEXT, &next);
1437 		if (ret)
1438 			return ret;
1439 
1440 		if (cap <= PCI_CAP_ID_MAX) {
1441 			len = pci_cap_length[cap];
1442 			if (len == 0xFF) { /* Variable length */
1443 				len = vfio_cap_len(vdev, cap, pos);
1444 				if (len < 0)
1445 					return len;
1446 			}
1447 		}
1448 
1449 		if (!len) {
1450 			pr_info("%s: %s hiding cap 0x%x\n",
1451 				__func__, dev_name(&pdev->dev), cap);
1452 			*prev = next;
1453 			pos = next;
1454 			continue;
1455 		}
1456 
1457 		/* Sanity check, do we overlap other capabilities? */
1458 		for (i = 0; i < len; i++) {
1459 			if (likely(map[pos + i] == PCI_CAP_ID_INVALID))
1460 				continue;
1461 
1462 			pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n",
1463 				__func__, dev_name(&pdev->dev),
1464 				pos + i, map[pos + i], cap);
1465 		}
1466 
1467 		BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1468 
1469 		memset(map + pos, cap, len);
1470 		ret = vfio_fill_vconfig_bytes(vdev, pos, len);
1471 		if (ret)
1472 			return ret;
1473 
1474 		prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT];
1475 		pos = next;
1476 		caps++;
1477 	}
1478 
1479 	/* If we didn't fill any capabilities, clear the status flag */
1480 	if (!caps) {
1481 		__le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS];
1482 		*vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST);
1483 	}
1484 
1485 	return 0;
1486 }
1487 
1488 static int vfio_ecap_init(struct vfio_pci_device *vdev)
1489 {
1490 	struct pci_dev *pdev = vdev->pdev;
1491 	u8 *map = vdev->pci_config_map;
1492 	u16 epos;
1493 	__le32 *prev = NULL;
1494 	int loops, ret, ecaps = 0;
1495 
1496 	if (!vdev->extended_caps)
1497 		return 0;
1498 
1499 	epos = PCI_CFG_SPACE_SIZE;
1500 
1501 	loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF;
1502 
1503 	while (loops-- && epos >= PCI_CFG_SPACE_SIZE) {
1504 		u32 header;
1505 		u16 ecap;
1506 		int i, len = 0;
1507 		bool hidden = false;
1508 
1509 		ret = pci_read_config_dword(pdev, epos, &header);
1510 		if (ret)
1511 			return ret;
1512 
1513 		ecap = PCI_EXT_CAP_ID(header);
1514 
1515 		if (ecap <= PCI_EXT_CAP_ID_MAX) {
1516 			len = pci_ext_cap_length[ecap];
1517 			if (len == 0xFF) {
1518 				len = vfio_ext_cap_len(vdev, ecap, epos);
1519 				if (len < 0)
1520 					return ret;
1521 			}
1522 		}
1523 
1524 		if (!len) {
1525 			pr_info("%s: %s hiding ecap 0x%x@0x%x\n",
1526 				__func__, dev_name(&pdev->dev), ecap, epos);
1527 
1528 			/* If not the first in the chain, we can skip over it */
1529 			if (prev) {
1530 				u32 val = epos = PCI_EXT_CAP_NEXT(header);
1531 				*prev &= cpu_to_le32(~(0xffcU << 20));
1532 				*prev |= cpu_to_le32(val << 20);
1533 				continue;
1534 			}
1535 
1536 			/*
1537 			 * Otherwise, fill in a placeholder, the direct
1538 			 * readfn will virtualize this automatically
1539 			 */
1540 			len = PCI_CAP_SIZEOF;
1541 			hidden = true;
1542 		}
1543 
1544 		for (i = 0; i < len; i++) {
1545 			if (likely(map[epos + i] == PCI_CAP_ID_INVALID))
1546 				continue;
1547 
1548 			pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n",
1549 				__func__, dev_name(&pdev->dev),
1550 				epos + i, map[epos + i], ecap);
1551 		}
1552 
1553 		/*
1554 		 * Even though ecap is 2 bytes, we're currently a long way
1555 		 * from exceeding 1 byte capabilities.  If we ever make it
1556 		 * up to 0xFE we'll need to up this to a two-byte, byte map.
1557 		 */
1558 		BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT);
1559 
1560 		memset(map + epos, ecap, len);
1561 		ret = vfio_fill_vconfig_bytes(vdev, epos, len);
1562 		if (ret)
1563 			return ret;
1564 
1565 		/*
1566 		 * If we're just using this capability to anchor the list,
1567 		 * hide the real ID.  Only count real ecaps.  XXX PCI spec
1568 		 * indicates to use cap id = 0, version = 0, next = 0 if
1569 		 * ecaps are absent, hope users check all the way to next.
1570 		 */
1571 		if (hidden)
1572 			*(__le32 *)&vdev->vconfig[epos] &=
1573 				cpu_to_le32((0xffcU << 20));
1574 		else
1575 			ecaps++;
1576 
1577 		prev = (__le32 *)&vdev->vconfig[epos];
1578 		epos = PCI_EXT_CAP_NEXT(header);
1579 	}
1580 
1581 	if (!ecaps)
1582 		*(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0;
1583 
1584 	return 0;
1585 }
1586 
1587 /*
1588  * For each device we allocate a pci_config_map that indicates the
1589  * capability occupying each dword and thus the struct perm_bits we
1590  * use for read and write.  We also allocate a virtualized config
1591  * space which tracks reads and writes to bits that we emulate for
1592  * the user.  Initial values filled from device.
1593  *
1594  * Using shared struct perm_bits between all vfio-pci devices saves
1595  * us from allocating cfg_size buffers for virt and write for every
1596  * device.  We could remove vconfig and allocate individual buffers
1597  * for each area requiring emulated bits, but the array of pointers
1598  * would be comparable in size (at least for standard config space).
1599  */
1600 int vfio_config_init(struct vfio_pci_device *vdev)
1601 {
1602 	struct pci_dev *pdev = vdev->pdev;
1603 	u8 *map, *vconfig;
1604 	int ret;
1605 
1606 	/*
1607 	 * Config space, caps and ecaps are all dword aligned, so we could
1608 	 * use one byte per dword to record the type.  However, there are
1609 	 * no requiremenst on the length of a capability, so the gap between
1610 	 * capabilities needs byte granularity.
1611 	 */
1612 	map = kmalloc(pdev->cfg_size, GFP_KERNEL);
1613 	if (!map)
1614 		return -ENOMEM;
1615 
1616 	vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL);
1617 	if (!vconfig) {
1618 		kfree(map);
1619 		return -ENOMEM;
1620 	}
1621 
1622 	vdev->pci_config_map = map;
1623 	vdev->vconfig = vconfig;
1624 
1625 	memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF);
1626 	memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID,
1627 	       pdev->cfg_size - PCI_STD_HEADER_SIZEOF);
1628 
1629 	ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF);
1630 	if (ret)
1631 		goto out;
1632 
1633 	vdev->bardirty = true;
1634 
1635 	/*
1636 	 * XXX can we just pci_load_saved_state/pci_restore_state?
1637 	 * may need to rebuild vconfig after that
1638 	 */
1639 
1640 	/* For restore after reset */
1641 	vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]);
1642 	vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]);
1643 	vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]);
1644 	vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]);
1645 	vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]);
1646 	vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]);
1647 	vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]);
1648 
1649 	if (pdev->is_virtfn) {
1650 		*(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor);
1651 		*(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
1652 	}
1653 
1654 	if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
1655 		vconfig[PCI_INTERRUPT_PIN] = 0;
1656 
1657 	ret = vfio_cap_init(vdev);
1658 	if (ret)
1659 		goto out;
1660 
1661 	ret = vfio_ecap_init(vdev);
1662 	if (ret)
1663 		goto out;
1664 
1665 	return 0;
1666 
1667 out:
1668 	kfree(map);
1669 	vdev->pci_config_map = NULL;
1670 	kfree(vconfig);
1671 	vdev->vconfig = NULL;
1672 	return pcibios_err_to_errno(ret);
1673 }
1674 
1675 void vfio_config_free(struct vfio_pci_device *vdev)
1676 {
1677 	kfree(vdev->vconfig);
1678 	vdev->vconfig = NULL;
1679 	kfree(vdev->pci_config_map);
1680 	vdev->pci_config_map = NULL;
1681 	kfree(vdev->msi_perm);
1682 	vdev->msi_perm = NULL;
1683 }
1684 
1685 /*
1686  * Find the remaining number of bytes in a dword that match the given
1687  * position.  Stop at either the end of the capability or the dword boundary.
1688  */
1689 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev,
1690 					   loff_t pos)
1691 {
1692 	u8 cap = vdev->pci_config_map[pos];
1693 	size_t i;
1694 
1695 	for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++)
1696 		/* nop */;
1697 
1698 	return i;
1699 }
1700 
1701 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf,
1702 				 size_t count, loff_t *ppos, bool iswrite)
1703 {
1704 	struct pci_dev *pdev = vdev->pdev;
1705 	struct perm_bits *perm;
1706 	__le32 val = 0;
1707 	int cap_start = 0, offset;
1708 	u8 cap_id;
1709 	ssize_t ret;
1710 
1711 	if (*ppos < 0 || *ppos >= pdev->cfg_size ||
1712 	    *ppos + count > pdev->cfg_size)
1713 		return -EFAULT;
1714 
1715 	/*
1716 	 * Chop accesses into aligned chunks containing no more than a
1717 	 * single capability.  Caller increments to the next chunk.
1718 	 */
1719 	count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos));
1720 	if (count >= 4 && !(*ppos % 4))
1721 		count = 4;
1722 	else if (count >= 2 && !(*ppos % 2))
1723 		count = 2;
1724 	else
1725 		count = 1;
1726 
1727 	ret = count;
1728 
1729 	cap_id = vdev->pci_config_map[*ppos];
1730 
1731 	if (cap_id == PCI_CAP_ID_INVALID) {
1732 		perm = &unassigned_perms;
1733 		cap_start = *ppos;
1734 	} else if (cap_id == PCI_CAP_ID_INVALID_VIRT) {
1735 		perm = &virt_perms;
1736 		cap_start = *ppos;
1737 	} else {
1738 		if (*ppos >= PCI_CFG_SPACE_SIZE) {
1739 			WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX);
1740 
1741 			perm = &ecap_perms[cap_id];
1742 			cap_start = vfio_find_cap_start(vdev, *ppos);
1743 		} else {
1744 			WARN_ON(cap_id > PCI_CAP_ID_MAX);
1745 
1746 			perm = &cap_perms[cap_id];
1747 
1748 			if (cap_id == PCI_CAP_ID_MSI)
1749 				perm = vdev->msi_perm;
1750 
1751 			if (cap_id > PCI_CAP_ID_BASIC)
1752 				cap_start = vfio_find_cap_start(vdev, *ppos);
1753 		}
1754 	}
1755 
1756 	WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC);
1757 	WARN_ON(cap_start > *ppos);
1758 
1759 	offset = *ppos - cap_start;
1760 
1761 	if (iswrite) {
1762 		if (!perm->writefn)
1763 			return ret;
1764 
1765 		if (copy_from_user(&val, buf, count))
1766 			return -EFAULT;
1767 
1768 		ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1769 	} else {
1770 		if (perm->readfn) {
1771 			ret = perm->readfn(vdev, *ppos, count,
1772 					   perm, offset, &val);
1773 			if (ret < 0)
1774 				return ret;
1775 		}
1776 
1777 		if (copy_to_user(buf, &val, count))
1778 			return -EFAULT;
1779 	}
1780 
1781 	return ret;
1782 }
1783 
1784 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf,
1785 			   size_t count, loff_t *ppos, bool iswrite)
1786 {
1787 	size_t done = 0;
1788 	int ret = 0;
1789 	loff_t pos = *ppos;
1790 
1791 	pos &= VFIO_PCI_OFFSET_MASK;
1792 
1793 	while (count) {
1794 		ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite);
1795 		if (ret < 0)
1796 			return ret;
1797 
1798 		count -= ret;
1799 		done += ret;
1800 		buf += ret;
1801 		pos += ret;
1802 	}
1803 
1804 	*ppos += done;
1805 
1806 	return done;
1807 }
1808