1 /* 2 * VFIO PCI config space virtualization 3 * 4 * Copyright (C) 2012 Red Hat, Inc. All rights reserved. 5 * Author: Alex Williamson <alex.williamson@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Derived from original vfio: 12 * Copyright 2010 Cisco Systems, Inc. All rights reserved. 13 * Author: Tom Lyon, pugs@cisco.com 14 */ 15 16 /* 17 * This code handles reading and writing of PCI configuration registers. 18 * This is hairy because we want to allow a lot of flexibility to the 19 * user driver, but cannot trust it with all of the config fields. 20 * Tables determine which fields can be read and written, as well as 21 * which fields are 'virtualized' - special actions and translations to 22 * make it appear to the user that he has control, when in fact things 23 * must be negotiated with the underlying OS. 24 */ 25 26 #include <linux/fs.h> 27 #include <linux/pci.h> 28 #include <linux/uaccess.h> 29 #include <linux/vfio.h> 30 #include <linux/slab.h> 31 32 #include "vfio_pci_private.h" 33 34 #define PCI_CFG_SPACE_SIZE 256 35 36 /* Fake capability ID for standard config space */ 37 #define PCI_CAP_ID_BASIC 0 38 39 #define is_bar(offset) \ 40 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \ 41 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4)) 42 43 /* 44 * Lengths of PCI Config Capabilities 45 * 0: Removed from the user visible capability list 46 * FF: Variable length 47 */ 48 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = { 49 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */ 50 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF, 51 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF, 52 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF, 53 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */ 54 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */ 55 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */ 56 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */ 57 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */ 58 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */ 59 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */ 60 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */ 61 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */ 62 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */ 63 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */ 64 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */ 65 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */ 66 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF, 67 [PCI_CAP_ID_SATA] = 0xFF, 68 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF, 69 }; 70 71 /* 72 * Lengths of PCIe/PCI-X Extended Config Capabilities 73 * 0: Removed or masked from the user visible capabilty list 74 * FF: Variable length 75 */ 76 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = { 77 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND, 78 [PCI_EXT_CAP_ID_VC] = 0xFF, 79 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF, 80 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF, 81 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */ 82 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */ 83 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */ 84 [PCI_EXT_CAP_ID_MFVC] = 0xFF, 85 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */ 86 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */ 87 [PCI_EXT_CAP_ID_VNDR] = 0xFF, 88 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */ 89 [PCI_EXT_CAP_ID_ACS] = 0xFF, 90 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF, 91 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF, 92 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF, 93 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */ 94 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF, 95 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF, 96 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */ 97 [PCI_EXT_CAP_ID_REBAR] = 0xFF, 98 [PCI_EXT_CAP_ID_DPA] = 0xFF, 99 [PCI_EXT_CAP_ID_TPH] = 0xFF, 100 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF, 101 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */ 102 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */ 103 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */ 104 }; 105 106 /* 107 * Read/Write Permission Bits - one bit for each bit in capability 108 * Any field can be read if it exists, but what is read depends on 109 * whether the field is 'virtualized', or just pass thru to the 110 * hardware. Any virtualized field is also virtualized for writes. 111 * Writes are only permitted if they have a 1 bit here. 112 */ 113 struct perm_bits { 114 u8 *virt; /* read/write virtual data, not hw */ 115 u8 *write; /* writeable bits */ 116 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count, 117 struct perm_bits *perm, int offset, __le32 *val); 118 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count, 119 struct perm_bits *perm, int offset, __le32 val); 120 }; 121 122 #define NO_VIRT 0 123 #define ALL_VIRT 0xFFFFFFFFU 124 #define NO_WRITE 0 125 #define ALL_WRITE 0xFFFFFFFFU 126 127 static int vfio_user_config_read(struct pci_dev *pdev, int offset, 128 __le32 *val, int count) 129 { 130 int ret = -EINVAL; 131 u32 tmp_val = 0; 132 133 switch (count) { 134 case 1: 135 { 136 u8 tmp; 137 ret = pci_user_read_config_byte(pdev, offset, &tmp); 138 tmp_val = tmp; 139 break; 140 } 141 case 2: 142 { 143 u16 tmp; 144 ret = pci_user_read_config_word(pdev, offset, &tmp); 145 tmp_val = tmp; 146 break; 147 } 148 case 4: 149 ret = pci_user_read_config_dword(pdev, offset, &tmp_val); 150 break; 151 } 152 153 *val = cpu_to_le32(tmp_val); 154 155 return pcibios_err_to_errno(ret); 156 } 157 158 static int vfio_user_config_write(struct pci_dev *pdev, int offset, 159 __le32 val, int count) 160 { 161 int ret = -EINVAL; 162 u32 tmp_val = le32_to_cpu(val); 163 164 switch (count) { 165 case 1: 166 ret = pci_user_write_config_byte(pdev, offset, tmp_val); 167 break; 168 case 2: 169 ret = pci_user_write_config_word(pdev, offset, tmp_val); 170 break; 171 case 4: 172 ret = pci_user_write_config_dword(pdev, offset, tmp_val); 173 break; 174 } 175 176 return pcibios_err_to_errno(ret); 177 } 178 179 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos, 180 int count, struct perm_bits *perm, 181 int offset, __le32 *val) 182 { 183 __le32 virt = 0; 184 185 memcpy(val, vdev->vconfig + pos, count); 186 187 memcpy(&virt, perm->virt + offset, count); 188 189 /* Any non-virtualized bits? */ 190 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) { 191 struct pci_dev *pdev = vdev->pdev; 192 __le32 phys_val = 0; 193 int ret; 194 195 ret = vfio_user_config_read(pdev, pos, &phys_val, count); 196 if (ret) 197 return ret; 198 199 *val = (phys_val & ~virt) | (*val & virt); 200 } 201 202 return count; 203 } 204 205 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos, 206 int count, struct perm_bits *perm, 207 int offset, __le32 val) 208 { 209 __le32 virt = 0, write = 0; 210 211 memcpy(&write, perm->write + offset, count); 212 213 if (!write) 214 return count; /* drop, no writable bits */ 215 216 memcpy(&virt, perm->virt + offset, count); 217 218 /* Virtualized and writable bits go to vconfig */ 219 if (write & virt) { 220 __le32 virt_val = 0; 221 222 memcpy(&virt_val, vdev->vconfig + pos, count); 223 224 virt_val &= ~(write & virt); 225 virt_val |= (val & (write & virt)); 226 227 memcpy(vdev->vconfig + pos, &virt_val, count); 228 } 229 230 /* Non-virtualzed and writable bits go to hardware */ 231 if (write & ~virt) { 232 struct pci_dev *pdev = vdev->pdev; 233 __le32 phys_val = 0; 234 int ret; 235 236 ret = vfio_user_config_read(pdev, pos, &phys_val, count); 237 if (ret) 238 return ret; 239 240 phys_val &= ~(write & ~virt); 241 phys_val |= (val & (write & ~virt)); 242 243 ret = vfio_user_config_write(pdev, pos, phys_val, count); 244 if (ret) 245 return ret; 246 } 247 248 return count; 249 } 250 251 /* Allow direct read from hardware, except for capability next pointer */ 252 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos, 253 int count, struct perm_bits *perm, 254 int offset, __le32 *val) 255 { 256 int ret; 257 258 ret = vfio_user_config_read(vdev->pdev, pos, val, count); 259 if (ret) 260 return pcibios_err_to_errno(ret); 261 262 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */ 263 if (offset < 4) 264 memcpy(val, vdev->vconfig + pos, count); 265 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */ 266 if (offset == PCI_CAP_LIST_ID && count > 1) 267 memcpy(val, vdev->vconfig + pos, 268 min(PCI_CAP_FLAGS, count)); 269 else if (offset == PCI_CAP_LIST_NEXT) 270 memcpy(val, vdev->vconfig + pos, 1); 271 } 272 273 return count; 274 } 275 276 /* Raw access skips any kind of virtualization */ 277 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos, 278 int count, struct perm_bits *perm, 279 int offset, __le32 val) 280 { 281 int ret; 282 283 ret = vfio_user_config_write(vdev->pdev, pos, val, count); 284 if (ret) 285 return ret; 286 287 return count; 288 } 289 290 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos, 291 int count, struct perm_bits *perm, 292 int offset, __le32 *val) 293 { 294 int ret; 295 296 ret = vfio_user_config_read(vdev->pdev, pos, val, count); 297 if (ret) 298 return pcibios_err_to_errno(ret); 299 300 return count; 301 } 302 303 /* Virt access uses only virtualization */ 304 static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos, 305 int count, struct perm_bits *perm, 306 int offset, __le32 val) 307 { 308 memcpy(vdev->vconfig + pos, &val, count); 309 return count; 310 } 311 312 static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos, 313 int count, struct perm_bits *perm, 314 int offset, __le32 *val) 315 { 316 memcpy(val, vdev->vconfig + pos, count); 317 return count; 318 } 319 320 /* Default capability regions to read-only, no-virtualization */ 321 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = { 322 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } 323 }; 324 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = { 325 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } 326 }; 327 /* 328 * Default unassigned regions to raw read-write access. Some devices 329 * require this to function as they hide registers between the gaps in 330 * config space (be2net). Like MMIO and I/O port registers, we have 331 * to trust the hardware isolation. 332 */ 333 static struct perm_bits unassigned_perms = { 334 .readfn = vfio_raw_config_read, 335 .writefn = vfio_raw_config_write 336 }; 337 338 static struct perm_bits virt_perms = { 339 .readfn = vfio_virt_config_read, 340 .writefn = vfio_virt_config_write 341 }; 342 343 static void free_perm_bits(struct perm_bits *perm) 344 { 345 kfree(perm->virt); 346 kfree(perm->write); 347 perm->virt = NULL; 348 perm->write = NULL; 349 } 350 351 static int alloc_perm_bits(struct perm_bits *perm, int size) 352 { 353 /* 354 * Round up all permission bits to the next dword, this lets us 355 * ignore whether a read/write exceeds the defined capability 356 * structure. We can do this because: 357 * - Standard config space is already dword aligned 358 * - Capabilities are all dword alinged (bits 0:1 of next reserved) 359 * - Express capabilities defined as dword aligned 360 */ 361 size = round_up(size, 4); 362 363 /* 364 * Zero state is 365 * - All Readable, None Writeable, None Virtualized 366 */ 367 perm->virt = kzalloc(size, GFP_KERNEL); 368 perm->write = kzalloc(size, GFP_KERNEL); 369 if (!perm->virt || !perm->write) { 370 free_perm_bits(perm); 371 return -ENOMEM; 372 } 373 374 perm->readfn = vfio_default_config_read; 375 perm->writefn = vfio_default_config_write; 376 377 return 0; 378 } 379 380 /* 381 * Helper functions for filling in permission tables 382 */ 383 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write) 384 { 385 p->virt[off] = virt; 386 p->write[off] = write; 387 } 388 389 /* Handle endian-ness - pci and tables are little-endian */ 390 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write) 391 { 392 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt); 393 *(__le16 *)(&p->write[off]) = cpu_to_le16(write); 394 } 395 396 /* Handle endian-ness - pci and tables are little-endian */ 397 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write) 398 { 399 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt); 400 *(__le32 *)(&p->write[off]) = cpu_to_le32(write); 401 } 402 403 /* 404 * Restore the *real* BARs after we detect a FLR or backdoor reset. 405 * (backdoor = some device specific technique that we didn't catch) 406 */ 407 static void vfio_bar_restore(struct vfio_pci_device *vdev) 408 { 409 struct pci_dev *pdev = vdev->pdev; 410 u32 *rbar = vdev->rbar; 411 u16 cmd; 412 int i; 413 414 if (pdev->is_virtfn) 415 return; 416 417 pr_info("%s: %s reset recovery - restoring bars\n", 418 __func__, dev_name(&pdev->dev)); 419 420 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++) 421 pci_user_write_config_dword(pdev, i, *rbar); 422 423 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar); 424 425 if (vdev->nointx) { 426 pci_user_read_config_word(pdev, PCI_COMMAND, &cmd); 427 cmd |= PCI_COMMAND_INTX_DISABLE; 428 pci_user_write_config_word(pdev, PCI_COMMAND, cmd); 429 } 430 } 431 432 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar) 433 { 434 unsigned long flags = pci_resource_flags(pdev, bar); 435 u32 val; 436 437 if (flags & IORESOURCE_IO) 438 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO); 439 440 val = PCI_BASE_ADDRESS_SPACE_MEMORY; 441 442 if (flags & IORESOURCE_PREFETCH) 443 val |= PCI_BASE_ADDRESS_MEM_PREFETCH; 444 445 if (flags & IORESOURCE_MEM_64) 446 val |= PCI_BASE_ADDRESS_MEM_TYPE_64; 447 448 return cpu_to_le32(val); 449 } 450 451 /* 452 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs 453 * to reflect the hardware capabilities. This implements BAR sizing. 454 */ 455 static void vfio_bar_fixup(struct vfio_pci_device *vdev) 456 { 457 struct pci_dev *pdev = vdev->pdev; 458 int i; 459 __le32 *bar; 460 u64 mask; 461 462 bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0]; 463 464 for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) { 465 if (!pci_resource_start(pdev, i)) { 466 *bar = 0; /* Unmapped by host = unimplemented to user */ 467 continue; 468 } 469 470 mask = ~(pci_resource_len(pdev, i) - 1); 471 472 *bar &= cpu_to_le32((u32)mask); 473 *bar |= vfio_generate_bar_flags(pdev, i); 474 475 if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) { 476 bar++; 477 *bar &= cpu_to_le32((u32)(mask >> 32)); 478 i++; 479 } 480 } 481 482 bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS]; 483 484 /* 485 * NB. REGION_INFO will have reported zero size if we weren't able 486 * to read the ROM, but we still return the actual BAR size here if 487 * it exists (or the shadow ROM space). 488 */ 489 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) { 490 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1); 491 mask |= PCI_ROM_ADDRESS_ENABLE; 492 *bar &= cpu_to_le32((u32)mask); 493 } else if (pdev->resource[PCI_ROM_RESOURCE].flags & 494 IORESOURCE_ROM_SHADOW) { 495 mask = ~(0x20000 - 1); 496 mask |= PCI_ROM_ADDRESS_ENABLE; 497 *bar &= cpu_to_le32((u32)mask); 498 } else 499 *bar = 0; 500 501 vdev->bardirty = false; 502 } 503 504 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos, 505 int count, struct perm_bits *perm, 506 int offset, __le32 *val) 507 { 508 if (is_bar(offset)) /* pos == offset for basic config */ 509 vfio_bar_fixup(vdev); 510 511 count = vfio_default_config_read(vdev, pos, count, perm, offset, val); 512 513 /* Mask in virtual memory enable for SR-IOV devices */ 514 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) { 515 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]); 516 u32 tmp_val = le32_to_cpu(*val); 517 518 tmp_val |= cmd & PCI_COMMAND_MEMORY; 519 *val = cpu_to_le32(tmp_val); 520 } 521 522 return count; 523 } 524 525 /* Test whether BARs match the value we think they should contain */ 526 static bool vfio_need_bar_restore(struct vfio_pci_device *vdev) 527 { 528 int i = 0, pos = PCI_BASE_ADDRESS_0, ret; 529 u32 bar; 530 531 for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) { 532 if (vdev->rbar[i]) { 533 ret = pci_user_read_config_dword(vdev->pdev, pos, &bar); 534 if (ret || vdev->rbar[i] != bar) 535 return true; 536 } 537 } 538 539 return false; 540 } 541 542 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos, 543 int count, struct perm_bits *perm, 544 int offset, __le32 val) 545 { 546 struct pci_dev *pdev = vdev->pdev; 547 __le16 *virt_cmd; 548 u16 new_cmd = 0; 549 int ret; 550 551 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND]; 552 553 if (offset == PCI_COMMAND) { 554 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io; 555 u16 phys_cmd; 556 557 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd); 558 if (ret) 559 return ret; 560 561 new_cmd = le32_to_cpu(val); 562 563 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY); 564 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY); 565 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY); 566 567 phys_io = !!(phys_cmd & PCI_COMMAND_IO); 568 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO); 569 new_io = !!(new_cmd & PCI_COMMAND_IO); 570 571 /* 572 * If the user is writing mem/io enable (new_mem/io) and we 573 * think it's already enabled (virt_mem/io), but the hardware 574 * shows it disabled (phys_mem/io, then the device has 575 * undergone some kind of backdoor reset and needs to be 576 * restored before we allow it to enable the bars. 577 * SR-IOV devices will trigger this, but we catch them later 578 */ 579 if ((new_mem && virt_mem && !phys_mem) || 580 (new_io && virt_io && !phys_io) || 581 vfio_need_bar_restore(vdev)) 582 vfio_bar_restore(vdev); 583 } 584 585 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 586 if (count < 0) 587 return count; 588 589 /* 590 * Save current memory/io enable bits in vconfig to allow for 591 * the test above next time. 592 */ 593 if (offset == PCI_COMMAND) { 594 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO; 595 596 *virt_cmd &= cpu_to_le16(~mask); 597 *virt_cmd |= cpu_to_le16(new_cmd & mask); 598 } 599 600 /* Emulate INTx disable */ 601 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) { 602 bool virt_intx_disable; 603 604 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) & 605 PCI_COMMAND_INTX_DISABLE); 606 607 if (virt_intx_disable && !vdev->virq_disabled) { 608 vdev->virq_disabled = true; 609 vfio_pci_intx_mask(vdev); 610 } else if (!virt_intx_disable && vdev->virq_disabled) { 611 vdev->virq_disabled = false; 612 vfio_pci_intx_unmask(vdev); 613 } 614 } 615 616 if (is_bar(offset)) 617 vdev->bardirty = true; 618 619 return count; 620 } 621 622 /* Permissions for the Basic PCI Header */ 623 static int __init init_pci_cap_basic_perm(struct perm_bits *perm) 624 { 625 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF)) 626 return -ENOMEM; 627 628 perm->readfn = vfio_basic_config_read; 629 perm->writefn = vfio_basic_config_write; 630 631 /* Virtualized for SR-IOV functions, which just have FFFF */ 632 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE); 633 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE); 634 635 /* 636 * Virtualize INTx disable, we use it internally for interrupt 637 * control and can emulate it for non-PCI 2.3 devices. 638 */ 639 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE); 640 641 /* Virtualize capability list, we might want to skip/disable */ 642 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE); 643 644 /* No harm to write */ 645 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE); 646 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE); 647 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE); 648 649 /* Virtualize all bars, can't touch the real ones */ 650 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE); 651 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE); 652 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE); 653 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE); 654 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE); 655 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE); 656 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE); 657 658 /* Allow us to adjust capability chain */ 659 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE); 660 661 /* Sometimes used by sw, just virtualize */ 662 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE); 663 664 /* Virtualize interrupt pin to allow hiding INTx */ 665 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE); 666 667 return 0; 668 } 669 670 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos, 671 int count, struct perm_bits *perm, 672 int offset, __le32 val) 673 { 674 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 675 if (count < 0) 676 return count; 677 678 if (offset == PCI_PM_CTRL) { 679 pci_power_t state; 680 681 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) { 682 case 0: 683 state = PCI_D0; 684 break; 685 case 1: 686 state = PCI_D1; 687 break; 688 case 2: 689 state = PCI_D2; 690 break; 691 case 3: 692 state = PCI_D3hot; 693 break; 694 } 695 696 pci_set_power_state(vdev->pdev, state); 697 } 698 699 return count; 700 } 701 702 /* Permissions for the Power Management capability */ 703 static int __init init_pci_cap_pm_perm(struct perm_bits *perm) 704 { 705 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM])) 706 return -ENOMEM; 707 708 perm->writefn = vfio_pm_config_write; 709 710 /* 711 * We always virtualize the next field so we can remove 712 * capabilities from the chain if we want to. 713 */ 714 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 715 716 /* 717 * Power management is defined *per function*, so we can let 718 * the user change power state, but we trap and initiate the 719 * change ourselves, so the state bits are read-only. 720 */ 721 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK); 722 return 0; 723 } 724 725 static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos, 726 int count, struct perm_bits *perm, 727 int offset, __le32 val) 728 { 729 struct pci_dev *pdev = vdev->pdev; 730 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR); 731 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA); 732 u16 addr; 733 u32 data; 734 735 /* 736 * Write through to emulation. If the write includes the upper byte 737 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we 738 * have work to do. 739 */ 740 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 741 if (count < 0 || offset > PCI_VPD_ADDR + 1 || 742 offset + count <= PCI_VPD_ADDR + 1) 743 return count; 744 745 addr = le16_to_cpu(*paddr); 746 747 if (addr & PCI_VPD_ADDR_F) { 748 data = le32_to_cpu(*pdata); 749 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4) 750 return count; 751 } else { 752 if (pci_read_vpd(pdev, addr, 4, &data) != 4) 753 return count; 754 *pdata = cpu_to_le32(data); 755 } 756 757 /* 758 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to 759 * signal completion. If an error occurs above, we assume that not 760 * toggling this bit will induce a driver timeout. 761 */ 762 addr ^= PCI_VPD_ADDR_F; 763 *paddr = cpu_to_le16(addr); 764 765 return count; 766 } 767 768 /* Permissions for Vital Product Data capability */ 769 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm) 770 { 771 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD])) 772 return -ENOMEM; 773 774 perm->writefn = vfio_vpd_config_write; 775 776 /* 777 * We always virtualize the next field so we can remove 778 * capabilities from the chain if we want to. 779 */ 780 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 781 782 /* 783 * Both the address and data registers are virtualized to 784 * enable access through the pci_vpd_read/write functions 785 */ 786 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE); 787 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE); 788 789 return 0; 790 } 791 792 /* Permissions for PCI-X capability */ 793 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm) 794 { 795 /* Alloc 24, but only 8 are used in v0 */ 796 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2)) 797 return -ENOMEM; 798 799 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 800 801 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE); 802 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE); 803 return 0; 804 } 805 806 /* Permissions for PCI Express capability */ 807 static int __init init_pci_cap_exp_perm(struct perm_bits *perm) 808 { 809 /* Alloc larger of two possible sizes */ 810 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2)) 811 return -ENOMEM; 812 813 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 814 815 /* 816 * Allow writes to device control fields (includes FLR!) 817 * but not to devctl_phantom which could confuse IOMMU 818 * or to the ARI bit in devctl2 which is set at probe time 819 */ 820 p_setw(perm, PCI_EXP_DEVCTL, NO_VIRT, ~PCI_EXP_DEVCTL_PHANTOM); 821 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI); 822 return 0; 823 } 824 825 /* Permissions for Advanced Function capability */ 826 static int __init init_pci_cap_af_perm(struct perm_bits *perm) 827 { 828 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF])) 829 return -ENOMEM; 830 831 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 832 p_setb(perm, PCI_AF_CTRL, NO_VIRT, PCI_AF_CTRL_FLR); 833 return 0; 834 } 835 836 /* Permissions for Advanced Error Reporting extended capability */ 837 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm) 838 { 839 u32 mask; 840 841 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR])) 842 return -ENOMEM; 843 844 /* 845 * Virtualize the first dword of all express capabilities 846 * because it includes the next pointer. This lets us later 847 * remove capabilities from the chain if we need to. 848 */ 849 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 850 851 /* Writable bits mask */ 852 mask = PCI_ERR_UNC_UND | /* Undefined */ 853 PCI_ERR_UNC_DLP | /* Data Link Protocol */ 854 PCI_ERR_UNC_SURPDN | /* Surprise Down */ 855 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */ 856 PCI_ERR_UNC_FCP | /* Flow Control Protocol */ 857 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */ 858 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */ 859 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */ 860 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */ 861 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */ 862 PCI_ERR_UNC_ECRC | /* ECRC Error Status */ 863 PCI_ERR_UNC_UNSUP | /* Unsupported Request */ 864 PCI_ERR_UNC_ACSV | /* ACS Violation */ 865 PCI_ERR_UNC_INTN | /* internal error */ 866 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */ 867 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */ 868 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */ 869 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask); 870 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask); 871 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask); 872 873 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */ 874 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */ 875 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */ 876 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */ 877 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */ 878 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */ 879 PCI_ERR_COR_INTERNAL | /* Corrected Internal */ 880 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */ 881 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask); 882 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask); 883 884 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */ 885 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */ 886 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask); 887 return 0; 888 } 889 890 /* Permissions for Power Budgeting extended capability */ 891 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm) 892 { 893 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR])) 894 return -ENOMEM; 895 896 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 897 898 /* Writing the data selector is OK, the info is still read-only */ 899 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE); 900 return 0; 901 } 902 903 /* 904 * Initialize the shared permission tables 905 */ 906 void vfio_pci_uninit_perm_bits(void) 907 { 908 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]); 909 910 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]); 911 free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]); 912 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]); 913 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]); 914 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]); 915 916 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]); 917 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]); 918 } 919 920 int __init vfio_pci_init_perm_bits(void) 921 { 922 int ret; 923 924 /* Basic config space */ 925 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]); 926 927 /* Capabilities */ 928 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]); 929 ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]); 930 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]); 931 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write; 932 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]); 933 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]); 934 935 /* Extended capabilities */ 936 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]); 937 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]); 938 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write; 939 940 if (ret) 941 vfio_pci_uninit_perm_bits(); 942 943 return ret; 944 } 945 946 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos) 947 { 948 u8 cap; 949 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE : 950 PCI_STD_HEADER_SIZEOF; 951 cap = vdev->pci_config_map[pos]; 952 953 if (cap == PCI_CAP_ID_BASIC) 954 return 0; 955 956 /* XXX Can we have to abutting capabilities of the same type? */ 957 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap) 958 pos--; 959 960 return pos; 961 } 962 963 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos, 964 int count, struct perm_bits *perm, 965 int offset, __le32 *val) 966 { 967 /* Update max available queue size from msi_qmax */ 968 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) { 969 __le16 *flags; 970 int start; 971 972 start = vfio_find_cap_start(vdev, pos); 973 974 flags = (__le16 *)&vdev->vconfig[start]; 975 976 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK); 977 *flags |= cpu_to_le16(vdev->msi_qmax << 1); 978 } 979 980 return vfio_default_config_read(vdev, pos, count, perm, offset, val); 981 } 982 983 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos, 984 int count, struct perm_bits *perm, 985 int offset, __le32 val) 986 { 987 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 988 if (count < 0) 989 return count; 990 991 /* Fixup and write configured queue size and enable to hardware */ 992 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) { 993 __le16 *pflags; 994 u16 flags; 995 int start, ret; 996 997 start = vfio_find_cap_start(vdev, pos); 998 999 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS]; 1000 1001 flags = le16_to_cpu(*pflags); 1002 1003 /* MSI is enabled via ioctl */ 1004 if (!is_msi(vdev)) 1005 flags &= ~PCI_MSI_FLAGS_ENABLE; 1006 1007 /* Check queue size */ 1008 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) { 1009 flags &= ~PCI_MSI_FLAGS_QSIZE; 1010 flags |= vdev->msi_qmax << 4; 1011 } 1012 1013 /* Write back to virt and to hardware */ 1014 *pflags = cpu_to_le16(flags); 1015 ret = pci_user_write_config_word(vdev->pdev, 1016 start + PCI_MSI_FLAGS, 1017 flags); 1018 if (ret) 1019 return pcibios_err_to_errno(ret); 1020 } 1021 1022 return count; 1023 } 1024 1025 /* 1026 * MSI determination is per-device, so this routine gets used beyond 1027 * initialization time. Don't add __init 1028 */ 1029 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags) 1030 { 1031 if (alloc_perm_bits(perm, len)) 1032 return -ENOMEM; 1033 1034 perm->readfn = vfio_msi_config_read; 1035 perm->writefn = vfio_msi_config_write; 1036 1037 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 1038 1039 /* 1040 * The upper byte of the control register is reserved, 1041 * just setup the lower byte. 1042 */ 1043 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE); 1044 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE); 1045 if (flags & PCI_MSI_FLAGS_64BIT) { 1046 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE); 1047 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE); 1048 if (flags & PCI_MSI_FLAGS_MASKBIT) { 1049 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE); 1050 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE); 1051 } 1052 } else { 1053 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE); 1054 if (flags & PCI_MSI_FLAGS_MASKBIT) { 1055 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE); 1056 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE); 1057 } 1058 } 1059 return 0; 1060 } 1061 1062 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */ 1063 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos) 1064 { 1065 struct pci_dev *pdev = vdev->pdev; 1066 int len, ret; 1067 u16 flags; 1068 1069 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags); 1070 if (ret) 1071 return pcibios_err_to_errno(ret); 1072 1073 len = 10; /* Minimum size */ 1074 if (flags & PCI_MSI_FLAGS_64BIT) 1075 len += 4; 1076 if (flags & PCI_MSI_FLAGS_MASKBIT) 1077 len += 10; 1078 1079 if (vdev->msi_perm) 1080 return len; 1081 1082 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL); 1083 if (!vdev->msi_perm) 1084 return -ENOMEM; 1085 1086 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags); 1087 if (ret) 1088 return ret; 1089 1090 return len; 1091 } 1092 1093 /* Determine extended capability length for VC (2 & 9) and MFVC */ 1094 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos) 1095 { 1096 struct pci_dev *pdev = vdev->pdev; 1097 u32 tmp; 1098 int ret, evcc, phases, vc_arb; 1099 int len = PCI_CAP_VC_BASE_SIZEOF; 1100 1101 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp); 1102 if (ret) 1103 return pcibios_err_to_errno(ret); 1104 1105 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */ 1106 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp); 1107 if (ret) 1108 return pcibios_err_to_errno(ret); 1109 1110 if (tmp & PCI_VC_CAP2_128_PHASE) 1111 phases = 128; 1112 else if (tmp & PCI_VC_CAP2_64_PHASE) 1113 phases = 64; 1114 else if (tmp & PCI_VC_CAP2_32_PHASE) 1115 phases = 32; 1116 else 1117 phases = 0; 1118 1119 vc_arb = phases * 4; 1120 1121 /* 1122 * Port arbitration tables are root & switch only; 1123 * function arbitration tables are function 0 only. 1124 * In either case, we'll never let user write them so 1125 * we don't care how big they are 1126 */ 1127 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF; 1128 if (vc_arb) { 1129 len = round_up(len, 16); 1130 len += vc_arb / 8; 1131 } 1132 return len; 1133 } 1134 1135 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos) 1136 { 1137 struct pci_dev *pdev = vdev->pdev; 1138 u32 dword; 1139 u16 word; 1140 u8 byte; 1141 int ret; 1142 1143 switch (cap) { 1144 case PCI_CAP_ID_MSI: 1145 return vfio_msi_cap_len(vdev, pos); 1146 case PCI_CAP_ID_PCIX: 1147 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word); 1148 if (ret) 1149 return pcibios_err_to_errno(ret); 1150 1151 if (PCI_X_CMD_VERSION(word)) { 1152 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) { 1153 /* Test for extended capabilities */ 1154 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, 1155 &dword); 1156 vdev->extended_caps = (dword != 0); 1157 } 1158 return PCI_CAP_PCIX_SIZEOF_V2; 1159 } else 1160 return PCI_CAP_PCIX_SIZEOF_V0; 1161 case PCI_CAP_ID_VNDR: 1162 /* length follows next field */ 1163 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte); 1164 if (ret) 1165 return pcibios_err_to_errno(ret); 1166 1167 return byte; 1168 case PCI_CAP_ID_EXP: 1169 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) { 1170 /* Test for extended capabilities */ 1171 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword); 1172 vdev->extended_caps = (dword != 0); 1173 } 1174 1175 /* length based on version */ 1176 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) 1177 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1; 1178 else 1179 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2; 1180 case PCI_CAP_ID_HT: 1181 ret = pci_read_config_byte(pdev, pos + 3, &byte); 1182 if (ret) 1183 return pcibios_err_to_errno(ret); 1184 1185 return (byte & HT_3BIT_CAP_MASK) ? 1186 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG; 1187 case PCI_CAP_ID_SATA: 1188 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte); 1189 if (ret) 1190 return pcibios_err_to_errno(ret); 1191 1192 byte &= PCI_SATA_REGS_MASK; 1193 if (byte == PCI_SATA_REGS_INLINE) 1194 return PCI_SATA_SIZEOF_LONG; 1195 else 1196 return PCI_SATA_SIZEOF_SHORT; 1197 default: 1198 pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n", 1199 dev_name(&pdev->dev), __func__, cap, pos); 1200 } 1201 1202 return 0; 1203 } 1204 1205 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos) 1206 { 1207 struct pci_dev *pdev = vdev->pdev; 1208 u8 byte; 1209 u32 dword; 1210 int ret; 1211 1212 switch (ecap) { 1213 case PCI_EXT_CAP_ID_VNDR: 1214 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword); 1215 if (ret) 1216 return pcibios_err_to_errno(ret); 1217 1218 return dword >> PCI_VSEC_HDR_LEN_SHIFT; 1219 case PCI_EXT_CAP_ID_VC: 1220 case PCI_EXT_CAP_ID_VC9: 1221 case PCI_EXT_CAP_ID_MFVC: 1222 return vfio_vc_cap_len(vdev, epos); 1223 case PCI_EXT_CAP_ID_ACS: 1224 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte); 1225 if (ret) 1226 return pcibios_err_to_errno(ret); 1227 1228 if (byte & PCI_ACS_EC) { 1229 int bits; 1230 1231 ret = pci_read_config_byte(pdev, 1232 epos + PCI_ACS_EGRESS_BITS, 1233 &byte); 1234 if (ret) 1235 return pcibios_err_to_errno(ret); 1236 1237 bits = byte ? round_up(byte, 32) : 256; 1238 return 8 + (bits / 8); 1239 } 1240 return 8; 1241 1242 case PCI_EXT_CAP_ID_REBAR: 1243 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte); 1244 if (ret) 1245 return pcibios_err_to_errno(ret); 1246 1247 byte &= PCI_REBAR_CTRL_NBAR_MASK; 1248 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT; 1249 1250 return 4 + (byte * 8); 1251 case PCI_EXT_CAP_ID_DPA: 1252 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte); 1253 if (ret) 1254 return pcibios_err_to_errno(ret); 1255 1256 byte &= PCI_DPA_CAP_SUBSTATE_MASK; 1257 return PCI_DPA_BASE_SIZEOF + byte + 1; 1258 case PCI_EXT_CAP_ID_TPH: 1259 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword); 1260 if (ret) 1261 return pcibios_err_to_errno(ret); 1262 1263 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) { 1264 int sts; 1265 1266 sts = dword & PCI_TPH_CAP_ST_MASK; 1267 sts >>= PCI_TPH_CAP_ST_SHIFT; 1268 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2; 1269 } 1270 return PCI_TPH_BASE_SIZEOF; 1271 default: 1272 pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n", 1273 dev_name(&pdev->dev), __func__, ecap, epos); 1274 } 1275 1276 return 0; 1277 } 1278 1279 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev, 1280 int offset, int size) 1281 { 1282 struct pci_dev *pdev = vdev->pdev; 1283 int ret = 0; 1284 1285 /* 1286 * We try to read physical config space in the largest chunks 1287 * we can, assuming that all of the fields support dword access. 1288 * pci_save_state() makes this same assumption and seems to do ok. 1289 */ 1290 while (size) { 1291 int filled; 1292 1293 if (size >= 4 && !(offset % 4)) { 1294 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset]; 1295 u32 dword; 1296 1297 ret = pci_read_config_dword(pdev, offset, &dword); 1298 if (ret) 1299 return ret; 1300 *dwordp = cpu_to_le32(dword); 1301 filled = 4; 1302 } else if (size >= 2 && !(offset % 2)) { 1303 __le16 *wordp = (__le16 *)&vdev->vconfig[offset]; 1304 u16 word; 1305 1306 ret = pci_read_config_word(pdev, offset, &word); 1307 if (ret) 1308 return ret; 1309 *wordp = cpu_to_le16(word); 1310 filled = 2; 1311 } else { 1312 u8 *byte = &vdev->vconfig[offset]; 1313 ret = pci_read_config_byte(pdev, offset, byte); 1314 if (ret) 1315 return ret; 1316 filled = 1; 1317 } 1318 1319 offset += filled; 1320 size -= filled; 1321 } 1322 1323 return ret; 1324 } 1325 1326 static int vfio_cap_init(struct vfio_pci_device *vdev) 1327 { 1328 struct pci_dev *pdev = vdev->pdev; 1329 u8 *map = vdev->pci_config_map; 1330 u16 status; 1331 u8 pos, *prev, cap; 1332 int loops, ret, caps = 0; 1333 1334 /* Any capabilities? */ 1335 ret = pci_read_config_word(pdev, PCI_STATUS, &status); 1336 if (ret) 1337 return ret; 1338 1339 if (!(status & PCI_STATUS_CAP_LIST)) 1340 return 0; /* Done */ 1341 1342 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos); 1343 if (ret) 1344 return ret; 1345 1346 /* Mark the previous position in case we want to skip a capability */ 1347 prev = &vdev->vconfig[PCI_CAPABILITY_LIST]; 1348 1349 /* We can bound our loop, capabilities are dword aligned */ 1350 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF; 1351 while (pos && loops--) { 1352 u8 next; 1353 int i, len = 0; 1354 1355 ret = pci_read_config_byte(pdev, pos, &cap); 1356 if (ret) 1357 return ret; 1358 1359 ret = pci_read_config_byte(pdev, 1360 pos + PCI_CAP_LIST_NEXT, &next); 1361 if (ret) 1362 return ret; 1363 1364 if (cap <= PCI_CAP_ID_MAX) { 1365 len = pci_cap_length[cap]; 1366 if (len == 0xFF) { /* Variable length */ 1367 len = vfio_cap_len(vdev, cap, pos); 1368 if (len < 0) 1369 return len; 1370 } 1371 } 1372 1373 if (!len) { 1374 pr_info("%s: %s hiding cap 0x%x\n", 1375 __func__, dev_name(&pdev->dev), cap); 1376 *prev = next; 1377 pos = next; 1378 continue; 1379 } 1380 1381 /* Sanity check, do we overlap other capabilities? */ 1382 for (i = 0; i < len; i++) { 1383 if (likely(map[pos + i] == PCI_CAP_ID_INVALID)) 1384 continue; 1385 1386 pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n", 1387 __func__, dev_name(&pdev->dev), 1388 pos + i, map[pos + i], cap); 1389 } 1390 1391 BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT); 1392 1393 memset(map + pos, cap, len); 1394 ret = vfio_fill_vconfig_bytes(vdev, pos, len); 1395 if (ret) 1396 return ret; 1397 1398 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT]; 1399 pos = next; 1400 caps++; 1401 } 1402 1403 /* If we didn't fill any capabilities, clear the status flag */ 1404 if (!caps) { 1405 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS]; 1406 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST); 1407 } 1408 1409 return 0; 1410 } 1411 1412 static int vfio_ecap_init(struct vfio_pci_device *vdev) 1413 { 1414 struct pci_dev *pdev = vdev->pdev; 1415 u8 *map = vdev->pci_config_map; 1416 u16 epos; 1417 __le32 *prev = NULL; 1418 int loops, ret, ecaps = 0; 1419 1420 if (!vdev->extended_caps) 1421 return 0; 1422 1423 epos = PCI_CFG_SPACE_SIZE; 1424 1425 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF; 1426 1427 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) { 1428 u32 header; 1429 u16 ecap; 1430 int i, len = 0; 1431 bool hidden = false; 1432 1433 ret = pci_read_config_dword(pdev, epos, &header); 1434 if (ret) 1435 return ret; 1436 1437 ecap = PCI_EXT_CAP_ID(header); 1438 1439 if (ecap <= PCI_EXT_CAP_ID_MAX) { 1440 len = pci_ext_cap_length[ecap]; 1441 if (len == 0xFF) { 1442 len = vfio_ext_cap_len(vdev, ecap, epos); 1443 if (len < 0) 1444 return ret; 1445 } 1446 } 1447 1448 if (!len) { 1449 pr_info("%s: %s hiding ecap 0x%x@0x%x\n", 1450 __func__, dev_name(&pdev->dev), ecap, epos); 1451 1452 /* If not the first in the chain, we can skip over it */ 1453 if (prev) { 1454 u32 val = epos = PCI_EXT_CAP_NEXT(header); 1455 *prev &= cpu_to_le32(~(0xffcU << 20)); 1456 *prev |= cpu_to_le32(val << 20); 1457 continue; 1458 } 1459 1460 /* 1461 * Otherwise, fill in a placeholder, the direct 1462 * readfn will virtualize this automatically 1463 */ 1464 len = PCI_CAP_SIZEOF; 1465 hidden = true; 1466 } 1467 1468 for (i = 0; i < len; i++) { 1469 if (likely(map[epos + i] == PCI_CAP_ID_INVALID)) 1470 continue; 1471 1472 pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n", 1473 __func__, dev_name(&pdev->dev), 1474 epos + i, map[epos + i], ecap); 1475 } 1476 1477 /* 1478 * Even though ecap is 2 bytes, we're currently a long way 1479 * from exceeding 1 byte capabilities. If we ever make it 1480 * up to 0xFE we'll need to up this to a two-byte, byte map. 1481 */ 1482 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT); 1483 1484 memset(map + epos, ecap, len); 1485 ret = vfio_fill_vconfig_bytes(vdev, epos, len); 1486 if (ret) 1487 return ret; 1488 1489 /* 1490 * If we're just using this capability to anchor the list, 1491 * hide the real ID. Only count real ecaps. XXX PCI spec 1492 * indicates to use cap id = 0, version = 0, next = 0 if 1493 * ecaps are absent, hope users check all the way to next. 1494 */ 1495 if (hidden) 1496 *(__le32 *)&vdev->vconfig[epos] &= 1497 cpu_to_le32((0xffcU << 20)); 1498 else 1499 ecaps++; 1500 1501 prev = (__le32 *)&vdev->vconfig[epos]; 1502 epos = PCI_EXT_CAP_NEXT(header); 1503 } 1504 1505 if (!ecaps) 1506 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0; 1507 1508 return 0; 1509 } 1510 1511 /* 1512 * For each device we allocate a pci_config_map that indicates the 1513 * capability occupying each dword and thus the struct perm_bits we 1514 * use for read and write. We also allocate a virtualized config 1515 * space which tracks reads and writes to bits that we emulate for 1516 * the user. Initial values filled from device. 1517 * 1518 * Using shared stuct perm_bits between all vfio-pci devices saves 1519 * us from allocating cfg_size buffers for virt and write for every 1520 * device. We could remove vconfig and allocate individual buffers 1521 * for each area requring emulated bits, but the array of pointers 1522 * would be comparable in size (at least for standard config space). 1523 */ 1524 int vfio_config_init(struct vfio_pci_device *vdev) 1525 { 1526 struct pci_dev *pdev = vdev->pdev; 1527 u8 *map, *vconfig; 1528 int ret; 1529 1530 /* 1531 * Config space, caps and ecaps are all dword aligned, so we could 1532 * use one byte per dword to record the type. However, there are 1533 * no requiremenst on the length of a capability, so the gap between 1534 * capabilities needs byte granularity. 1535 */ 1536 map = kmalloc(pdev->cfg_size, GFP_KERNEL); 1537 if (!map) 1538 return -ENOMEM; 1539 1540 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL); 1541 if (!vconfig) { 1542 kfree(map); 1543 return -ENOMEM; 1544 } 1545 1546 vdev->pci_config_map = map; 1547 vdev->vconfig = vconfig; 1548 1549 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF); 1550 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID, 1551 pdev->cfg_size - PCI_STD_HEADER_SIZEOF); 1552 1553 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF); 1554 if (ret) 1555 goto out; 1556 1557 vdev->bardirty = true; 1558 1559 /* 1560 * XXX can we just pci_load_saved_state/pci_restore_state? 1561 * may need to rebuild vconfig after that 1562 */ 1563 1564 /* For restore after reset */ 1565 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]); 1566 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]); 1567 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]); 1568 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]); 1569 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]); 1570 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]); 1571 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]); 1572 1573 if (pdev->is_virtfn) { 1574 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor); 1575 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device); 1576 } 1577 1578 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx) 1579 vconfig[PCI_INTERRUPT_PIN] = 0; 1580 1581 ret = vfio_cap_init(vdev); 1582 if (ret) 1583 goto out; 1584 1585 ret = vfio_ecap_init(vdev); 1586 if (ret) 1587 goto out; 1588 1589 return 0; 1590 1591 out: 1592 kfree(map); 1593 vdev->pci_config_map = NULL; 1594 kfree(vconfig); 1595 vdev->vconfig = NULL; 1596 return pcibios_err_to_errno(ret); 1597 } 1598 1599 void vfio_config_free(struct vfio_pci_device *vdev) 1600 { 1601 kfree(vdev->vconfig); 1602 vdev->vconfig = NULL; 1603 kfree(vdev->pci_config_map); 1604 vdev->pci_config_map = NULL; 1605 kfree(vdev->msi_perm); 1606 vdev->msi_perm = NULL; 1607 } 1608 1609 /* 1610 * Find the remaining number of bytes in a dword that match the given 1611 * position. Stop at either the end of the capability or the dword boundary. 1612 */ 1613 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev, 1614 loff_t pos) 1615 { 1616 u8 cap = vdev->pci_config_map[pos]; 1617 size_t i; 1618 1619 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++) 1620 /* nop */; 1621 1622 return i; 1623 } 1624 1625 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf, 1626 size_t count, loff_t *ppos, bool iswrite) 1627 { 1628 struct pci_dev *pdev = vdev->pdev; 1629 struct perm_bits *perm; 1630 __le32 val = 0; 1631 int cap_start = 0, offset; 1632 u8 cap_id; 1633 ssize_t ret; 1634 1635 if (*ppos < 0 || *ppos >= pdev->cfg_size || 1636 *ppos + count > pdev->cfg_size) 1637 return -EFAULT; 1638 1639 /* 1640 * Chop accesses into aligned chunks containing no more than a 1641 * single capability. Caller increments to the next chunk. 1642 */ 1643 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos)); 1644 if (count >= 4 && !(*ppos % 4)) 1645 count = 4; 1646 else if (count >= 2 && !(*ppos % 2)) 1647 count = 2; 1648 else 1649 count = 1; 1650 1651 ret = count; 1652 1653 cap_id = vdev->pci_config_map[*ppos]; 1654 1655 if (cap_id == PCI_CAP_ID_INVALID) { 1656 perm = &unassigned_perms; 1657 cap_start = *ppos; 1658 } else if (cap_id == PCI_CAP_ID_INVALID_VIRT) { 1659 perm = &virt_perms; 1660 cap_start = *ppos; 1661 } else { 1662 if (*ppos >= PCI_CFG_SPACE_SIZE) { 1663 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX); 1664 1665 perm = &ecap_perms[cap_id]; 1666 cap_start = vfio_find_cap_start(vdev, *ppos); 1667 } else { 1668 WARN_ON(cap_id > PCI_CAP_ID_MAX); 1669 1670 perm = &cap_perms[cap_id]; 1671 1672 if (cap_id == PCI_CAP_ID_MSI) 1673 perm = vdev->msi_perm; 1674 1675 if (cap_id > PCI_CAP_ID_BASIC) 1676 cap_start = vfio_find_cap_start(vdev, *ppos); 1677 } 1678 } 1679 1680 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC); 1681 WARN_ON(cap_start > *ppos); 1682 1683 offset = *ppos - cap_start; 1684 1685 if (iswrite) { 1686 if (!perm->writefn) 1687 return ret; 1688 1689 if (copy_from_user(&val, buf, count)) 1690 return -EFAULT; 1691 1692 ret = perm->writefn(vdev, *ppos, count, perm, offset, val); 1693 } else { 1694 if (perm->readfn) { 1695 ret = perm->readfn(vdev, *ppos, count, 1696 perm, offset, &val); 1697 if (ret < 0) 1698 return ret; 1699 } 1700 1701 if (copy_to_user(buf, &val, count)) 1702 return -EFAULT; 1703 } 1704 1705 return ret; 1706 } 1707 1708 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf, 1709 size_t count, loff_t *ppos, bool iswrite) 1710 { 1711 size_t done = 0; 1712 int ret = 0; 1713 loff_t pos = *ppos; 1714 1715 pos &= VFIO_PCI_OFFSET_MASK; 1716 1717 while (count) { 1718 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite); 1719 if (ret < 0) 1720 return ret; 1721 1722 count -= ret; 1723 done += ret; 1724 buf += ret; 1725 pos += ret; 1726 } 1727 1728 *ppos += done; 1729 1730 return done; 1731 } 1732