1 /* 2 * VFIO PCI config space virtualization 3 * 4 * Copyright (C) 2012 Red Hat, Inc. All rights reserved. 5 * Author: Alex Williamson <alex.williamson@redhat.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Derived from original vfio: 12 * Copyright 2010 Cisco Systems, Inc. All rights reserved. 13 * Author: Tom Lyon, pugs@cisco.com 14 */ 15 16 /* 17 * This code handles reading and writing of PCI configuration registers. 18 * This is hairy because we want to allow a lot of flexibility to the 19 * user driver, but cannot trust it with all of the config fields. 20 * Tables determine which fields can be read and written, as well as 21 * which fields are 'virtualized' - special actions and translations to 22 * make it appear to the user that he has control, when in fact things 23 * must be negotiated with the underlying OS. 24 */ 25 26 #include <linux/fs.h> 27 #include <linux/pci.h> 28 #include <linux/uaccess.h> 29 #include <linux/vfio.h> 30 #include <linux/slab.h> 31 32 #include "vfio_pci_private.h" 33 34 /* Fake capability ID for standard config space */ 35 #define PCI_CAP_ID_BASIC 0 36 37 #define is_bar(offset) \ 38 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \ 39 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4)) 40 41 /* 42 * Lengths of PCI Config Capabilities 43 * 0: Removed from the user visible capability list 44 * FF: Variable length 45 */ 46 static const u8 pci_cap_length[PCI_CAP_ID_MAX + 1] = { 47 [PCI_CAP_ID_BASIC] = PCI_STD_HEADER_SIZEOF, /* pci config header */ 48 [PCI_CAP_ID_PM] = PCI_PM_SIZEOF, 49 [PCI_CAP_ID_AGP] = PCI_AGP_SIZEOF, 50 [PCI_CAP_ID_VPD] = PCI_CAP_VPD_SIZEOF, 51 [PCI_CAP_ID_SLOTID] = 0, /* bridge - don't care */ 52 [PCI_CAP_ID_MSI] = 0xFF, /* 10, 14, 20, or 24 */ 53 [PCI_CAP_ID_CHSWP] = 0, /* cpci - not yet */ 54 [PCI_CAP_ID_PCIX] = 0xFF, /* 8 or 24 */ 55 [PCI_CAP_ID_HT] = 0xFF, /* hypertransport */ 56 [PCI_CAP_ID_VNDR] = 0xFF, /* variable */ 57 [PCI_CAP_ID_DBG] = 0, /* debug - don't care */ 58 [PCI_CAP_ID_CCRC] = 0, /* cpci - not yet */ 59 [PCI_CAP_ID_SHPC] = 0, /* hotswap - not yet */ 60 [PCI_CAP_ID_SSVID] = 0, /* bridge - don't care */ 61 [PCI_CAP_ID_AGP3] = 0, /* AGP8x - not yet */ 62 [PCI_CAP_ID_SECDEV] = 0, /* secure device not yet */ 63 [PCI_CAP_ID_EXP] = 0xFF, /* 20 or 44 */ 64 [PCI_CAP_ID_MSIX] = PCI_CAP_MSIX_SIZEOF, 65 [PCI_CAP_ID_SATA] = 0xFF, 66 [PCI_CAP_ID_AF] = PCI_CAP_AF_SIZEOF, 67 }; 68 69 /* 70 * Lengths of PCIe/PCI-X Extended Config Capabilities 71 * 0: Removed or masked from the user visible capability list 72 * FF: Variable length 73 */ 74 static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = { 75 [PCI_EXT_CAP_ID_ERR] = PCI_ERR_ROOT_COMMAND, 76 [PCI_EXT_CAP_ID_VC] = 0xFF, 77 [PCI_EXT_CAP_ID_DSN] = PCI_EXT_CAP_DSN_SIZEOF, 78 [PCI_EXT_CAP_ID_PWR] = PCI_EXT_CAP_PWR_SIZEOF, 79 [PCI_EXT_CAP_ID_RCLD] = 0, /* root only - don't care */ 80 [PCI_EXT_CAP_ID_RCILC] = 0, /* root only - don't care */ 81 [PCI_EXT_CAP_ID_RCEC] = 0, /* root only - don't care */ 82 [PCI_EXT_CAP_ID_MFVC] = 0xFF, 83 [PCI_EXT_CAP_ID_VC9] = 0xFF, /* same as CAP_ID_VC */ 84 [PCI_EXT_CAP_ID_RCRB] = 0, /* root only - don't care */ 85 [PCI_EXT_CAP_ID_VNDR] = 0xFF, 86 [PCI_EXT_CAP_ID_CAC] = 0, /* obsolete */ 87 [PCI_EXT_CAP_ID_ACS] = 0xFF, 88 [PCI_EXT_CAP_ID_ARI] = PCI_EXT_CAP_ARI_SIZEOF, 89 [PCI_EXT_CAP_ID_ATS] = PCI_EXT_CAP_ATS_SIZEOF, 90 [PCI_EXT_CAP_ID_SRIOV] = PCI_EXT_CAP_SRIOV_SIZEOF, 91 [PCI_EXT_CAP_ID_MRIOV] = 0, /* not yet */ 92 [PCI_EXT_CAP_ID_MCAST] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF, 93 [PCI_EXT_CAP_ID_PRI] = PCI_EXT_CAP_PRI_SIZEOF, 94 [PCI_EXT_CAP_ID_AMD_XXX] = 0, /* not yet */ 95 [PCI_EXT_CAP_ID_REBAR] = 0xFF, 96 [PCI_EXT_CAP_ID_DPA] = 0xFF, 97 [PCI_EXT_CAP_ID_TPH] = 0xFF, 98 [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF, 99 [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */ 100 [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */ 101 [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */ 102 }; 103 104 /* 105 * Read/Write Permission Bits - one bit for each bit in capability 106 * Any field can be read if it exists, but what is read depends on 107 * whether the field is 'virtualized', or just pass thru to the 108 * hardware. Any virtualized field is also virtualized for writes. 109 * Writes are only permitted if they have a 1 bit here. 110 */ 111 struct perm_bits { 112 u8 *virt; /* read/write virtual data, not hw */ 113 u8 *write; /* writeable bits */ 114 int (*readfn)(struct vfio_pci_device *vdev, int pos, int count, 115 struct perm_bits *perm, int offset, __le32 *val); 116 int (*writefn)(struct vfio_pci_device *vdev, int pos, int count, 117 struct perm_bits *perm, int offset, __le32 val); 118 }; 119 120 #define NO_VIRT 0 121 #define ALL_VIRT 0xFFFFFFFFU 122 #define NO_WRITE 0 123 #define ALL_WRITE 0xFFFFFFFFU 124 125 static int vfio_user_config_read(struct pci_dev *pdev, int offset, 126 __le32 *val, int count) 127 { 128 int ret = -EINVAL; 129 u32 tmp_val = 0; 130 131 switch (count) { 132 case 1: 133 { 134 u8 tmp; 135 ret = pci_user_read_config_byte(pdev, offset, &tmp); 136 tmp_val = tmp; 137 break; 138 } 139 case 2: 140 { 141 u16 tmp; 142 ret = pci_user_read_config_word(pdev, offset, &tmp); 143 tmp_val = tmp; 144 break; 145 } 146 case 4: 147 ret = pci_user_read_config_dword(pdev, offset, &tmp_val); 148 break; 149 } 150 151 *val = cpu_to_le32(tmp_val); 152 153 return ret; 154 } 155 156 static int vfio_user_config_write(struct pci_dev *pdev, int offset, 157 __le32 val, int count) 158 { 159 int ret = -EINVAL; 160 u32 tmp_val = le32_to_cpu(val); 161 162 switch (count) { 163 case 1: 164 ret = pci_user_write_config_byte(pdev, offset, tmp_val); 165 break; 166 case 2: 167 ret = pci_user_write_config_word(pdev, offset, tmp_val); 168 break; 169 case 4: 170 ret = pci_user_write_config_dword(pdev, offset, tmp_val); 171 break; 172 } 173 174 return ret; 175 } 176 177 static int vfio_default_config_read(struct vfio_pci_device *vdev, int pos, 178 int count, struct perm_bits *perm, 179 int offset, __le32 *val) 180 { 181 __le32 virt = 0; 182 183 memcpy(val, vdev->vconfig + pos, count); 184 185 memcpy(&virt, perm->virt + offset, count); 186 187 /* Any non-virtualized bits? */ 188 if (cpu_to_le32(~0U >> (32 - (count * 8))) != virt) { 189 struct pci_dev *pdev = vdev->pdev; 190 __le32 phys_val = 0; 191 int ret; 192 193 ret = vfio_user_config_read(pdev, pos, &phys_val, count); 194 if (ret) 195 return ret; 196 197 *val = (phys_val & ~virt) | (*val & virt); 198 } 199 200 return count; 201 } 202 203 static int vfio_default_config_write(struct vfio_pci_device *vdev, int pos, 204 int count, struct perm_bits *perm, 205 int offset, __le32 val) 206 { 207 __le32 virt = 0, write = 0; 208 209 memcpy(&write, perm->write + offset, count); 210 211 if (!write) 212 return count; /* drop, no writable bits */ 213 214 memcpy(&virt, perm->virt + offset, count); 215 216 /* Virtualized and writable bits go to vconfig */ 217 if (write & virt) { 218 __le32 virt_val = 0; 219 220 memcpy(&virt_val, vdev->vconfig + pos, count); 221 222 virt_val &= ~(write & virt); 223 virt_val |= (val & (write & virt)); 224 225 memcpy(vdev->vconfig + pos, &virt_val, count); 226 } 227 228 /* Non-virtualzed and writable bits go to hardware */ 229 if (write & ~virt) { 230 struct pci_dev *pdev = vdev->pdev; 231 __le32 phys_val = 0; 232 int ret; 233 234 ret = vfio_user_config_read(pdev, pos, &phys_val, count); 235 if (ret) 236 return ret; 237 238 phys_val &= ~(write & ~virt); 239 phys_val |= (val & (write & ~virt)); 240 241 ret = vfio_user_config_write(pdev, pos, phys_val, count); 242 if (ret) 243 return ret; 244 } 245 246 return count; 247 } 248 249 /* Allow direct read from hardware, except for capability next pointer */ 250 static int vfio_direct_config_read(struct vfio_pci_device *vdev, int pos, 251 int count, struct perm_bits *perm, 252 int offset, __le32 *val) 253 { 254 int ret; 255 256 ret = vfio_user_config_read(vdev->pdev, pos, val, count); 257 if (ret) 258 return ret; 259 260 if (pos >= PCI_CFG_SPACE_SIZE) { /* Extended cap header mangling */ 261 if (offset < 4) 262 memcpy(val, vdev->vconfig + pos, count); 263 } else if (pos >= PCI_STD_HEADER_SIZEOF) { /* Std cap mangling */ 264 if (offset == PCI_CAP_LIST_ID && count > 1) 265 memcpy(val, vdev->vconfig + pos, 266 min(PCI_CAP_FLAGS, count)); 267 else if (offset == PCI_CAP_LIST_NEXT) 268 memcpy(val, vdev->vconfig + pos, 1); 269 } 270 271 return count; 272 } 273 274 /* Raw access skips any kind of virtualization */ 275 static int vfio_raw_config_write(struct vfio_pci_device *vdev, int pos, 276 int count, struct perm_bits *perm, 277 int offset, __le32 val) 278 { 279 int ret; 280 281 ret = vfio_user_config_write(vdev->pdev, pos, val, count); 282 if (ret) 283 return ret; 284 285 return count; 286 } 287 288 static int vfio_raw_config_read(struct vfio_pci_device *vdev, int pos, 289 int count, struct perm_bits *perm, 290 int offset, __le32 *val) 291 { 292 int ret; 293 294 ret = vfio_user_config_read(vdev->pdev, pos, val, count); 295 if (ret) 296 return ret; 297 298 return count; 299 } 300 301 /* Virt access uses only virtualization */ 302 static int vfio_virt_config_write(struct vfio_pci_device *vdev, int pos, 303 int count, struct perm_bits *perm, 304 int offset, __le32 val) 305 { 306 memcpy(vdev->vconfig + pos, &val, count); 307 return count; 308 } 309 310 static int vfio_virt_config_read(struct vfio_pci_device *vdev, int pos, 311 int count, struct perm_bits *perm, 312 int offset, __le32 *val) 313 { 314 memcpy(val, vdev->vconfig + pos, count); 315 return count; 316 } 317 318 /* Default capability regions to read-only, no-virtualization */ 319 static struct perm_bits cap_perms[PCI_CAP_ID_MAX + 1] = { 320 [0 ... PCI_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } 321 }; 322 static struct perm_bits ecap_perms[PCI_EXT_CAP_ID_MAX + 1] = { 323 [0 ... PCI_EXT_CAP_ID_MAX] = { .readfn = vfio_direct_config_read } 324 }; 325 /* 326 * Default unassigned regions to raw read-write access. Some devices 327 * require this to function as they hide registers between the gaps in 328 * config space (be2net). Like MMIO and I/O port registers, we have 329 * to trust the hardware isolation. 330 */ 331 static struct perm_bits unassigned_perms = { 332 .readfn = vfio_raw_config_read, 333 .writefn = vfio_raw_config_write 334 }; 335 336 static struct perm_bits virt_perms = { 337 .readfn = vfio_virt_config_read, 338 .writefn = vfio_virt_config_write 339 }; 340 341 static void free_perm_bits(struct perm_bits *perm) 342 { 343 kfree(perm->virt); 344 kfree(perm->write); 345 perm->virt = NULL; 346 perm->write = NULL; 347 } 348 349 static int alloc_perm_bits(struct perm_bits *perm, int size) 350 { 351 /* 352 * Round up all permission bits to the next dword, this lets us 353 * ignore whether a read/write exceeds the defined capability 354 * structure. We can do this because: 355 * - Standard config space is already dword aligned 356 * - Capabilities are all dword aligned (bits 0:1 of next reserved) 357 * - Express capabilities defined as dword aligned 358 */ 359 size = round_up(size, 4); 360 361 /* 362 * Zero state is 363 * - All Readable, None Writeable, None Virtualized 364 */ 365 perm->virt = kzalloc(size, GFP_KERNEL); 366 perm->write = kzalloc(size, GFP_KERNEL); 367 if (!perm->virt || !perm->write) { 368 free_perm_bits(perm); 369 return -ENOMEM; 370 } 371 372 perm->readfn = vfio_default_config_read; 373 perm->writefn = vfio_default_config_write; 374 375 return 0; 376 } 377 378 /* 379 * Helper functions for filling in permission tables 380 */ 381 static inline void p_setb(struct perm_bits *p, int off, u8 virt, u8 write) 382 { 383 p->virt[off] = virt; 384 p->write[off] = write; 385 } 386 387 /* Handle endian-ness - pci and tables are little-endian */ 388 static inline void p_setw(struct perm_bits *p, int off, u16 virt, u16 write) 389 { 390 *(__le16 *)(&p->virt[off]) = cpu_to_le16(virt); 391 *(__le16 *)(&p->write[off]) = cpu_to_le16(write); 392 } 393 394 /* Handle endian-ness - pci and tables are little-endian */ 395 static inline void p_setd(struct perm_bits *p, int off, u32 virt, u32 write) 396 { 397 *(__le32 *)(&p->virt[off]) = cpu_to_le32(virt); 398 *(__le32 *)(&p->write[off]) = cpu_to_le32(write); 399 } 400 401 /* 402 * Restore the *real* BARs after we detect a FLR or backdoor reset. 403 * (backdoor = some device specific technique that we didn't catch) 404 */ 405 static void vfio_bar_restore(struct vfio_pci_device *vdev) 406 { 407 struct pci_dev *pdev = vdev->pdev; 408 u32 *rbar = vdev->rbar; 409 u16 cmd; 410 int i; 411 412 if (pdev->is_virtfn) 413 return; 414 415 pci_info(pdev, "%s: reset recovery - restoring BARs\n", __func__); 416 417 for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4, rbar++) 418 pci_user_write_config_dword(pdev, i, *rbar); 419 420 pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar); 421 422 if (vdev->nointx) { 423 pci_user_read_config_word(pdev, PCI_COMMAND, &cmd); 424 cmd |= PCI_COMMAND_INTX_DISABLE; 425 pci_user_write_config_word(pdev, PCI_COMMAND, cmd); 426 } 427 } 428 429 static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar) 430 { 431 unsigned long flags = pci_resource_flags(pdev, bar); 432 u32 val; 433 434 if (flags & IORESOURCE_IO) 435 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO); 436 437 val = PCI_BASE_ADDRESS_SPACE_MEMORY; 438 439 if (flags & IORESOURCE_PREFETCH) 440 val |= PCI_BASE_ADDRESS_MEM_PREFETCH; 441 442 if (flags & IORESOURCE_MEM_64) 443 val |= PCI_BASE_ADDRESS_MEM_TYPE_64; 444 445 return cpu_to_le32(val); 446 } 447 448 /* 449 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs 450 * to reflect the hardware capabilities. This implements BAR sizing. 451 */ 452 static void vfio_bar_fixup(struct vfio_pci_device *vdev) 453 { 454 struct pci_dev *pdev = vdev->pdev; 455 int i; 456 __le32 *bar; 457 u64 mask; 458 459 bar = (__le32 *)&vdev->vconfig[PCI_BASE_ADDRESS_0]; 460 461 for (i = PCI_STD_RESOURCES; i <= PCI_STD_RESOURCE_END; i++, bar++) { 462 if (!pci_resource_start(pdev, i)) { 463 *bar = 0; /* Unmapped by host = unimplemented to user */ 464 continue; 465 } 466 467 mask = ~(pci_resource_len(pdev, i) - 1); 468 469 *bar &= cpu_to_le32((u32)mask); 470 *bar |= vfio_generate_bar_flags(pdev, i); 471 472 if (*bar & cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64)) { 473 bar++; 474 *bar &= cpu_to_le32((u32)(mask >> 32)); 475 i++; 476 } 477 } 478 479 bar = (__le32 *)&vdev->vconfig[PCI_ROM_ADDRESS]; 480 481 /* 482 * NB. REGION_INFO will have reported zero size if we weren't able 483 * to read the ROM, but we still return the actual BAR size here if 484 * it exists (or the shadow ROM space). 485 */ 486 if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) { 487 mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1); 488 mask |= PCI_ROM_ADDRESS_ENABLE; 489 *bar &= cpu_to_le32((u32)mask); 490 } else if (pdev->resource[PCI_ROM_RESOURCE].flags & 491 IORESOURCE_ROM_SHADOW) { 492 mask = ~(0x20000 - 1); 493 mask |= PCI_ROM_ADDRESS_ENABLE; 494 *bar &= cpu_to_le32((u32)mask); 495 } else 496 *bar = 0; 497 498 vdev->bardirty = false; 499 } 500 501 static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos, 502 int count, struct perm_bits *perm, 503 int offset, __le32 *val) 504 { 505 if (is_bar(offset)) /* pos == offset for basic config */ 506 vfio_bar_fixup(vdev); 507 508 count = vfio_default_config_read(vdev, pos, count, perm, offset, val); 509 510 /* Mask in virtual memory enable for SR-IOV devices */ 511 if (offset == PCI_COMMAND && vdev->pdev->is_virtfn) { 512 u16 cmd = le16_to_cpu(*(__le16 *)&vdev->vconfig[PCI_COMMAND]); 513 u32 tmp_val = le32_to_cpu(*val); 514 515 tmp_val |= cmd & PCI_COMMAND_MEMORY; 516 *val = cpu_to_le32(tmp_val); 517 } 518 519 return count; 520 } 521 522 /* Test whether BARs match the value we think they should contain */ 523 static bool vfio_need_bar_restore(struct vfio_pci_device *vdev) 524 { 525 int i = 0, pos = PCI_BASE_ADDRESS_0, ret; 526 u32 bar; 527 528 for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) { 529 if (vdev->rbar[i]) { 530 ret = pci_user_read_config_dword(vdev->pdev, pos, &bar); 531 if (ret || vdev->rbar[i] != bar) 532 return true; 533 } 534 } 535 536 return false; 537 } 538 539 static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos, 540 int count, struct perm_bits *perm, 541 int offset, __le32 val) 542 { 543 struct pci_dev *pdev = vdev->pdev; 544 __le16 *virt_cmd; 545 u16 new_cmd = 0; 546 int ret; 547 548 virt_cmd = (__le16 *)&vdev->vconfig[PCI_COMMAND]; 549 550 if (offset == PCI_COMMAND) { 551 bool phys_mem, virt_mem, new_mem, phys_io, virt_io, new_io; 552 u16 phys_cmd; 553 554 ret = pci_user_read_config_word(pdev, PCI_COMMAND, &phys_cmd); 555 if (ret) 556 return ret; 557 558 new_cmd = le32_to_cpu(val); 559 560 phys_mem = !!(phys_cmd & PCI_COMMAND_MEMORY); 561 virt_mem = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_MEMORY); 562 new_mem = !!(new_cmd & PCI_COMMAND_MEMORY); 563 564 phys_io = !!(phys_cmd & PCI_COMMAND_IO); 565 virt_io = !!(le16_to_cpu(*virt_cmd) & PCI_COMMAND_IO); 566 new_io = !!(new_cmd & PCI_COMMAND_IO); 567 568 /* 569 * If the user is writing mem/io enable (new_mem/io) and we 570 * think it's already enabled (virt_mem/io), but the hardware 571 * shows it disabled (phys_mem/io, then the device has 572 * undergone some kind of backdoor reset and needs to be 573 * restored before we allow it to enable the bars. 574 * SR-IOV devices will trigger this, but we catch them later 575 */ 576 if ((new_mem && virt_mem && !phys_mem) || 577 (new_io && virt_io && !phys_io) || 578 vfio_need_bar_restore(vdev)) 579 vfio_bar_restore(vdev); 580 } 581 582 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 583 if (count < 0) 584 return count; 585 586 /* 587 * Save current memory/io enable bits in vconfig to allow for 588 * the test above next time. 589 */ 590 if (offset == PCI_COMMAND) { 591 u16 mask = PCI_COMMAND_MEMORY | PCI_COMMAND_IO; 592 593 *virt_cmd &= cpu_to_le16(~mask); 594 *virt_cmd |= cpu_to_le16(new_cmd & mask); 595 } 596 597 /* Emulate INTx disable */ 598 if (offset >= PCI_COMMAND && offset <= PCI_COMMAND + 1) { 599 bool virt_intx_disable; 600 601 virt_intx_disable = !!(le16_to_cpu(*virt_cmd) & 602 PCI_COMMAND_INTX_DISABLE); 603 604 if (virt_intx_disable && !vdev->virq_disabled) { 605 vdev->virq_disabled = true; 606 vfio_pci_intx_mask(vdev); 607 } else if (!virt_intx_disable && vdev->virq_disabled) { 608 vdev->virq_disabled = false; 609 vfio_pci_intx_unmask(vdev); 610 } 611 } 612 613 if (is_bar(offset)) 614 vdev->bardirty = true; 615 616 return count; 617 } 618 619 /* Permissions for the Basic PCI Header */ 620 static int __init init_pci_cap_basic_perm(struct perm_bits *perm) 621 { 622 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF)) 623 return -ENOMEM; 624 625 perm->readfn = vfio_basic_config_read; 626 perm->writefn = vfio_basic_config_write; 627 628 /* Virtualized for SR-IOV functions, which just have FFFF */ 629 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE); 630 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE); 631 632 /* 633 * Virtualize INTx disable, we use it internally for interrupt 634 * control and can emulate it for non-PCI 2.3 devices. 635 */ 636 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE); 637 638 /* Virtualize capability list, we might want to skip/disable */ 639 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE); 640 641 /* No harm to write */ 642 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE); 643 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE); 644 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE); 645 646 /* Virtualize all bars, can't touch the real ones */ 647 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE); 648 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE); 649 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE); 650 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE); 651 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE); 652 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE); 653 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE); 654 655 /* Allow us to adjust capability chain */ 656 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE); 657 658 /* Sometimes used by sw, just virtualize */ 659 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE); 660 661 /* Virtualize interrupt pin to allow hiding INTx */ 662 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE); 663 664 return 0; 665 } 666 667 static int vfio_pm_config_write(struct vfio_pci_device *vdev, int pos, 668 int count, struct perm_bits *perm, 669 int offset, __le32 val) 670 { 671 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 672 if (count < 0) 673 return count; 674 675 if (offset == PCI_PM_CTRL) { 676 pci_power_t state; 677 678 switch (le32_to_cpu(val) & PCI_PM_CTRL_STATE_MASK) { 679 case 0: 680 state = PCI_D0; 681 break; 682 case 1: 683 state = PCI_D1; 684 break; 685 case 2: 686 state = PCI_D2; 687 break; 688 case 3: 689 state = PCI_D3hot; 690 break; 691 } 692 693 vfio_pci_set_power_state(vdev, state); 694 } 695 696 return count; 697 } 698 699 /* Permissions for the Power Management capability */ 700 static int __init init_pci_cap_pm_perm(struct perm_bits *perm) 701 { 702 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM])) 703 return -ENOMEM; 704 705 perm->writefn = vfio_pm_config_write; 706 707 /* 708 * We always virtualize the next field so we can remove 709 * capabilities from the chain if we want to. 710 */ 711 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 712 713 /* 714 * Power management is defined *per function*, so we can let 715 * the user change power state, but we trap and initiate the 716 * change ourselves, so the state bits are read-only. 717 */ 718 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK); 719 return 0; 720 } 721 722 static int vfio_vpd_config_write(struct vfio_pci_device *vdev, int pos, 723 int count, struct perm_bits *perm, 724 int offset, __le32 val) 725 { 726 struct pci_dev *pdev = vdev->pdev; 727 __le16 *paddr = (__le16 *)(vdev->vconfig + pos - offset + PCI_VPD_ADDR); 728 __le32 *pdata = (__le32 *)(vdev->vconfig + pos - offset + PCI_VPD_DATA); 729 u16 addr; 730 u32 data; 731 732 /* 733 * Write through to emulation. If the write includes the upper byte 734 * of PCI_VPD_ADDR, then the PCI_VPD_ADDR_F bit is written and we 735 * have work to do. 736 */ 737 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 738 if (count < 0 || offset > PCI_VPD_ADDR + 1 || 739 offset + count <= PCI_VPD_ADDR + 1) 740 return count; 741 742 addr = le16_to_cpu(*paddr); 743 744 if (addr & PCI_VPD_ADDR_F) { 745 data = le32_to_cpu(*pdata); 746 if (pci_write_vpd(pdev, addr & ~PCI_VPD_ADDR_F, 4, &data) != 4) 747 return count; 748 } else { 749 data = 0; 750 if (pci_read_vpd(pdev, addr, 4, &data) < 0) 751 return count; 752 *pdata = cpu_to_le32(data); 753 } 754 755 /* 756 * Toggle PCI_VPD_ADDR_F in the emulated PCI_VPD_ADDR register to 757 * signal completion. If an error occurs above, we assume that not 758 * toggling this bit will induce a driver timeout. 759 */ 760 addr ^= PCI_VPD_ADDR_F; 761 *paddr = cpu_to_le16(addr); 762 763 return count; 764 } 765 766 /* Permissions for Vital Product Data capability */ 767 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm) 768 { 769 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD])) 770 return -ENOMEM; 771 772 perm->writefn = vfio_vpd_config_write; 773 774 /* 775 * We always virtualize the next field so we can remove 776 * capabilities from the chain if we want to. 777 */ 778 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 779 780 /* 781 * Both the address and data registers are virtualized to 782 * enable access through the pci_vpd_read/write functions 783 */ 784 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE); 785 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE); 786 787 return 0; 788 } 789 790 /* Permissions for PCI-X capability */ 791 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm) 792 { 793 /* Alloc 24, but only 8 are used in v0 */ 794 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2)) 795 return -ENOMEM; 796 797 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 798 799 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE); 800 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE); 801 return 0; 802 } 803 804 static int vfio_exp_config_write(struct vfio_pci_device *vdev, int pos, 805 int count, struct perm_bits *perm, 806 int offset, __le32 val) 807 { 808 __le16 *ctrl = (__le16 *)(vdev->vconfig + pos - 809 offset + PCI_EXP_DEVCTL); 810 int readrq = le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ; 811 812 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 813 if (count < 0) 814 return count; 815 816 /* 817 * The FLR bit is virtualized, if set and the device supports PCIe 818 * FLR, issue a reset_function. Regardless, clear the bit, the spec 819 * requires it to be always read as zero. NB, reset_function might 820 * not use a PCIe FLR, we don't have that level of granularity. 821 */ 822 if (*ctrl & cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR)) { 823 u32 cap; 824 int ret; 825 826 *ctrl &= ~cpu_to_le16(PCI_EXP_DEVCTL_BCR_FLR); 827 828 ret = pci_user_read_config_dword(vdev->pdev, 829 pos - offset + PCI_EXP_DEVCAP, 830 &cap); 831 832 if (!ret && (cap & PCI_EXP_DEVCAP_FLR)) 833 pci_try_reset_function(vdev->pdev); 834 } 835 836 /* 837 * MPS is virtualized to the user, writes do not change the physical 838 * register since determining a proper MPS value requires a system wide 839 * device view. The MRRS is largely independent of MPS, but since the 840 * user does not have that system-wide view, they might set a safe, but 841 * inefficiently low value. Here we allow writes through to hardware, 842 * but we set the floor to the physical device MPS setting, so that 843 * we can at least use full TLPs, as defined by the MPS value. 844 * 845 * NB, if any devices actually depend on an artificially low MRRS 846 * setting, this will need to be revisited, perhaps with a quirk 847 * though pcie_set_readrq(). 848 */ 849 if (readrq != (le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ)) { 850 readrq = 128 << 851 ((le16_to_cpu(*ctrl) & PCI_EXP_DEVCTL_READRQ) >> 12); 852 readrq = max(readrq, pcie_get_mps(vdev->pdev)); 853 854 pcie_set_readrq(vdev->pdev, readrq); 855 } 856 857 return count; 858 } 859 860 /* Permissions for PCI Express capability */ 861 static int __init init_pci_cap_exp_perm(struct perm_bits *perm) 862 { 863 /* Alloc largest of possible sizes */ 864 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2)) 865 return -ENOMEM; 866 867 perm->writefn = vfio_exp_config_write; 868 869 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 870 871 /* 872 * Allow writes to device control fields, except devctl_phantom, 873 * which could confuse IOMMU, MPS, which can break communication 874 * with other physical devices, and the ARI bit in devctl2, which 875 * is set at probe time. FLR and MRRS get virtualized via our 876 * writefn. 877 */ 878 p_setw(perm, PCI_EXP_DEVCTL, 879 PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_PAYLOAD | 880 PCI_EXP_DEVCTL_READRQ, ~PCI_EXP_DEVCTL_PHANTOM); 881 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI); 882 return 0; 883 } 884 885 static int vfio_af_config_write(struct vfio_pci_device *vdev, int pos, 886 int count, struct perm_bits *perm, 887 int offset, __le32 val) 888 { 889 u8 *ctrl = vdev->vconfig + pos - offset + PCI_AF_CTRL; 890 891 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 892 if (count < 0) 893 return count; 894 895 /* 896 * The FLR bit is virtualized, if set and the device supports AF 897 * FLR, issue a reset_function. Regardless, clear the bit, the spec 898 * requires it to be always read as zero. NB, reset_function might 899 * not use an AF FLR, we don't have that level of granularity. 900 */ 901 if (*ctrl & PCI_AF_CTRL_FLR) { 902 u8 cap; 903 int ret; 904 905 *ctrl &= ~PCI_AF_CTRL_FLR; 906 907 ret = pci_user_read_config_byte(vdev->pdev, 908 pos - offset + PCI_AF_CAP, 909 &cap); 910 911 if (!ret && (cap & PCI_AF_CAP_FLR) && (cap & PCI_AF_CAP_TP)) 912 pci_try_reset_function(vdev->pdev); 913 } 914 915 return count; 916 } 917 918 /* Permissions for Advanced Function capability */ 919 static int __init init_pci_cap_af_perm(struct perm_bits *perm) 920 { 921 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF])) 922 return -ENOMEM; 923 924 perm->writefn = vfio_af_config_write; 925 926 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 927 p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR); 928 return 0; 929 } 930 931 /* Permissions for Advanced Error Reporting extended capability */ 932 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm) 933 { 934 u32 mask; 935 936 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR])) 937 return -ENOMEM; 938 939 /* 940 * Virtualize the first dword of all express capabilities 941 * because it includes the next pointer. This lets us later 942 * remove capabilities from the chain if we need to. 943 */ 944 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 945 946 /* Writable bits mask */ 947 mask = PCI_ERR_UNC_UND | /* Undefined */ 948 PCI_ERR_UNC_DLP | /* Data Link Protocol */ 949 PCI_ERR_UNC_SURPDN | /* Surprise Down */ 950 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */ 951 PCI_ERR_UNC_FCP | /* Flow Control Protocol */ 952 PCI_ERR_UNC_COMP_TIME | /* Completion Timeout */ 953 PCI_ERR_UNC_COMP_ABORT | /* Completer Abort */ 954 PCI_ERR_UNC_UNX_COMP | /* Unexpected Completion */ 955 PCI_ERR_UNC_RX_OVER | /* Receiver Overflow */ 956 PCI_ERR_UNC_MALF_TLP | /* Malformed TLP */ 957 PCI_ERR_UNC_ECRC | /* ECRC Error Status */ 958 PCI_ERR_UNC_UNSUP | /* Unsupported Request */ 959 PCI_ERR_UNC_ACSV | /* ACS Violation */ 960 PCI_ERR_UNC_INTN | /* internal error */ 961 PCI_ERR_UNC_MCBTLP | /* MC blocked TLP */ 962 PCI_ERR_UNC_ATOMEG | /* Atomic egress blocked */ 963 PCI_ERR_UNC_TLPPRE; /* TLP prefix blocked */ 964 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask); 965 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask); 966 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask); 967 968 mask = PCI_ERR_COR_RCVR | /* Receiver Error Status */ 969 PCI_ERR_COR_BAD_TLP | /* Bad TLP Status */ 970 PCI_ERR_COR_BAD_DLLP | /* Bad DLLP Status */ 971 PCI_ERR_COR_REP_ROLL | /* REPLAY_NUM Rollover */ 972 PCI_ERR_COR_REP_TIMER | /* Replay Timer Timeout */ 973 PCI_ERR_COR_ADV_NFAT | /* Advisory Non-Fatal */ 974 PCI_ERR_COR_INTERNAL | /* Corrected Internal */ 975 PCI_ERR_COR_LOG_OVER; /* Header Log Overflow */ 976 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask); 977 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask); 978 979 mask = PCI_ERR_CAP_ECRC_GENE | /* ECRC Generation Enable */ 980 PCI_ERR_CAP_ECRC_CHKE; /* ECRC Check Enable */ 981 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask); 982 return 0; 983 } 984 985 /* Permissions for Power Budgeting extended capability */ 986 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm) 987 { 988 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR])) 989 return -ENOMEM; 990 991 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 992 993 /* Writing the data selector is OK, the info is still read-only */ 994 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE); 995 return 0; 996 } 997 998 /* 999 * Initialize the shared permission tables 1000 */ 1001 void vfio_pci_uninit_perm_bits(void) 1002 { 1003 free_perm_bits(&cap_perms[PCI_CAP_ID_BASIC]); 1004 1005 free_perm_bits(&cap_perms[PCI_CAP_ID_PM]); 1006 free_perm_bits(&cap_perms[PCI_CAP_ID_VPD]); 1007 free_perm_bits(&cap_perms[PCI_CAP_ID_PCIX]); 1008 free_perm_bits(&cap_perms[PCI_CAP_ID_EXP]); 1009 free_perm_bits(&cap_perms[PCI_CAP_ID_AF]); 1010 1011 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_ERR]); 1012 free_perm_bits(&ecap_perms[PCI_EXT_CAP_ID_PWR]); 1013 } 1014 1015 int __init vfio_pci_init_perm_bits(void) 1016 { 1017 int ret; 1018 1019 /* Basic config space */ 1020 ret = init_pci_cap_basic_perm(&cap_perms[PCI_CAP_ID_BASIC]); 1021 1022 /* Capabilities */ 1023 ret |= init_pci_cap_pm_perm(&cap_perms[PCI_CAP_ID_PM]); 1024 ret |= init_pci_cap_vpd_perm(&cap_perms[PCI_CAP_ID_VPD]); 1025 ret |= init_pci_cap_pcix_perm(&cap_perms[PCI_CAP_ID_PCIX]); 1026 cap_perms[PCI_CAP_ID_VNDR].writefn = vfio_raw_config_write; 1027 ret |= init_pci_cap_exp_perm(&cap_perms[PCI_CAP_ID_EXP]); 1028 ret |= init_pci_cap_af_perm(&cap_perms[PCI_CAP_ID_AF]); 1029 1030 /* Extended capabilities */ 1031 ret |= init_pci_ext_cap_err_perm(&ecap_perms[PCI_EXT_CAP_ID_ERR]); 1032 ret |= init_pci_ext_cap_pwr_perm(&ecap_perms[PCI_EXT_CAP_ID_PWR]); 1033 ecap_perms[PCI_EXT_CAP_ID_VNDR].writefn = vfio_raw_config_write; 1034 1035 if (ret) 1036 vfio_pci_uninit_perm_bits(); 1037 1038 return ret; 1039 } 1040 1041 static int vfio_find_cap_start(struct vfio_pci_device *vdev, int pos) 1042 { 1043 u8 cap; 1044 int base = (pos >= PCI_CFG_SPACE_SIZE) ? PCI_CFG_SPACE_SIZE : 1045 PCI_STD_HEADER_SIZEOF; 1046 cap = vdev->pci_config_map[pos]; 1047 1048 if (cap == PCI_CAP_ID_BASIC) 1049 return 0; 1050 1051 /* XXX Can we have to abutting capabilities of the same type? */ 1052 while (pos - 1 >= base && vdev->pci_config_map[pos - 1] == cap) 1053 pos--; 1054 1055 return pos; 1056 } 1057 1058 static int vfio_msi_config_read(struct vfio_pci_device *vdev, int pos, 1059 int count, struct perm_bits *perm, 1060 int offset, __le32 *val) 1061 { 1062 /* Update max available queue size from msi_qmax */ 1063 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) { 1064 __le16 *flags; 1065 int start; 1066 1067 start = vfio_find_cap_start(vdev, pos); 1068 1069 flags = (__le16 *)&vdev->vconfig[start]; 1070 1071 *flags &= cpu_to_le16(~PCI_MSI_FLAGS_QMASK); 1072 *flags |= cpu_to_le16(vdev->msi_qmax << 1); 1073 } 1074 1075 return vfio_default_config_read(vdev, pos, count, perm, offset, val); 1076 } 1077 1078 static int vfio_msi_config_write(struct vfio_pci_device *vdev, int pos, 1079 int count, struct perm_bits *perm, 1080 int offset, __le32 val) 1081 { 1082 count = vfio_default_config_write(vdev, pos, count, perm, offset, val); 1083 if (count < 0) 1084 return count; 1085 1086 /* Fixup and write configured queue size and enable to hardware */ 1087 if (offset <= PCI_MSI_FLAGS && offset + count >= PCI_MSI_FLAGS) { 1088 __le16 *pflags; 1089 u16 flags; 1090 int start, ret; 1091 1092 start = vfio_find_cap_start(vdev, pos); 1093 1094 pflags = (__le16 *)&vdev->vconfig[start + PCI_MSI_FLAGS]; 1095 1096 flags = le16_to_cpu(*pflags); 1097 1098 /* MSI is enabled via ioctl */ 1099 if (!is_msi(vdev)) 1100 flags &= ~PCI_MSI_FLAGS_ENABLE; 1101 1102 /* Check queue size */ 1103 if ((flags & PCI_MSI_FLAGS_QSIZE) >> 4 > vdev->msi_qmax) { 1104 flags &= ~PCI_MSI_FLAGS_QSIZE; 1105 flags |= vdev->msi_qmax << 4; 1106 } 1107 1108 /* Write back to virt and to hardware */ 1109 *pflags = cpu_to_le16(flags); 1110 ret = pci_user_write_config_word(vdev->pdev, 1111 start + PCI_MSI_FLAGS, 1112 flags); 1113 if (ret) 1114 return ret; 1115 } 1116 1117 return count; 1118 } 1119 1120 /* 1121 * MSI determination is per-device, so this routine gets used beyond 1122 * initialization time. Don't add __init 1123 */ 1124 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags) 1125 { 1126 if (alloc_perm_bits(perm, len)) 1127 return -ENOMEM; 1128 1129 perm->readfn = vfio_msi_config_read; 1130 perm->writefn = vfio_msi_config_write; 1131 1132 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE); 1133 1134 /* 1135 * The upper byte of the control register is reserved, 1136 * just setup the lower byte. 1137 */ 1138 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE); 1139 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE); 1140 if (flags & PCI_MSI_FLAGS_64BIT) { 1141 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE); 1142 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE); 1143 if (flags & PCI_MSI_FLAGS_MASKBIT) { 1144 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE); 1145 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE); 1146 } 1147 } else { 1148 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE); 1149 if (flags & PCI_MSI_FLAGS_MASKBIT) { 1150 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE); 1151 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE); 1152 } 1153 } 1154 return 0; 1155 } 1156 1157 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */ 1158 static int vfio_msi_cap_len(struct vfio_pci_device *vdev, u8 pos) 1159 { 1160 struct pci_dev *pdev = vdev->pdev; 1161 int len, ret; 1162 u16 flags; 1163 1164 ret = pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &flags); 1165 if (ret) 1166 return pcibios_err_to_errno(ret); 1167 1168 len = 10; /* Minimum size */ 1169 if (flags & PCI_MSI_FLAGS_64BIT) 1170 len += 4; 1171 if (flags & PCI_MSI_FLAGS_MASKBIT) 1172 len += 10; 1173 1174 if (vdev->msi_perm) 1175 return len; 1176 1177 vdev->msi_perm = kmalloc(sizeof(struct perm_bits), GFP_KERNEL); 1178 if (!vdev->msi_perm) 1179 return -ENOMEM; 1180 1181 ret = init_pci_cap_msi_perm(vdev->msi_perm, len, flags); 1182 if (ret) { 1183 kfree(vdev->msi_perm); 1184 return ret; 1185 } 1186 1187 return len; 1188 } 1189 1190 /* Determine extended capability length for VC (2 & 9) and MFVC */ 1191 static int vfio_vc_cap_len(struct vfio_pci_device *vdev, u16 pos) 1192 { 1193 struct pci_dev *pdev = vdev->pdev; 1194 u32 tmp; 1195 int ret, evcc, phases, vc_arb; 1196 int len = PCI_CAP_VC_BASE_SIZEOF; 1197 1198 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP1, &tmp); 1199 if (ret) 1200 return pcibios_err_to_errno(ret); 1201 1202 evcc = tmp & PCI_VC_CAP1_EVCC; /* extended vc count */ 1203 ret = pci_read_config_dword(pdev, pos + PCI_VC_PORT_CAP2, &tmp); 1204 if (ret) 1205 return pcibios_err_to_errno(ret); 1206 1207 if (tmp & PCI_VC_CAP2_128_PHASE) 1208 phases = 128; 1209 else if (tmp & PCI_VC_CAP2_64_PHASE) 1210 phases = 64; 1211 else if (tmp & PCI_VC_CAP2_32_PHASE) 1212 phases = 32; 1213 else 1214 phases = 0; 1215 1216 vc_arb = phases * 4; 1217 1218 /* 1219 * Port arbitration tables are root & switch only; 1220 * function arbitration tables are function 0 only. 1221 * In either case, we'll never let user write them so 1222 * we don't care how big they are 1223 */ 1224 len += (1 + evcc) * PCI_CAP_VC_PER_VC_SIZEOF; 1225 if (vc_arb) { 1226 len = round_up(len, 16); 1227 len += vc_arb / 8; 1228 } 1229 return len; 1230 } 1231 1232 static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos) 1233 { 1234 struct pci_dev *pdev = vdev->pdev; 1235 u32 dword; 1236 u16 word; 1237 u8 byte; 1238 int ret; 1239 1240 switch (cap) { 1241 case PCI_CAP_ID_MSI: 1242 return vfio_msi_cap_len(vdev, pos); 1243 case PCI_CAP_ID_PCIX: 1244 ret = pci_read_config_word(pdev, pos + PCI_X_CMD, &word); 1245 if (ret) 1246 return pcibios_err_to_errno(ret); 1247 1248 if (PCI_X_CMD_VERSION(word)) { 1249 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) { 1250 /* Test for extended capabilities */ 1251 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, 1252 &dword); 1253 vdev->extended_caps = (dword != 0); 1254 } 1255 return PCI_CAP_PCIX_SIZEOF_V2; 1256 } else 1257 return PCI_CAP_PCIX_SIZEOF_V0; 1258 case PCI_CAP_ID_VNDR: 1259 /* length follows next field */ 1260 ret = pci_read_config_byte(pdev, pos + PCI_CAP_FLAGS, &byte); 1261 if (ret) 1262 return pcibios_err_to_errno(ret); 1263 1264 return byte; 1265 case PCI_CAP_ID_EXP: 1266 if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) { 1267 /* Test for extended capabilities */ 1268 pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword); 1269 vdev->extended_caps = (dword != 0); 1270 } 1271 1272 /* length based on version and type */ 1273 if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) { 1274 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END) 1275 return 0xc; /* "All Devices" only, no link */ 1276 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1; 1277 } else { 1278 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END) 1279 return 0x2c; /* No link */ 1280 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2; 1281 } 1282 case PCI_CAP_ID_HT: 1283 ret = pci_read_config_byte(pdev, pos + 3, &byte); 1284 if (ret) 1285 return pcibios_err_to_errno(ret); 1286 1287 return (byte & HT_3BIT_CAP_MASK) ? 1288 HT_CAP_SIZEOF_SHORT : HT_CAP_SIZEOF_LONG; 1289 case PCI_CAP_ID_SATA: 1290 ret = pci_read_config_byte(pdev, pos + PCI_SATA_REGS, &byte); 1291 if (ret) 1292 return pcibios_err_to_errno(ret); 1293 1294 byte &= PCI_SATA_REGS_MASK; 1295 if (byte == PCI_SATA_REGS_INLINE) 1296 return PCI_SATA_SIZEOF_LONG; 1297 else 1298 return PCI_SATA_SIZEOF_SHORT; 1299 default: 1300 pci_warn(pdev, "%s: unknown length for PCI cap %#x@%#x\n", 1301 __func__, cap, pos); 1302 } 1303 1304 return 0; 1305 } 1306 1307 static int vfio_ext_cap_len(struct vfio_pci_device *vdev, u16 ecap, u16 epos) 1308 { 1309 struct pci_dev *pdev = vdev->pdev; 1310 u8 byte; 1311 u32 dword; 1312 int ret; 1313 1314 switch (ecap) { 1315 case PCI_EXT_CAP_ID_VNDR: 1316 ret = pci_read_config_dword(pdev, epos + PCI_VSEC_HDR, &dword); 1317 if (ret) 1318 return pcibios_err_to_errno(ret); 1319 1320 return dword >> PCI_VSEC_HDR_LEN_SHIFT; 1321 case PCI_EXT_CAP_ID_VC: 1322 case PCI_EXT_CAP_ID_VC9: 1323 case PCI_EXT_CAP_ID_MFVC: 1324 return vfio_vc_cap_len(vdev, epos); 1325 case PCI_EXT_CAP_ID_ACS: 1326 ret = pci_read_config_byte(pdev, epos + PCI_ACS_CAP, &byte); 1327 if (ret) 1328 return pcibios_err_to_errno(ret); 1329 1330 if (byte & PCI_ACS_EC) { 1331 int bits; 1332 1333 ret = pci_read_config_byte(pdev, 1334 epos + PCI_ACS_EGRESS_BITS, 1335 &byte); 1336 if (ret) 1337 return pcibios_err_to_errno(ret); 1338 1339 bits = byte ? round_up(byte, 32) : 256; 1340 return 8 + (bits / 8); 1341 } 1342 return 8; 1343 1344 case PCI_EXT_CAP_ID_REBAR: 1345 ret = pci_read_config_byte(pdev, epos + PCI_REBAR_CTRL, &byte); 1346 if (ret) 1347 return pcibios_err_to_errno(ret); 1348 1349 byte &= PCI_REBAR_CTRL_NBAR_MASK; 1350 byte >>= PCI_REBAR_CTRL_NBAR_SHIFT; 1351 1352 return 4 + (byte * 8); 1353 case PCI_EXT_CAP_ID_DPA: 1354 ret = pci_read_config_byte(pdev, epos + PCI_DPA_CAP, &byte); 1355 if (ret) 1356 return pcibios_err_to_errno(ret); 1357 1358 byte &= PCI_DPA_CAP_SUBSTATE_MASK; 1359 return PCI_DPA_BASE_SIZEOF + byte + 1; 1360 case PCI_EXT_CAP_ID_TPH: 1361 ret = pci_read_config_dword(pdev, epos + PCI_TPH_CAP, &dword); 1362 if (ret) 1363 return pcibios_err_to_errno(ret); 1364 1365 if ((dword & PCI_TPH_CAP_LOC_MASK) == PCI_TPH_LOC_CAP) { 1366 int sts; 1367 1368 sts = dword & PCI_TPH_CAP_ST_MASK; 1369 sts >>= PCI_TPH_CAP_ST_SHIFT; 1370 return PCI_TPH_BASE_SIZEOF + (sts * 2) + 2; 1371 } 1372 return PCI_TPH_BASE_SIZEOF; 1373 default: 1374 pci_warn(pdev, "%s: unknown length for PCI ecap %#x@%#x\n", 1375 __func__, ecap, epos); 1376 } 1377 1378 return 0; 1379 } 1380 1381 static int vfio_fill_vconfig_bytes(struct vfio_pci_device *vdev, 1382 int offset, int size) 1383 { 1384 struct pci_dev *pdev = vdev->pdev; 1385 int ret = 0; 1386 1387 /* 1388 * We try to read physical config space in the largest chunks 1389 * we can, assuming that all of the fields support dword access. 1390 * pci_save_state() makes this same assumption and seems to do ok. 1391 */ 1392 while (size) { 1393 int filled; 1394 1395 if (size >= 4 && !(offset % 4)) { 1396 __le32 *dwordp = (__le32 *)&vdev->vconfig[offset]; 1397 u32 dword; 1398 1399 ret = pci_read_config_dword(pdev, offset, &dword); 1400 if (ret) 1401 return ret; 1402 *dwordp = cpu_to_le32(dword); 1403 filled = 4; 1404 } else if (size >= 2 && !(offset % 2)) { 1405 __le16 *wordp = (__le16 *)&vdev->vconfig[offset]; 1406 u16 word; 1407 1408 ret = pci_read_config_word(pdev, offset, &word); 1409 if (ret) 1410 return ret; 1411 *wordp = cpu_to_le16(word); 1412 filled = 2; 1413 } else { 1414 u8 *byte = &vdev->vconfig[offset]; 1415 ret = pci_read_config_byte(pdev, offset, byte); 1416 if (ret) 1417 return ret; 1418 filled = 1; 1419 } 1420 1421 offset += filled; 1422 size -= filled; 1423 } 1424 1425 return ret; 1426 } 1427 1428 static int vfio_cap_init(struct vfio_pci_device *vdev) 1429 { 1430 struct pci_dev *pdev = vdev->pdev; 1431 u8 *map = vdev->pci_config_map; 1432 u16 status; 1433 u8 pos, *prev, cap; 1434 int loops, ret, caps = 0; 1435 1436 /* Any capabilities? */ 1437 ret = pci_read_config_word(pdev, PCI_STATUS, &status); 1438 if (ret) 1439 return ret; 1440 1441 if (!(status & PCI_STATUS_CAP_LIST)) 1442 return 0; /* Done */ 1443 1444 ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos); 1445 if (ret) 1446 return ret; 1447 1448 /* Mark the previous position in case we want to skip a capability */ 1449 prev = &vdev->vconfig[PCI_CAPABILITY_LIST]; 1450 1451 /* We can bound our loop, capabilities are dword aligned */ 1452 loops = (PCI_CFG_SPACE_SIZE - PCI_STD_HEADER_SIZEOF) / PCI_CAP_SIZEOF; 1453 while (pos && loops--) { 1454 u8 next; 1455 int i, len = 0; 1456 1457 ret = pci_read_config_byte(pdev, pos, &cap); 1458 if (ret) 1459 return ret; 1460 1461 ret = pci_read_config_byte(pdev, 1462 pos + PCI_CAP_LIST_NEXT, &next); 1463 if (ret) 1464 return ret; 1465 1466 if (cap <= PCI_CAP_ID_MAX) { 1467 len = pci_cap_length[cap]; 1468 if (len == 0xFF) { /* Variable length */ 1469 len = vfio_cap_len(vdev, cap, pos); 1470 if (len < 0) 1471 return len; 1472 } 1473 } 1474 1475 if (!len) { 1476 pci_info(pdev, "%s: hiding cap %#x@%#x\n", __func__, 1477 cap, pos); 1478 *prev = next; 1479 pos = next; 1480 continue; 1481 } 1482 1483 /* Sanity check, do we overlap other capabilities? */ 1484 for (i = 0; i < len; i++) { 1485 if (likely(map[pos + i] == PCI_CAP_ID_INVALID)) 1486 continue; 1487 1488 pci_warn(pdev, "%s: PCI config conflict @%#x, was cap %#x now cap %#x\n", 1489 __func__, pos + i, map[pos + i], cap); 1490 } 1491 1492 BUILD_BUG_ON(PCI_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT); 1493 1494 memset(map + pos, cap, len); 1495 ret = vfio_fill_vconfig_bytes(vdev, pos, len); 1496 if (ret) 1497 return ret; 1498 1499 prev = &vdev->vconfig[pos + PCI_CAP_LIST_NEXT]; 1500 pos = next; 1501 caps++; 1502 } 1503 1504 /* If we didn't fill any capabilities, clear the status flag */ 1505 if (!caps) { 1506 __le16 *vstatus = (__le16 *)&vdev->vconfig[PCI_STATUS]; 1507 *vstatus &= ~cpu_to_le16(PCI_STATUS_CAP_LIST); 1508 } 1509 1510 return 0; 1511 } 1512 1513 static int vfio_ecap_init(struct vfio_pci_device *vdev) 1514 { 1515 struct pci_dev *pdev = vdev->pdev; 1516 u8 *map = vdev->pci_config_map; 1517 u16 epos; 1518 __le32 *prev = NULL; 1519 int loops, ret, ecaps = 0; 1520 1521 if (!vdev->extended_caps) 1522 return 0; 1523 1524 epos = PCI_CFG_SPACE_SIZE; 1525 1526 loops = (pdev->cfg_size - PCI_CFG_SPACE_SIZE) / PCI_CAP_SIZEOF; 1527 1528 while (loops-- && epos >= PCI_CFG_SPACE_SIZE) { 1529 u32 header; 1530 u16 ecap; 1531 int i, len = 0; 1532 bool hidden = false; 1533 1534 ret = pci_read_config_dword(pdev, epos, &header); 1535 if (ret) 1536 return ret; 1537 1538 ecap = PCI_EXT_CAP_ID(header); 1539 1540 if (ecap <= PCI_EXT_CAP_ID_MAX) { 1541 len = pci_ext_cap_length[ecap]; 1542 if (len == 0xFF) { 1543 len = vfio_ext_cap_len(vdev, ecap, epos); 1544 if (len < 0) 1545 return ret; 1546 } 1547 } 1548 1549 if (!len) { 1550 pci_info(pdev, "%s: hiding ecap %#x@%#x\n", 1551 __func__, ecap, epos); 1552 1553 /* If not the first in the chain, we can skip over it */ 1554 if (prev) { 1555 u32 val = epos = PCI_EXT_CAP_NEXT(header); 1556 *prev &= cpu_to_le32(~(0xffcU << 20)); 1557 *prev |= cpu_to_le32(val << 20); 1558 continue; 1559 } 1560 1561 /* 1562 * Otherwise, fill in a placeholder, the direct 1563 * readfn will virtualize this automatically 1564 */ 1565 len = PCI_CAP_SIZEOF; 1566 hidden = true; 1567 } 1568 1569 for (i = 0; i < len; i++) { 1570 if (likely(map[epos + i] == PCI_CAP_ID_INVALID)) 1571 continue; 1572 1573 pci_warn(pdev, "%s: PCI config conflict @%#x, was ecap %#x now ecap %#x\n", 1574 __func__, epos + i, map[epos + i], ecap); 1575 } 1576 1577 /* 1578 * Even though ecap is 2 bytes, we're currently a long way 1579 * from exceeding 1 byte capabilities. If we ever make it 1580 * up to 0xFE we'll need to up this to a two-byte, byte map. 1581 */ 1582 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX >= PCI_CAP_ID_INVALID_VIRT); 1583 1584 memset(map + epos, ecap, len); 1585 ret = vfio_fill_vconfig_bytes(vdev, epos, len); 1586 if (ret) 1587 return ret; 1588 1589 /* 1590 * If we're just using this capability to anchor the list, 1591 * hide the real ID. Only count real ecaps. XXX PCI spec 1592 * indicates to use cap id = 0, version = 0, next = 0 if 1593 * ecaps are absent, hope users check all the way to next. 1594 */ 1595 if (hidden) 1596 *(__le32 *)&vdev->vconfig[epos] &= 1597 cpu_to_le32((0xffcU << 20)); 1598 else 1599 ecaps++; 1600 1601 prev = (__le32 *)&vdev->vconfig[epos]; 1602 epos = PCI_EXT_CAP_NEXT(header); 1603 } 1604 1605 if (!ecaps) 1606 *(u32 *)&vdev->vconfig[PCI_CFG_SPACE_SIZE] = 0; 1607 1608 return 0; 1609 } 1610 1611 /* 1612 * Nag about hardware bugs, hopefully to have vendors fix them, but at least 1613 * to collect a list of dependencies for the VF INTx pin quirk below. 1614 */ 1615 static const struct pci_device_id known_bogus_vf_intx_pin[] = { 1616 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x270c) }, 1617 {} 1618 }; 1619 1620 /* 1621 * For each device we allocate a pci_config_map that indicates the 1622 * capability occupying each dword and thus the struct perm_bits we 1623 * use for read and write. We also allocate a virtualized config 1624 * space which tracks reads and writes to bits that we emulate for 1625 * the user. Initial values filled from device. 1626 * 1627 * Using shared struct perm_bits between all vfio-pci devices saves 1628 * us from allocating cfg_size buffers for virt and write for every 1629 * device. We could remove vconfig and allocate individual buffers 1630 * for each area requiring emulated bits, but the array of pointers 1631 * would be comparable in size (at least for standard config space). 1632 */ 1633 int vfio_config_init(struct vfio_pci_device *vdev) 1634 { 1635 struct pci_dev *pdev = vdev->pdev; 1636 u8 *map, *vconfig; 1637 int ret; 1638 1639 /* 1640 * Config space, caps and ecaps are all dword aligned, so we could 1641 * use one byte per dword to record the type. However, there are 1642 * no requiremenst on the length of a capability, so the gap between 1643 * capabilities needs byte granularity. 1644 */ 1645 map = kmalloc(pdev->cfg_size, GFP_KERNEL); 1646 if (!map) 1647 return -ENOMEM; 1648 1649 vconfig = kmalloc(pdev->cfg_size, GFP_KERNEL); 1650 if (!vconfig) { 1651 kfree(map); 1652 return -ENOMEM; 1653 } 1654 1655 vdev->pci_config_map = map; 1656 vdev->vconfig = vconfig; 1657 1658 memset(map, PCI_CAP_ID_BASIC, PCI_STD_HEADER_SIZEOF); 1659 memset(map + PCI_STD_HEADER_SIZEOF, PCI_CAP_ID_INVALID, 1660 pdev->cfg_size - PCI_STD_HEADER_SIZEOF); 1661 1662 ret = vfio_fill_vconfig_bytes(vdev, 0, PCI_STD_HEADER_SIZEOF); 1663 if (ret) 1664 goto out; 1665 1666 vdev->bardirty = true; 1667 1668 /* 1669 * XXX can we just pci_load_saved_state/pci_restore_state? 1670 * may need to rebuild vconfig after that 1671 */ 1672 1673 /* For restore after reset */ 1674 vdev->rbar[0] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_0]); 1675 vdev->rbar[1] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_1]); 1676 vdev->rbar[2] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_2]); 1677 vdev->rbar[3] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_3]); 1678 vdev->rbar[4] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_4]); 1679 vdev->rbar[5] = le32_to_cpu(*(__le32 *)&vconfig[PCI_BASE_ADDRESS_5]); 1680 vdev->rbar[6] = le32_to_cpu(*(__le32 *)&vconfig[PCI_ROM_ADDRESS]); 1681 1682 if (pdev->is_virtfn) { 1683 *(__le16 *)&vconfig[PCI_VENDOR_ID] = cpu_to_le16(pdev->vendor); 1684 *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device); 1685 1686 /* 1687 * Per SR-IOV spec rev 1.1, 3.4.1.18 the interrupt pin register 1688 * does not apply to VFs and VFs must implement this register 1689 * as read-only with value zero. Userspace is not readily able 1690 * to identify whether a device is a VF and thus that the pin 1691 * definition on the device is bogus should it violate this 1692 * requirement. We already virtualize the pin register for 1693 * other purposes, so we simply need to replace the bogus value 1694 * and consider VFs when we determine INTx IRQ count. 1695 */ 1696 if (vconfig[PCI_INTERRUPT_PIN] && 1697 !pci_match_id(known_bogus_vf_intx_pin, pdev)) 1698 pci_warn(pdev, 1699 "Hardware bug: VF reports bogus INTx pin %d\n", 1700 vconfig[PCI_INTERRUPT_PIN]); 1701 1702 vconfig[PCI_INTERRUPT_PIN] = 0; /* Gratuitous for good VFs */ 1703 } 1704 1705 if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx) 1706 vconfig[PCI_INTERRUPT_PIN] = 0; 1707 1708 ret = vfio_cap_init(vdev); 1709 if (ret) 1710 goto out; 1711 1712 ret = vfio_ecap_init(vdev); 1713 if (ret) 1714 goto out; 1715 1716 return 0; 1717 1718 out: 1719 kfree(map); 1720 vdev->pci_config_map = NULL; 1721 kfree(vconfig); 1722 vdev->vconfig = NULL; 1723 return pcibios_err_to_errno(ret); 1724 } 1725 1726 void vfio_config_free(struct vfio_pci_device *vdev) 1727 { 1728 kfree(vdev->vconfig); 1729 vdev->vconfig = NULL; 1730 kfree(vdev->pci_config_map); 1731 vdev->pci_config_map = NULL; 1732 kfree(vdev->msi_perm); 1733 vdev->msi_perm = NULL; 1734 } 1735 1736 /* 1737 * Find the remaining number of bytes in a dword that match the given 1738 * position. Stop at either the end of the capability or the dword boundary. 1739 */ 1740 static size_t vfio_pci_cap_remaining_dword(struct vfio_pci_device *vdev, 1741 loff_t pos) 1742 { 1743 u8 cap = vdev->pci_config_map[pos]; 1744 size_t i; 1745 1746 for (i = 1; (pos + i) % 4 && vdev->pci_config_map[pos + i] == cap; i++) 1747 /* nop */; 1748 1749 return i; 1750 } 1751 1752 static ssize_t vfio_config_do_rw(struct vfio_pci_device *vdev, char __user *buf, 1753 size_t count, loff_t *ppos, bool iswrite) 1754 { 1755 struct pci_dev *pdev = vdev->pdev; 1756 struct perm_bits *perm; 1757 __le32 val = 0; 1758 int cap_start = 0, offset; 1759 u8 cap_id; 1760 ssize_t ret; 1761 1762 if (*ppos < 0 || *ppos >= pdev->cfg_size || 1763 *ppos + count > pdev->cfg_size) 1764 return -EFAULT; 1765 1766 /* 1767 * Chop accesses into aligned chunks containing no more than a 1768 * single capability. Caller increments to the next chunk. 1769 */ 1770 count = min(count, vfio_pci_cap_remaining_dword(vdev, *ppos)); 1771 if (count >= 4 && !(*ppos % 4)) 1772 count = 4; 1773 else if (count >= 2 && !(*ppos % 2)) 1774 count = 2; 1775 else 1776 count = 1; 1777 1778 ret = count; 1779 1780 cap_id = vdev->pci_config_map[*ppos]; 1781 1782 if (cap_id == PCI_CAP_ID_INVALID) { 1783 perm = &unassigned_perms; 1784 cap_start = *ppos; 1785 } else if (cap_id == PCI_CAP_ID_INVALID_VIRT) { 1786 perm = &virt_perms; 1787 cap_start = *ppos; 1788 } else { 1789 if (*ppos >= PCI_CFG_SPACE_SIZE) { 1790 WARN_ON(cap_id > PCI_EXT_CAP_ID_MAX); 1791 1792 perm = &ecap_perms[cap_id]; 1793 cap_start = vfio_find_cap_start(vdev, *ppos); 1794 } else { 1795 WARN_ON(cap_id > PCI_CAP_ID_MAX); 1796 1797 perm = &cap_perms[cap_id]; 1798 1799 if (cap_id == PCI_CAP_ID_MSI) 1800 perm = vdev->msi_perm; 1801 1802 if (cap_id > PCI_CAP_ID_BASIC) 1803 cap_start = vfio_find_cap_start(vdev, *ppos); 1804 } 1805 } 1806 1807 WARN_ON(!cap_start && cap_id != PCI_CAP_ID_BASIC); 1808 WARN_ON(cap_start > *ppos); 1809 1810 offset = *ppos - cap_start; 1811 1812 if (iswrite) { 1813 if (!perm->writefn) 1814 return ret; 1815 1816 if (copy_from_user(&val, buf, count)) 1817 return -EFAULT; 1818 1819 ret = perm->writefn(vdev, *ppos, count, perm, offset, val); 1820 } else { 1821 if (perm->readfn) { 1822 ret = perm->readfn(vdev, *ppos, count, 1823 perm, offset, &val); 1824 if (ret < 0) 1825 return ret; 1826 } 1827 1828 if (copy_to_user(buf, &val, count)) 1829 return -EFAULT; 1830 } 1831 1832 return ret; 1833 } 1834 1835 ssize_t vfio_pci_config_rw(struct vfio_pci_device *vdev, char __user *buf, 1836 size_t count, loff_t *ppos, bool iswrite) 1837 { 1838 size_t done = 0; 1839 int ret = 0; 1840 loff_t pos = *ppos; 1841 1842 pos &= VFIO_PCI_OFFSET_MASK; 1843 1844 while (count) { 1845 ret = vfio_config_do_rw(vdev, buf, count, &pos, iswrite); 1846 if (ret < 0) 1847 return ret; 1848 1849 count -= ret; 1850 done += ret; 1851 buf += ret; 1852 pos += ret; 1853 } 1854 1855 *ppos += done; 1856 1857 return done; 1858 } 1859