1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, HiSilicon Ltd. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/eventfd.h> 8 #include <linux/file.h> 9 #include <linux/hisi_acc_qm.h> 10 #include <linux/interrupt.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/vfio.h> 14 #include <linux/vfio_pci_core.h> 15 #include <linux/anon_inodes.h> 16 17 #include "hisi_acc_vfio_pci.h" 18 19 /* return 0 on VM acc device ready, -ETIMEDOUT hardware timeout */ 20 static int qm_wait_dev_not_ready(struct hisi_qm *qm) 21 { 22 u32 val; 23 24 return readl_relaxed_poll_timeout(qm->io_base + QM_VF_STATE, 25 val, !(val & 0x1), MB_POLL_PERIOD_US, 26 MB_POLL_TIMEOUT_US); 27 } 28 29 /* 30 * Each state Reg is checked 100 times, 31 * with a delay of 100 microseconds after each check 32 */ 33 static u32 qm_check_reg_state(struct hisi_qm *qm, u32 regs) 34 { 35 int check_times = 0; 36 u32 state; 37 38 state = readl(qm->io_base + regs); 39 while (state && check_times < ERROR_CHECK_TIMEOUT) { 40 udelay(CHECK_DELAY_TIME); 41 state = readl(qm->io_base + regs); 42 check_times++; 43 } 44 45 return state; 46 } 47 48 static int qm_read_regs(struct hisi_qm *qm, u32 reg_addr, 49 u32 *data, u8 nums) 50 { 51 int i; 52 53 if (nums < 1 || nums > QM_REGS_MAX_LEN) 54 return -EINVAL; 55 56 for (i = 0; i < nums; i++) { 57 data[i] = readl(qm->io_base + reg_addr); 58 reg_addr += QM_REG_ADDR_OFFSET; 59 } 60 61 return 0; 62 } 63 64 static int qm_write_regs(struct hisi_qm *qm, u32 reg, 65 u32 *data, u8 nums) 66 { 67 int i; 68 69 if (nums < 1 || nums > QM_REGS_MAX_LEN) 70 return -EINVAL; 71 72 for (i = 0; i < nums; i++) 73 writel(data[i], qm->io_base + reg + i * QM_REG_ADDR_OFFSET); 74 75 return 0; 76 } 77 78 static int qm_get_vft(struct hisi_qm *qm, u32 *base) 79 { 80 u64 sqc_vft; 81 u32 qp_num; 82 int ret; 83 84 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1); 85 if (ret) 86 return ret; 87 88 sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) | 89 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 90 QM_XQC_ADDR_OFFSET); 91 *base = QM_SQC_VFT_BASE_MASK_V2 & (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2); 92 qp_num = (QM_SQC_VFT_NUM_MASK_V2 & 93 (sqc_vft >> QM_SQC_VFT_NUM_SHIFT_V2)) + 1; 94 95 return qp_num; 96 } 97 98 static int qm_get_sqc(struct hisi_qm *qm, u64 *addr) 99 { 100 int ret; 101 102 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, 0, 0, 1); 103 if (ret) 104 return ret; 105 106 *addr = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) | 107 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 108 QM_XQC_ADDR_OFFSET); 109 110 return 0; 111 } 112 113 static int qm_get_cqc(struct hisi_qm *qm, u64 *addr) 114 { 115 int ret; 116 117 ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, 0, 0, 1); 118 if (ret) 119 return ret; 120 121 *addr = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) | 122 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 123 QM_XQC_ADDR_OFFSET); 124 125 return 0; 126 } 127 128 static int qm_get_regs(struct hisi_qm *qm, struct acc_vf_data *vf_data) 129 { 130 struct device *dev = &qm->pdev->dev; 131 int ret; 132 133 ret = qm_read_regs(qm, QM_VF_AEQ_INT_MASK, &vf_data->aeq_int_mask, 1); 134 if (ret) { 135 dev_err(dev, "failed to read QM_VF_AEQ_INT_MASK\n"); 136 return ret; 137 } 138 139 ret = qm_read_regs(qm, QM_VF_EQ_INT_MASK, &vf_data->eq_int_mask, 1); 140 if (ret) { 141 dev_err(dev, "failed to read QM_VF_EQ_INT_MASK\n"); 142 return ret; 143 } 144 145 ret = qm_read_regs(qm, QM_IFC_INT_SOURCE_V, 146 &vf_data->ifc_int_source, 1); 147 if (ret) { 148 dev_err(dev, "failed to read QM_IFC_INT_SOURCE_V\n"); 149 return ret; 150 } 151 152 ret = qm_read_regs(qm, QM_IFC_INT_MASK, &vf_data->ifc_int_mask, 1); 153 if (ret) { 154 dev_err(dev, "failed to read QM_IFC_INT_MASK\n"); 155 return ret; 156 } 157 158 ret = qm_read_regs(qm, QM_IFC_INT_SET_V, &vf_data->ifc_int_set, 1); 159 if (ret) { 160 dev_err(dev, "failed to read QM_IFC_INT_SET_V\n"); 161 return ret; 162 } 163 164 ret = qm_read_regs(qm, QM_PAGE_SIZE, &vf_data->page_size, 1); 165 if (ret) { 166 dev_err(dev, "failed to read QM_PAGE_SIZE\n"); 167 return ret; 168 } 169 170 /* QM_EQC_DW has 7 regs */ 171 ret = qm_read_regs(qm, QM_EQC_DW0, vf_data->qm_eqc_dw, 7); 172 if (ret) { 173 dev_err(dev, "failed to read QM_EQC_DW\n"); 174 return ret; 175 } 176 177 /* QM_AEQC_DW has 7 regs */ 178 ret = qm_read_regs(qm, QM_AEQC_DW0, vf_data->qm_aeqc_dw, 7); 179 if (ret) { 180 dev_err(dev, "failed to read QM_AEQC_DW\n"); 181 return ret; 182 } 183 184 return 0; 185 } 186 187 static int qm_set_regs(struct hisi_qm *qm, struct acc_vf_data *vf_data) 188 { 189 struct device *dev = &qm->pdev->dev; 190 int ret; 191 192 /* check VF state */ 193 if (unlikely(hisi_qm_wait_mb_ready(qm))) { 194 dev_err(&qm->pdev->dev, "QM device is not ready to write\n"); 195 return -EBUSY; 196 } 197 198 ret = qm_write_regs(qm, QM_VF_AEQ_INT_MASK, &vf_data->aeq_int_mask, 1); 199 if (ret) { 200 dev_err(dev, "failed to write QM_VF_AEQ_INT_MASK\n"); 201 return ret; 202 } 203 204 ret = qm_write_regs(qm, QM_VF_EQ_INT_MASK, &vf_data->eq_int_mask, 1); 205 if (ret) { 206 dev_err(dev, "failed to write QM_VF_EQ_INT_MASK\n"); 207 return ret; 208 } 209 210 ret = qm_write_regs(qm, QM_IFC_INT_SOURCE_V, 211 &vf_data->ifc_int_source, 1); 212 if (ret) { 213 dev_err(dev, "failed to write QM_IFC_INT_SOURCE_V\n"); 214 return ret; 215 } 216 217 ret = qm_write_regs(qm, QM_IFC_INT_MASK, &vf_data->ifc_int_mask, 1); 218 if (ret) { 219 dev_err(dev, "failed to write QM_IFC_INT_MASK\n"); 220 return ret; 221 } 222 223 ret = qm_write_regs(qm, QM_IFC_INT_SET_V, &vf_data->ifc_int_set, 1); 224 if (ret) { 225 dev_err(dev, "failed to write QM_IFC_INT_SET_V\n"); 226 return ret; 227 } 228 229 ret = qm_write_regs(qm, QM_QUE_ISO_CFG_V, &vf_data->que_iso_cfg, 1); 230 if (ret) { 231 dev_err(dev, "failed to write QM_QUE_ISO_CFG_V\n"); 232 return ret; 233 } 234 235 ret = qm_write_regs(qm, QM_PAGE_SIZE, &vf_data->page_size, 1); 236 if (ret) { 237 dev_err(dev, "failed to write QM_PAGE_SIZE\n"); 238 return ret; 239 } 240 241 /* QM_EQC_DW has 7 regs */ 242 ret = qm_write_regs(qm, QM_EQC_DW0, vf_data->qm_eqc_dw, 7); 243 if (ret) { 244 dev_err(dev, "failed to write QM_EQC_DW\n"); 245 return ret; 246 } 247 248 /* QM_AEQC_DW has 7 regs */ 249 ret = qm_write_regs(qm, QM_AEQC_DW0, vf_data->qm_aeqc_dw, 7); 250 if (ret) { 251 dev_err(dev, "failed to write QM_AEQC_DW\n"); 252 return ret; 253 } 254 255 return 0; 256 } 257 258 static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd, 259 u16 index, u8 priority) 260 { 261 u64 doorbell; 262 u64 dbase; 263 u16 randata = 0; 264 265 if (cmd == QM_DOORBELL_CMD_SQ || cmd == QM_DOORBELL_CMD_CQ) 266 dbase = QM_DOORBELL_SQ_CQ_BASE_V2; 267 else 268 dbase = QM_DOORBELL_EQ_AEQ_BASE_V2; 269 270 doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V2) | 271 ((u64)randata << QM_DB_RAND_SHIFT_V2) | 272 ((u64)index << QM_DB_INDEX_SHIFT_V2) | 273 ((u64)priority << QM_DB_PRIORITY_SHIFT_V2); 274 275 writeq(doorbell, qm->io_base + dbase); 276 } 277 278 static int pf_qm_get_qp_num(struct hisi_qm *qm, int vf_id, u32 *rbase) 279 { 280 unsigned int val; 281 u64 sqc_vft; 282 u32 qp_num; 283 int ret; 284 285 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val, 286 val & BIT(0), MB_POLL_PERIOD_US, 287 MB_POLL_TIMEOUT_US); 288 if (ret) 289 return ret; 290 291 writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR); 292 /* 0 mean SQC VFT */ 293 writel(0x0, qm->io_base + QM_VFT_CFG_TYPE); 294 writel(vf_id, qm->io_base + QM_VFT_CFG); 295 296 writel(0x0, qm->io_base + QM_VFT_CFG_RDY); 297 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE); 298 299 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val, 300 val & BIT(0), MB_POLL_PERIOD_US, 301 MB_POLL_TIMEOUT_US); 302 if (ret) 303 return ret; 304 305 sqc_vft = readl(qm->io_base + QM_VFT_CFG_DATA_L) | 306 ((u64)readl(qm->io_base + QM_VFT_CFG_DATA_H) << 307 QM_XQC_ADDR_OFFSET); 308 *rbase = QM_SQC_VFT_BASE_MASK_V2 & 309 (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2); 310 qp_num = (QM_SQC_VFT_NUM_MASK_V2 & 311 (sqc_vft >> QM_SQC_VFT_NUM_SHIFT_V2)) + 1; 312 313 return qp_num; 314 } 315 316 static void qm_dev_cmd_init(struct hisi_qm *qm) 317 { 318 /* Clear VF communication status registers. */ 319 writel(0x1, qm->io_base + QM_IFC_INT_SOURCE_V); 320 321 /* Enable pf and vf communication. */ 322 writel(0x0, qm->io_base + QM_IFC_INT_MASK); 323 } 324 325 static int vf_qm_cache_wb(struct hisi_qm *qm) 326 { 327 unsigned int val; 328 329 writel(0x1, qm->io_base + QM_CACHE_WB_START); 330 if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE, 331 val, val & BIT(0), MB_POLL_PERIOD_US, 332 MB_POLL_TIMEOUT_US)) { 333 dev_err(&qm->pdev->dev, "vf QM writeback sqc cache fail\n"); 334 return -EINVAL; 335 } 336 337 return 0; 338 } 339 340 static void vf_qm_fun_reset(struct hisi_acc_vf_core_device *hisi_acc_vdev, 341 struct hisi_qm *qm) 342 { 343 int i; 344 345 for (i = 0; i < qm->qp_num; i++) 346 qm_db(qm, i, QM_DOORBELL_CMD_SQ, 0, 1); 347 } 348 349 static int vf_qm_func_stop(struct hisi_qm *qm) 350 { 351 return hisi_qm_mb(qm, QM_MB_CMD_PAUSE_QM, 0, 0, 0); 352 } 353 354 static int vf_qm_check_match(struct hisi_acc_vf_core_device *hisi_acc_vdev, 355 struct hisi_acc_vf_migration_file *migf) 356 { 357 struct acc_vf_data *vf_data = &migf->vf_data; 358 struct hisi_qm *vf_qm = &hisi_acc_vdev->vf_qm; 359 struct hisi_qm *pf_qm = hisi_acc_vdev->pf_qm; 360 struct device *dev = &vf_qm->pdev->dev; 361 u32 que_iso_state; 362 int ret; 363 364 if (migf->total_length < QM_MATCH_SIZE) 365 return -EINVAL; 366 367 if (vf_data->acc_magic != ACC_DEV_MAGIC) { 368 dev_err(dev, "failed to match ACC_DEV_MAGIC\n"); 369 return -EINVAL; 370 } 371 372 if (vf_data->dev_id != hisi_acc_vdev->vf_dev->device) { 373 dev_err(dev, "failed to match VF devices\n"); 374 return -EINVAL; 375 } 376 377 /* vf qp num check */ 378 ret = qm_get_vft(vf_qm, &vf_qm->qp_base); 379 if (ret <= 0) { 380 dev_err(dev, "failed to get vft qp nums\n"); 381 return -EINVAL; 382 } 383 384 if (ret != vf_data->qp_num) { 385 dev_err(dev, "failed to match VF qp num\n"); 386 return -EINVAL; 387 } 388 389 vf_qm->qp_num = ret; 390 391 /* vf isolation state check */ 392 ret = qm_read_regs(pf_qm, QM_QUE_ISO_CFG_V, &que_iso_state, 1); 393 if (ret) { 394 dev_err(dev, "failed to read QM_QUE_ISO_CFG_V\n"); 395 return ret; 396 } 397 398 if (vf_data->que_iso_cfg != que_iso_state) { 399 dev_err(dev, "failed to match isolation state\n"); 400 return ret; 401 } 402 403 ret = qm_write_regs(vf_qm, QM_VF_STATE, &vf_data->vf_qm_state, 1); 404 if (ret) { 405 dev_err(dev, "failed to write QM_VF_STATE\n"); 406 return ret; 407 } 408 409 hisi_acc_vdev->vf_qm_state = vf_data->vf_qm_state; 410 return 0; 411 } 412 413 static int vf_qm_get_match_data(struct hisi_acc_vf_core_device *hisi_acc_vdev, 414 struct acc_vf_data *vf_data) 415 { 416 struct hisi_qm *pf_qm = hisi_acc_vdev->pf_qm; 417 struct device *dev = &pf_qm->pdev->dev; 418 int vf_id = hisi_acc_vdev->vf_id; 419 int ret; 420 421 vf_data->acc_magic = ACC_DEV_MAGIC; 422 /* save device id */ 423 vf_data->dev_id = hisi_acc_vdev->vf_dev->device; 424 425 /* vf qp num save from PF */ 426 ret = pf_qm_get_qp_num(pf_qm, vf_id, &vf_data->qp_base); 427 if (ret <= 0) { 428 dev_err(dev, "failed to get vft qp nums!\n"); 429 return -EINVAL; 430 } 431 432 vf_data->qp_num = ret; 433 434 /* VF isolation state save from PF */ 435 ret = qm_read_regs(pf_qm, QM_QUE_ISO_CFG_V, &vf_data->que_iso_cfg, 1); 436 if (ret) { 437 dev_err(dev, "failed to read QM_QUE_ISO_CFG_V!\n"); 438 return ret; 439 } 440 441 return 0; 442 } 443 444 static int vf_qm_load_data(struct hisi_acc_vf_core_device *hisi_acc_vdev, 445 struct hisi_acc_vf_migration_file *migf) 446 { 447 struct hisi_qm *qm = &hisi_acc_vdev->vf_qm; 448 struct device *dev = &qm->pdev->dev; 449 struct acc_vf_data *vf_data = &migf->vf_data; 450 int ret; 451 452 /* Return if only match data was transferred */ 453 if (migf->total_length == QM_MATCH_SIZE) 454 return 0; 455 456 if (migf->total_length < sizeof(struct acc_vf_data)) 457 return -EINVAL; 458 459 qm->eqe_dma = vf_data->eqe_dma; 460 qm->aeqe_dma = vf_data->aeqe_dma; 461 qm->sqc_dma = vf_data->sqc_dma; 462 qm->cqc_dma = vf_data->cqc_dma; 463 464 qm->qp_base = vf_data->qp_base; 465 qm->qp_num = vf_data->qp_num; 466 467 ret = qm_set_regs(qm, vf_data); 468 if (ret) { 469 dev_err(dev, "Set VF regs failed\n"); 470 return ret; 471 } 472 473 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0); 474 if (ret) { 475 dev_err(dev, "Set sqc failed\n"); 476 return ret; 477 } 478 479 ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0); 480 if (ret) { 481 dev_err(dev, "Set cqc failed\n"); 482 return ret; 483 } 484 485 qm_dev_cmd_init(qm); 486 return 0; 487 } 488 489 static int vf_qm_state_save(struct hisi_acc_vf_core_device *hisi_acc_vdev, 490 struct hisi_acc_vf_migration_file *migf) 491 { 492 struct acc_vf_data *vf_data = &migf->vf_data; 493 struct hisi_qm *vf_qm = &hisi_acc_vdev->vf_qm; 494 struct device *dev = &vf_qm->pdev->dev; 495 int ret; 496 497 ret = vf_qm_get_match_data(hisi_acc_vdev, vf_data); 498 if (ret) 499 return ret; 500 501 if (unlikely(qm_wait_dev_not_ready(vf_qm))) { 502 /* Update state and return with match data */ 503 vf_data->vf_qm_state = QM_NOT_READY; 504 hisi_acc_vdev->vf_qm_state = vf_data->vf_qm_state; 505 migf->total_length = QM_MATCH_SIZE; 506 return 0; 507 } 508 509 vf_data->vf_qm_state = QM_READY; 510 hisi_acc_vdev->vf_qm_state = vf_data->vf_qm_state; 511 512 ret = vf_qm_cache_wb(vf_qm); 513 if (ret) { 514 dev_err(dev, "failed to writeback QM Cache!\n"); 515 return ret; 516 } 517 518 ret = qm_get_regs(vf_qm, vf_data); 519 if (ret) 520 return -EINVAL; 521 522 /* Every reg is 32 bit, the dma address is 64 bit. */ 523 vf_data->eqe_dma = vf_data->qm_eqc_dw[2]; 524 vf_data->eqe_dma <<= QM_XQC_ADDR_OFFSET; 525 vf_data->eqe_dma |= vf_data->qm_eqc_dw[1]; 526 vf_data->aeqe_dma = vf_data->qm_aeqc_dw[2]; 527 vf_data->aeqe_dma <<= QM_XQC_ADDR_OFFSET; 528 vf_data->aeqe_dma |= vf_data->qm_aeqc_dw[1]; 529 530 /* Through SQC_BT/CQC_BT to get sqc and cqc address */ 531 ret = qm_get_sqc(vf_qm, &vf_data->sqc_dma); 532 if (ret) { 533 dev_err(dev, "failed to read SQC addr!\n"); 534 return -EINVAL; 535 } 536 537 ret = qm_get_cqc(vf_qm, &vf_data->cqc_dma); 538 if (ret) { 539 dev_err(dev, "failed to read CQC addr!\n"); 540 return -EINVAL; 541 } 542 543 migf->total_length = sizeof(struct acc_vf_data); 544 return 0; 545 } 546 547 /* Check the PF's RAS state and Function INT state */ 548 static int 549 hisi_acc_check_int_state(struct hisi_acc_vf_core_device *hisi_acc_vdev) 550 { 551 struct hisi_qm *vfqm = &hisi_acc_vdev->vf_qm; 552 struct hisi_qm *qm = hisi_acc_vdev->pf_qm; 553 struct pci_dev *vf_pdev = hisi_acc_vdev->vf_dev; 554 struct device *dev = &qm->pdev->dev; 555 u32 state; 556 557 /* Check RAS state */ 558 state = qm_check_reg_state(qm, QM_ABNORMAL_INT_STATUS); 559 if (state) { 560 dev_err(dev, "failed to check QM RAS state!\n"); 561 return -EBUSY; 562 } 563 564 /* Check Function Communication state between PF and VF */ 565 state = qm_check_reg_state(vfqm, QM_IFC_INT_STATUS); 566 if (state) { 567 dev_err(dev, "failed to check QM IFC INT state!\n"); 568 return -EBUSY; 569 } 570 state = qm_check_reg_state(vfqm, QM_IFC_INT_SET_V); 571 if (state) { 572 dev_err(dev, "failed to check QM IFC INT SET state!\n"); 573 return -EBUSY; 574 } 575 576 /* Check submodule task state */ 577 switch (vf_pdev->device) { 578 case PCI_DEVICE_ID_HUAWEI_SEC_VF: 579 state = qm_check_reg_state(qm, SEC_CORE_INT_STATUS); 580 if (state) { 581 dev_err(dev, "failed to check QM SEC Core INT state!\n"); 582 return -EBUSY; 583 } 584 return 0; 585 case PCI_DEVICE_ID_HUAWEI_HPRE_VF: 586 state = qm_check_reg_state(qm, HPRE_HAC_INT_STATUS); 587 if (state) { 588 dev_err(dev, "failed to check QM HPRE HAC INT state!\n"); 589 return -EBUSY; 590 } 591 return 0; 592 case PCI_DEVICE_ID_HUAWEI_ZIP_VF: 593 state = qm_check_reg_state(qm, HZIP_CORE_INT_STATUS); 594 if (state) { 595 dev_err(dev, "failed to check QM ZIP Core INT state!\n"); 596 return -EBUSY; 597 } 598 return 0; 599 default: 600 dev_err(dev, "failed to detect acc module type!\n"); 601 return -EINVAL; 602 } 603 } 604 605 static void hisi_acc_vf_disable_fd(struct hisi_acc_vf_migration_file *migf) 606 { 607 mutex_lock(&migf->lock); 608 migf->disabled = true; 609 migf->total_length = 0; 610 migf->filp->f_pos = 0; 611 mutex_unlock(&migf->lock); 612 } 613 614 static void hisi_acc_vf_disable_fds(struct hisi_acc_vf_core_device *hisi_acc_vdev) 615 { 616 if (hisi_acc_vdev->resuming_migf) { 617 hisi_acc_vf_disable_fd(hisi_acc_vdev->resuming_migf); 618 fput(hisi_acc_vdev->resuming_migf->filp); 619 hisi_acc_vdev->resuming_migf = NULL; 620 } 621 622 if (hisi_acc_vdev->saving_migf) { 623 hisi_acc_vf_disable_fd(hisi_acc_vdev->saving_migf); 624 fput(hisi_acc_vdev->saving_migf->filp); 625 hisi_acc_vdev->saving_migf = NULL; 626 } 627 } 628 629 /* 630 * This function is called in all state_mutex unlock cases to 631 * handle a 'deferred_reset' if exists. 632 */ 633 static void 634 hisi_acc_vf_state_mutex_unlock(struct hisi_acc_vf_core_device *hisi_acc_vdev) 635 { 636 again: 637 spin_lock(&hisi_acc_vdev->reset_lock); 638 if (hisi_acc_vdev->deferred_reset) { 639 hisi_acc_vdev->deferred_reset = false; 640 spin_unlock(&hisi_acc_vdev->reset_lock); 641 hisi_acc_vdev->vf_qm_state = QM_NOT_READY; 642 hisi_acc_vdev->mig_state = VFIO_DEVICE_STATE_RUNNING; 643 hisi_acc_vf_disable_fds(hisi_acc_vdev); 644 goto again; 645 } 646 mutex_unlock(&hisi_acc_vdev->state_mutex); 647 spin_unlock(&hisi_acc_vdev->reset_lock); 648 } 649 650 static void hisi_acc_vf_start_device(struct hisi_acc_vf_core_device *hisi_acc_vdev) 651 { 652 struct hisi_qm *vf_qm = &hisi_acc_vdev->vf_qm; 653 654 if (hisi_acc_vdev->vf_qm_state != QM_READY) 655 return; 656 657 vf_qm_fun_reset(hisi_acc_vdev, vf_qm); 658 } 659 660 static int hisi_acc_vf_load_state(struct hisi_acc_vf_core_device *hisi_acc_vdev) 661 { 662 struct device *dev = &hisi_acc_vdev->vf_dev->dev; 663 struct hisi_acc_vf_migration_file *migf = hisi_acc_vdev->resuming_migf; 664 int ret; 665 666 /* Check dev compatibility */ 667 ret = vf_qm_check_match(hisi_acc_vdev, migf); 668 if (ret) { 669 dev_err(dev, "failed to match the VF!\n"); 670 return ret; 671 } 672 /* Recover data to VF */ 673 ret = vf_qm_load_data(hisi_acc_vdev, migf); 674 if (ret) { 675 dev_err(dev, "failed to recover the VF!\n"); 676 return ret; 677 } 678 679 return 0; 680 } 681 682 static int hisi_acc_vf_release_file(struct inode *inode, struct file *filp) 683 { 684 struct hisi_acc_vf_migration_file *migf = filp->private_data; 685 686 hisi_acc_vf_disable_fd(migf); 687 mutex_destroy(&migf->lock); 688 kfree(migf); 689 return 0; 690 } 691 692 static ssize_t hisi_acc_vf_resume_write(struct file *filp, const char __user *buf, 693 size_t len, loff_t *pos) 694 { 695 struct hisi_acc_vf_migration_file *migf = filp->private_data; 696 loff_t requested_length; 697 ssize_t done = 0; 698 int ret; 699 700 if (pos) 701 return -ESPIPE; 702 pos = &filp->f_pos; 703 704 if (*pos < 0 || 705 check_add_overflow((loff_t)len, *pos, &requested_length)) 706 return -EINVAL; 707 708 if (requested_length > sizeof(struct acc_vf_data)) 709 return -ENOMEM; 710 711 mutex_lock(&migf->lock); 712 if (migf->disabled) { 713 done = -ENODEV; 714 goto out_unlock; 715 } 716 717 ret = copy_from_user(&migf->vf_data, buf, len); 718 if (ret) { 719 done = -EFAULT; 720 goto out_unlock; 721 } 722 *pos += len; 723 done = len; 724 migf->total_length += len; 725 out_unlock: 726 mutex_unlock(&migf->lock); 727 return done; 728 } 729 730 static const struct file_operations hisi_acc_vf_resume_fops = { 731 .owner = THIS_MODULE, 732 .write = hisi_acc_vf_resume_write, 733 .release = hisi_acc_vf_release_file, 734 .llseek = no_llseek, 735 }; 736 737 static struct hisi_acc_vf_migration_file * 738 hisi_acc_vf_pci_resume(struct hisi_acc_vf_core_device *hisi_acc_vdev) 739 { 740 struct hisi_acc_vf_migration_file *migf; 741 742 migf = kzalloc(sizeof(*migf), GFP_KERNEL); 743 if (!migf) 744 return ERR_PTR(-ENOMEM); 745 746 migf->filp = anon_inode_getfile("hisi_acc_vf_mig", &hisi_acc_vf_resume_fops, migf, 747 O_WRONLY); 748 if (IS_ERR(migf->filp)) { 749 int err = PTR_ERR(migf->filp); 750 751 kfree(migf); 752 return ERR_PTR(err); 753 } 754 755 stream_open(migf->filp->f_inode, migf->filp); 756 mutex_init(&migf->lock); 757 return migf; 758 } 759 760 static ssize_t hisi_acc_vf_save_read(struct file *filp, char __user *buf, size_t len, 761 loff_t *pos) 762 { 763 struct hisi_acc_vf_migration_file *migf = filp->private_data; 764 ssize_t done = 0; 765 int ret; 766 767 if (pos) 768 return -ESPIPE; 769 pos = &filp->f_pos; 770 771 mutex_lock(&migf->lock); 772 if (*pos > migf->total_length) { 773 done = -EINVAL; 774 goto out_unlock; 775 } 776 777 if (migf->disabled) { 778 done = -ENODEV; 779 goto out_unlock; 780 } 781 782 len = min_t(size_t, migf->total_length - *pos, len); 783 if (len) { 784 ret = copy_to_user(buf, &migf->vf_data, len); 785 if (ret) { 786 done = -EFAULT; 787 goto out_unlock; 788 } 789 *pos += len; 790 done = len; 791 } 792 out_unlock: 793 mutex_unlock(&migf->lock); 794 return done; 795 } 796 797 static const struct file_operations hisi_acc_vf_save_fops = { 798 .owner = THIS_MODULE, 799 .read = hisi_acc_vf_save_read, 800 .release = hisi_acc_vf_release_file, 801 .llseek = no_llseek, 802 }; 803 804 static struct hisi_acc_vf_migration_file * 805 hisi_acc_vf_stop_copy(struct hisi_acc_vf_core_device *hisi_acc_vdev) 806 { 807 struct hisi_acc_vf_migration_file *migf; 808 int ret; 809 810 migf = kzalloc(sizeof(*migf), GFP_KERNEL); 811 if (!migf) 812 return ERR_PTR(-ENOMEM); 813 814 migf->filp = anon_inode_getfile("hisi_acc_vf_mig", &hisi_acc_vf_save_fops, migf, 815 O_RDONLY); 816 if (IS_ERR(migf->filp)) { 817 int err = PTR_ERR(migf->filp); 818 819 kfree(migf); 820 return ERR_PTR(err); 821 } 822 823 stream_open(migf->filp->f_inode, migf->filp); 824 mutex_init(&migf->lock); 825 826 ret = vf_qm_state_save(hisi_acc_vdev, migf); 827 if (ret) { 828 fput(migf->filp); 829 return ERR_PTR(ret); 830 } 831 832 return migf; 833 } 834 835 static int hisi_acc_vf_stop_device(struct hisi_acc_vf_core_device *hisi_acc_vdev) 836 { 837 struct device *dev = &hisi_acc_vdev->vf_dev->dev; 838 struct hisi_qm *vf_qm = &hisi_acc_vdev->vf_qm; 839 int ret; 840 841 ret = vf_qm_func_stop(vf_qm); 842 if (ret) { 843 dev_err(dev, "failed to stop QM VF function!\n"); 844 return ret; 845 } 846 847 ret = hisi_acc_check_int_state(hisi_acc_vdev); 848 if (ret) { 849 dev_err(dev, "failed to check QM INT state!\n"); 850 return ret; 851 } 852 return 0; 853 } 854 855 static struct file * 856 hisi_acc_vf_set_device_state(struct hisi_acc_vf_core_device *hisi_acc_vdev, 857 u32 new) 858 { 859 u32 cur = hisi_acc_vdev->mig_state; 860 int ret; 861 862 if (cur == VFIO_DEVICE_STATE_RUNNING && new == VFIO_DEVICE_STATE_STOP) { 863 ret = hisi_acc_vf_stop_device(hisi_acc_vdev); 864 if (ret) 865 return ERR_PTR(ret); 866 return NULL; 867 } 868 869 if (cur == VFIO_DEVICE_STATE_STOP && new == VFIO_DEVICE_STATE_STOP_COPY) { 870 struct hisi_acc_vf_migration_file *migf; 871 872 migf = hisi_acc_vf_stop_copy(hisi_acc_vdev); 873 if (IS_ERR(migf)) 874 return ERR_CAST(migf); 875 get_file(migf->filp); 876 hisi_acc_vdev->saving_migf = migf; 877 return migf->filp; 878 } 879 880 if ((cur == VFIO_DEVICE_STATE_STOP_COPY && new == VFIO_DEVICE_STATE_STOP)) { 881 hisi_acc_vf_disable_fds(hisi_acc_vdev); 882 return NULL; 883 } 884 885 if (cur == VFIO_DEVICE_STATE_STOP && new == VFIO_DEVICE_STATE_RESUMING) { 886 struct hisi_acc_vf_migration_file *migf; 887 888 migf = hisi_acc_vf_pci_resume(hisi_acc_vdev); 889 if (IS_ERR(migf)) 890 return ERR_CAST(migf); 891 get_file(migf->filp); 892 hisi_acc_vdev->resuming_migf = migf; 893 return migf->filp; 894 } 895 896 if (cur == VFIO_DEVICE_STATE_RESUMING && new == VFIO_DEVICE_STATE_STOP) { 897 ret = hisi_acc_vf_load_state(hisi_acc_vdev); 898 if (ret) 899 return ERR_PTR(ret); 900 hisi_acc_vf_disable_fds(hisi_acc_vdev); 901 return NULL; 902 } 903 904 if (cur == VFIO_DEVICE_STATE_STOP && new == VFIO_DEVICE_STATE_RUNNING) { 905 hisi_acc_vf_start_device(hisi_acc_vdev); 906 return NULL; 907 } 908 909 /* 910 * vfio_mig_get_next_state() does not use arcs other than the above 911 */ 912 WARN_ON(true); 913 return ERR_PTR(-EINVAL); 914 } 915 916 static struct file * 917 hisi_acc_vfio_pci_set_device_state(struct vfio_device *vdev, 918 enum vfio_device_mig_state new_state) 919 { 920 struct hisi_acc_vf_core_device *hisi_acc_vdev = container_of(vdev, 921 struct hisi_acc_vf_core_device, core_device.vdev); 922 enum vfio_device_mig_state next_state; 923 struct file *res = NULL; 924 int ret; 925 926 mutex_lock(&hisi_acc_vdev->state_mutex); 927 while (new_state != hisi_acc_vdev->mig_state) { 928 ret = vfio_mig_get_next_state(vdev, 929 hisi_acc_vdev->mig_state, 930 new_state, &next_state); 931 if (ret) { 932 res = ERR_PTR(-EINVAL); 933 break; 934 } 935 936 res = hisi_acc_vf_set_device_state(hisi_acc_vdev, next_state); 937 if (IS_ERR(res)) 938 break; 939 hisi_acc_vdev->mig_state = next_state; 940 if (WARN_ON(res && new_state != hisi_acc_vdev->mig_state)) { 941 fput(res); 942 res = ERR_PTR(-EINVAL); 943 break; 944 } 945 } 946 hisi_acc_vf_state_mutex_unlock(hisi_acc_vdev); 947 return res; 948 } 949 950 static int 951 hisi_acc_vfio_pci_get_device_state(struct vfio_device *vdev, 952 enum vfio_device_mig_state *curr_state) 953 { 954 struct hisi_acc_vf_core_device *hisi_acc_vdev = container_of(vdev, 955 struct hisi_acc_vf_core_device, core_device.vdev); 956 957 mutex_lock(&hisi_acc_vdev->state_mutex); 958 *curr_state = hisi_acc_vdev->mig_state; 959 hisi_acc_vf_state_mutex_unlock(hisi_acc_vdev); 960 return 0; 961 } 962 963 static void hisi_acc_vf_pci_aer_reset_done(struct pci_dev *pdev) 964 { 965 struct hisi_acc_vf_core_device *hisi_acc_vdev = dev_get_drvdata(&pdev->dev); 966 967 if (hisi_acc_vdev->core_device.vdev.migration_flags != 968 VFIO_MIGRATION_STOP_COPY) 969 return; 970 971 /* 972 * As the higher VFIO layers are holding locks across reset and using 973 * those same locks with the mm_lock we need to prevent ABBA deadlock 974 * with the state_mutex and mm_lock. 975 * In case the state_mutex was taken already we defer the cleanup work 976 * to the unlock flow of the other running context. 977 */ 978 spin_lock(&hisi_acc_vdev->reset_lock); 979 hisi_acc_vdev->deferred_reset = true; 980 if (!mutex_trylock(&hisi_acc_vdev->state_mutex)) { 981 spin_unlock(&hisi_acc_vdev->reset_lock); 982 return; 983 } 984 spin_unlock(&hisi_acc_vdev->reset_lock); 985 hisi_acc_vf_state_mutex_unlock(hisi_acc_vdev); 986 } 987 988 static int hisi_acc_vf_qm_init(struct hisi_acc_vf_core_device *hisi_acc_vdev) 989 { 990 struct vfio_pci_core_device *vdev = &hisi_acc_vdev->core_device; 991 struct hisi_qm *vf_qm = &hisi_acc_vdev->vf_qm; 992 struct pci_dev *vf_dev = vdev->pdev; 993 994 /* 995 * ACC VF dev BAR2 region consists of both functional register space 996 * and migration control register space. For migration to work, we 997 * need access to both. Hence, we map the entire BAR2 region here. 998 * But unnecessarily exposing the migration BAR region to the Guest 999 * has the potential to prevent/corrupt the Guest migration. Hence, 1000 * we restrict access to the migration control space from 1001 * Guest(Please see mmap/ioctl/read/write override functions). 1002 * 1003 * Please note that it is OK to expose the entire VF BAR if migration 1004 * is not supported or required as this cannot affect the ACC PF 1005 * configurations. 1006 * 1007 * Also the HiSilicon ACC VF devices supported by this driver on 1008 * HiSilicon hardware platforms are integrated end point devices 1009 * and the platform lacks the capability to perform any PCIe P2P 1010 * between these devices. 1011 */ 1012 1013 vf_qm->io_base = 1014 ioremap(pci_resource_start(vf_dev, VFIO_PCI_BAR2_REGION_INDEX), 1015 pci_resource_len(vf_dev, VFIO_PCI_BAR2_REGION_INDEX)); 1016 if (!vf_qm->io_base) 1017 return -EIO; 1018 1019 vf_qm->fun_type = QM_HW_VF; 1020 vf_qm->pdev = vf_dev; 1021 mutex_init(&vf_qm->mailbox_lock); 1022 1023 return 0; 1024 } 1025 1026 static struct hisi_qm *hisi_acc_get_pf_qm(struct pci_dev *pdev) 1027 { 1028 struct hisi_qm *pf_qm; 1029 struct pci_driver *pf_driver; 1030 1031 if (!pdev->is_virtfn) 1032 return NULL; 1033 1034 switch (pdev->device) { 1035 case PCI_DEVICE_ID_HUAWEI_SEC_VF: 1036 pf_driver = hisi_sec_get_pf_driver(); 1037 break; 1038 case PCI_DEVICE_ID_HUAWEI_HPRE_VF: 1039 pf_driver = hisi_hpre_get_pf_driver(); 1040 break; 1041 case PCI_DEVICE_ID_HUAWEI_ZIP_VF: 1042 pf_driver = hisi_zip_get_pf_driver(); 1043 break; 1044 default: 1045 return NULL; 1046 } 1047 1048 if (!pf_driver) 1049 return NULL; 1050 1051 pf_qm = pci_iov_get_pf_drvdata(pdev, pf_driver); 1052 1053 return !IS_ERR(pf_qm) ? pf_qm : NULL; 1054 } 1055 1056 static int hisi_acc_pci_rw_access_check(struct vfio_device *core_vdev, 1057 size_t count, loff_t *ppos, 1058 size_t *new_count) 1059 { 1060 unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos); 1061 struct vfio_pci_core_device *vdev = 1062 container_of(core_vdev, struct vfio_pci_core_device, vdev); 1063 1064 if (index == VFIO_PCI_BAR2_REGION_INDEX) { 1065 loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; 1066 resource_size_t end = pci_resource_len(vdev->pdev, index) / 2; 1067 1068 /* Check if access is for migration control region */ 1069 if (pos >= end) 1070 return -EINVAL; 1071 1072 *new_count = min(count, (size_t)(end - pos)); 1073 } 1074 1075 return 0; 1076 } 1077 1078 static int hisi_acc_vfio_pci_mmap(struct vfio_device *core_vdev, 1079 struct vm_area_struct *vma) 1080 { 1081 struct vfio_pci_core_device *vdev = 1082 container_of(core_vdev, struct vfio_pci_core_device, vdev); 1083 unsigned int index; 1084 1085 index = vma->vm_pgoff >> (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT); 1086 if (index == VFIO_PCI_BAR2_REGION_INDEX) { 1087 u64 req_len, pgoff, req_start; 1088 resource_size_t end = pci_resource_len(vdev->pdev, index) / 2; 1089 1090 req_len = vma->vm_end - vma->vm_start; 1091 pgoff = vma->vm_pgoff & 1092 ((1U << (VFIO_PCI_OFFSET_SHIFT - PAGE_SHIFT)) - 1); 1093 req_start = pgoff << PAGE_SHIFT; 1094 1095 if (req_start + req_len > end) 1096 return -EINVAL; 1097 } 1098 1099 return vfio_pci_core_mmap(core_vdev, vma); 1100 } 1101 1102 static ssize_t hisi_acc_vfio_pci_write(struct vfio_device *core_vdev, 1103 const char __user *buf, size_t count, 1104 loff_t *ppos) 1105 { 1106 size_t new_count = count; 1107 int ret; 1108 1109 ret = hisi_acc_pci_rw_access_check(core_vdev, count, ppos, &new_count); 1110 if (ret) 1111 return ret; 1112 1113 return vfio_pci_core_write(core_vdev, buf, new_count, ppos); 1114 } 1115 1116 static ssize_t hisi_acc_vfio_pci_read(struct vfio_device *core_vdev, 1117 char __user *buf, size_t count, 1118 loff_t *ppos) 1119 { 1120 size_t new_count = count; 1121 int ret; 1122 1123 ret = hisi_acc_pci_rw_access_check(core_vdev, count, ppos, &new_count); 1124 if (ret) 1125 return ret; 1126 1127 return vfio_pci_core_read(core_vdev, buf, new_count, ppos); 1128 } 1129 1130 static long hisi_acc_vfio_pci_ioctl(struct vfio_device *core_vdev, unsigned int cmd, 1131 unsigned long arg) 1132 { 1133 if (cmd == VFIO_DEVICE_GET_REGION_INFO) { 1134 struct vfio_pci_core_device *vdev = 1135 container_of(core_vdev, struct vfio_pci_core_device, vdev); 1136 struct pci_dev *pdev = vdev->pdev; 1137 struct vfio_region_info info; 1138 unsigned long minsz; 1139 1140 minsz = offsetofend(struct vfio_region_info, offset); 1141 1142 if (copy_from_user(&info, (void __user *)arg, minsz)) 1143 return -EFAULT; 1144 1145 if (info.argsz < minsz) 1146 return -EINVAL; 1147 1148 if (info.index == VFIO_PCI_BAR2_REGION_INDEX) { 1149 info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); 1150 1151 /* 1152 * ACC VF dev BAR2 region consists of both functional 1153 * register space and migration control register space. 1154 * Report only the functional region to Guest. 1155 */ 1156 info.size = pci_resource_len(pdev, info.index) / 2; 1157 1158 info.flags = VFIO_REGION_INFO_FLAG_READ | 1159 VFIO_REGION_INFO_FLAG_WRITE | 1160 VFIO_REGION_INFO_FLAG_MMAP; 1161 1162 return copy_to_user((void __user *)arg, &info, minsz) ? 1163 -EFAULT : 0; 1164 } 1165 } 1166 return vfio_pci_core_ioctl(core_vdev, cmd, arg); 1167 } 1168 1169 static int hisi_acc_vfio_pci_open_device(struct vfio_device *core_vdev) 1170 { 1171 struct hisi_acc_vf_core_device *hisi_acc_vdev = container_of(core_vdev, 1172 struct hisi_acc_vf_core_device, core_device.vdev); 1173 struct vfio_pci_core_device *vdev = &hisi_acc_vdev->core_device; 1174 int ret; 1175 1176 ret = vfio_pci_core_enable(vdev); 1177 if (ret) 1178 return ret; 1179 1180 if (core_vdev->ops->migration_set_state) { 1181 ret = hisi_acc_vf_qm_init(hisi_acc_vdev); 1182 if (ret) { 1183 vfio_pci_core_disable(vdev); 1184 return ret; 1185 } 1186 hisi_acc_vdev->mig_state = VFIO_DEVICE_STATE_RUNNING; 1187 } 1188 1189 vfio_pci_core_finish_enable(vdev); 1190 return 0; 1191 } 1192 1193 static void hisi_acc_vfio_pci_close_device(struct vfio_device *core_vdev) 1194 { 1195 struct hisi_acc_vf_core_device *hisi_acc_vdev = container_of(core_vdev, 1196 struct hisi_acc_vf_core_device, core_device.vdev); 1197 struct hisi_qm *vf_qm = &hisi_acc_vdev->vf_qm; 1198 1199 iounmap(vf_qm->io_base); 1200 vfio_pci_core_close_device(core_vdev); 1201 } 1202 1203 static const struct vfio_device_ops hisi_acc_vfio_pci_migrn_ops = { 1204 .name = "hisi-acc-vfio-pci-migration", 1205 .open_device = hisi_acc_vfio_pci_open_device, 1206 .close_device = hisi_acc_vfio_pci_close_device, 1207 .ioctl = hisi_acc_vfio_pci_ioctl, 1208 .device_feature = vfio_pci_core_ioctl_feature, 1209 .read = hisi_acc_vfio_pci_read, 1210 .write = hisi_acc_vfio_pci_write, 1211 .mmap = hisi_acc_vfio_pci_mmap, 1212 .request = vfio_pci_core_request, 1213 .match = vfio_pci_core_match, 1214 .migration_set_state = hisi_acc_vfio_pci_set_device_state, 1215 .migration_get_state = hisi_acc_vfio_pci_get_device_state, 1216 }; 1217 1218 static const struct vfio_device_ops hisi_acc_vfio_pci_ops = { 1219 .name = "hisi-acc-vfio-pci", 1220 .open_device = hisi_acc_vfio_pci_open_device, 1221 .close_device = vfio_pci_core_close_device, 1222 .ioctl = vfio_pci_core_ioctl, 1223 .device_feature = vfio_pci_core_ioctl_feature, 1224 .read = vfio_pci_core_read, 1225 .write = vfio_pci_core_write, 1226 .mmap = vfio_pci_core_mmap, 1227 .request = vfio_pci_core_request, 1228 .match = vfio_pci_core_match, 1229 }; 1230 1231 static int 1232 hisi_acc_vfio_pci_migrn_init(struct hisi_acc_vf_core_device *hisi_acc_vdev, 1233 struct pci_dev *pdev, struct hisi_qm *pf_qm) 1234 { 1235 int vf_id; 1236 1237 vf_id = pci_iov_vf_id(pdev); 1238 if (vf_id < 0) 1239 return vf_id; 1240 1241 hisi_acc_vdev->vf_id = vf_id + 1; 1242 hisi_acc_vdev->core_device.vdev.migration_flags = 1243 VFIO_MIGRATION_STOP_COPY; 1244 hisi_acc_vdev->pf_qm = pf_qm; 1245 hisi_acc_vdev->vf_dev = pdev; 1246 mutex_init(&hisi_acc_vdev->state_mutex); 1247 1248 return 0; 1249 } 1250 1251 static int hisi_acc_vfio_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1252 { 1253 struct hisi_acc_vf_core_device *hisi_acc_vdev; 1254 struct hisi_qm *pf_qm; 1255 int ret; 1256 1257 hisi_acc_vdev = kzalloc(sizeof(*hisi_acc_vdev), GFP_KERNEL); 1258 if (!hisi_acc_vdev) 1259 return -ENOMEM; 1260 1261 pf_qm = hisi_acc_get_pf_qm(pdev); 1262 if (pf_qm && pf_qm->ver >= QM_HW_V3) { 1263 ret = hisi_acc_vfio_pci_migrn_init(hisi_acc_vdev, pdev, pf_qm); 1264 if (!ret) { 1265 vfio_pci_core_init_device(&hisi_acc_vdev->core_device, pdev, 1266 &hisi_acc_vfio_pci_migrn_ops); 1267 } else { 1268 pci_warn(pdev, "migration support failed, continue with generic interface\n"); 1269 vfio_pci_core_init_device(&hisi_acc_vdev->core_device, pdev, 1270 &hisi_acc_vfio_pci_ops); 1271 } 1272 } else { 1273 vfio_pci_core_init_device(&hisi_acc_vdev->core_device, pdev, 1274 &hisi_acc_vfio_pci_ops); 1275 } 1276 1277 ret = vfio_pci_core_register_device(&hisi_acc_vdev->core_device); 1278 if (ret) 1279 goto out_free; 1280 1281 dev_set_drvdata(&pdev->dev, hisi_acc_vdev); 1282 return 0; 1283 1284 out_free: 1285 vfio_pci_core_uninit_device(&hisi_acc_vdev->core_device); 1286 kfree(hisi_acc_vdev); 1287 return ret; 1288 } 1289 1290 static void hisi_acc_vfio_pci_remove(struct pci_dev *pdev) 1291 { 1292 struct hisi_acc_vf_core_device *hisi_acc_vdev = dev_get_drvdata(&pdev->dev); 1293 1294 vfio_pci_core_unregister_device(&hisi_acc_vdev->core_device); 1295 vfio_pci_core_uninit_device(&hisi_acc_vdev->core_device); 1296 kfree(hisi_acc_vdev); 1297 } 1298 1299 static const struct pci_device_id hisi_acc_vfio_pci_table[] = { 1300 { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_VF) }, 1301 { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_VF) }, 1302 { PCI_DRIVER_OVERRIDE_DEVICE_VFIO(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_ZIP_VF) }, 1303 { } 1304 }; 1305 1306 MODULE_DEVICE_TABLE(pci, hisi_acc_vfio_pci_table); 1307 1308 static const struct pci_error_handlers hisi_acc_vf_err_handlers = { 1309 .reset_done = hisi_acc_vf_pci_aer_reset_done, 1310 .error_detected = vfio_pci_core_aer_err_detected, 1311 }; 1312 1313 static struct pci_driver hisi_acc_vfio_pci_driver = { 1314 .name = KBUILD_MODNAME, 1315 .id_table = hisi_acc_vfio_pci_table, 1316 .probe = hisi_acc_vfio_pci_probe, 1317 .remove = hisi_acc_vfio_pci_remove, 1318 .err_handler = &hisi_acc_vf_err_handlers, 1319 }; 1320 1321 module_pci_driver(hisi_acc_vfio_pci_driver); 1322 1323 MODULE_LICENSE("GPL v2"); 1324 MODULE_AUTHOR("Liu Longfang <liulongfang@huawei.com>"); 1325 MODULE_AUTHOR("Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>"); 1326 MODULE_DESCRIPTION("HiSilicon VFIO PCI - VFIO PCI driver with live migration support for HiSilicon ACC device family"); 1327