1fb1ff4c1SBharat Bhushan /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2fb1ff4c1SBharat Bhushan /* 3fb1ff4c1SBharat Bhushan * Copyright 2013-2016 Freescale Semiconductor Inc. 4fb1ff4c1SBharat Bhushan * Copyright 2016,2019-2020 NXP 5fb1ff4c1SBharat Bhushan */ 6fb1ff4c1SBharat Bhushan 7fb1ff4c1SBharat Bhushan #ifndef VFIO_FSL_MC_PRIVATE_H 8fb1ff4c1SBharat Bhushan #define VFIO_FSL_MC_PRIVATE_H 9fb1ff4c1SBharat Bhushan 10df747bcdSDiana Craciun #define VFIO_FSL_MC_OFFSET_SHIFT 40 11df747bcdSDiana Craciun #define VFIO_FSL_MC_OFFSET_MASK (((u64)(1) << VFIO_FSL_MC_OFFSET_SHIFT) - 1) 12df747bcdSDiana Craciun 13df747bcdSDiana Craciun #define VFIO_FSL_MC_OFFSET_TO_INDEX(off) ((off) >> VFIO_FSL_MC_OFFSET_SHIFT) 14df747bcdSDiana Craciun 15df747bcdSDiana Craciun #define VFIO_FSL_MC_INDEX_TO_OFFSET(index) \ 16df747bcdSDiana Craciun ((u64)(index) << VFIO_FSL_MC_OFFSET_SHIFT) 17df747bcdSDiana Craciun 18f2ba7e8cSDiana Craciun struct vfio_fsl_mc_reflck { 19f2ba7e8cSDiana Craciun struct kref kref; 20f2ba7e8cSDiana Craciun struct mutex lock; 21f2ba7e8cSDiana Craciun }; 22f2ba7e8cSDiana Craciun 23df747bcdSDiana Craciun struct vfio_fsl_mc_region { 24df747bcdSDiana Craciun u32 flags; 25df747bcdSDiana Craciun u32 type; 26df747bcdSDiana Craciun u64 addr; 27df747bcdSDiana Craciun resource_size_t size; 28df747bcdSDiana Craciun }; 29df747bcdSDiana Craciun 30fb1ff4c1SBharat Bhushan struct vfio_fsl_mc_device { 31fb1ff4c1SBharat Bhushan struct fsl_mc_device *mc_dev; 32704f5082SDiana Craciun struct notifier_block nb; 33df747bcdSDiana Craciun int refcnt; 34df747bcdSDiana Craciun struct vfio_fsl_mc_region *regions; 35f2ba7e8cSDiana Craciun struct vfio_fsl_mc_reflck *reflck; 36fb1ff4c1SBharat Bhushan }; 37fb1ff4c1SBharat Bhushan 38fb1ff4c1SBharat Bhushan #endif /* VFIO_FSL_MC_PRIVATE_H */ 39