1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * UCSI driver for Cypress CCGx Type-C controller 4 * 5 * Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved. 6 * Author: Ajay Gupta <ajayg@nvidia.com> 7 * 8 * Some code borrowed from drivers/usb/typec/ucsi/ucsi_acpi.c 9 */ 10 #include <linux/acpi.h> 11 #include <linux/delay.h> 12 #include <linux/firmware.h> 13 #include <linux/i2c.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/usb/typec_dp.h> 20 21 #include <asm/unaligned.h> 22 #include "ucsi.h" 23 24 enum enum_fw_mode { 25 BOOT, /* bootloader */ 26 FW1, /* FW partition-1 (contains secondary fw) */ 27 FW2, /* FW partition-2 (contains primary fw) */ 28 FW_INVALID, 29 }; 30 31 #define CCGX_RAB_DEVICE_MODE 0x0000 32 #define CCGX_RAB_INTR_REG 0x0006 33 #define DEV_INT BIT(0) 34 #define PORT0_INT BIT(1) 35 #define PORT1_INT BIT(2) 36 #define UCSI_READ_INT BIT(7) 37 #define CCGX_RAB_JUMP_TO_BOOT 0x0007 38 #define TO_BOOT 'J' 39 #define TO_ALT_FW 'A' 40 #define CCGX_RAB_RESET_REQ 0x0008 41 #define RESET_SIG 'R' 42 #define CMD_RESET_I2C 0x0 43 #define CMD_RESET_DEV 0x1 44 #define CCGX_RAB_ENTER_FLASHING 0x000A 45 #define FLASH_ENTER_SIG 'P' 46 #define CCGX_RAB_VALIDATE_FW 0x000B 47 #define CCGX_RAB_FLASH_ROW_RW 0x000C 48 #define FLASH_SIG 'F' 49 #define FLASH_RD_CMD 0x0 50 #define FLASH_WR_CMD 0x1 51 #define FLASH_FWCT1_WR_CMD 0x2 52 #define FLASH_FWCT2_WR_CMD 0x3 53 #define FLASH_FWCT_SIG_WR_CMD 0x4 54 #define CCGX_RAB_READ_ALL_VER 0x0010 55 #define CCGX_RAB_READ_FW2_VER 0x0020 56 #define CCGX_RAB_UCSI_CONTROL 0x0039 57 #define CCGX_RAB_UCSI_CONTROL_START BIT(0) 58 #define CCGX_RAB_UCSI_CONTROL_STOP BIT(1) 59 #define CCGX_RAB_UCSI_DATA_BLOCK(offset) (0xf000 | ((offset) & 0xff)) 60 #define REG_FLASH_RW_MEM 0x0200 61 #define DEV_REG_IDX CCGX_RAB_DEVICE_MODE 62 #define CCGX_RAB_PDPORT_ENABLE 0x002C 63 #define PDPORT_1 BIT(0) 64 #define PDPORT_2 BIT(1) 65 #define CCGX_RAB_RESPONSE 0x007E 66 #define ASYNC_EVENT BIT(7) 67 68 /* CCGx events & async msg codes */ 69 #define RESET_COMPLETE 0x80 70 #define EVENT_INDEX RESET_COMPLETE 71 #define PORT_CONNECT_DET 0x84 72 #define PORT_DISCONNECT_DET 0x85 73 #define ROLE_SWAP_COMPELETE 0x87 74 75 /* ccg firmware */ 76 #define CYACD_LINE_SIZE 527 77 #define CCG4_ROW_SIZE 256 78 #define FW1_METADATA_ROW 0x1FF 79 #define FW2_METADATA_ROW 0x1FE 80 #define FW_CFG_TABLE_SIG_SIZE 256 81 82 static int secondary_fw_min_ver = 41; 83 84 enum enum_flash_mode { 85 SECONDARY_BL, /* update secondary using bootloader */ 86 PRIMARY, /* update primary using secondary */ 87 SECONDARY, /* update secondary using primary */ 88 FLASH_NOT_NEEDED, /* update not required */ 89 FLASH_INVALID, 90 }; 91 92 static const char * const ccg_fw_names[] = { 93 "ccg_boot.cyacd", 94 "ccg_primary.cyacd", 95 "ccg_secondary.cyacd" 96 }; 97 98 struct ccg_dev_info { 99 #define CCG_DEVINFO_FWMODE_SHIFT (0) 100 #define CCG_DEVINFO_FWMODE_MASK (0x3 << CCG_DEVINFO_FWMODE_SHIFT) 101 #define CCG_DEVINFO_PDPORTS_SHIFT (2) 102 #define CCG_DEVINFO_PDPORTS_MASK (0x3 << CCG_DEVINFO_PDPORTS_SHIFT) 103 u8 mode; 104 u8 bl_mode; 105 __le16 silicon_id; 106 __le16 bl_last_row; 107 } __packed; 108 109 struct version_format { 110 __le16 build; 111 u8 patch; 112 u8 ver; 113 #define CCG_VERSION_PATCH(x) ((x) << 16) 114 #define CCG_VERSION(x) ((x) << 24) 115 #define CCG_VERSION_MIN_SHIFT (0) 116 #define CCG_VERSION_MIN_MASK (0xf << CCG_VERSION_MIN_SHIFT) 117 #define CCG_VERSION_MAJ_SHIFT (4) 118 #define CCG_VERSION_MAJ_MASK (0xf << CCG_VERSION_MAJ_SHIFT) 119 } __packed; 120 121 /* 122 * Firmware version 3.1.10 or earlier, built for NVIDIA has known issue 123 * of missing interrupt when a device is connected for runtime resume 124 */ 125 #define CCG_FW_BUILD_NVIDIA (('n' << 8) | 'v') 126 #define CCG_OLD_FW_VERSION (CCG_VERSION(0x31) | CCG_VERSION_PATCH(10)) 127 128 /* Altmode offset for NVIDIA Function Test Board (FTB) */ 129 #define NVIDIA_FTB_DP_OFFSET (2) 130 #define NVIDIA_FTB_DBG_OFFSET (3) 131 132 struct version_info { 133 struct version_format base; 134 struct version_format app; 135 }; 136 137 struct fw_config_table { 138 u32 identity; 139 u16 table_size; 140 u8 fwct_version; 141 u8 is_key_change; 142 u8 guid[16]; 143 struct version_format base; 144 struct version_format app; 145 u8 primary_fw_digest[32]; 146 u32 key_exp_length; 147 u8 key_modulus[256]; 148 u8 key_exp[4]; 149 }; 150 151 /* CCGx response codes */ 152 enum ccg_resp_code { 153 CMD_NO_RESP = 0x00, 154 CMD_SUCCESS = 0x02, 155 FLASH_DATA_AVAILABLE = 0x03, 156 CMD_INVALID = 0x05, 157 FLASH_UPDATE_FAIL = 0x07, 158 INVALID_FW = 0x08, 159 INVALID_ARG = 0x09, 160 CMD_NOT_SUPPORT = 0x0A, 161 TRANSACTION_FAIL = 0x0C, 162 PD_CMD_FAIL = 0x0D, 163 UNDEF_ERROR = 0x0F, 164 INVALID_RESP = 0x10, 165 }; 166 167 #define CCG_EVENT_MAX (EVENT_INDEX + 43) 168 169 struct ccg_cmd { 170 u16 reg; 171 u32 data; 172 int len; 173 u32 delay; /* ms delay for cmd timeout */ 174 }; 175 176 struct ccg_resp { 177 u8 code; 178 u8 length; 179 }; 180 181 struct ucsi_ccg_altmode { 182 u16 svid; 183 u32 mid; 184 u8 linked_idx; 185 u8 active_idx; 186 #define UCSI_MULTI_DP_INDEX (0xff) 187 bool checked; 188 } __packed; 189 190 struct ucsi_ccg { 191 struct device *dev; 192 struct ucsi *ucsi; 193 struct i2c_client *client; 194 195 struct ccg_dev_info info; 196 /* version info for boot, primary and secondary */ 197 struct version_info version[FW2 + 1]; 198 u32 fw_version; 199 /* CCG HPI communication flags */ 200 unsigned long flags; 201 #define RESET_PENDING 0 202 #define DEV_CMD_PENDING 1 203 struct ccg_resp dev_resp; 204 u8 cmd_resp; 205 int port_num; 206 int irq; 207 struct work_struct work; 208 struct mutex lock; /* to sync between user and driver thread */ 209 210 /* fw build with vendor information */ 211 u16 fw_build; 212 struct work_struct pm_work; 213 214 struct completion complete; 215 216 u64 last_cmd_sent; 217 bool has_multiple_dp; 218 struct ucsi_ccg_altmode orig[UCSI_MAX_ALTMODES]; 219 struct ucsi_ccg_altmode updated[UCSI_MAX_ALTMODES]; 220 }; 221 222 static int ccg_read(struct ucsi_ccg *uc, u16 rab, u8 *data, u32 len) 223 { 224 struct i2c_client *client = uc->client; 225 const struct i2c_adapter_quirks *quirks = client->adapter->quirks; 226 unsigned char buf[2]; 227 struct i2c_msg msgs[] = { 228 { 229 .addr = client->addr, 230 .flags = 0x0, 231 .len = sizeof(buf), 232 .buf = buf, 233 }, 234 { 235 .addr = client->addr, 236 .flags = I2C_M_RD, 237 .buf = data, 238 }, 239 }; 240 u32 rlen, rem_len = len, max_read_len = len; 241 int status; 242 243 /* check any max_read_len limitation on i2c adapter */ 244 if (quirks && quirks->max_read_len) 245 max_read_len = quirks->max_read_len; 246 247 pm_runtime_get_sync(uc->dev); 248 while (rem_len > 0) { 249 msgs[1].buf = &data[len - rem_len]; 250 rlen = min_t(u16, rem_len, max_read_len); 251 msgs[1].len = rlen; 252 put_unaligned_le16(rab, buf); 253 status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 254 if (status < 0) { 255 dev_err(uc->dev, "i2c_transfer failed %d\n", status); 256 pm_runtime_put_sync(uc->dev); 257 return status; 258 } 259 rab += rlen; 260 rem_len -= rlen; 261 } 262 263 pm_runtime_put_sync(uc->dev); 264 return 0; 265 } 266 267 static int ccg_write(struct ucsi_ccg *uc, u16 rab, const u8 *data, u32 len) 268 { 269 struct i2c_client *client = uc->client; 270 unsigned char *buf; 271 struct i2c_msg msgs[] = { 272 { 273 .addr = client->addr, 274 .flags = 0x0, 275 } 276 }; 277 int status; 278 279 buf = kzalloc(len + sizeof(rab), GFP_KERNEL); 280 if (!buf) 281 return -ENOMEM; 282 283 put_unaligned_le16(rab, buf); 284 memcpy(buf + sizeof(rab), data, len); 285 286 msgs[0].len = len + sizeof(rab); 287 msgs[0].buf = buf; 288 289 pm_runtime_get_sync(uc->dev); 290 status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 291 if (status < 0) { 292 dev_err(uc->dev, "i2c_transfer failed %d\n", status); 293 pm_runtime_put_sync(uc->dev); 294 kfree(buf); 295 return status; 296 } 297 298 pm_runtime_put_sync(uc->dev); 299 kfree(buf); 300 return 0; 301 } 302 303 static int ucsi_ccg_init(struct ucsi_ccg *uc) 304 { 305 unsigned int count = 10; 306 u8 data; 307 int status; 308 309 data = CCGX_RAB_UCSI_CONTROL_STOP; 310 status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data)); 311 if (status < 0) 312 return status; 313 314 data = CCGX_RAB_UCSI_CONTROL_START; 315 status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data)); 316 if (status < 0) 317 return status; 318 319 /* 320 * Flush CCGx RESPONSE queue by acking interrupts. Above ucsi control 321 * register write will push response which must be cleared. 322 */ 323 do { 324 status = ccg_read(uc, CCGX_RAB_INTR_REG, &data, sizeof(data)); 325 if (status < 0) 326 return status; 327 328 if (!(data & DEV_INT)) 329 return 0; 330 331 status = ccg_write(uc, CCGX_RAB_INTR_REG, &data, sizeof(data)); 332 if (status < 0) 333 return status; 334 335 usleep_range(10000, 11000); 336 } while (--count); 337 338 return -ETIMEDOUT; 339 } 340 341 static void ucsi_ccg_update_get_current_cam_cmd(struct ucsi_ccg *uc, u8 *data) 342 { 343 u8 cam, new_cam; 344 345 cam = data[0]; 346 new_cam = uc->orig[cam].linked_idx; 347 uc->updated[new_cam].active_idx = cam; 348 data[0] = new_cam; 349 } 350 351 static bool ucsi_ccg_update_altmodes(struct ucsi *ucsi, 352 struct ucsi_altmode *orig, 353 struct ucsi_altmode *updated) 354 { 355 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi); 356 struct ucsi_ccg_altmode *alt, *new_alt; 357 int i, j, k = 0; 358 bool found = false; 359 360 alt = uc->orig; 361 new_alt = uc->updated; 362 memset(uc->updated, 0, sizeof(uc->updated)); 363 364 /* 365 * Copy original connector altmodes to new structure. 366 * We need this before second loop since second loop 367 * checks for duplicate altmodes. 368 */ 369 for (i = 0; i < UCSI_MAX_ALTMODES; i++) { 370 alt[i].svid = orig[i].svid; 371 alt[i].mid = orig[i].mid; 372 if (!alt[i].svid) 373 break; 374 } 375 376 for (i = 0; i < UCSI_MAX_ALTMODES; i++) { 377 if (!alt[i].svid) 378 break; 379 380 /* already checked and considered */ 381 if (alt[i].checked) 382 continue; 383 384 if (!DP_CONF_GET_PIN_ASSIGN(alt[i].mid)) { 385 /* Found Non DP altmode */ 386 new_alt[k].svid = alt[i].svid; 387 new_alt[k].mid |= alt[i].mid; 388 new_alt[k].linked_idx = i; 389 alt[i].linked_idx = k; 390 updated[k].svid = new_alt[k].svid; 391 updated[k].mid = new_alt[k].mid; 392 k++; 393 continue; 394 } 395 396 for (j = i + 1; j < UCSI_MAX_ALTMODES; j++) { 397 if (alt[i].svid != alt[j].svid || 398 !DP_CONF_GET_PIN_ASSIGN(alt[j].mid)) { 399 continue; 400 } else { 401 /* Found duplicate DP mode */ 402 new_alt[k].svid = alt[i].svid; 403 new_alt[k].mid |= alt[i].mid | alt[j].mid; 404 new_alt[k].linked_idx = UCSI_MULTI_DP_INDEX; 405 alt[i].linked_idx = k; 406 alt[j].linked_idx = k; 407 alt[j].checked = true; 408 found = true; 409 } 410 } 411 if (found) { 412 uc->has_multiple_dp = true; 413 } else { 414 /* Didn't find any duplicate DP altmode */ 415 new_alt[k].svid = alt[i].svid; 416 new_alt[k].mid |= alt[i].mid; 417 new_alt[k].linked_idx = i; 418 alt[i].linked_idx = k; 419 } 420 updated[k].svid = new_alt[k].svid; 421 updated[k].mid = new_alt[k].mid; 422 k++; 423 } 424 return found; 425 } 426 427 static void ucsi_ccg_update_set_new_cam_cmd(struct ucsi_ccg *uc, 428 struct ucsi_connector *con, 429 u64 *cmd) 430 { 431 struct ucsi_ccg_altmode *new_port, *port; 432 struct typec_altmode *alt = NULL; 433 u8 new_cam, cam, pin; 434 bool enter_new_mode; 435 int i, j, k = 0xff; 436 437 port = uc->orig; 438 new_cam = UCSI_SET_NEW_CAM_GET_AM(*cmd); 439 new_port = &uc->updated[new_cam]; 440 cam = new_port->linked_idx; 441 enter_new_mode = UCSI_SET_NEW_CAM_ENTER(*cmd); 442 443 /* 444 * If CAM is UCSI_MULTI_DP_INDEX then this is DP altmode 445 * with multiple DP mode. Find out CAM for best pin assignment 446 * among all DP mode. Priorite pin E->D->C after making sure 447 * the partner supports that pin. 448 */ 449 if (cam == UCSI_MULTI_DP_INDEX) { 450 if (enter_new_mode) { 451 for (i = 0; con->partner_altmode[i]; i++) { 452 alt = con->partner_altmode[i]; 453 if (alt->svid == new_port->svid) 454 break; 455 } 456 /* 457 * alt will always be non NULL since this is 458 * UCSI_SET_NEW_CAM command and so there will be 459 * at least one con->partner_altmode[i] with svid 460 * matching with new_port->svid. 461 */ 462 for (j = 0; port[j].svid; j++) { 463 pin = DP_CONF_GET_PIN_ASSIGN(port[j].mid); 464 if (alt && port[j].svid == alt->svid && 465 (pin & DP_CONF_GET_PIN_ASSIGN(alt->vdo))) { 466 /* prioritize pin E->D->C */ 467 if (k == 0xff || (k != 0xff && pin > 468 DP_CONF_GET_PIN_ASSIGN(port[k].mid)) 469 ) { 470 k = j; 471 } 472 } 473 } 474 cam = k; 475 new_port->active_idx = cam; 476 } else { 477 cam = new_port->active_idx; 478 } 479 } 480 *cmd &= ~UCSI_SET_NEW_CAM_AM_MASK; 481 *cmd |= UCSI_SET_NEW_CAM_SET_AM(cam); 482 } 483 484 /* 485 * Change the order of vdo values of NVIDIA test device FTB 486 * (Function Test Board) which reports altmode list with vdo=0x3 487 * first and then vdo=0x. Current logic to assign mode value is 488 * based on order in altmode list and it causes a mismatch of CON 489 * and SOP altmodes since NVIDIA GPU connector has order of vdo=0x1 490 * first and then vdo=0x3 491 */ 492 static void ucsi_ccg_nvidia_altmode(struct ucsi_ccg *uc, 493 struct ucsi_altmode *alt) 494 { 495 switch (UCSI_ALTMODE_OFFSET(uc->last_cmd_sent)) { 496 case NVIDIA_FTB_DP_OFFSET: 497 if (alt[0].mid == USB_TYPEC_NVIDIA_VLINK_DBG_VDO) 498 alt[0].mid = USB_TYPEC_NVIDIA_VLINK_DP_VDO | 499 DP_CAP_DP_SIGNALING | DP_CAP_USB | 500 DP_CONF_SET_PIN_ASSIGN(BIT(DP_PIN_ASSIGN_E)); 501 break; 502 case NVIDIA_FTB_DBG_OFFSET: 503 if (alt[0].mid == USB_TYPEC_NVIDIA_VLINK_DP_VDO) 504 alt[0].mid = USB_TYPEC_NVIDIA_VLINK_DBG_VDO; 505 break; 506 default: 507 break; 508 } 509 } 510 511 static int ucsi_ccg_read(struct ucsi *ucsi, unsigned int offset, 512 void *val, size_t val_len) 513 { 514 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi); 515 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(offset); 516 struct ucsi_altmode *alt; 517 int ret; 518 519 ret = ccg_read(uc, reg, val, val_len); 520 if (ret) 521 return ret; 522 523 if (offset != UCSI_MESSAGE_IN) 524 return ret; 525 526 switch (UCSI_COMMAND(uc->last_cmd_sent)) { 527 case UCSI_GET_CURRENT_CAM: 528 if (uc->has_multiple_dp) 529 ucsi_ccg_update_get_current_cam_cmd(uc, (u8 *)val); 530 break; 531 case UCSI_GET_ALTERNATE_MODES: 532 if (UCSI_ALTMODE_RECIPIENT(uc->last_cmd_sent) == 533 UCSI_RECIPIENT_SOP) { 534 alt = val; 535 if (alt[0].svid == USB_TYPEC_NVIDIA_VLINK_SID) 536 ucsi_ccg_nvidia_altmode(uc, alt); 537 } 538 break; 539 default: 540 break; 541 } 542 uc->last_cmd_sent = 0; 543 544 return ret; 545 } 546 547 static int ucsi_ccg_async_write(struct ucsi *ucsi, unsigned int offset, 548 const void *val, size_t val_len) 549 { 550 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(offset); 551 552 return ccg_write(ucsi_get_drvdata(ucsi), reg, val, val_len); 553 } 554 555 static int ucsi_ccg_sync_write(struct ucsi *ucsi, unsigned int offset, 556 const void *val, size_t val_len) 557 { 558 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi); 559 struct ucsi_connector *con; 560 int con_index; 561 int ret; 562 563 mutex_lock(&uc->lock); 564 pm_runtime_get_sync(uc->dev); 565 set_bit(DEV_CMD_PENDING, &uc->flags); 566 567 if (offset == UCSI_CONTROL && val_len == sizeof(uc->last_cmd_sent)) { 568 uc->last_cmd_sent = *(u64 *)val; 569 570 if (UCSI_COMMAND(uc->last_cmd_sent) == UCSI_SET_NEW_CAM && 571 uc->has_multiple_dp) { 572 con_index = (uc->last_cmd_sent >> 16) & 573 UCSI_CMD_CONNECTOR_MASK; 574 con = &uc->ucsi->connector[con_index - 1]; 575 ucsi_ccg_update_set_new_cam_cmd(uc, con, (u64 *)val); 576 } 577 } 578 579 ret = ucsi_ccg_async_write(ucsi, offset, val, val_len); 580 if (ret) 581 goto err_clear_bit; 582 583 if (!wait_for_completion_timeout(&uc->complete, msecs_to_jiffies(5000))) 584 ret = -ETIMEDOUT; 585 586 err_clear_bit: 587 clear_bit(DEV_CMD_PENDING, &uc->flags); 588 pm_runtime_put_sync(uc->dev); 589 mutex_unlock(&uc->lock); 590 591 return ret; 592 } 593 594 static const struct ucsi_operations ucsi_ccg_ops = { 595 .read = ucsi_ccg_read, 596 .sync_write = ucsi_ccg_sync_write, 597 .async_write = ucsi_ccg_async_write, 598 .update_altmodes = ucsi_ccg_update_altmodes 599 }; 600 601 static irqreturn_t ccg_irq_handler(int irq, void *data) 602 { 603 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_CCI); 604 struct ucsi_ccg *uc = data; 605 u8 intr_reg; 606 u32 cci; 607 int ret; 608 609 ret = ccg_read(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg)); 610 if (ret) 611 return ret; 612 613 ret = ccg_read(uc, reg, (void *)&cci, sizeof(cci)); 614 if (ret) 615 goto err_clear_irq; 616 617 if (UCSI_CCI_CONNECTOR(cci)) 618 ucsi_connector_change(uc->ucsi, UCSI_CCI_CONNECTOR(cci)); 619 620 if (test_bit(DEV_CMD_PENDING, &uc->flags) && 621 cci & (UCSI_CCI_ACK_COMPLETE | UCSI_CCI_COMMAND_COMPLETE)) 622 complete(&uc->complete); 623 624 err_clear_irq: 625 ccg_write(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg)); 626 627 return IRQ_HANDLED; 628 } 629 630 static int ccg_request_irq(struct ucsi_ccg *uc) 631 { 632 unsigned long flags = IRQF_ONESHOT; 633 634 if (!has_acpi_companion(uc->dev)) 635 flags |= IRQF_TRIGGER_HIGH; 636 637 return request_threaded_irq(uc->irq, NULL, ccg_irq_handler, flags, dev_name(uc->dev), uc); 638 } 639 640 static void ccg_pm_workaround_work(struct work_struct *pm_work) 641 { 642 ccg_irq_handler(0, container_of(pm_work, struct ucsi_ccg, pm_work)); 643 } 644 645 static int get_fw_info(struct ucsi_ccg *uc) 646 { 647 int err; 648 649 err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)(&uc->version), 650 sizeof(uc->version)); 651 if (err < 0) 652 return err; 653 654 uc->fw_version = CCG_VERSION(uc->version[FW2].app.ver) | 655 CCG_VERSION_PATCH(uc->version[FW2].app.patch); 656 657 err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info), 658 sizeof(uc->info)); 659 if (err < 0) 660 return err; 661 662 return 0; 663 } 664 665 static inline bool invalid_async_evt(int code) 666 { 667 return (code >= CCG_EVENT_MAX) || (code < EVENT_INDEX); 668 } 669 670 static void ccg_process_response(struct ucsi_ccg *uc) 671 { 672 struct device *dev = uc->dev; 673 674 if (uc->dev_resp.code & ASYNC_EVENT) { 675 if (uc->dev_resp.code == RESET_COMPLETE) { 676 if (test_bit(RESET_PENDING, &uc->flags)) 677 uc->cmd_resp = uc->dev_resp.code; 678 get_fw_info(uc); 679 } 680 if (invalid_async_evt(uc->dev_resp.code)) 681 dev_err(dev, "invalid async evt %d\n", 682 uc->dev_resp.code); 683 } else { 684 if (test_bit(DEV_CMD_PENDING, &uc->flags)) { 685 uc->cmd_resp = uc->dev_resp.code; 686 clear_bit(DEV_CMD_PENDING, &uc->flags); 687 } else { 688 dev_err(dev, "dev resp 0x%04x but no cmd pending\n", 689 uc->dev_resp.code); 690 } 691 } 692 } 693 694 static int ccg_read_response(struct ucsi_ccg *uc) 695 { 696 unsigned long target = jiffies + msecs_to_jiffies(1000); 697 struct device *dev = uc->dev; 698 u8 intval; 699 int status; 700 701 /* wait for interrupt status to get updated */ 702 do { 703 status = ccg_read(uc, CCGX_RAB_INTR_REG, &intval, 704 sizeof(intval)); 705 if (status < 0) 706 return status; 707 708 if (intval & DEV_INT) 709 break; 710 usleep_range(500, 600); 711 } while (time_is_after_jiffies(target)); 712 713 if (time_is_before_jiffies(target)) { 714 dev_err(dev, "response timeout error\n"); 715 return -ETIME; 716 } 717 718 status = ccg_read(uc, CCGX_RAB_RESPONSE, (u8 *)&uc->dev_resp, 719 sizeof(uc->dev_resp)); 720 if (status < 0) 721 return status; 722 723 status = ccg_write(uc, CCGX_RAB_INTR_REG, &intval, sizeof(intval)); 724 if (status < 0) 725 return status; 726 727 return 0; 728 } 729 730 /* Caller must hold uc->lock */ 731 static int ccg_send_command(struct ucsi_ccg *uc, struct ccg_cmd *cmd) 732 { 733 struct device *dev = uc->dev; 734 int ret; 735 736 switch (cmd->reg & 0xF000) { 737 case DEV_REG_IDX: 738 set_bit(DEV_CMD_PENDING, &uc->flags); 739 break; 740 default: 741 dev_err(dev, "invalid cmd register\n"); 742 break; 743 } 744 745 ret = ccg_write(uc, cmd->reg, (u8 *)&cmd->data, cmd->len); 746 if (ret < 0) 747 return ret; 748 749 msleep(cmd->delay); 750 751 ret = ccg_read_response(uc); 752 if (ret < 0) { 753 dev_err(dev, "response read error\n"); 754 switch (cmd->reg & 0xF000) { 755 case DEV_REG_IDX: 756 clear_bit(DEV_CMD_PENDING, &uc->flags); 757 break; 758 default: 759 dev_err(dev, "invalid cmd register\n"); 760 break; 761 } 762 return -EIO; 763 } 764 ccg_process_response(uc); 765 766 return uc->cmd_resp; 767 } 768 769 static int ccg_cmd_enter_flashing(struct ucsi_ccg *uc) 770 { 771 struct ccg_cmd cmd; 772 int ret; 773 774 cmd.reg = CCGX_RAB_ENTER_FLASHING; 775 cmd.data = FLASH_ENTER_SIG; 776 cmd.len = 1; 777 cmd.delay = 50; 778 779 mutex_lock(&uc->lock); 780 781 ret = ccg_send_command(uc, &cmd); 782 783 mutex_unlock(&uc->lock); 784 785 if (ret != CMD_SUCCESS) { 786 dev_err(uc->dev, "enter flashing failed ret=%d\n", ret); 787 return ret; 788 } 789 790 return 0; 791 } 792 793 static int ccg_cmd_reset(struct ucsi_ccg *uc) 794 { 795 struct ccg_cmd cmd; 796 u8 *p; 797 int ret; 798 799 p = (u8 *)&cmd.data; 800 cmd.reg = CCGX_RAB_RESET_REQ; 801 p[0] = RESET_SIG; 802 p[1] = CMD_RESET_DEV; 803 cmd.len = 2; 804 cmd.delay = 5000; 805 806 mutex_lock(&uc->lock); 807 808 set_bit(RESET_PENDING, &uc->flags); 809 810 ret = ccg_send_command(uc, &cmd); 811 if (ret != RESET_COMPLETE) 812 goto err_clear_flag; 813 814 ret = 0; 815 816 err_clear_flag: 817 clear_bit(RESET_PENDING, &uc->flags); 818 819 mutex_unlock(&uc->lock); 820 821 return ret; 822 } 823 824 static int ccg_cmd_port_control(struct ucsi_ccg *uc, bool enable) 825 { 826 struct ccg_cmd cmd; 827 int ret; 828 829 cmd.reg = CCGX_RAB_PDPORT_ENABLE; 830 if (enable) 831 cmd.data = (uc->port_num == 1) ? 832 PDPORT_1 : (PDPORT_1 | PDPORT_2); 833 else 834 cmd.data = 0x0; 835 cmd.len = 1; 836 cmd.delay = 10; 837 838 mutex_lock(&uc->lock); 839 840 ret = ccg_send_command(uc, &cmd); 841 842 mutex_unlock(&uc->lock); 843 844 if (ret != CMD_SUCCESS) { 845 dev_err(uc->dev, "port control failed ret=%d\n", ret); 846 return ret; 847 } 848 return 0; 849 } 850 851 static int ccg_cmd_jump_boot_mode(struct ucsi_ccg *uc, int bl_mode) 852 { 853 struct ccg_cmd cmd; 854 int ret; 855 856 cmd.reg = CCGX_RAB_JUMP_TO_BOOT; 857 858 if (bl_mode) 859 cmd.data = TO_BOOT; 860 else 861 cmd.data = TO_ALT_FW; 862 863 cmd.len = 1; 864 cmd.delay = 100; 865 866 mutex_lock(&uc->lock); 867 868 set_bit(RESET_PENDING, &uc->flags); 869 870 ret = ccg_send_command(uc, &cmd); 871 if (ret != RESET_COMPLETE) 872 goto err_clear_flag; 873 874 ret = 0; 875 876 err_clear_flag: 877 clear_bit(RESET_PENDING, &uc->flags); 878 879 mutex_unlock(&uc->lock); 880 881 return ret; 882 } 883 884 static int 885 ccg_cmd_write_flash_row(struct ucsi_ccg *uc, u16 row, 886 const void *data, u8 fcmd) 887 { 888 struct i2c_client *client = uc->client; 889 struct ccg_cmd cmd; 890 u8 buf[CCG4_ROW_SIZE + 2]; 891 u8 *p; 892 int ret; 893 894 /* Copy the data into the flash read/write memory. */ 895 put_unaligned_le16(REG_FLASH_RW_MEM, buf); 896 897 memcpy(buf + 2, data, CCG4_ROW_SIZE); 898 899 mutex_lock(&uc->lock); 900 901 ret = i2c_master_send(client, buf, CCG4_ROW_SIZE + 2); 902 if (ret != CCG4_ROW_SIZE + 2) { 903 dev_err(uc->dev, "REG_FLASH_RW_MEM write fail %d\n", ret); 904 mutex_unlock(&uc->lock); 905 return ret < 0 ? ret : -EIO; 906 } 907 908 /* Use the FLASH_ROW_READ_WRITE register to trigger */ 909 /* writing of data to the desired flash row */ 910 p = (u8 *)&cmd.data; 911 cmd.reg = CCGX_RAB_FLASH_ROW_RW; 912 p[0] = FLASH_SIG; 913 p[1] = fcmd; 914 put_unaligned_le16(row, &p[2]); 915 cmd.len = 4; 916 cmd.delay = 50; 917 if (fcmd == FLASH_FWCT_SIG_WR_CMD) 918 cmd.delay += 400; 919 if (row == 510) 920 cmd.delay += 220; 921 ret = ccg_send_command(uc, &cmd); 922 923 mutex_unlock(&uc->lock); 924 925 if (ret != CMD_SUCCESS) { 926 dev_err(uc->dev, "write flash row failed ret=%d\n", ret); 927 return ret; 928 } 929 930 return 0; 931 } 932 933 static int ccg_cmd_validate_fw(struct ucsi_ccg *uc, unsigned int fwid) 934 { 935 struct ccg_cmd cmd; 936 int ret; 937 938 cmd.reg = CCGX_RAB_VALIDATE_FW; 939 cmd.data = fwid; 940 cmd.len = 1; 941 cmd.delay = 500; 942 943 mutex_lock(&uc->lock); 944 945 ret = ccg_send_command(uc, &cmd); 946 947 mutex_unlock(&uc->lock); 948 949 if (ret != CMD_SUCCESS) 950 return ret; 951 952 return 0; 953 } 954 955 static bool ccg_check_vendor_version(struct ucsi_ccg *uc, 956 struct version_format *app, 957 struct fw_config_table *fw_cfg) 958 { 959 struct device *dev = uc->dev; 960 961 /* Check if the fw build is for supported vendors */ 962 if (le16_to_cpu(app->build) != uc->fw_build) { 963 dev_info(dev, "current fw is not from supported vendor\n"); 964 return false; 965 } 966 967 /* Check if the new fw build is for supported vendors */ 968 if (le16_to_cpu(fw_cfg->app.build) != uc->fw_build) { 969 dev_info(dev, "new fw is not from supported vendor\n"); 970 return false; 971 } 972 return true; 973 } 974 975 static bool ccg_check_fw_version(struct ucsi_ccg *uc, const char *fw_name, 976 struct version_format *app) 977 { 978 const struct firmware *fw = NULL; 979 struct device *dev = uc->dev; 980 struct fw_config_table fw_cfg; 981 u32 cur_version, new_version; 982 bool is_later = false; 983 984 if (request_firmware(&fw, fw_name, dev) != 0) { 985 dev_err(dev, "error: Failed to open cyacd file %s\n", fw_name); 986 return false; 987 } 988 989 /* 990 * check if signed fw 991 * last part of fw image is fw cfg table and signature 992 */ 993 if (fw->size < sizeof(fw_cfg) + FW_CFG_TABLE_SIG_SIZE) 994 goto out_release_firmware; 995 996 memcpy((uint8_t *)&fw_cfg, fw->data + fw->size - 997 sizeof(fw_cfg) - FW_CFG_TABLE_SIG_SIZE, sizeof(fw_cfg)); 998 999 if (fw_cfg.identity != ('F' | 'W' << 8 | 'C' << 16 | 'T' << 24)) { 1000 dev_info(dev, "not a signed image\n"); 1001 goto out_release_firmware; 1002 } 1003 1004 /* compare input version with FWCT version */ 1005 cur_version = le16_to_cpu(app->build) | CCG_VERSION_PATCH(app->patch) | 1006 CCG_VERSION(app->ver); 1007 1008 new_version = le16_to_cpu(fw_cfg.app.build) | 1009 CCG_VERSION_PATCH(fw_cfg.app.patch) | 1010 CCG_VERSION(fw_cfg.app.ver); 1011 1012 if (!ccg_check_vendor_version(uc, app, &fw_cfg)) 1013 goto out_release_firmware; 1014 1015 if (new_version > cur_version) 1016 is_later = true; 1017 1018 out_release_firmware: 1019 release_firmware(fw); 1020 return is_later; 1021 } 1022 1023 static int ccg_fw_update_needed(struct ucsi_ccg *uc, 1024 enum enum_flash_mode *mode) 1025 { 1026 struct device *dev = uc->dev; 1027 int err; 1028 struct version_info version[3]; 1029 1030 err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info), 1031 sizeof(uc->info)); 1032 if (err) { 1033 dev_err(dev, "read device mode failed\n"); 1034 return err; 1035 } 1036 1037 err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)version, 1038 sizeof(version)); 1039 if (err) { 1040 dev_err(dev, "read device mode failed\n"); 1041 return err; 1042 } 1043 1044 if (memcmp(&version[FW1], "\0\0\0\0\0\0\0\0", 1045 sizeof(struct version_info)) == 0) { 1046 dev_info(dev, "secondary fw is not flashed\n"); 1047 *mode = SECONDARY_BL; 1048 } else if (le16_to_cpu(version[FW1].base.build) < 1049 secondary_fw_min_ver) { 1050 dev_info(dev, "secondary fw version is too low (< %d)\n", 1051 secondary_fw_min_ver); 1052 *mode = SECONDARY; 1053 } else if (memcmp(&version[FW2], "\0\0\0\0\0\0\0\0", 1054 sizeof(struct version_info)) == 0) { 1055 dev_info(dev, "primary fw is not flashed\n"); 1056 *mode = PRIMARY; 1057 } else if (ccg_check_fw_version(uc, ccg_fw_names[PRIMARY], 1058 &version[FW2].app)) { 1059 dev_info(dev, "found primary fw with later version\n"); 1060 *mode = PRIMARY; 1061 } else { 1062 dev_info(dev, "secondary and primary fw are the latest\n"); 1063 *mode = FLASH_NOT_NEEDED; 1064 } 1065 return 0; 1066 } 1067 1068 static int do_flash(struct ucsi_ccg *uc, enum enum_flash_mode mode) 1069 { 1070 struct device *dev = uc->dev; 1071 const struct firmware *fw = NULL; 1072 const char *p, *s; 1073 const char *eof; 1074 int err, row, len, line_sz, line_cnt = 0; 1075 unsigned long start_time = jiffies; 1076 struct fw_config_table fw_cfg; 1077 u8 fw_cfg_sig[FW_CFG_TABLE_SIG_SIZE]; 1078 u8 *wr_buf; 1079 1080 err = request_firmware(&fw, ccg_fw_names[mode], dev); 1081 if (err) { 1082 dev_err(dev, "request %s failed err=%d\n", 1083 ccg_fw_names[mode], err); 1084 return err; 1085 } 1086 1087 if (((uc->info.mode & CCG_DEVINFO_FWMODE_MASK) >> 1088 CCG_DEVINFO_FWMODE_SHIFT) == FW2) { 1089 err = ccg_cmd_port_control(uc, false); 1090 if (err < 0) 1091 goto release_fw; 1092 err = ccg_cmd_jump_boot_mode(uc, 0); 1093 if (err < 0) 1094 goto release_fw; 1095 } 1096 1097 eof = fw->data + fw->size; 1098 1099 /* 1100 * check if signed fw 1101 * last part of fw image is fw cfg table and signature 1102 */ 1103 if (fw->size < sizeof(fw_cfg) + sizeof(fw_cfg_sig)) 1104 goto not_signed_fw; 1105 1106 memcpy((uint8_t *)&fw_cfg, fw->data + fw->size - 1107 sizeof(fw_cfg) - sizeof(fw_cfg_sig), sizeof(fw_cfg)); 1108 1109 if (fw_cfg.identity != ('F' | ('W' << 8) | ('C' << 16) | ('T' << 24))) { 1110 dev_info(dev, "not a signed image\n"); 1111 goto not_signed_fw; 1112 } 1113 eof = fw->data + fw->size - sizeof(fw_cfg) - sizeof(fw_cfg_sig); 1114 1115 memcpy((uint8_t *)&fw_cfg_sig, 1116 fw->data + fw->size - sizeof(fw_cfg_sig), sizeof(fw_cfg_sig)); 1117 1118 /* flash fw config table and signature first */ 1119 err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg, 1120 FLASH_FWCT1_WR_CMD); 1121 if (err) 1122 goto release_fw; 1123 1124 err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg + CCG4_ROW_SIZE, 1125 FLASH_FWCT2_WR_CMD); 1126 if (err) 1127 goto release_fw; 1128 1129 err = ccg_cmd_write_flash_row(uc, 0, &fw_cfg_sig, 1130 FLASH_FWCT_SIG_WR_CMD); 1131 if (err) 1132 goto release_fw; 1133 1134 not_signed_fw: 1135 wr_buf = kzalloc(CCG4_ROW_SIZE + 4, GFP_KERNEL); 1136 if (!wr_buf) { 1137 err = -ENOMEM; 1138 goto release_fw; 1139 } 1140 1141 err = ccg_cmd_enter_flashing(uc); 1142 if (err) 1143 goto release_mem; 1144 1145 /***************************************************************** 1146 * CCG firmware image (.cyacd) file line format 1147 * 1148 * :00rrrrllll[dd....]cc/r/n 1149 * 1150 * :00 header 1151 * rrrr is row number to flash (4 char) 1152 * llll is data len to flash (4 char) 1153 * dd is a data field represents one byte of data (512 char) 1154 * cc is checksum (2 char) 1155 * \r\n newline 1156 * 1157 * Total length: 3 + 4 + 4 + 512 + 2 + 2 = 527 1158 * 1159 *****************************************************************/ 1160 1161 p = strnchr(fw->data, fw->size, ':'); 1162 while (p < eof) { 1163 s = strnchr(p + 1, eof - p - 1, ':'); 1164 1165 if (!s) 1166 s = eof; 1167 1168 line_sz = s - p; 1169 1170 if (line_sz != CYACD_LINE_SIZE) { 1171 dev_err(dev, "Bad FW format line_sz=%d\n", line_sz); 1172 err = -EINVAL; 1173 goto release_mem; 1174 } 1175 1176 if (hex2bin(wr_buf, p + 3, CCG4_ROW_SIZE + 4)) { 1177 err = -EINVAL; 1178 goto release_mem; 1179 } 1180 1181 row = get_unaligned_be16(wr_buf); 1182 len = get_unaligned_be16(&wr_buf[2]); 1183 1184 if (len != CCG4_ROW_SIZE) { 1185 err = -EINVAL; 1186 goto release_mem; 1187 } 1188 1189 err = ccg_cmd_write_flash_row(uc, row, wr_buf + 4, 1190 FLASH_WR_CMD); 1191 if (err) 1192 goto release_mem; 1193 1194 line_cnt++; 1195 p = s; 1196 } 1197 1198 dev_info(dev, "total %d row flashed. time: %dms\n", 1199 line_cnt, jiffies_to_msecs(jiffies - start_time)); 1200 1201 err = ccg_cmd_validate_fw(uc, (mode == PRIMARY) ? FW2 : FW1); 1202 if (err) 1203 dev_err(dev, "%s validation failed err=%d\n", 1204 (mode == PRIMARY) ? "FW2" : "FW1", err); 1205 else 1206 dev_info(dev, "%s validated\n", 1207 (mode == PRIMARY) ? "FW2" : "FW1"); 1208 1209 err = ccg_cmd_port_control(uc, false); 1210 if (err < 0) 1211 goto release_mem; 1212 1213 err = ccg_cmd_reset(uc); 1214 if (err < 0) 1215 goto release_mem; 1216 1217 err = ccg_cmd_port_control(uc, true); 1218 if (err < 0) 1219 goto release_mem; 1220 1221 release_mem: 1222 kfree(wr_buf); 1223 1224 release_fw: 1225 release_firmware(fw); 1226 return err; 1227 } 1228 1229 /******************************************************************************* 1230 * CCG4 has two copies of the firmware in addition to the bootloader. 1231 * If the device is running FW1, FW2 can be updated with the new version. 1232 * Dual firmware mode allows the CCG device to stay in a PD contract and support 1233 * USB PD and Type-C functionality while a firmware update is in progress. 1234 ******************************************************************************/ 1235 static int ccg_fw_update(struct ucsi_ccg *uc, enum enum_flash_mode flash_mode) 1236 { 1237 int err = 0; 1238 1239 while (flash_mode != FLASH_NOT_NEEDED) { 1240 err = do_flash(uc, flash_mode); 1241 if (err < 0) 1242 return err; 1243 err = ccg_fw_update_needed(uc, &flash_mode); 1244 if (err < 0) 1245 return err; 1246 } 1247 dev_info(uc->dev, "CCG FW update successful\n"); 1248 1249 return err; 1250 } 1251 1252 static int ccg_restart(struct ucsi_ccg *uc) 1253 { 1254 struct device *dev = uc->dev; 1255 int status; 1256 1257 status = ucsi_ccg_init(uc); 1258 if (status < 0) { 1259 dev_err(dev, "ucsi_ccg_start fail, err=%d\n", status); 1260 return status; 1261 } 1262 1263 status = ccg_request_irq(uc); 1264 if (status < 0) { 1265 dev_err(dev, "request_threaded_irq failed - %d\n", status); 1266 return status; 1267 } 1268 1269 status = ucsi_register(uc->ucsi); 1270 if (status) { 1271 dev_err(uc->dev, "failed to register the interface\n"); 1272 return status; 1273 } 1274 1275 pm_runtime_enable(uc->dev); 1276 return 0; 1277 } 1278 1279 static void ccg_update_firmware(struct work_struct *work) 1280 { 1281 struct ucsi_ccg *uc = container_of(work, struct ucsi_ccg, work); 1282 enum enum_flash_mode flash_mode; 1283 int status; 1284 1285 status = ccg_fw_update_needed(uc, &flash_mode); 1286 if (status < 0) 1287 return; 1288 1289 if (flash_mode != FLASH_NOT_NEEDED) { 1290 ucsi_unregister(uc->ucsi); 1291 pm_runtime_disable(uc->dev); 1292 free_irq(uc->irq, uc); 1293 1294 ccg_fw_update(uc, flash_mode); 1295 ccg_restart(uc); 1296 } 1297 } 1298 1299 static ssize_t do_flash_store(struct device *dev, 1300 struct device_attribute *attr, 1301 const char *buf, size_t n) 1302 { 1303 struct ucsi_ccg *uc = i2c_get_clientdata(to_i2c_client(dev)); 1304 bool flash; 1305 1306 if (kstrtobool(buf, &flash)) 1307 return -EINVAL; 1308 1309 if (!flash) 1310 return n; 1311 1312 if (uc->fw_build == 0x0) { 1313 dev_err(dev, "fail to flash FW due to missing FW build info\n"); 1314 return -EINVAL; 1315 } 1316 1317 schedule_work(&uc->work); 1318 return n; 1319 } 1320 1321 static DEVICE_ATTR_WO(do_flash); 1322 1323 static struct attribute *ucsi_ccg_attrs[] = { 1324 &dev_attr_do_flash.attr, 1325 NULL, 1326 }; 1327 ATTRIBUTE_GROUPS(ucsi_ccg); 1328 1329 static int ucsi_ccg_probe(struct i2c_client *client, 1330 const struct i2c_device_id *id) 1331 { 1332 struct device *dev = &client->dev; 1333 struct ucsi_ccg *uc; 1334 int status; 1335 1336 uc = devm_kzalloc(dev, sizeof(*uc), GFP_KERNEL); 1337 if (!uc) 1338 return -ENOMEM; 1339 1340 uc->dev = dev; 1341 uc->client = client; 1342 uc->irq = client->irq; 1343 mutex_init(&uc->lock); 1344 init_completion(&uc->complete); 1345 INIT_WORK(&uc->work, ccg_update_firmware); 1346 INIT_WORK(&uc->pm_work, ccg_pm_workaround_work); 1347 1348 /* Only fail FW flashing when FW build information is not provided */ 1349 status = device_property_read_u16(dev, "ccgx,firmware-build", 1350 &uc->fw_build); 1351 if (status) 1352 dev_err(uc->dev, "failed to get FW build information\n"); 1353 1354 /* reset ccg device and initialize ucsi */ 1355 status = ucsi_ccg_init(uc); 1356 if (status < 0) { 1357 dev_err(uc->dev, "ucsi_ccg_init failed - %d\n", status); 1358 return status; 1359 } 1360 1361 status = get_fw_info(uc); 1362 if (status < 0) { 1363 dev_err(uc->dev, "get_fw_info failed - %d\n", status); 1364 return status; 1365 } 1366 1367 uc->port_num = 1; 1368 1369 if (uc->info.mode & CCG_DEVINFO_PDPORTS_MASK) 1370 uc->port_num++; 1371 1372 uc->ucsi = ucsi_create(dev, &ucsi_ccg_ops); 1373 if (IS_ERR(uc->ucsi)) 1374 return PTR_ERR(uc->ucsi); 1375 1376 ucsi_set_drvdata(uc->ucsi, uc); 1377 1378 status = ccg_request_irq(uc); 1379 if (status < 0) { 1380 dev_err(uc->dev, "request_threaded_irq failed - %d\n", status); 1381 goto out_ucsi_destroy; 1382 } 1383 1384 status = ucsi_register(uc->ucsi); 1385 if (status) 1386 goto out_free_irq; 1387 1388 i2c_set_clientdata(client, uc); 1389 1390 pm_runtime_set_active(uc->dev); 1391 pm_runtime_enable(uc->dev); 1392 pm_runtime_use_autosuspend(uc->dev); 1393 pm_runtime_set_autosuspend_delay(uc->dev, 5000); 1394 pm_runtime_idle(uc->dev); 1395 1396 return 0; 1397 1398 out_free_irq: 1399 free_irq(uc->irq, uc); 1400 out_ucsi_destroy: 1401 ucsi_destroy(uc->ucsi); 1402 1403 return status; 1404 } 1405 1406 static int ucsi_ccg_remove(struct i2c_client *client) 1407 { 1408 struct ucsi_ccg *uc = i2c_get_clientdata(client); 1409 1410 cancel_work_sync(&uc->pm_work); 1411 cancel_work_sync(&uc->work); 1412 pm_runtime_disable(uc->dev); 1413 ucsi_unregister(uc->ucsi); 1414 ucsi_destroy(uc->ucsi); 1415 free_irq(uc->irq, uc); 1416 1417 return 0; 1418 } 1419 1420 static const struct i2c_device_id ucsi_ccg_device_id[] = { 1421 {"ccgx-ucsi", 0}, 1422 {} 1423 }; 1424 MODULE_DEVICE_TABLE(i2c, ucsi_ccg_device_id); 1425 1426 static const struct acpi_device_id amd_i2c_ucsi_match[] = { 1427 {"AMDI0042"}, 1428 {} 1429 }; 1430 MODULE_DEVICE_TABLE(acpi, amd_i2c_ucsi_match); 1431 1432 static int ucsi_ccg_resume(struct device *dev) 1433 { 1434 struct i2c_client *client = to_i2c_client(dev); 1435 struct ucsi_ccg *uc = i2c_get_clientdata(client); 1436 1437 return ucsi_resume(uc->ucsi); 1438 } 1439 1440 static int ucsi_ccg_runtime_suspend(struct device *dev) 1441 { 1442 return 0; 1443 } 1444 1445 static int ucsi_ccg_runtime_resume(struct device *dev) 1446 { 1447 struct i2c_client *client = to_i2c_client(dev); 1448 struct ucsi_ccg *uc = i2c_get_clientdata(client); 1449 1450 /* 1451 * Firmware version 3.1.10 or earlier, built for NVIDIA has known issue 1452 * of missing interrupt when a device is connected for runtime resume. 1453 * Schedule a work to call ISR as a workaround. 1454 */ 1455 if (uc->fw_build == CCG_FW_BUILD_NVIDIA && 1456 uc->fw_version <= CCG_OLD_FW_VERSION) 1457 schedule_work(&uc->pm_work); 1458 1459 return 0; 1460 } 1461 1462 static const struct dev_pm_ops ucsi_ccg_pm = { 1463 .resume = ucsi_ccg_resume, 1464 .runtime_suspend = ucsi_ccg_runtime_suspend, 1465 .runtime_resume = ucsi_ccg_runtime_resume, 1466 }; 1467 1468 static struct i2c_driver ucsi_ccg_driver = { 1469 .driver = { 1470 .name = "ucsi_ccg", 1471 .pm = &ucsi_ccg_pm, 1472 .dev_groups = ucsi_ccg_groups, 1473 .acpi_match_table = amd_i2c_ucsi_match, 1474 }, 1475 .probe = ucsi_ccg_probe, 1476 .remove = ucsi_ccg_remove, 1477 .id_table = ucsi_ccg_device_id, 1478 }; 1479 1480 module_i2c_driver(ucsi_ccg_driver); 1481 1482 MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>"); 1483 MODULE_DESCRIPTION("UCSI driver for Cypress CCGx Type-C controller"); 1484 MODULE_LICENSE("GPL v2"); 1485