1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015-2017 Google, Inc 4 * 5 * USB Type-C Port Controller Interface. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/usb/pd.h> 16 #include <linux/usb/tcpm.h> 17 #include <linux/usb/typec.h> 18 19 #include "tcpci.h" 20 21 #define PD_RETRY_COUNT_DEFAULT 3 22 #define PD_RETRY_COUNT_3_0_OR_HIGHER 2 23 #define AUTO_DISCHARGE_DEFAULT_THRESHOLD_MV 3500 24 #define AUTO_DISCHARGE_PD_HEADROOM_MV 850 25 #define AUTO_DISCHARGE_PPS_HEADROOM_MV 1250 26 27 #define tcpc_presenting_rd(reg, cc) \ 28 (!(TCPC_ROLE_CTRL_DRP & (reg)) && \ 29 (((reg) & (TCPC_ROLE_CTRL_## cc ##_MASK << TCPC_ROLE_CTRL_## cc ##_SHIFT)) == \ 30 (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_## cc ##_SHIFT))) 31 32 struct tcpci { 33 struct device *dev; 34 35 struct tcpm_port *port; 36 37 struct regmap *regmap; 38 39 bool controls_vbus; 40 41 struct tcpc_dev tcpc; 42 struct tcpci_data *data; 43 }; 44 45 struct tcpci_chip { 46 struct tcpci *tcpci; 47 struct tcpci_data data; 48 }; 49 50 struct tcpm_port *tcpci_get_tcpm_port(struct tcpci *tcpci) 51 { 52 return tcpci->port; 53 } 54 EXPORT_SYMBOL_GPL(tcpci_get_tcpm_port); 55 56 static inline struct tcpci *tcpc_to_tcpci(struct tcpc_dev *tcpc) 57 { 58 return container_of(tcpc, struct tcpci, tcpc); 59 } 60 61 static int tcpci_read16(struct tcpci *tcpci, unsigned int reg, u16 *val) 62 { 63 return regmap_raw_read(tcpci->regmap, reg, val, sizeof(u16)); 64 } 65 66 static int tcpci_write16(struct tcpci *tcpci, unsigned int reg, u16 val) 67 { 68 return regmap_raw_write(tcpci->regmap, reg, &val, sizeof(u16)); 69 } 70 71 static int tcpci_set_cc(struct tcpc_dev *tcpc, enum typec_cc_status cc) 72 { 73 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 74 unsigned int reg; 75 int ret; 76 77 switch (cc) { 78 case TYPEC_CC_RA: 79 reg = (TCPC_ROLE_CTRL_CC_RA << TCPC_ROLE_CTRL_CC1_SHIFT) | 80 (TCPC_ROLE_CTRL_CC_RA << TCPC_ROLE_CTRL_CC2_SHIFT); 81 break; 82 case TYPEC_CC_RD: 83 reg = (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) | 84 (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT); 85 break; 86 case TYPEC_CC_RP_DEF: 87 reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | 88 (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) | 89 (TCPC_ROLE_CTRL_RP_VAL_DEF << 90 TCPC_ROLE_CTRL_RP_VAL_SHIFT); 91 break; 92 case TYPEC_CC_RP_1_5: 93 reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | 94 (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) | 95 (TCPC_ROLE_CTRL_RP_VAL_1_5 << 96 TCPC_ROLE_CTRL_RP_VAL_SHIFT); 97 break; 98 case TYPEC_CC_RP_3_0: 99 reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | 100 (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) | 101 (TCPC_ROLE_CTRL_RP_VAL_3_0 << 102 TCPC_ROLE_CTRL_RP_VAL_SHIFT); 103 break; 104 case TYPEC_CC_OPEN: 105 default: 106 reg = (TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT) | 107 (TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC2_SHIFT); 108 break; 109 } 110 111 ret = regmap_write(tcpci->regmap, TCPC_ROLE_CTRL, reg); 112 if (ret < 0) 113 return ret; 114 115 return 0; 116 } 117 118 static int tcpci_start_toggling(struct tcpc_dev *tcpc, 119 enum typec_port_type port_type, 120 enum typec_cc_status cc) 121 { 122 int ret; 123 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 124 unsigned int reg = TCPC_ROLE_CTRL_DRP; 125 126 if (port_type != TYPEC_PORT_DRP) 127 return -EOPNOTSUPP; 128 129 /* Handle vendor drp toggling */ 130 if (tcpci->data->start_drp_toggling) { 131 ret = tcpci->data->start_drp_toggling(tcpci, tcpci->data, cc); 132 if (ret < 0) 133 return ret; 134 } 135 136 switch (cc) { 137 default: 138 case TYPEC_CC_RP_DEF: 139 reg |= (TCPC_ROLE_CTRL_RP_VAL_DEF << 140 TCPC_ROLE_CTRL_RP_VAL_SHIFT); 141 break; 142 case TYPEC_CC_RP_1_5: 143 reg |= (TCPC_ROLE_CTRL_RP_VAL_1_5 << 144 TCPC_ROLE_CTRL_RP_VAL_SHIFT); 145 break; 146 case TYPEC_CC_RP_3_0: 147 reg |= (TCPC_ROLE_CTRL_RP_VAL_3_0 << 148 TCPC_ROLE_CTRL_RP_VAL_SHIFT); 149 break; 150 } 151 152 if (cc == TYPEC_CC_RD) 153 reg |= (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) | 154 (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT); 155 else 156 reg |= (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | 157 (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT); 158 ret = regmap_write(tcpci->regmap, TCPC_ROLE_CTRL, reg); 159 if (ret < 0) 160 return ret; 161 return regmap_write(tcpci->regmap, TCPC_COMMAND, 162 TCPC_CMD_LOOK4CONNECTION); 163 } 164 165 static enum typec_cc_status tcpci_to_typec_cc(unsigned int cc, bool sink) 166 { 167 switch (cc) { 168 case 0x1: 169 return sink ? TYPEC_CC_RP_DEF : TYPEC_CC_RA; 170 case 0x2: 171 return sink ? TYPEC_CC_RP_1_5 : TYPEC_CC_RD; 172 case 0x3: 173 if (sink) 174 return TYPEC_CC_RP_3_0; 175 fallthrough; 176 case 0x0: 177 default: 178 return TYPEC_CC_OPEN; 179 } 180 } 181 182 static int tcpci_get_cc(struct tcpc_dev *tcpc, 183 enum typec_cc_status *cc1, enum typec_cc_status *cc2) 184 { 185 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 186 unsigned int reg, role_control; 187 int ret; 188 189 ret = regmap_read(tcpci->regmap, TCPC_ROLE_CTRL, &role_control); 190 if (ret < 0) 191 return ret; 192 193 ret = regmap_read(tcpci->regmap, TCPC_CC_STATUS, ®); 194 if (ret < 0) 195 return ret; 196 197 *cc1 = tcpci_to_typec_cc((reg >> TCPC_CC_STATUS_CC1_SHIFT) & 198 TCPC_CC_STATUS_CC1_MASK, 199 reg & TCPC_CC_STATUS_TERM || 200 tcpc_presenting_rd(role_control, CC1)); 201 *cc2 = tcpci_to_typec_cc((reg >> TCPC_CC_STATUS_CC2_SHIFT) & 202 TCPC_CC_STATUS_CC2_MASK, 203 reg & TCPC_CC_STATUS_TERM || 204 tcpc_presenting_rd(role_control, CC2)); 205 206 return 0; 207 } 208 209 static int tcpci_set_polarity(struct tcpc_dev *tcpc, 210 enum typec_cc_polarity polarity) 211 { 212 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 213 unsigned int reg; 214 int ret; 215 enum typec_cc_status cc1, cc2; 216 217 /* Obtain Rp setting from role control */ 218 ret = regmap_read(tcpci->regmap, TCPC_ROLE_CTRL, ®); 219 if (ret < 0) 220 return ret; 221 222 ret = tcpci_get_cc(tcpc, &cc1, &cc2); 223 if (ret < 0) 224 return ret; 225 226 /* 227 * When port has drp toggling enabled, ROLE_CONTROL would only have the initial 228 * terminations for the toggling and does not indicate the final cc 229 * terminations when ConnectionResult is 0 i.e. drp toggling stops and 230 * the connection is resolbed. Infer port role from TCPC_CC_STATUS based on the 231 * terminations seen. The port role is then used to set the cc terminations. 232 */ 233 if (reg & TCPC_ROLE_CTRL_DRP) { 234 /* Disable DRP for the OPEN setting to take effect */ 235 reg = reg & ~TCPC_ROLE_CTRL_DRP; 236 237 if (polarity == TYPEC_POLARITY_CC2) { 238 reg &= ~(TCPC_ROLE_CTRL_CC2_MASK << TCPC_ROLE_CTRL_CC2_SHIFT); 239 /* Local port is source */ 240 if (cc2 == TYPEC_CC_RD) 241 /* Role control would have the Rp setting when DRP was enabled */ 242 reg |= TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT; 243 else 244 reg |= TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT; 245 } else { 246 reg &= ~(TCPC_ROLE_CTRL_CC1_MASK << TCPC_ROLE_CTRL_CC1_SHIFT); 247 /* Local port is source */ 248 if (cc1 == TYPEC_CC_RD) 249 /* Role control would have the Rp setting when DRP was enabled */ 250 reg |= TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT; 251 else 252 reg |= TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT; 253 } 254 } 255 256 if (polarity == TYPEC_POLARITY_CC2) 257 reg |= TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT; 258 else 259 reg |= TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC2_SHIFT; 260 ret = regmap_write(tcpci->regmap, TCPC_ROLE_CTRL, reg); 261 if (ret < 0) 262 return ret; 263 264 return regmap_write(tcpci->regmap, TCPC_TCPC_CTRL, 265 (polarity == TYPEC_POLARITY_CC2) ? 266 TCPC_TCPC_CTRL_ORIENTATION : 0); 267 } 268 269 static void tcpci_set_partner_usb_comm_capable(struct tcpc_dev *tcpc, bool capable) 270 { 271 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 272 273 if (tcpci->data->set_partner_usb_comm_capable) 274 tcpci->data->set_partner_usb_comm_capable(tcpci, tcpci->data, capable); 275 } 276 277 static int tcpci_set_vconn(struct tcpc_dev *tcpc, bool enable) 278 { 279 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 280 int ret; 281 282 /* Handle vendor set vconn */ 283 if (tcpci->data->set_vconn) { 284 ret = tcpci->data->set_vconn(tcpci, tcpci->data, enable); 285 if (ret < 0) 286 return ret; 287 } 288 289 return regmap_update_bits(tcpci->regmap, TCPC_POWER_CTRL, 290 TCPC_POWER_CTRL_VCONN_ENABLE, 291 enable ? TCPC_POWER_CTRL_VCONN_ENABLE : 0); 292 } 293 294 static int tcpci_enable_auto_vbus_discharge(struct tcpc_dev *dev, bool enable) 295 { 296 struct tcpci *tcpci = tcpc_to_tcpci(dev); 297 int ret; 298 299 ret = regmap_update_bits(tcpci->regmap, TCPC_POWER_CTRL, TCPC_POWER_CTRL_AUTO_DISCHARGE, 300 enable ? TCPC_POWER_CTRL_AUTO_DISCHARGE : 0); 301 return ret; 302 } 303 304 static int tcpci_set_auto_vbus_discharge_threshold(struct tcpc_dev *dev, enum typec_pwr_opmode mode, 305 bool pps_active, u32 requested_vbus_voltage_mv) 306 { 307 struct tcpci *tcpci = tcpc_to_tcpci(dev); 308 unsigned int pwr_ctrl, threshold = 0; 309 int ret; 310 311 /* 312 * Indicates that vbus is going to go away due PR_SWAP, hard reset etc. 313 * Do not discharge vbus here. 314 */ 315 if (requested_vbus_voltage_mv == 0) 316 goto write_thresh; 317 318 ret = regmap_read(tcpci->regmap, TCPC_POWER_CTRL, &pwr_ctrl); 319 if (ret < 0) 320 return ret; 321 322 if (pwr_ctrl & TCPC_FAST_ROLE_SWAP_EN) { 323 /* To prevent disconnect when the source is fast role swap is capable. */ 324 threshold = AUTO_DISCHARGE_DEFAULT_THRESHOLD_MV; 325 } else if (mode == TYPEC_PWR_MODE_PD) { 326 if (pps_active) 327 threshold = (95 * requested_vbus_voltage_mv / 100) - 328 AUTO_DISCHARGE_PD_HEADROOM_MV; 329 else 330 threshold = (95 * requested_vbus_voltage_mv / 100) - 331 AUTO_DISCHARGE_PPS_HEADROOM_MV; 332 } else { 333 /* 3.5V for non-pd sink */ 334 threshold = AUTO_DISCHARGE_DEFAULT_THRESHOLD_MV; 335 } 336 337 threshold = threshold / TCPC_VBUS_SINK_DISCONNECT_THRESH_LSB_MV; 338 339 if (threshold > TCPC_VBUS_SINK_DISCONNECT_THRESH_MAX) 340 return -EINVAL; 341 342 write_thresh: 343 return tcpci_write16(tcpci, TCPC_VBUS_SINK_DISCONNECT_THRESH, threshold); 344 } 345 346 static int tcpci_enable_frs(struct tcpc_dev *dev, bool enable) 347 { 348 struct tcpci *tcpci = tcpc_to_tcpci(dev); 349 int ret; 350 351 /* To prevent disconnect during FRS, set disconnect threshold to 3.5V */ 352 ret = tcpci_write16(tcpci, TCPC_VBUS_SINK_DISCONNECT_THRESH, enable ? 0 : 0x8c); 353 if (ret < 0) 354 return ret; 355 356 ret = regmap_update_bits(tcpci->regmap, TCPC_POWER_CTRL, TCPC_FAST_ROLE_SWAP_EN, enable ? 357 TCPC_FAST_ROLE_SWAP_EN : 0); 358 359 return ret; 360 } 361 362 static void tcpci_frs_sourcing_vbus(struct tcpc_dev *dev) 363 { 364 struct tcpci *tcpci = tcpc_to_tcpci(dev); 365 366 if (tcpci->data->frs_sourcing_vbus) 367 tcpci->data->frs_sourcing_vbus(tcpci, tcpci->data); 368 } 369 370 static int tcpci_set_bist_data(struct tcpc_dev *tcpc, bool enable) 371 { 372 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 373 374 return regmap_update_bits(tcpci->regmap, TCPC_TCPC_CTRL, TCPC_TCPC_CTRL_BIST_TM, 375 enable ? TCPC_TCPC_CTRL_BIST_TM : 0); 376 } 377 378 static int tcpci_set_roles(struct tcpc_dev *tcpc, bool attached, 379 enum typec_role role, enum typec_data_role data) 380 { 381 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 382 unsigned int reg; 383 int ret; 384 385 reg = PD_REV20 << TCPC_MSG_HDR_INFO_REV_SHIFT; 386 if (role == TYPEC_SOURCE) 387 reg |= TCPC_MSG_HDR_INFO_PWR_ROLE; 388 if (data == TYPEC_HOST) 389 reg |= TCPC_MSG_HDR_INFO_DATA_ROLE; 390 ret = regmap_write(tcpci->regmap, TCPC_MSG_HDR_INFO, reg); 391 if (ret < 0) 392 return ret; 393 394 return 0; 395 } 396 397 static int tcpci_set_pd_rx(struct tcpc_dev *tcpc, bool enable) 398 { 399 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 400 unsigned int reg = 0; 401 int ret; 402 403 if (enable) 404 reg = TCPC_RX_DETECT_SOP | TCPC_RX_DETECT_HARD_RESET; 405 ret = regmap_write(tcpci->regmap, TCPC_RX_DETECT, reg); 406 if (ret < 0) 407 return ret; 408 409 return 0; 410 } 411 412 static int tcpci_get_vbus(struct tcpc_dev *tcpc) 413 { 414 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 415 unsigned int reg; 416 int ret; 417 418 ret = regmap_read(tcpci->regmap, TCPC_POWER_STATUS, ®); 419 if (ret < 0) 420 return ret; 421 422 return !!(reg & TCPC_POWER_STATUS_VBUS_PRES); 423 } 424 425 static bool tcpci_is_vbus_vsafe0v(struct tcpc_dev *tcpc) 426 { 427 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 428 unsigned int reg; 429 int ret; 430 431 ret = regmap_read(tcpci->regmap, TCPC_EXTENDED_STATUS, ®); 432 if (ret < 0) 433 return false; 434 435 return !!(reg & TCPC_EXTENDED_STATUS_VSAFE0V); 436 } 437 438 static int tcpci_set_vbus(struct tcpc_dev *tcpc, bool source, bool sink) 439 { 440 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 441 int ret; 442 443 if (tcpci->data->set_vbus) { 444 ret = tcpci->data->set_vbus(tcpci, tcpci->data, source, sink); 445 /* Bypass when ret > 0 */ 446 if (ret != 0) 447 return ret < 0 ? ret : 0; 448 } 449 450 /* Disable both source and sink first before enabling anything */ 451 452 if (!source) { 453 ret = regmap_write(tcpci->regmap, TCPC_COMMAND, 454 TCPC_CMD_DISABLE_SRC_VBUS); 455 if (ret < 0) 456 return ret; 457 } 458 459 if (!sink) { 460 ret = regmap_write(tcpci->regmap, TCPC_COMMAND, 461 TCPC_CMD_DISABLE_SINK_VBUS); 462 if (ret < 0) 463 return ret; 464 } 465 466 if (source) { 467 ret = regmap_write(tcpci->regmap, TCPC_COMMAND, 468 TCPC_CMD_SRC_VBUS_DEFAULT); 469 if (ret < 0) 470 return ret; 471 } 472 473 if (sink) { 474 ret = regmap_write(tcpci->regmap, TCPC_COMMAND, 475 TCPC_CMD_SINK_VBUS); 476 if (ret < 0) 477 return ret; 478 } 479 480 return 0; 481 } 482 483 static int tcpci_pd_transmit(struct tcpc_dev *tcpc, enum tcpm_transmit_type type, 484 const struct pd_message *msg, unsigned int negotiated_rev) 485 { 486 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 487 u16 header = msg ? le16_to_cpu(msg->header) : 0; 488 unsigned int reg, cnt; 489 int ret; 490 491 cnt = msg ? pd_header_cnt(header) * 4 : 0; 492 /** 493 * TCPCI spec forbids direct access of TCPC_TX_DATA. 494 * But, since some of the chipsets offer this capability, 495 * it's fair to support both. 496 */ 497 if (tcpci->data->TX_BUF_BYTE_x_hidden) { 498 u8 buf[TCPC_TRANSMIT_BUFFER_MAX_LEN] = {0,}; 499 u8 pos = 0; 500 501 /* Payload + header + TCPC_TX_BYTE_CNT */ 502 buf[pos++] = cnt + 2; 503 504 if (msg) 505 memcpy(&buf[pos], &msg->header, sizeof(msg->header)); 506 507 pos += sizeof(header); 508 509 if (cnt > 0) 510 memcpy(&buf[pos], msg->payload, cnt); 511 512 pos += cnt; 513 ret = regmap_raw_write(tcpci->regmap, TCPC_TX_BYTE_CNT, buf, pos); 514 if (ret < 0) 515 return ret; 516 } else { 517 ret = regmap_write(tcpci->regmap, TCPC_TX_BYTE_CNT, cnt + 2); 518 if (ret < 0) 519 return ret; 520 521 ret = tcpci_write16(tcpci, TCPC_TX_HDR, header); 522 if (ret < 0) 523 return ret; 524 525 if (cnt > 0) { 526 ret = regmap_raw_write(tcpci->regmap, TCPC_TX_DATA, &msg->payload, cnt); 527 if (ret < 0) 528 return ret; 529 } 530 } 531 532 /* nRetryCount is 3 in PD2.0 spec where 2 in PD3.0 spec */ 533 reg = ((negotiated_rev > PD_REV20 ? PD_RETRY_COUNT_3_0_OR_HIGHER : PD_RETRY_COUNT_DEFAULT) 534 << TCPC_TRANSMIT_RETRY_SHIFT) | (type << TCPC_TRANSMIT_TYPE_SHIFT); 535 ret = regmap_write(tcpci->regmap, TCPC_TRANSMIT, reg); 536 if (ret < 0) 537 return ret; 538 539 return 0; 540 } 541 542 static int tcpci_init(struct tcpc_dev *tcpc) 543 { 544 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 545 unsigned long timeout = jiffies + msecs_to_jiffies(2000); /* XXX */ 546 unsigned int reg; 547 int ret; 548 549 while (time_before_eq(jiffies, timeout)) { 550 ret = regmap_read(tcpci->regmap, TCPC_POWER_STATUS, ®); 551 if (ret < 0) 552 return ret; 553 if (!(reg & TCPC_POWER_STATUS_UNINIT)) 554 break; 555 usleep_range(10000, 20000); 556 } 557 if (time_after(jiffies, timeout)) 558 return -ETIMEDOUT; 559 560 /* Handle vendor init */ 561 if (tcpci->data->init) { 562 ret = tcpci->data->init(tcpci, tcpci->data); 563 if (ret < 0) 564 return ret; 565 } 566 567 /* Clear all events */ 568 ret = tcpci_write16(tcpci, TCPC_ALERT, 0xffff); 569 if (ret < 0) 570 return ret; 571 572 if (tcpci->controls_vbus) 573 reg = TCPC_POWER_STATUS_VBUS_PRES; 574 else 575 reg = 0; 576 ret = regmap_write(tcpci->regmap, TCPC_POWER_STATUS_MASK, reg); 577 if (ret < 0) 578 return ret; 579 580 /* Enable Vbus detection */ 581 ret = regmap_write(tcpci->regmap, TCPC_COMMAND, 582 TCPC_CMD_ENABLE_VBUS_DETECT); 583 if (ret < 0) 584 return ret; 585 586 reg = TCPC_ALERT_TX_SUCCESS | TCPC_ALERT_TX_FAILED | 587 TCPC_ALERT_TX_DISCARDED | TCPC_ALERT_RX_STATUS | 588 TCPC_ALERT_RX_HARD_RST | TCPC_ALERT_CC_STATUS; 589 if (tcpci->controls_vbus) 590 reg |= TCPC_ALERT_POWER_STATUS; 591 /* Enable VSAFE0V status interrupt when detecting VSAFE0V is supported */ 592 if (tcpci->data->vbus_vsafe0v) { 593 reg |= TCPC_ALERT_EXTENDED_STATUS; 594 ret = regmap_write(tcpci->regmap, TCPC_EXTENDED_STATUS_MASK, 595 TCPC_EXTENDED_STATUS_VSAFE0V); 596 if (ret < 0) 597 return ret; 598 } 599 return tcpci_write16(tcpci, TCPC_ALERT_MASK, reg); 600 } 601 602 irqreturn_t tcpci_irq(struct tcpci *tcpci) 603 { 604 u16 status; 605 int ret; 606 unsigned int raw; 607 608 tcpci_read16(tcpci, TCPC_ALERT, &status); 609 610 /* 611 * Clear alert status for everything except RX_STATUS, which shouldn't 612 * be cleared until we have successfully retrieved message. 613 */ 614 if (status & ~TCPC_ALERT_RX_STATUS) 615 tcpci_write16(tcpci, TCPC_ALERT, 616 status & ~TCPC_ALERT_RX_STATUS); 617 618 if (status & TCPC_ALERT_CC_STATUS) 619 tcpm_cc_change(tcpci->port); 620 621 if (status & TCPC_ALERT_POWER_STATUS) { 622 regmap_read(tcpci->regmap, TCPC_POWER_STATUS_MASK, &raw); 623 /* 624 * If power status mask has been reset, then the TCPC 625 * has reset. 626 */ 627 if (raw == 0xff) 628 tcpm_tcpc_reset(tcpci->port); 629 else 630 tcpm_vbus_change(tcpci->port); 631 } 632 633 if (status & TCPC_ALERT_RX_STATUS) { 634 struct pd_message msg; 635 unsigned int cnt, payload_cnt; 636 u16 header; 637 638 regmap_read(tcpci->regmap, TCPC_RX_BYTE_CNT, &cnt); 639 /* 640 * 'cnt' corresponds to READABLE_BYTE_COUNT in section 4.4.14 641 * of the TCPCI spec [Rev 2.0 Ver 1.0 October 2017] and is 642 * defined in table 4-36 as one greater than the number of 643 * bytes received. And that number includes the header. So: 644 */ 645 if (cnt > 3) 646 payload_cnt = cnt - (1 + sizeof(msg.header)); 647 else 648 payload_cnt = 0; 649 650 tcpci_read16(tcpci, TCPC_RX_HDR, &header); 651 msg.header = cpu_to_le16(header); 652 653 if (WARN_ON(payload_cnt > sizeof(msg.payload))) 654 payload_cnt = sizeof(msg.payload); 655 656 if (payload_cnt > 0) 657 regmap_raw_read(tcpci->regmap, TCPC_RX_DATA, 658 &msg.payload, payload_cnt); 659 660 /* Read complete, clear RX status alert bit */ 661 tcpci_write16(tcpci, TCPC_ALERT, TCPC_ALERT_RX_STATUS); 662 663 tcpm_pd_receive(tcpci->port, &msg); 664 } 665 666 if (status & TCPC_ALERT_EXTENDED_STATUS) { 667 ret = regmap_read(tcpci->regmap, TCPC_EXTENDED_STATUS, &raw); 668 if (!ret && (raw & TCPC_EXTENDED_STATUS_VSAFE0V)) 669 tcpm_vbus_change(tcpci->port); 670 } 671 672 if (status & TCPC_ALERT_RX_HARD_RST) 673 tcpm_pd_hard_reset(tcpci->port); 674 675 if (status & TCPC_ALERT_TX_SUCCESS) 676 tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_SUCCESS); 677 else if (status & TCPC_ALERT_TX_DISCARDED) 678 tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_DISCARDED); 679 else if (status & TCPC_ALERT_TX_FAILED) 680 tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_FAILED); 681 682 return IRQ_HANDLED; 683 } 684 EXPORT_SYMBOL_GPL(tcpci_irq); 685 686 static irqreturn_t _tcpci_irq(int irq, void *dev_id) 687 { 688 struct tcpci_chip *chip = dev_id; 689 690 return tcpci_irq(chip->tcpci); 691 } 692 693 static const struct regmap_config tcpci_regmap_config = { 694 .reg_bits = 8, 695 .val_bits = 8, 696 697 .max_register = 0x7F, /* 0x80 .. 0xFF are vendor defined */ 698 }; 699 700 static int tcpci_parse_config(struct tcpci *tcpci) 701 { 702 tcpci->controls_vbus = true; /* XXX */ 703 704 tcpci->tcpc.fwnode = device_get_named_child_node(tcpci->dev, 705 "connector"); 706 if (!tcpci->tcpc.fwnode) { 707 dev_err(tcpci->dev, "Can't find connector node.\n"); 708 return -EINVAL; 709 } 710 711 return 0; 712 } 713 714 struct tcpci *tcpci_register_port(struct device *dev, struct tcpci_data *data) 715 { 716 struct tcpci *tcpci; 717 int err; 718 719 tcpci = devm_kzalloc(dev, sizeof(*tcpci), GFP_KERNEL); 720 if (!tcpci) 721 return ERR_PTR(-ENOMEM); 722 723 tcpci->dev = dev; 724 tcpci->data = data; 725 tcpci->regmap = data->regmap; 726 727 tcpci->tcpc.init = tcpci_init; 728 tcpci->tcpc.get_vbus = tcpci_get_vbus; 729 tcpci->tcpc.set_vbus = tcpci_set_vbus; 730 tcpci->tcpc.set_cc = tcpci_set_cc; 731 tcpci->tcpc.get_cc = tcpci_get_cc; 732 tcpci->tcpc.set_polarity = tcpci_set_polarity; 733 tcpci->tcpc.set_vconn = tcpci_set_vconn; 734 tcpci->tcpc.start_toggling = tcpci_start_toggling; 735 736 tcpci->tcpc.set_pd_rx = tcpci_set_pd_rx; 737 tcpci->tcpc.set_roles = tcpci_set_roles; 738 tcpci->tcpc.pd_transmit = tcpci_pd_transmit; 739 tcpci->tcpc.set_bist_data = tcpci_set_bist_data; 740 tcpci->tcpc.enable_frs = tcpci_enable_frs; 741 tcpci->tcpc.frs_sourcing_vbus = tcpci_frs_sourcing_vbus; 742 tcpci->tcpc.set_partner_usb_comm_capable = tcpci_set_partner_usb_comm_capable; 743 744 if (tcpci->data->auto_discharge_disconnect) { 745 tcpci->tcpc.enable_auto_vbus_discharge = tcpci_enable_auto_vbus_discharge; 746 tcpci->tcpc.set_auto_vbus_discharge_threshold = 747 tcpci_set_auto_vbus_discharge_threshold; 748 regmap_update_bits(tcpci->regmap, TCPC_POWER_CTRL, TCPC_POWER_CTRL_BLEED_DISCHARGE, 749 TCPC_POWER_CTRL_BLEED_DISCHARGE); 750 } 751 752 if (tcpci->data->vbus_vsafe0v) 753 tcpci->tcpc.is_vbus_vsafe0v = tcpci_is_vbus_vsafe0v; 754 755 err = tcpci_parse_config(tcpci); 756 if (err < 0) 757 return ERR_PTR(err); 758 759 tcpci->port = tcpm_register_port(tcpci->dev, &tcpci->tcpc); 760 if (IS_ERR(tcpci->port)) 761 return ERR_CAST(tcpci->port); 762 763 return tcpci; 764 } 765 EXPORT_SYMBOL_GPL(tcpci_register_port); 766 767 void tcpci_unregister_port(struct tcpci *tcpci) 768 { 769 tcpm_unregister_port(tcpci->port); 770 } 771 EXPORT_SYMBOL_GPL(tcpci_unregister_port); 772 773 static int tcpci_probe(struct i2c_client *client, 774 const struct i2c_device_id *i2c_id) 775 { 776 struct tcpci_chip *chip; 777 int err; 778 u16 val = 0; 779 780 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 781 if (!chip) 782 return -ENOMEM; 783 784 chip->data.regmap = devm_regmap_init_i2c(client, &tcpci_regmap_config); 785 if (IS_ERR(chip->data.regmap)) 786 return PTR_ERR(chip->data.regmap); 787 788 i2c_set_clientdata(client, chip); 789 790 /* Disable chip interrupts before requesting irq */ 791 err = regmap_raw_write(chip->data.regmap, TCPC_ALERT_MASK, &val, 792 sizeof(u16)); 793 if (err < 0) 794 return err; 795 796 chip->tcpci = tcpci_register_port(&client->dev, &chip->data); 797 if (IS_ERR(chip->tcpci)) 798 return PTR_ERR(chip->tcpci); 799 800 err = devm_request_threaded_irq(&client->dev, client->irq, NULL, 801 _tcpci_irq, 802 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 803 dev_name(&client->dev), chip); 804 if (err < 0) { 805 tcpci_unregister_port(chip->tcpci); 806 return err; 807 } 808 809 return 0; 810 } 811 812 static int tcpci_remove(struct i2c_client *client) 813 { 814 struct tcpci_chip *chip = i2c_get_clientdata(client); 815 int err; 816 817 /* Disable chip interrupts before unregistering port */ 818 err = tcpci_write16(chip->tcpci, TCPC_ALERT_MASK, 0); 819 if (err < 0) 820 return err; 821 822 tcpci_unregister_port(chip->tcpci); 823 824 return 0; 825 } 826 827 static const struct i2c_device_id tcpci_id[] = { 828 { "tcpci", 0 }, 829 { } 830 }; 831 MODULE_DEVICE_TABLE(i2c, tcpci_id); 832 833 #ifdef CONFIG_OF 834 static const struct of_device_id tcpci_of_match[] = { 835 { .compatible = "nxp,ptn5110", }, 836 {}, 837 }; 838 MODULE_DEVICE_TABLE(of, tcpci_of_match); 839 #endif 840 841 static struct i2c_driver tcpci_i2c_driver = { 842 .driver = { 843 .name = "tcpci", 844 .of_match_table = of_match_ptr(tcpci_of_match), 845 }, 846 .probe = tcpci_probe, 847 .remove = tcpci_remove, 848 .id_table = tcpci_id, 849 }; 850 module_i2c_driver(tcpci_i2c_driver); 851 852 MODULE_DESCRIPTION("USB Type-C Port Controller Interface driver"); 853 MODULE_LICENSE("GPL"); 854