1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015-2017 Google, Inc 4 * 5 * USB Type-C Port Controller Interface. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/usb/pd.h> 16 #include <linux/usb/tcpm.h> 17 #include <linux/usb/typec.h> 18 19 #include "tcpci.h" 20 21 #define PD_RETRY_COUNT_DEFAULT 3 22 #define PD_RETRY_COUNT_3_0_OR_HIGHER 2 23 #define AUTO_DISCHARGE_DEFAULT_THRESHOLD_MV 3500 24 #define VSINKPD_MIN_IR_DROP_MV 750 25 #define VSRC_NEW_MIN_PERCENT 95 26 #define VSRC_VALID_MIN_MV 500 27 #define VPPS_NEW_MIN_PERCENT 95 28 #define VPPS_VALID_MIN_MV 100 29 #define VSINKDISCONNECT_PD_MIN_PERCENT 90 30 31 #define tcpc_presenting_rd(reg, cc) \ 32 (!(TCPC_ROLE_CTRL_DRP & (reg)) && \ 33 (((reg) & (TCPC_ROLE_CTRL_## cc ##_MASK << TCPC_ROLE_CTRL_## cc ##_SHIFT)) == \ 34 (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_## cc ##_SHIFT))) 35 36 struct tcpci { 37 struct device *dev; 38 39 struct tcpm_port *port; 40 41 struct regmap *regmap; 42 43 bool controls_vbus; 44 45 struct tcpc_dev tcpc; 46 struct tcpci_data *data; 47 }; 48 49 struct tcpci_chip { 50 struct tcpci *tcpci; 51 struct tcpci_data data; 52 }; 53 54 struct tcpm_port *tcpci_get_tcpm_port(struct tcpci *tcpci) 55 { 56 return tcpci->port; 57 } 58 EXPORT_SYMBOL_GPL(tcpci_get_tcpm_port); 59 60 static inline struct tcpci *tcpc_to_tcpci(struct tcpc_dev *tcpc) 61 { 62 return container_of(tcpc, struct tcpci, tcpc); 63 } 64 65 static int tcpci_read16(struct tcpci *tcpci, unsigned int reg, u16 *val) 66 { 67 return regmap_raw_read(tcpci->regmap, reg, val, sizeof(u16)); 68 } 69 70 static int tcpci_write16(struct tcpci *tcpci, unsigned int reg, u16 val) 71 { 72 return regmap_raw_write(tcpci->regmap, reg, &val, sizeof(u16)); 73 } 74 75 static int tcpci_set_cc(struct tcpc_dev *tcpc, enum typec_cc_status cc) 76 { 77 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 78 bool vconn_pres; 79 enum typec_cc_polarity polarity = TYPEC_POLARITY_CC1; 80 unsigned int reg; 81 int ret; 82 83 ret = regmap_read(tcpci->regmap, TCPC_POWER_STATUS, ®); 84 if (ret < 0) 85 return ret; 86 87 vconn_pres = !!(reg & TCPC_POWER_STATUS_VCONN_PRES); 88 if (vconn_pres) { 89 ret = regmap_read(tcpci->regmap, TCPC_TCPC_CTRL, ®); 90 if (ret < 0) 91 return ret; 92 93 if (reg & TCPC_TCPC_CTRL_ORIENTATION) 94 polarity = TYPEC_POLARITY_CC2; 95 } 96 97 switch (cc) { 98 case TYPEC_CC_RA: 99 reg = (TCPC_ROLE_CTRL_CC_RA << TCPC_ROLE_CTRL_CC1_SHIFT) | 100 (TCPC_ROLE_CTRL_CC_RA << TCPC_ROLE_CTRL_CC2_SHIFT); 101 break; 102 case TYPEC_CC_RD: 103 reg = (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) | 104 (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT); 105 break; 106 case TYPEC_CC_RP_DEF: 107 reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | 108 (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) | 109 (TCPC_ROLE_CTRL_RP_VAL_DEF << 110 TCPC_ROLE_CTRL_RP_VAL_SHIFT); 111 break; 112 case TYPEC_CC_RP_1_5: 113 reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | 114 (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) | 115 (TCPC_ROLE_CTRL_RP_VAL_1_5 << 116 TCPC_ROLE_CTRL_RP_VAL_SHIFT); 117 break; 118 case TYPEC_CC_RP_3_0: 119 reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | 120 (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) | 121 (TCPC_ROLE_CTRL_RP_VAL_3_0 << 122 TCPC_ROLE_CTRL_RP_VAL_SHIFT); 123 break; 124 case TYPEC_CC_OPEN: 125 default: 126 reg = (TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT) | 127 (TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC2_SHIFT); 128 break; 129 } 130 131 if (vconn_pres) { 132 if (polarity == TYPEC_POLARITY_CC2) { 133 reg &= ~(TCPC_ROLE_CTRL_CC1_MASK << TCPC_ROLE_CTRL_CC1_SHIFT); 134 reg |= (TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT); 135 } else { 136 reg &= ~(TCPC_ROLE_CTRL_CC2_MASK << TCPC_ROLE_CTRL_CC2_SHIFT); 137 reg |= (TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC2_SHIFT); 138 } 139 } 140 141 ret = regmap_write(tcpci->regmap, TCPC_ROLE_CTRL, reg); 142 if (ret < 0) 143 return ret; 144 145 return 0; 146 } 147 148 static int tcpci_apply_rc(struct tcpc_dev *tcpc, enum typec_cc_status cc, 149 enum typec_cc_polarity polarity) 150 { 151 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 152 unsigned int reg; 153 int ret; 154 155 ret = regmap_read(tcpci->regmap, TCPC_ROLE_CTRL, ®); 156 if (ret < 0) 157 return ret; 158 159 /* 160 * APPLY_RC state is when ROLE_CONTROL.CC1 != ROLE_CONTROL.CC2 and vbus autodischarge on 161 * disconnect is disabled. Bail out when ROLE_CONTROL.CC1 != ROLE_CONTROL.CC2. 162 */ 163 if (((reg & (TCPC_ROLE_CTRL_CC2_MASK << TCPC_ROLE_CTRL_CC2_SHIFT)) >> 164 TCPC_ROLE_CTRL_CC2_SHIFT) != 165 ((reg & (TCPC_ROLE_CTRL_CC1_MASK << TCPC_ROLE_CTRL_CC1_SHIFT)) >> 166 TCPC_ROLE_CTRL_CC1_SHIFT)) 167 return 0; 168 169 return regmap_update_bits(tcpci->regmap, TCPC_ROLE_CTRL, polarity == TYPEC_POLARITY_CC1 ? 170 TCPC_ROLE_CTRL_CC2_MASK << TCPC_ROLE_CTRL_CC2_SHIFT : 171 TCPC_ROLE_CTRL_CC1_MASK << TCPC_ROLE_CTRL_CC1_SHIFT, 172 TCPC_ROLE_CTRL_CC_OPEN); 173 } 174 175 static int tcpci_start_toggling(struct tcpc_dev *tcpc, 176 enum typec_port_type port_type, 177 enum typec_cc_status cc) 178 { 179 int ret; 180 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 181 unsigned int reg = TCPC_ROLE_CTRL_DRP; 182 183 if (port_type != TYPEC_PORT_DRP) 184 return -EOPNOTSUPP; 185 186 /* Handle vendor drp toggling */ 187 if (tcpci->data->start_drp_toggling) { 188 ret = tcpci->data->start_drp_toggling(tcpci, tcpci->data, cc); 189 if (ret < 0) 190 return ret; 191 } 192 193 switch (cc) { 194 default: 195 case TYPEC_CC_RP_DEF: 196 reg |= (TCPC_ROLE_CTRL_RP_VAL_DEF << 197 TCPC_ROLE_CTRL_RP_VAL_SHIFT); 198 break; 199 case TYPEC_CC_RP_1_5: 200 reg |= (TCPC_ROLE_CTRL_RP_VAL_1_5 << 201 TCPC_ROLE_CTRL_RP_VAL_SHIFT); 202 break; 203 case TYPEC_CC_RP_3_0: 204 reg |= (TCPC_ROLE_CTRL_RP_VAL_3_0 << 205 TCPC_ROLE_CTRL_RP_VAL_SHIFT); 206 break; 207 } 208 209 if (cc == TYPEC_CC_RD) 210 reg |= (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) | 211 (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT); 212 else 213 reg |= (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | 214 (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT); 215 ret = regmap_write(tcpci->regmap, TCPC_ROLE_CTRL, reg); 216 if (ret < 0) 217 return ret; 218 return regmap_write(tcpci->regmap, TCPC_COMMAND, 219 TCPC_CMD_LOOK4CONNECTION); 220 } 221 222 static enum typec_cc_status tcpci_to_typec_cc(unsigned int cc, bool sink) 223 { 224 switch (cc) { 225 case 0x1: 226 return sink ? TYPEC_CC_RP_DEF : TYPEC_CC_RA; 227 case 0x2: 228 return sink ? TYPEC_CC_RP_1_5 : TYPEC_CC_RD; 229 case 0x3: 230 if (sink) 231 return TYPEC_CC_RP_3_0; 232 fallthrough; 233 case 0x0: 234 default: 235 return TYPEC_CC_OPEN; 236 } 237 } 238 239 static int tcpci_get_cc(struct tcpc_dev *tcpc, 240 enum typec_cc_status *cc1, enum typec_cc_status *cc2) 241 { 242 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 243 unsigned int reg, role_control; 244 int ret; 245 246 ret = regmap_read(tcpci->regmap, TCPC_ROLE_CTRL, &role_control); 247 if (ret < 0) 248 return ret; 249 250 ret = regmap_read(tcpci->regmap, TCPC_CC_STATUS, ®); 251 if (ret < 0) 252 return ret; 253 254 *cc1 = tcpci_to_typec_cc((reg >> TCPC_CC_STATUS_CC1_SHIFT) & 255 TCPC_CC_STATUS_CC1_MASK, 256 reg & TCPC_CC_STATUS_TERM || 257 tcpc_presenting_rd(role_control, CC1)); 258 *cc2 = tcpci_to_typec_cc((reg >> TCPC_CC_STATUS_CC2_SHIFT) & 259 TCPC_CC_STATUS_CC2_MASK, 260 reg & TCPC_CC_STATUS_TERM || 261 tcpc_presenting_rd(role_control, CC2)); 262 263 return 0; 264 } 265 266 static int tcpci_set_polarity(struct tcpc_dev *tcpc, 267 enum typec_cc_polarity polarity) 268 { 269 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 270 unsigned int reg; 271 int ret; 272 enum typec_cc_status cc1, cc2; 273 274 /* Obtain Rp setting from role control */ 275 ret = regmap_read(tcpci->regmap, TCPC_ROLE_CTRL, ®); 276 if (ret < 0) 277 return ret; 278 279 ret = tcpci_get_cc(tcpc, &cc1, &cc2); 280 if (ret < 0) 281 return ret; 282 283 /* 284 * When port has drp toggling enabled, ROLE_CONTROL would only have the initial 285 * terminations for the toggling and does not indicate the final cc 286 * terminations when ConnectionResult is 0 i.e. drp toggling stops and 287 * the connection is resolved. Infer port role from TCPC_CC_STATUS based on the 288 * terminations seen. The port role is then used to set the cc terminations. 289 */ 290 if (reg & TCPC_ROLE_CTRL_DRP) { 291 /* Disable DRP for the OPEN setting to take effect */ 292 reg = reg & ~TCPC_ROLE_CTRL_DRP; 293 294 if (polarity == TYPEC_POLARITY_CC2) { 295 reg &= ~(TCPC_ROLE_CTRL_CC2_MASK << TCPC_ROLE_CTRL_CC2_SHIFT); 296 /* Local port is source */ 297 if (cc2 == TYPEC_CC_RD) 298 /* Role control would have the Rp setting when DRP was enabled */ 299 reg |= TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT; 300 else 301 reg |= TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT; 302 } else { 303 reg &= ~(TCPC_ROLE_CTRL_CC1_MASK << TCPC_ROLE_CTRL_CC1_SHIFT); 304 /* Local port is source */ 305 if (cc1 == TYPEC_CC_RD) 306 /* Role control would have the Rp setting when DRP was enabled */ 307 reg |= TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT; 308 else 309 reg |= TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT; 310 } 311 } 312 313 if (polarity == TYPEC_POLARITY_CC2) 314 reg |= TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT; 315 else 316 reg |= TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC2_SHIFT; 317 ret = regmap_write(tcpci->regmap, TCPC_ROLE_CTRL, reg); 318 if (ret < 0) 319 return ret; 320 321 return regmap_write(tcpci->regmap, TCPC_TCPC_CTRL, 322 (polarity == TYPEC_POLARITY_CC2) ? 323 TCPC_TCPC_CTRL_ORIENTATION : 0); 324 } 325 326 static void tcpci_set_partner_usb_comm_capable(struct tcpc_dev *tcpc, bool capable) 327 { 328 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 329 330 if (tcpci->data->set_partner_usb_comm_capable) 331 tcpci->data->set_partner_usb_comm_capable(tcpci, tcpci->data, capable); 332 } 333 334 static int tcpci_set_vconn(struct tcpc_dev *tcpc, bool enable) 335 { 336 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 337 int ret; 338 339 /* Handle vendor set vconn */ 340 if (tcpci->data->set_vconn) { 341 ret = tcpci->data->set_vconn(tcpci, tcpci->data, enable); 342 if (ret < 0) 343 return ret; 344 } 345 346 return regmap_update_bits(tcpci->regmap, TCPC_POWER_CTRL, 347 TCPC_POWER_CTRL_VCONN_ENABLE, 348 enable ? TCPC_POWER_CTRL_VCONN_ENABLE : 0); 349 } 350 351 static int tcpci_enable_auto_vbus_discharge(struct tcpc_dev *dev, bool enable) 352 { 353 struct tcpci *tcpci = tcpc_to_tcpci(dev); 354 int ret; 355 356 ret = regmap_update_bits(tcpci->regmap, TCPC_POWER_CTRL, TCPC_POWER_CTRL_AUTO_DISCHARGE, 357 enable ? TCPC_POWER_CTRL_AUTO_DISCHARGE : 0); 358 return ret; 359 } 360 361 static int tcpci_set_auto_vbus_discharge_threshold(struct tcpc_dev *dev, enum typec_pwr_opmode mode, 362 bool pps_active, u32 requested_vbus_voltage_mv) 363 { 364 struct tcpci *tcpci = tcpc_to_tcpci(dev); 365 unsigned int pwr_ctrl, threshold = 0; 366 int ret; 367 368 /* 369 * Indicates that vbus is going to go away due PR_SWAP, hard reset etc. 370 * Do not discharge vbus here. 371 */ 372 if (requested_vbus_voltage_mv == 0) 373 goto write_thresh; 374 375 ret = regmap_read(tcpci->regmap, TCPC_POWER_CTRL, &pwr_ctrl); 376 if (ret < 0) 377 return ret; 378 379 if (pwr_ctrl & TCPC_FAST_ROLE_SWAP_EN) { 380 /* To prevent disconnect when the source is fast role swap is capable. */ 381 threshold = AUTO_DISCHARGE_DEFAULT_THRESHOLD_MV; 382 } else if (mode == TYPEC_PWR_MODE_PD) { 383 if (pps_active) 384 threshold = ((VPPS_NEW_MIN_PERCENT * requested_vbus_voltage_mv / 100) - 385 VSINKPD_MIN_IR_DROP_MV - VPPS_VALID_MIN_MV) * 386 VSINKDISCONNECT_PD_MIN_PERCENT / 100; 387 else 388 threshold = ((VSRC_NEW_MIN_PERCENT * requested_vbus_voltage_mv / 100) - 389 VSINKPD_MIN_IR_DROP_MV - VSRC_VALID_MIN_MV) * 390 VSINKDISCONNECT_PD_MIN_PERCENT / 100; 391 } else { 392 /* 3.5V for non-pd sink */ 393 threshold = AUTO_DISCHARGE_DEFAULT_THRESHOLD_MV; 394 } 395 396 threshold = threshold / TCPC_VBUS_SINK_DISCONNECT_THRESH_LSB_MV; 397 398 if (threshold > TCPC_VBUS_SINK_DISCONNECT_THRESH_MAX) 399 return -EINVAL; 400 401 write_thresh: 402 return tcpci_write16(tcpci, TCPC_VBUS_SINK_DISCONNECT_THRESH, threshold); 403 } 404 405 static int tcpci_enable_frs(struct tcpc_dev *dev, bool enable) 406 { 407 struct tcpci *tcpci = tcpc_to_tcpci(dev); 408 int ret; 409 410 /* To prevent disconnect during FRS, set disconnect threshold to 3.5V */ 411 ret = tcpci_write16(tcpci, TCPC_VBUS_SINK_DISCONNECT_THRESH, enable ? 0 : 0x8c); 412 if (ret < 0) 413 return ret; 414 415 ret = regmap_update_bits(tcpci->regmap, TCPC_POWER_CTRL, TCPC_FAST_ROLE_SWAP_EN, enable ? 416 TCPC_FAST_ROLE_SWAP_EN : 0); 417 418 return ret; 419 } 420 421 static void tcpci_frs_sourcing_vbus(struct tcpc_dev *dev) 422 { 423 struct tcpci *tcpci = tcpc_to_tcpci(dev); 424 425 if (tcpci->data->frs_sourcing_vbus) 426 tcpci->data->frs_sourcing_vbus(tcpci, tcpci->data); 427 } 428 429 static int tcpci_set_bist_data(struct tcpc_dev *tcpc, bool enable) 430 { 431 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 432 433 return regmap_update_bits(tcpci->regmap, TCPC_TCPC_CTRL, TCPC_TCPC_CTRL_BIST_TM, 434 enable ? TCPC_TCPC_CTRL_BIST_TM : 0); 435 } 436 437 static int tcpci_set_roles(struct tcpc_dev *tcpc, bool attached, 438 enum typec_role role, enum typec_data_role data) 439 { 440 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 441 unsigned int reg; 442 int ret; 443 444 reg = PD_REV20 << TCPC_MSG_HDR_INFO_REV_SHIFT; 445 if (role == TYPEC_SOURCE) 446 reg |= TCPC_MSG_HDR_INFO_PWR_ROLE; 447 if (data == TYPEC_HOST) 448 reg |= TCPC_MSG_HDR_INFO_DATA_ROLE; 449 ret = regmap_write(tcpci->regmap, TCPC_MSG_HDR_INFO, reg); 450 if (ret < 0) 451 return ret; 452 453 return 0; 454 } 455 456 static int tcpci_set_pd_rx(struct tcpc_dev *tcpc, bool enable) 457 { 458 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 459 unsigned int reg = 0; 460 int ret; 461 462 if (enable) 463 reg = TCPC_RX_DETECT_SOP | TCPC_RX_DETECT_HARD_RESET; 464 ret = regmap_write(tcpci->regmap, TCPC_RX_DETECT, reg); 465 if (ret < 0) 466 return ret; 467 468 return 0; 469 } 470 471 static int tcpci_get_vbus(struct tcpc_dev *tcpc) 472 { 473 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 474 unsigned int reg; 475 int ret; 476 477 ret = regmap_read(tcpci->regmap, TCPC_POWER_STATUS, ®); 478 if (ret < 0) 479 return ret; 480 481 return !!(reg & TCPC_POWER_STATUS_VBUS_PRES); 482 } 483 484 static bool tcpci_is_vbus_vsafe0v(struct tcpc_dev *tcpc) 485 { 486 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 487 unsigned int reg; 488 int ret; 489 490 ret = regmap_read(tcpci->regmap, TCPC_EXTENDED_STATUS, ®); 491 if (ret < 0) 492 return false; 493 494 return !!(reg & TCPC_EXTENDED_STATUS_VSAFE0V); 495 } 496 497 static int tcpci_set_vbus(struct tcpc_dev *tcpc, bool source, bool sink) 498 { 499 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 500 int ret; 501 502 if (tcpci->data->set_vbus) { 503 ret = tcpci->data->set_vbus(tcpci, tcpci->data, source, sink); 504 /* Bypass when ret > 0 */ 505 if (ret != 0) 506 return ret < 0 ? ret : 0; 507 } 508 509 /* Disable both source and sink first before enabling anything */ 510 511 if (!source) { 512 ret = regmap_write(tcpci->regmap, TCPC_COMMAND, 513 TCPC_CMD_DISABLE_SRC_VBUS); 514 if (ret < 0) 515 return ret; 516 } 517 518 if (!sink) { 519 ret = regmap_write(tcpci->regmap, TCPC_COMMAND, 520 TCPC_CMD_DISABLE_SINK_VBUS); 521 if (ret < 0) 522 return ret; 523 } 524 525 if (source) { 526 ret = regmap_write(tcpci->regmap, TCPC_COMMAND, 527 TCPC_CMD_SRC_VBUS_DEFAULT); 528 if (ret < 0) 529 return ret; 530 } 531 532 if (sink) { 533 ret = regmap_write(tcpci->regmap, TCPC_COMMAND, 534 TCPC_CMD_SINK_VBUS); 535 if (ret < 0) 536 return ret; 537 } 538 539 return 0; 540 } 541 542 static int tcpci_pd_transmit(struct tcpc_dev *tcpc, enum tcpm_transmit_type type, 543 const struct pd_message *msg, unsigned int negotiated_rev) 544 { 545 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 546 u16 header = msg ? le16_to_cpu(msg->header) : 0; 547 unsigned int reg, cnt; 548 int ret; 549 550 cnt = msg ? pd_header_cnt(header) * 4 : 0; 551 /** 552 * TCPCI spec forbids direct access of TCPC_TX_DATA. 553 * But, since some of the chipsets offer this capability, 554 * it's fair to support both. 555 */ 556 if (tcpci->data->TX_BUF_BYTE_x_hidden) { 557 u8 buf[TCPC_TRANSMIT_BUFFER_MAX_LEN] = {0,}; 558 u8 pos = 0; 559 560 /* Payload + header + TCPC_TX_BYTE_CNT */ 561 buf[pos++] = cnt + 2; 562 563 if (msg) 564 memcpy(&buf[pos], &msg->header, sizeof(msg->header)); 565 566 pos += sizeof(header); 567 568 if (cnt > 0) 569 memcpy(&buf[pos], msg->payload, cnt); 570 571 pos += cnt; 572 ret = regmap_raw_write(tcpci->regmap, TCPC_TX_BYTE_CNT, buf, pos); 573 if (ret < 0) 574 return ret; 575 } else { 576 ret = regmap_write(tcpci->regmap, TCPC_TX_BYTE_CNT, cnt + 2); 577 if (ret < 0) 578 return ret; 579 580 ret = tcpci_write16(tcpci, TCPC_TX_HDR, header); 581 if (ret < 0) 582 return ret; 583 584 if (cnt > 0) { 585 ret = regmap_raw_write(tcpci->regmap, TCPC_TX_DATA, &msg->payload, cnt); 586 if (ret < 0) 587 return ret; 588 } 589 } 590 591 /* nRetryCount is 3 in PD2.0 spec where 2 in PD3.0 spec */ 592 reg = ((negotiated_rev > PD_REV20 ? PD_RETRY_COUNT_3_0_OR_HIGHER : PD_RETRY_COUNT_DEFAULT) 593 << TCPC_TRANSMIT_RETRY_SHIFT) | (type << TCPC_TRANSMIT_TYPE_SHIFT); 594 ret = regmap_write(tcpci->regmap, TCPC_TRANSMIT, reg); 595 if (ret < 0) 596 return ret; 597 598 return 0; 599 } 600 601 static int tcpci_init(struct tcpc_dev *tcpc) 602 { 603 struct tcpci *tcpci = tcpc_to_tcpci(tcpc); 604 unsigned long timeout = jiffies + msecs_to_jiffies(2000); /* XXX */ 605 unsigned int reg; 606 int ret; 607 608 while (time_before_eq(jiffies, timeout)) { 609 ret = regmap_read(tcpci->regmap, TCPC_POWER_STATUS, ®); 610 if (ret < 0) 611 return ret; 612 if (!(reg & TCPC_POWER_STATUS_UNINIT)) 613 break; 614 usleep_range(10000, 20000); 615 } 616 if (time_after(jiffies, timeout)) 617 return -ETIMEDOUT; 618 619 /* Handle vendor init */ 620 if (tcpci->data->init) { 621 ret = tcpci->data->init(tcpci, tcpci->data); 622 if (ret < 0) 623 return ret; 624 } 625 626 /* Clear all events */ 627 ret = tcpci_write16(tcpci, TCPC_ALERT, 0xffff); 628 if (ret < 0) 629 return ret; 630 631 if (tcpci->controls_vbus) 632 reg = TCPC_POWER_STATUS_VBUS_PRES; 633 else 634 reg = 0; 635 ret = regmap_write(tcpci->regmap, TCPC_POWER_STATUS_MASK, reg); 636 if (ret < 0) 637 return ret; 638 639 /* Enable Vbus detection */ 640 ret = regmap_write(tcpci->regmap, TCPC_COMMAND, 641 TCPC_CMD_ENABLE_VBUS_DETECT); 642 if (ret < 0) 643 return ret; 644 645 reg = TCPC_ALERT_TX_SUCCESS | TCPC_ALERT_TX_FAILED | 646 TCPC_ALERT_TX_DISCARDED | TCPC_ALERT_RX_STATUS | 647 TCPC_ALERT_RX_HARD_RST | TCPC_ALERT_CC_STATUS; 648 if (tcpci->controls_vbus) 649 reg |= TCPC_ALERT_POWER_STATUS; 650 /* Enable VSAFE0V status interrupt when detecting VSAFE0V is supported */ 651 if (tcpci->data->vbus_vsafe0v) { 652 reg |= TCPC_ALERT_EXTENDED_STATUS; 653 ret = regmap_write(tcpci->regmap, TCPC_EXTENDED_STATUS_MASK, 654 TCPC_EXTENDED_STATUS_VSAFE0V); 655 if (ret < 0) 656 return ret; 657 } 658 return tcpci_write16(tcpci, TCPC_ALERT_MASK, reg); 659 } 660 661 irqreturn_t tcpci_irq(struct tcpci *tcpci) 662 { 663 u16 status; 664 int ret; 665 unsigned int raw; 666 667 tcpci_read16(tcpci, TCPC_ALERT, &status); 668 669 /* 670 * Clear alert status for everything except RX_STATUS, which shouldn't 671 * be cleared until we have successfully retrieved message. 672 */ 673 if (status & ~TCPC_ALERT_RX_STATUS) 674 tcpci_write16(tcpci, TCPC_ALERT, 675 status & ~TCPC_ALERT_RX_STATUS); 676 677 if (status & TCPC_ALERT_CC_STATUS) 678 tcpm_cc_change(tcpci->port); 679 680 if (status & TCPC_ALERT_POWER_STATUS) { 681 regmap_read(tcpci->regmap, TCPC_POWER_STATUS_MASK, &raw); 682 /* 683 * If power status mask has been reset, then the TCPC 684 * has reset. 685 */ 686 if (raw == 0xff) 687 tcpm_tcpc_reset(tcpci->port); 688 else 689 tcpm_vbus_change(tcpci->port); 690 } 691 692 if (status & TCPC_ALERT_RX_STATUS) { 693 struct pd_message msg; 694 unsigned int cnt, payload_cnt; 695 u16 header; 696 697 regmap_read(tcpci->regmap, TCPC_RX_BYTE_CNT, &cnt); 698 /* 699 * 'cnt' corresponds to READABLE_BYTE_COUNT in section 4.4.14 700 * of the TCPCI spec [Rev 2.0 Ver 1.0 October 2017] and is 701 * defined in table 4-36 as one greater than the number of 702 * bytes received. And that number includes the header. So: 703 */ 704 if (cnt > 3) 705 payload_cnt = cnt - (1 + sizeof(msg.header)); 706 else 707 payload_cnt = 0; 708 709 tcpci_read16(tcpci, TCPC_RX_HDR, &header); 710 msg.header = cpu_to_le16(header); 711 712 if (WARN_ON(payload_cnt > sizeof(msg.payload))) 713 payload_cnt = sizeof(msg.payload); 714 715 if (payload_cnt > 0) 716 regmap_raw_read(tcpci->regmap, TCPC_RX_DATA, 717 &msg.payload, payload_cnt); 718 719 /* Read complete, clear RX status alert bit */ 720 tcpci_write16(tcpci, TCPC_ALERT, TCPC_ALERT_RX_STATUS); 721 722 tcpm_pd_receive(tcpci->port, &msg); 723 } 724 725 if (tcpci->data->vbus_vsafe0v && (status & TCPC_ALERT_EXTENDED_STATUS)) { 726 ret = regmap_read(tcpci->regmap, TCPC_EXTENDED_STATUS, &raw); 727 if (!ret && (raw & TCPC_EXTENDED_STATUS_VSAFE0V)) 728 tcpm_vbus_change(tcpci->port); 729 } 730 731 if (status & TCPC_ALERT_RX_HARD_RST) 732 tcpm_pd_hard_reset(tcpci->port); 733 734 if (status & TCPC_ALERT_TX_SUCCESS) 735 tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_SUCCESS); 736 else if (status & TCPC_ALERT_TX_DISCARDED) 737 tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_DISCARDED); 738 else if (status & TCPC_ALERT_TX_FAILED) 739 tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_FAILED); 740 741 return IRQ_HANDLED; 742 } 743 EXPORT_SYMBOL_GPL(tcpci_irq); 744 745 static irqreturn_t _tcpci_irq(int irq, void *dev_id) 746 { 747 struct tcpci_chip *chip = dev_id; 748 749 return tcpci_irq(chip->tcpci); 750 } 751 752 static const struct regmap_config tcpci_regmap_config = { 753 .reg_bits = 8, 754 .val_bits = 8, 755 756 .max_register = 0x7F, /* 0x80 .. 0xFF are vendor defined */ 757 }; 758 759 static int tcpci_parse_config(struct tcpci *tcpci) 760 { 761 tcpci->controls_vbus = true; /* XXX */ 762 763 tcpci->tcpc.fwnode = device_get_named_child_node(tcpci->dev, 764 "connector"); 765 if (!tcpci->tcpc.fwnode) { 766 dev_err(tcpci->dev, "Can't find connector node.\n"); 767 return -EINVAL; 768 } 769 770 return 0; 771 } 772 773 struct tcpci *tcpci_register_port(struct device *dev, struct tcpci_data *data) 774 { 775 struct tcpci *tcpci; 776 int err; 777 778 tcpci = devm_kzalloc(dev, sizeof(*tcpci), GFP_KERNEL); 779 if (!tcpci) 780 return ERR_PTR(-ENOMEM); 781 782 tcpci->dev = dev; 783 tcpci->data = data; 784 tcpci->regmap = data->regmap; 785 786 tcpci->tcpc.init = tcpci_init; 787 tcpci->tcpc.get_vbus = tcpci_get_vbus; 788 tcpci->tcpc.set_vbus = tcpci_set_vbus; 789 tcpci->tcpc.set_cc = tcpci_set_cc; 790 tcpci->tcpc.apply_rc = tcpci_apply_rc; 791 tcpci->tcpc.get_cc = tcpci_get_cc; 792 tcpci->tcpc.set_polarity = tcpci_set_polarity; 793 tcpci->tcpc.set_vconn = tcpci_set_vconn; 794 tcpci->tcpc.start_toggling = tcpci_start_toggling; 795 796 tcpci->tcpc.set_pd_rx = tcpci_set_pd_rx; 797 tcpci->tcpc.set_roles = tcpci_set_roles; 798 tcpci->tcpc.pd_transmit = tcpci_pd_transmit; 799 tcpci->tcpc.set_bist_data = tcpci_set_bist_data; 800 tcpci->tcpc.enable_frs = tcpci_enable_frs; 801 tcpci->tcpc.frs_sourcing_vbus = tcpci_frs_sourcing_vbus; 802 tcpci->tcpc.set_partner_usb_comm_capable = tcpci_set_partner_usb_comm_capable; 803 804 if (tcpci->data->auto_discharge_disconnect) { 805 tcpci->tcpc.enable_auto_vbus_discharge = tcpci_enable_auto_vbus_discharge; 806 tcpci->tcpc.set_auto_vbus_discharge_threshold = 807 tcpci_set_auto_vbus_discharge_threshold; 808 regmap_update_bits(tcpci->regmap, TCPC_POWER_CTRL, TCPC_POWER_CTRL_BLEED_DISCHARGE, 809 TCPC_POWER_CTRL_BLEED_DISCHARGE); 810 } 811 812 if (tcpci->data->vbus_vsafe0v) 813 tcpci->tcpc.is_vbus_vsafe0v = tcpci_is_vbus_vsafe0v; 814 815 err = tcpci_parse_config(tcpci); 816 if (err < 0) 817 return ERR_PTR(err); 818 819 tcpci->port = tcpm_register_port(tcpci->dev, &tcpci->tcpc); 820 if (IS_ERR(tcpci->port)) 821 return ERR_CAST(tcpci->port); 822 823 return tcpci; 824 } 825 EXPORT_SYMBOL_GPL(tcpci_register_port); 826 827 void tcpci_unregister_port(struct tcpci *tcpci) 828 { 829 tcpm_unregister_port(tcpci->port); 830 } 831 EXPORT_SYMBOL_GPL(tcpci_unregister_port); 832 833 static int tcpci_probe(struct i2c_client *client, 834 const struct i2c_device_id *i2c_id) 835 { 836 struct tcpci_chip *chip; 837 int err; 838 u16 val = 0; 839 840 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); 841 if (!chip) 842 return -ENOMEM; 843 844 chip->data.regmap = devm_regmap_init_i2c(client, &tcpci_regmap_config); 845 if (IS_ERR(chip->data.regmap)) 846 return PTR_ERR(chip->data.regmap); 847 848 i2c_set_clientdata(client, chip); 849 850 /* Disable chip interrupts before requesting irq */ 851 err = regmap_raw_write(chip->data.regmap, TCPC_ALERT_MASK, &val, 852 sizeof(u16)); 853 if (err < 0) 854 return err; 855 856 chip->tcpci = tcpci_register_port(&client->dev, &chip->data); 857 if (IS_ERR(chip->tcpci)) 858 return PTR_ERR(chip->tcpci); 859 860 err = devm_request_threaded_irq(&client->dev, client->irq, NULL, 861 _tcpci_irq, 862 IRQF_ONESHOT | IRQF_TRIGGER_LOW, 863 dev_name(&client->dev), chip); 864 if (err < 0) { 865 tcpci_unregister_port(chip->tcpci); 866 return err; 867 } 868 869 return 0; 870 } 871 872 static int tcpci_remove(struct i2c_client *client) 873 { 874 struct tcpci_chip *chip = i2c_get_clientdata(client); 875 int err; 876 877 /* Disable chip interrupts before unregistering port */ 878 err = tcpci_write16(chip->tcpci, TCPC_ALERT_MASK, 0); 879 if (err < 0) 880 dev_warn(&client->dev, "Failed to disable irqs (%pe)\n", ERR_PTR(err)); 881 882 tcpci_unregister_port(chip->tcpci); 883 884 return 0; 885 } 886 887 static const struct i2c_device_id tcpci_id[] = { 888 { "tcpci", 0 }, 889 { } 890 }; 891 MODULE_DEVICE_TABLE(i2c, tcpci_id); 892 893 #ifdef CONFIG_OF 894 static const struct of_device_id tcpci_of_match[] = { 895 { .compatible = "nxp,ptn5110", }, 896 {}, 897 }; 898 MODULE_DEVICE_TABLE(of, tcpci_of_match); 899 #endif 900 901 static struct i2c_driver tcpci_i2c_driver = { 902 .driver = { 903 .name = "tcpci", 904 .of_match_table = of_match_ptr(tcpci_of_match), 905 }, 906 .probe = tcpci_probe, 907 .remove = tcpci_remove, 908 .id_table = tcpci_id, 909 }; 910 module_i2c_driver(tcpci_i2c_driver); 911 912 MODULE_DESCRIPTION("USB Type-C Port Controller Interface driver"); 913 MODULE_LICENSE("GPL"); 914