1 // SPDX-License-Identifier: GPL-1.0+ 2 /* 3 * Renesas USB driver 4 * 5 * Copyright (C) 2011 Renesas Solutions Corp. 6 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 7 */ 8 #ifndef RENESAS_USB_DRIVER_H 9 #define RENESAS_USB_DRIVER_H 10 11 #include <linux/clk.h> 12 #include <linux/extcon.h> 13 #include <linux/platform_device.h> 14 #include <linux/reset.h> 15 #include <linux/usb/renesas_usbhs.h> 16 17 struct usbhs_priv; 18 19 #include "mod.h" 20 #include "pipe.h" 21 22 /* 23 * 24 * register define 25 * 26 */ 27 #define SYSCFG 0x0000 28 #define BUSWAIT 0x0002 29 #define DVSTCTR 0x0008 30 #define TESTMODE 0x000C 31 #define CFIFO 0x0014 32 #define CFIFOSEL 0x0020 33 #define CFIFOCTR 0x0022 34 #define D0FIFO 0x0100 35 #define D0FIFOSEL 0x0028 36 #define D0FIFOCTR 0x002A 37 #define D1FIFO 0x0120 38 #define D1FIFOSEL 0x002C 39 #define D1FIFOCTR 0x002E 40 #define INTENB0 0x0030 41 #define INTENB1 0x0032 42 #define BRDYENB 0x0036 43 #define NRDYENB 0x0038 44 #define BEMPENB 0x003A 45 #define INTSTS0 0x0040 46 #define INTSTS1 0x0042 47 #define BRDYSTS 0x0046 48 #define NRDYSTS 0x0048 49 #define BEMPSTS 0x004A 50 #define FRMNUM 0x004C 51 #define USBREQ 0x0054 /* USB request type register */ 52 #define USBVAL 0x0056 /* USB request value register */ 53 #define USBINDX 0x0058 /* USB request index register */ 54 #define USBLENG 0x005A /* USB request length register */ 55 #define DCPCFG 0x005C 56 #define DCPMAXP 0x005E 57 #define DCPCTR 0x0060 58 #define PIPESEL 0x0064 59 #define PIPECFG 0x0068 60 #define PIPEBUF 0x006A 61 #define PIPEMAXP 0x006C 62 #define PIPEPERI 0x006E 63 #define PIPEnCTR 0x0070 64 #define PIPE1TRE 0x0090 65 #define PIPE1TRN 0x0092 66 #define PIPE2TRE 0x0094 67 #define PIPE2TRN 0x0096 68 #define PIPE3TRE 0x0098 69 #define PIPE3TRN 0x009A 70 #define PIPE4TRE 0x009C 71 #define PIPE4TRN 0x009E 72 #define PIPE5TRE 0x00A0 73 #define PIPE5TRN 0x00A2 74 #define PIPEBTRE 0x00A4 75 #define PIPEBTRN 0x00A6 76 #define PIPECTRE 0x00A8 77 #define PIPECTRN 0x00AA 78 #define PIPEDTRE 0x00AC 79 #define PIPEDTRN 0x00AE 80 #define PIPEETRE 0x00B0 81 #define PIPEETRN 0x00B2 82 #define PIPEFTRE 0x00B4 83 #define PIPEFTRN 0x00B6 84 #define PIPE9TRE 0x00B8 85 #define PIPE9TRN 0x00BA 86 #define PIPEATRE 0x00BC 87 #define PIPEATRN 0x00BE 88 #define DEVADD0 0x00D0 /* Device address n configuration */ 89 #define DEVADD1 0x00D2 90 #define DEVADD2 0x00D4 91 #define DEVADD3 0x00D6 92 #define DEVADD4 0x00D8 93 #define DEVADD5 0x00DA 94 #define DEVADD6 0x00DC 95 #define DEVADD7 0x00DE 96 #define DEVADD8 0x00E0 97 #define DEVADD9 0x00E2 98 #define DEVADDA 0x00E4 99 #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */ 100 #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */ 101 #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */ 102 #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */ 103 #define SUSPMODE 0x0102 /* for RZ/A */ 104 105 /* SYSCFG */ 106 #define SCKE (1 << 10) /* USB Module Clock Enable */ 107 #define HSE (1 << 7) /* High-Speed Operation Enable */ 108 #define DCFM (1 << 6) /* Controller Function Select */ 109 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */ 110 #define DPRPU (1 << 4) /* D+ Line Resistance Control */ 111 #define USBE (1 << 0) /* USB Module Operation Enable */ 112 #define UCKSEL (1 << 2) /* Clock Select for RZ/A1 */ 113 #define UPLLE (1 << 1) /* USB PLL Enable for RZ/A1 */ 114 115 /* DVSTCTR */ 116 #define EXTLP (1 << 10) /* Controls the EXTLP pin output state */ 117 #define PWEN (1 << 9) /* Controls the PWEN pin output state */ 118 #define USBRST (1 << 6) /* Bus Reset Output */ 119 #define UACT (1 << 4) /* USB Bus Enable */ 120 #define RHST (0x7) /* Reset Handshake */ 121 #define RHST_LOW_SPEED 1 /* Low-speed connection */ 122 #define RHST_FULL_SPEED 2 /* Full-speed connection */ 123 #define RHST_HIGH_SPEED 3 /* High-speed connection */ 124 125 /* CFIFOSEL */ 126 #define DREQE (1 << 12) /* DMA Transfer Request Enable */ 127 #define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */ 128 129 /* CFIFOCTR */ 130 #define BVAL (1 << 15) /* Buffer Memory Enable Flag */ 131 #define BCLR (1 << 14) /* CPU buffer clear */ 132 #define FRDY (1 << 13) /* FIFO Port Ready */ 133 #define DTLN_MASK (0x0FFF) /* Receive Data Length */ 134 135 /* INTENB0 */ 136 #define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */ 137 #define RSME (1 << 14) /* Enable IRQ Resume */ 138 #define SOFE (1 << 13) /* Enable IRQ Frame Number Update */ 139 #define DVSE (1 << 12) /* Enable IRQ Device State Transition */ 140 #define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */ 141 #define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */ 142 #define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */ 143 #define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */ 144 145 /* INTENB1 */ 146 #define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */ 147 #define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */ 148 #define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */ 149 #define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */ 150 #define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */ 151 #define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */ 152 153 /* INTSTS0 */ 154 #define VBINT (1 << 15) /* VBUS0_0 and VBUS1_0 Interrupt Status */ 155 #define DVST (1 << 12) /* Device State Transition Interrupt Status */ 156 #define CTRT (1 << 11) /* Control Stage Interrupt Status */ 157 #define BEMP (1 << 10) /* Buffer Empty Interrupt Status */ 158 #define BRDY (1 << 8) /* Buffer Ready Interrupt Status */ 159 #define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */ 160 #define VALID (1 << 3) /* USB Request Receive */ 161 162 #define DVSQ_MASK (0x3 << 4) /* Device State */ 163 #define POWER_STATE (0 << 4) 164 #define DEFAULT_STATE (1 << 4) 165 #define ADDRESS_STATE (2 << 4) 166 #define CONFIGURATION_STATE (3 << 4) 167 168 #define CTSQ_MASK (0x7) /* Control Transfer Stage */ 169 #define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */ 170 #define READ_DATA_STAGE 1 /* Control read data stage */ 171 #define READ_STATUS_STAGE 2 /* Control read status stage */ 172 #define WRITE_DATA_STAGE 3 /* Control write data stage */ 173 #define WRITE_STATUS_STAGE 4 /* Control write status stage */ 174 #define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */ 175 #define SEQUENCE_ERROR 6 /* Control transfer sequence error */ 176 177 /* INTSTS1 */ 178 #define OVRCR (1 << 15) /* OVRCR Interrupt Status */ 179 #define BCHG (1 << 14) /* USB Bus Change Interrupt Status */ 180 #define DTCH (1 << 12) /* USB Disconnection Detect Interrupt Status */ 181 #define ATTCH (1 << 11) /* ATTCH Interrupt Status */ 182 #define EOFERR (1 << 6) /* EOF Error Detect Interrupt Status */ 183 #define SIGN (1 << 5) /* Setup Transaction Error Interrupt Status */ 184 #define SACK (1 << 4) /* Setup Transaction ACK Response Interrupt Status */ 185 186 /* PIPECFG */ 187 /* DCPCFG */ 188 #define TYPE_NONE (0 << 14) /* Transfer Type */ 189 #define TYPE_BULK (1 << 14) 190 #define TYPE_INT (2 << 14) 191 #define TYPE_ISO (3 << 14) 192 #define BFRE (1 << 10) /* BRDY Interrupt Operation Spec. */ 193 #define DBLB (1 << 9) /* Double Buffer Mode */ 194 #define SHTNAK (1 << 7) /* Pipe Disable in Transfer End */ 195 #define DIR_OUT (1 << 4) /* Transfer Direction */ 196 197 /* PIPEMAXP */ 198 /* DCPMAXP */ 199 #define DEVSEL_MASK (0xF << 12) /* Device Select */ 200 #define DCP_MAXP_MASK (0x7F) 201 #define PIPE_MAXP_MASK (0x7FF) 202 203 /* PIPEBUF */ 204 #define BUFSIZE_SHIFT 10 205 #define BUFSIZE_MASK (0x1F << BUFSIZE_SHIFT) 206 #define BUFNMB_MASK (0xFF) 207 208 /* PIPEnCTR */ 209 /* DCPCTR */ 210 #define BSTS (1 << 15) /* Buffer Status */ 211 #define SUREQ (1 << 14) /* Sending SETUP Token */ 212 #define CSSTS (1 << 12) /* CSSTS Status */ 213 #define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */ 214 #define SQCLR (1 << 8) /* Toggle Bit Clear */ 215 #define SQSET (1 << 7) /* Toggle Bit Set */ 216 #define SQMON (1 << 6) /* Toggle Bit Check */ 217 #define PBUSY (1 << 5) /* Pipe Busy */ 218 #define PID_MASK (0x3) /* Response PID */ 219 #define PID_NAK 0 220 #define PID_BUF 1 221 #define PID_STALL10 2 222 #define PID_STALL11 3 223 224 #define CCPL (1 << 2) /* Control Transfer End Enable */ 225 226 /* PIPEnTRE */ 227 #define TRENB (1 << 9) /* Transaction Counter Enable */ 228 #define TRCLR (1 << 8) /* Transaction Counter Clear */ 229 230 /* FRMNUM */ 231 #define FRNM_MASK (0x7FF) 232 233 /* DEVADDn */ 234 #define UPPHUB(x) (((x) & 0xF) << 11) /* HUB Register */ 235 #define HUBPORT(x) (((x) & 0x7) << 8) /* HUB Port for Target Device */ 236 #define USBSPD(x) (((x) & 0x3) << 6) /* Device Transfer Rate */ 237 #define USBSPD_SPEED_LOW 0x1 238 #define USBSPD_SPEED_FULL 0x2 239 #define USBSPD_SPEED_HIGH 0x3 240 241 /* SUSPMODE */ 242 #define SUSPM (1 << 14) /* SuspendM Control */ 243 244 /* 245 * struct 246 */ 247 struct usbhs_priv { 248 249 void __iomem *base; 250 unsigned int irq; 251 unsigned long irqflags; 252 253 struct renesas_usbhs_platform_callback pfunc; 254 struct renesas_usbhs_driver_param dparam; 255 256 struct delayed_work notify_hotplug_work; 257 struct platform_device *pdev; 258 259 struct extcon_dev *edev; 260 261 spinlock_t lock; 262 263 u32 flags; 264 265 /* 266 * module control 267 */ 268 struct usbhs_mod_info mod_info; 269 270 /* 271 * pipe control 272 */ 273 struct usbhs_pipe_info pipe_info; 274 275 /* 276 * fifo control 277 */ 278 struct usbhs_fifo_info fifo_info; 279 280 struct phy *phy; 281 struct reset_control *rsts; 282 struct clk *clks[2]; 283 }; 284 285 /* 286 * common 287 */ 288 u16 usbhs_read(struct usbhs_priv *priv, u32 reg); 289 void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data); 290 void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data); 291 292 #define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f) 293 #define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f) 294 295 /* 296 * sysconfig 297 */ 298 void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable); 299 void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable); 300 void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable); 301 void usbhs_sys_set_test_mode(struct usbhs_priv *priv, u16 mode); 302 303 /* 304 * usb request 305 */ 306 void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req); 307 void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req); 308 309 /* 310 * bus 311 */ 312 void usbhs_bus_send_sof_enable(struct usbhs_priv *priv); 313 void usbhs_bus_send_reset(struct usbhs_priv *priv); 314 int usbhs_bus_get_speed(struct usbhs_priv *priv); 315 int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable); 316 317 /* 318 * frame 319 */ 320 int usbhs_frame_get_num(struct usbhs_priv *priv); 321 322 /* 323 * device config 324 */ 325 int usbhs_set_device_config(struct usbhs_priv *priv, int devnum, u16 upphub, 326 u16 hubport, u16 speed); 327 328 /* 329 * interrupt functions 330 */ 331 void usbhs_xxxsts_clear(struct usbhs_priv *priv, u16 sts_reg, u16 bit); 332 333 /* 334 * data 335 */ 336 struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev); 337 #define usbhs_get_dparam(priv, param) (priv->dparam.param) 338 #define usbhs_priv_to_pdev(priv) (priv->pdev) 339 #define usbhs_priv_to_dev(priv) (&priv->pdev->dev) 340 #define usbhs_priv_to_lock(priv) (&priv->lock) 341 342 #endif /* RENESAS_USB_DRIVER_H */ 343