1 /* 2 * Copyright (C) 2010 Google, Inc. 3 * 4 * Author: 5 * Erik Gilling <konkers@google.com> 6 * Benoit Goby <benoit@android.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #include <linux/resource.h> 20 #include <linux/delay.h> 21 #include <linux/slab.h> 22 #include <linux/err.h> 23 #include <linux/export.h> 24 #include <linux/platform_device.h> 25 #include <linux/io.h> 26 #include <linux/gpio.h> 27 #include <linux/of.h> 28 #include <linux/of_gpio.h> 29 #include <linux/usb/otg.h> 30 #include <linux/usb/ulpi.h> 31 #include <asm/mach-types.h> 32 #include <linux/usb/tegra_usb_phy.h> 33 34 #define TEGRA_USB_BASE 0xC5000000 35 #define TEGRA_USB_SIZE SZ_16K 36 37 #define ULPI_VIEWPORT 0x170 38 39 #define USB_SUSP_CTRL 0x400 40 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) 41 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) 42 #define USB_SUSP_CLR (1 << 5) 43 #define USB_PHY_CLK_VALID (1 << 7) 44 #define UTMIP_RESET (1 << 11) 45 #define UHSIC_RESET (1 << 11) 46 #define UTMIP_PHY_ENABLE (1 << 12) 47 #define ULPI_PHY_ENABLE (1 << 13) 48 #define USB_SUSP_SET (1 << 14) 49 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) 50 51 #define USB1_LEGACY_CTRL 0x410 52 #define USB1_NO_LEGACY_MODE (1 << 0) 53 #define USB1_VBUS_SENSE_CTL_MASK (3 << 1) 54 #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1) 55 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \ 56 (1 << 1) 57 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1) 58 #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1) 59 60 #define ULPI_TIMING_CTRL_0 0x424 61 #define ULPI_OUTPUT_PINMUX_BYP (1 << 10) 62 #define ULPI_CLKOUT_PINMUX_BYP (1 << 11) 63 64 #define ULPI_TIMING_CTRL_1 0x428 65 #define ULPI_DATA_TRIMMER_LOAD (1 << 0) 66 #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) 67 #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) 68 #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) 69 #define ULPI_DIR_TRIMMER_LOAD (1 << 24) 70 #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) 71 72 #define UTMIP_PLL_CFG1 0x804 73 #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 74 #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) 75 76 #define UTMIP_XCVR_CFG0 0x808 77 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) 78 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) 79 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) 80 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) 81 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) 82 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) 83 #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25) 84 85 #define UTMIP_BIAS_CFG0 0x80c 86 #define UTMIP_OTGPD (1 << 11) 87 #define UTMIP_BIASPD (1 << 10) 88 89 #define UTMIP_HSRX_CFG0 0x810 90 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) 91 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) 92 93 #define UTMIP_HSRX_CFG1 0x814 94 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) 95 96 #define UTMIP_TX_CFG0 0x820 97 #define UTMIP_FS_PREABMLE_J (1 << 19) 98 #define UTMIP_HS_DISCON_DISABLE (1 << 8) 99 100 #define UTMIP_MISC_CFG0 0x824 101 #define UTMIP_DPDM_OBSERVE (1 << 26) 102 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) 103 #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf) 104 #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe) 105 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd) 106 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc) 107 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) 108 109 #define UTMIP_MISC_CFG1 0x828 110 #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18) 111 #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6) 112 113 #define UTMIP_DEBOUNCE_CFG0 0x82c 114 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) 115 116 #define UTMIP_BAT_CHRG_CFG0 0x830 117 #define UTMIP_PD_CHRG (1 << 0) 118 119 #define UTMIP_SPARE_CFG0 0x834 120 #define FUSE_SETUP_SEL (1 << 3) 121 122 #define UTMIP_XCVR_CFG1 0x838 123 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) 124 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) 125 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) 126 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) 127 128 #define UTMIP_BIAS_CFG1 0x83c 129 #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) 130 131 static DEFINE_SPINLOCK(utmip_pad_lock); 132 static int utmip_pad_count; 133 134 struct tegra_xtal_freq { 135 int freq; 136 u8 enable_delay; 137 u8 stable_count; 138 u8 active_delay; 139 u8 xtal_freq_count; 140 u16 debounce; 141 }; 142 143 static const struct tegra_xtal_freq tegra_freq_table[] = { 144 { 145 .freq = 12000000, 146 .enable_delay = 0x02, 147 .stable_count = 0x2F, 148 .active_delay = 0x04, 149 .xtal_freq_count = 0x76, 150 .debounce = 0x7530, 151 }, 152 { 153 .freq = 13000000, 154 .enable_delay = 0x02, 155 .stable_count = 0x33, 156 .active_delay = 0x05, 157 .xtal_freq_count = 0x7F, 158 .debounce = 0x7EF4, 159 }, 160 { 161 .freq = 19200000, 162 .enable_delay = 0x03, 163 .stable_count = 0x4B, 164 .active_delay = 0x06, 165 .xtal_freq_count = 0xBB, 166 .debounce = 0xBB80, 167 }, 168 { 169 .freq = 26000000, 170 .enable_delay = 0x04, 171 .stable_count = 0x66, 172 .active_delay = 0x09, 173 .xtal_freq_count = 0xFE, 174 .debounce = 0xFDE8, 175 }, 176 }; 177 178 static struct tegra_utmip_config utmip_default[] = { 179 [0] = { 180 .hssync_start_delay = 9, 181 .idle_wait_delay = 17, 182 .elastic_limit = 16, 183 .term_range_adj = 6, 184 .xcvr_setup = 9, 185 .xcvr_lsfslew = 1, 186 .xcvr_lsrslew = 1, 187 }, 188 [2] = { 189 .hssync_start_delay = 9, 190 .idle_wait_delay = 17, 191 .elastic_limit = 16, 192 .term_range_adj = 6, 193 .xcvr_setup = 9, 194 .xcvr_lsfslew = 2, 195 .xcvr_lsrslew = 2, 196 }, 197 }; 198 199 static int utmip_pad_open(struct tegra_usb_phy *phy) 200 { 201 phy->pad_clk = clk_get_sys("utmip-pad", NULL); 202 if (IS_ERR(phy->pad_clk)) { 203 pr_err("%s: can't get utmip pad clock\n", __func__); 204 return PTR_ERR(phy->pad_clk); 205 } 206 207 if (phy->is_legacy_phy) { 208 phy->pad_regs = phy->regs; 209 } else { 210 phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE); 211 if (!phy->pad_regs) { 212 pr_err("%s: can't remap usb registers\n", __func__); 213 clk_put(phy->pad_clk); 214 return -ENOMEM; 215 } 216 } 217 return 0; 218 } 219 220 static void utmip_pad_close(struct tegra_usb_phy *phy) 221 { 222 if (!phy->is_legacy_phy) 223 iounmap(phy->pad_regs); 224 clk_put(phy->pad_clk); 225 } 226 227 static void utmip_pad_power_on(struct tegra_usb_phy *phy) 228 { 229 unsigned long val, flags; 230 void __iomem *base = phy->pad_regs; 231 232 clk_prepare_enable(phy->pad_clk); 233 234 spin_lock_irqsave(&utmip_pad_lock, flags); 235 236 if (utmip_pad_count++ == 0) { 237 val = readl(base + UTMIP_BIAS_CFG0); 238 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); 239 writel(val, base + UTMIP_BIAS_CFG0); 240 } 241 242 spin_unlock_irqrestore(&utmip_pad_lock, flags); 243 244 clk_disable_unprepare(phy->pad_clk); 245 } 246 247 static int utmip_pad_power_off(struct tegra_usb_phy *phy) 248 { 249 unsigned long val, flags; 250 void __iomem *base = phy->pad_regs; 251 252 if (!utmip_pad_count) { 253 pr_err("%s: utmip pad already powered off\n", __func__); 254 return -EINVAL; 255 } 256 257 clk_prepare_enable(phy->pad_clk); 258 259 spin_lock_irqsave(&utmip_pad_lock, flags); 260 261 if (--utmip_pad_count == 0) { 262 val = readl(base + UTMIP_BIAS_CFG0); 263 val |= UTMIP_OTGPD | UTMIP_BIASPD; 264 writel(val, base + UTMIP_BIAS_CFG0); 265 } 266 267 spin_unlock_irqrestore(&utmip_pad_lock, flags); 268 269 clk_disable_unprepare(phy->pad_clk); 270 271 return 0; 272 } 273 274 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) 275 { 276 unsigned long timeout = 2000; 277 do { 278 if ((readl(reg) & mask) == result) 279 return 0; 280 udelay(1); 281 timeout--; 282 } while (timeout); 283 return -1; 284 } 285 286 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy) 287 { 288 unsigned long val; 289 void __iomem *base = phy->regs; 290 291 if (phy->is_legacy_phy) { 292 val = readl(base + USB_SUSP_CTRL); 293 val |= USB_SUSP_SET; 294 writel(val, base + USB_SUSP_CTRL); 295 296 udelay(10); 297 298 val = readl(base + USB_SUSP_CTRL); 299 val &= ~USB_SUSP_SET; 300 writel(val, base + USB_SUSP_CTRL); 301 } else 302 phy->set_phcd(&phy->u_phy, true); 303 304 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0) 305 pr_err("%s: timeout waiting for phy to stabilize\n", __func__); 306 } 307 308 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy) 309 { 310 unsigned long val; 311 void __iomem *base = phy->regs; 312 313 if (phy->is_legacy_phy) { 314 val = readl(base + USB_SUSP_CTRL); 315 val |= USB_SUSP_CLR; 316 writel(val, base + USB_SUSP_CTRL); 317 318 udelay(10); 319 320 val = readl(base + USB_SUSP_CTRL); 321 val &= ~USB_SUSP_CLR; 322 writel(val, base + USB_SUSP_CTRL); 323 } else 324 phy->set_phcd(&phy->u_phy, false); 325 326 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 327 USB_PHY_CLK_VALID)) 328 pr_err("%s: timeout waiting for phy to stabilize\n", __func__); 329 } 330 331 static int utmi_phy_power_on(struct tegra_usb_phy *phy) 332 { 333 unsigned long val; 334 void __iomem *base = phy->regs; 335 struct tegra_utmip_config *config = phy->config; 336 337 val = readl(base + USB_SUSP_CTRL); 338 val |= UTMIP_RESET; 339 writel(val, base + USB_SUSP_CTRL); 340 341 if (phy->is_legacy_phy) { 342 val = readl(base + USB1_LEGACY_CTRL); 343 val |= USB1_NO_LEGACY_MODE; 344 writel(val, base + USB1_LEGACY_CTRL); 345 } 346 347 val = readl(base + UTMIP_TX_CFG0); 348 val &= ~UTMIP_FS_PREABMLE_J; 349 writel(val, base + UTMIP_TX_CFG0); 350 351 val = readl(base + UTMIP_HSRX_CFG0); 352 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); 353 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); 354 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); 355 writel(val, base + UTMIP_HSRX_CFG0); 356 357 val = readl(base + UTMIP_HSRX_CFG1); 358 val &= ~UTMIP_HS_SYNC_START_DLY(~0); 359 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); 360 writel(val, base + UTMIP_HSRX_CFG1); 361 362 val = readl(base + UTMIP_DEBOUNCE_CFG0); 363 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); 364 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); 365 writel(val, base + UTMIP_DEBOUNCE_CFG0); 366 367 val = readl(base + UTMIP_MISC_CFG0); 368 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; 369 writel(val, base + UTMIP_MISC_CFG0); 370 371 val = readl(base + UTMIP_MISC_CFG1); 372 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0)); 373 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | 374 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count); 375 writel(val, base + UTMIP_MISC_CFG1); 376 377 val = readl(base + UTMIP_PLL_CFG1); 378 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0)); 379 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | 380 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay); 381 writel(val, base + UTMIP_PLL_CFG1); 382 383 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { 384 val = readl(base + USB_SUSP_CTRL); 385 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); 386 writel(val, base + USB_SUSP_CTRL); 387 } 388 389 utmip_pad_power_on(phy); 390 391 val = readl(base + UTMIP_XCVR_CFG0); 392 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | 393 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) | 394 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) | 395 UTMIP_XCVR_HSSLEW_MSB(~0)); 396 val |= UTMIP_XCVR_SETUP(config->xcvr_setup); 397 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); 398 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); 399 writel(val, base + UTMIP_XCVR_CFG0); 400 401 val = readl(base + UTMIP_XCVR_CFG1); 402 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | 403 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0)); 404 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); 405 writel(val, base + UTMIP_XCVR_CFG1); 406 407 val = readl(base + UTMIP_BAT_CHRG_CFG0); 408 val &= ~UTMIP_PD_CHRG; 409 writel(val, base + UTMIP_BAT_CHRG_CFG0); 410 411 val = readl(base + UTMIP_BIAS_CFG1); 412 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); 413 val |= UTMIP_BIAS_PDTRK_COUNT(0x5); 414 writel(val, base + UTMIP_BIAS_CFG1); 415 416 if (phy->is_legacy_phy) { 417 val = readl(base + UTMIP_SPARE_CFG0); 418 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) 419 val &= ~FUSE_SETUP_SEL; 420 else 421 val |= FUSE_SETUP_SEL; 422 writel(val, base + UTMIP_SPARE_CFG0); 423 } else { 424 val = readl(base + USB_SUSP_CTRL); 425 val |= UTMIP_PHY_ENABLE; 426 writel(val, base + USB_SUSP_CTRL); 427 } 428 429 val = readl(base + USB_SUSP_CTRL); 430 val &= ~UTMIP_RESET; 431 writel(val, base + USB_SUSP_CTRL); 432 433 if (phy->is_legacy_phy) { 434 val = readl(base + USB1_LEGACY_CTRL); 435 val &= ~USB1_VBUS_SENSE_CTL_MASK; 436 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; 437 writel(val, base + USB1_LEGACY_CTRL); 438 439 val = readl(base + USB_SUSP_CTRL); 440 val &= ~USB_SUSP_SET; 441 writel(val, base + USB_SUSP_CTRL); 442 } 443 444 utmi_phy_clk_enable(phy); 445 446 if (!phy->is_legacy_phy) 447 phy->set_pts(&phy->u_phy, 0); 448 449 return 0; 450 } 451 452 static int utmi_phy_power_off(struct tegra_usb_phy *phy) 453 { 454 unsigned long val; 455 void __iomem *base = phy->regs; 456 457 utmi_phy_clk_disable(phy); 458 459 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { 460 val = readl(base + USB_SUSP_CTRL); 461 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); 462 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); 463 writel(val, base + USB_SUSP_CTRL); 464 } 465 466 val = readl(base + USB_SUSP_CTRL); 467 val |= UTMIP_RESET; 468 writel(val, base + USB_SUSP_CTRL); 469 470 val = readl(base + UTMIP_BAT_CHRG_CFG0); 471 val |= UTMIP_PD_CHRG; 472 writel(val, base + UTMIP_BAT_CHRG_CFG0); 473 474 val = readl(base + UTMIP_XCVR_CFG0); 475 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | 476 UTMIP_FORCE_PDZI_POWERDOWN; 477 writel(val, base + UTMIP_XCVR_CFG0); 478 479 val = readl(base + UTMIP_XCVR_CFG1); 480 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | 481 UTMIP_FORCE_PDDR_POWERDOWN; 482 writel(val, base + UTMIP_XCVR_CFG1); 483 484 return utmip_pad_power_off(phy); 485 } 486 487 static void utmi_phy_preresume(struct tegra_usb_phy *phy) 488 { 489 unsigned long val; 490 void __iomem *base = phy->regs; 491 492 val = readl(base + UTMIP_TX_CFG0); 493 val |= UTMIP_HS_DISCON_DISABLE; 494 writel(val, base + UTMIP_TX_CFG0); 495 } 496 497 static void utmi_phy_postresume(struct tegra_usb_phy *phy) 498 { 499 unsigned long val; 500 void __iomem *base = phy->regs; 501 502 val = readl(base + UTMIP_TX_CFG0); 503 val &= ~UTMIP_HS_DISCON_DISABLE; 504 writel(val, base + UTMIP_TX_CFG0); 505 } 506 507 static void utmi_phy_restore_start(struct tegra_usb_phy *phy, 508 enum tegra_usb_phy_port_speed port_speed) 509 { 510 unsigned long val; 511 void __iomem *base = phy->regs; 512 513 val = readl(base + UTMIP_MISC_CFG0); 514 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); 515 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) 516 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; 517 else 518 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; 519 writel(val, base + UTMIP_MISC_CFG0); 520 udelay(1); 521 522 val = readl(base + UTMIP_MISC_CFG0); 523 val |= UTMIP_DPDM_OBSERVE; 524 writel(val, base + UTMIP_MISC_CFG0); 525 udelay(10); 526 } 527 528 static void utmi_phy_restore_end(struct tegra_usb_phy *phy) 529 { 530 unsigned long val; 531 void __iomem *base = phy->regs; 532 533 val = readl(base + UTMIP_MISC_CFG0); 534 val &= ~UTMIP_DPDM_OBSERVE; 535 writel(val, base + UTMIP_MISC_CFG0); 536 udelay(10); 537 } 538 539 static int ulpi_phy_power_on(struct tegra_usb_phy *phy) 540 { 541 int ret; 542 unsigned long val; 543 void __iomem *base = phy->regs; 544 struct tegra_ulpi_config *config = phy->config; 545 546 gpio_direction_output(config->reset_gpio, 0); 547 msleep(5); 548 gpio_direction_output(config->reset_gpio, 1); 549 550 clk_prepare_enable(phy->clk); 551 msleep(1); 552 553 val = readl(base + USB_SUSP_CTRL); 554 val |= UHSIC_RESET; 555 writel(val, base + USB_SUSP_CTRL); 556 557 val = readl(base + ULPI_TIMING_CTRL_0); 558 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; 559 writel(val, base + ULPI_TIMING_CTRL_0); 560 561 val = readl(base + USB_SUSP_CTRL); 562 val |= ULPI_PHY_ENABLE; 563 writel(val, base + USB_SUSP_CTRL); 564 565 val = 0; 566 writel(val, base + ULPI_TIMING_CTRL_1); 567 568 val |= ULPI_DATA_TRIMMER_SEL(4); 569 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 570 val |= ULPI_DIR_TRIMMER_SEL(4); 571 writel(val, base + ULPI_TIMING_CTRL_1); 572 udelay(10); 573 574 val |= ULPI_DATA_TRIMMER_LOAD; 575 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 576 val |= ULPI_DIR_TRIMMER_LOAD; 577 writel(val, base + ULPI_TIMING_CTRL_1); 578 579 /* Fix VbusInvalid due to floating VBUS */ 580 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08); 581 if (ret) { 582 pr_err("%s: ulpi write failed\n", __func__); 583 return ret; 584 } 585 586 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B); 587 if (ret) { 588 pr_err("%s: ulpi write failed\n", __func__); 589 return ret; 590 } 591 592 val = readl(base + USB_SUSP_CTRL); 593 val |= USB_SUSP_CLR; 594 writel(val, base + USB_SUSP_CTRL); 595 udelay(100); 596 597 val = readl(base + USB_SUSP_CTRL); 598 val &= ~USB_SUSP_CLR; 599 writel(val, base + USB_SUSP_CTRL); 600 601 return 0; 602 } 603 604 static int ulpi_phy_power_off(struct tegra_usb_phy *phy) 605 { 606 struct tegra_ulpi_config *config = phy->config; 607 608 clk_disable(phy->clk); 609 return gpio_direction_output(config->reset_gpio, 0); 610 } 611 612 static int tegra_phy_init(struct usb_phy *x) 613 { 614 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 615 struct tegra_ulpi_config *ulpi_config; 616 int err; 617 618 if (phy->is_ulpi_phy) { 619 ulpi_config = phy->config; 620 phy->clk = clk_get_sys(NULL, ulpi_config->clk); 621 if (IS_ERR(phy->clk)) { 622 pr_err("%s: can't get ulpi clock\n", __func__); 623 err = -ENXIO; 624 goto err1; 625 } 626 if (!gpio_is_valid(ulpi_config->reset_gpio)) 627 ulpi_config->reset_gpio = 628 of_get_named_gpio(phy->dev->of_node, 629 "nvidia,phy-reset-gpio", 0); 630 if (!gpio_is_valid(ulpi_config->reset_gpio)) { 631 pr_err("%s: invalid reset gpio: %d\n", __func__, 632 ulpi_config->reset_gpio); 633 err = -EINVAL; 634 goto err1; 635 } 636 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b"); 637 gpio_direction_output(ulpi_config->reset_gpio, 0); 638 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); 639 phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT; 640 } else { 641 err = utmip_pad_open(phy); 642 if (err < 0) 643 goto err1; 644 } 645 return 0; 646 err1: 647 clk_disable_unprepare(phy->pll_u); 648 clk_put(phy->pll_u); 649 return err; 650 } 651 652 static void tegra_usb_phy_close(struct usb_phy *x) 653 { 654 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 655 656 if (phy->is_ulpi_phy) 657 clk_put(phy->clk); 658 else 659 utmip_pad_close(phy); 660 clk_disable_unprepare(phy->pll_u); 661 clk_put(phy->pll_u); 662 kfree(phy); 663 } 664 665 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) 666 { 667 if (phy->is_ulpi_phy) 668 return ulpi_phy_power_on(phy); 669 else 670 return utmi_phy_power_on(phy); 671 } 672 673 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) 674 { 675 if (phy->is_ulpi_phy) 676 return ulpi_phy_power_off(phy); 677 else 678 return utmi_phy_power_off(phy); 679 } 680 681 static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend) 682 { 683 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 684 if (suspend) 685 return tegra_usb_phy_power_off(phy); 686 else 687 return tegra_usb_phy_power_on(phy); 688 } 689 690 struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance, 691 void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode, 692 void (*set_pts)(struct usb_phy *x, u8 pts_val), 693 void (*set_phcd)(struct usb_phy *x, bool enable)) 694 695 { 696 struct tegra_usb_phy *phy; 697 unsigned long parent_rate; 698 int i; 699 int err; 700 struct device_node *np = dev->of_node; 701 702 phy = kzalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL); 703 if (!phy) 704 return ERR_PTR(-ENOMEM); 705 706 phy->instance = instance; 707 phy->regs = regs; 708 phy->config = config; 709 phy->mode = phy_mode; 710 phy->dev = dev; 711 phy->is_legacy_phy = 712 of_property_read_bool(np, "nvidia,has-legacy-mode"); 713 phy->set_pts = set_pts; 714 phy->set_phcd = set_phcd; 715 err = of_property_match_string(np, "phy_type", "ulpi"); 716 if (err < 0) 717 phy->is_ulpi_phy = false; 718 else 719 phy->is_ulpi_phy = true; 720 721 if (!phy->config) { 722 if (phy->is_ulpi_phy) { 723 pr_err("%s: ulpi phy configuration missing", __func__); 724 err = -EINVAL; 725 goto err0; 726 } else { 727 phy->config = &utmip_default[instance]; 728 } 729 } 730 731 phy->pll_u = clk_get_sys(NULL, "pll_u"); 732 if (IS_ERR(phy->pll_u)) { 733 pr_err("Can't get pll_u clock\n"); 734 err = PTR_ERR(phy->pll_u); 735 goto err0; 736 } 737 clk_prepare_enable(phy->pll_u); 738 739 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); 740 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { 741 if (tegra_freq_table[i].freq == parent_rate) { 742 phy->freq = &tegra_freq_table[i]; 743 break; 744 } 745 } 746 if (!phy->freq) { 747 pr_err("invalid pll_u parent rate %ld\n", parent_rate); 748 err = -EINVAL; 749 goto err1; 750 } 751 752 phy->u_phy.init = tegra_phy_init; 753 phy->u_phy.shutdown = tegra_usb_phy_close; 754 phy->u_phy.set_suspend = tegra_usb_phy_suspend; 755 756 return phy; 757 758 err1: 759 clk_disable_unprepare(phy->pll_u); 760 clk_put(phy->pll_u); 761 err0: 762 kfree(phy); 763 return ERR_PTR(err); 764 } 765 EXPORT_SYMBOL_GPL(tegra_usb_phy_open); 766 767 void tegra_usb_phy_preresume(struct usb_phy *x) 768 { 769 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 770 771 if (!phy->is_ulpi_phy) 772 utmi_phy_preresume(phy); 773 } 774 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume); 775 776 void tegra_usb_phy_postresume(struct usb_phy *x) 777 { 778 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 779 780 if (!phy->is_ulpi_phy) 781 utmi_phy_postresume(phy); 782 } 783 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume); 784 785 void tegra_ehci_phy_restore_start(struct usb_phy *x, 786 enum tegra_usb_phy_port_speed port_speed) 787 { 788 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 789 790 if (!phy->is_ulpi_phy) 791 utmi_phy_restore_start(phy, port_speed); 792 } 793 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start); 794 795 void tegra_ehci_phy_restore_end(struct usb_phy *x) 796 { 797 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 798 799 if (!phy->is_ulpi_phy) 800 utmi_phy_restore_end(phy); 801 } 802 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end); 803 804