1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2010 Google, Inc. 4 * Copyright (C) 2013 NVIDIA Corporation 5 * 6 * Author: 7 * Erik Gilling <konkers@google.com> 8 * Benoit Goby <benoit@android.com> 9 * Venu Byravarasu <vbyravarasu@nvidia.com> 10 */ 11 12 #include <linux/resource.h> 13 #include <linux/delay.h> 14 #include <linux/slab.h> 15 #include <linux/err.h> 16 #include <linux/export.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/iopoll.h> 20 #include <linux/gpio.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/of_gpio.h> 24 #include <linux/usb/otg.h> 25 #include <linux/usb/ulpi.h> 26 #include <linux/usb/of.h> 27 #include <linux/usb/ehci_def.h> 28 #include <linux/usb/tegra_usb_phy.h> 29 #include <linux/regulator/consumer.h> 30 31 #define ULPI_VIEWPORT 0x170 32 33 /* PORTSC PTS/PHCD bits, Tegra20 only */ 34 #define TEGRA_USB_PORTSC1 0x184 35 #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30) 36 #define TEGRA_USB_PORTSC1_PHCD (1 << 23) 37 38 /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */ 39 #define TEGRA_USB_HOSTPC1_DEVLC 0x1b4 40 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29) 41 #define TEGRA_USB_HOSTPC1_DEVLC_PHCD (1 << 22) 42 43 /* Bits of PORTSC1, which will get cleared by writing 1 into them */ 44 #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) 45 46 #define USB_SUSP_CTRL 0x400 47 #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) 48 #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) 49 #define USB_SUSP_CLR (1 << 5) 50 #define USB_PHY_CLK_VALID (1 << 7) 51 #define UTMIP_RESET (1 << 11) 52 #define UHSIC_RESET (1 << 11) 53 #define UTMIP_PHY_ENABLE (1 << 12) 54 #define ULPI_PHY_ENABLE (1 << 13) 55 #define USB_SUSP_SET (1 << 14) 56 #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) 57 58 #define USB1_LEGACY_CTRL 0x410 59 #define USB1_NO_LEGACY_MODE (1 << 0) 60 #define USB1_VBUS_SENSE_CTL_MASK (3 << 1) 61 #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1) 62 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \ 63 (1 << 1) 64 #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1) 65 #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1) 66 67 #define ULPI_TIMING_CTRL_0 0x424 68 #define ULPI_OUTPUT_PINMUX_BYP (1 << 10) 69 #define ULPI_CLKOUT_PINMUX_BYP (1 << 11) 70 71 #define ULPI_TIMING_CTRL_1 0x428 72 #define ULPI_DATA_TRIMMER_LOAD (1 << 0) 73 #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) 74 #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) 75 #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) 76 #define ULPI_DIR_TRIMMER_LOAD (1 << 24) 77 #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) 78 79 #define UTMIP_PLL_CFG1 0x804 80 #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 81 #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) 82 83 #define UTMIP_XCVR_CFG0 0x808 84 #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) 85 #define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) 86 #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) 87 #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) 88 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) 89 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) 90 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) 91 #define UTMIP_XCVR_LSBIAS_SEL (1 << 21) 92 #define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4) 93 #define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25) 94 95 #define UTMIP_BIAS_CFG0 0x80c 96 #define UTMIP_OTGPD (1 << 11) 97 #define UTMIP_BIASPD (1 << 10) 98 #define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0) 99 #define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2) 100 #define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24) 101 102 #define UTMIP_HSRX_CFG0 0x810 103 #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) 104 #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) 105 106 #define UTMIP_HSRX_CFG1 0x814 107 #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) 108 109 #define UTMIP_TX_CFG0 0x820 110 #define UTMIP_FS_PREABMLE_J (1 << 19) 111 #define UTMIP_HS_DISCON_DISABLE (1 << 8) 112 113 #define UTMIP_MISC_CFG0 0x824 114 #define UTMIP_DPDM_OBSERVE (1 << 26) 115 #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) 116 #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf) 117 #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe) 118 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd) 119 #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc) 120 #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) 121 122 #define UTMIP_MISC_CFG1 0x828 123 #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18) 124 #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6) 125 126 #define UTMIP_DEBOUNCE_CFG0 0x82c 127 #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) 128 129 #define UTMIP_BAT_CHRG_CFG0 0x830 130 #define UTMIP_PD_CHRG (1 << 0) 131 132 #define UTMIP_SPARE_CFG0 0x834 133 #define FUSE_SETUP_SEL (1 << 3) 134 135 #define UTMIP_XCVR_CFG1 0x838 136 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) 137 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) 138 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) 139 #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) 140 141 #define UTMIP_BIAS_CFG1 0x83c 142 #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) 143 144 /* For Tegra30 and above only, the address is different in Tegra20 */ 145 #define USB_USBMODE 0x1f8 146 #define USB_USBMODE_MASK (3 << 0) 147 #define USB_USBMODE_HOST (3 << 0) 148 #define USB_USBMODE_DEVICE (2 << 0) 149 150 static DEFINE_SPINLOCK(utmip_pad_lock); 151 static int utmip_pad_count; 152 153 struct tegra_xtal_freq { 154 int freq; 155 u8 enable_delay; 156 u8 stable_count; 157 u8 active_delay; 158 u8 xtal_freq_count; 159 u16 debounce; 160 }; 161 162 static const struct tegra_xtal_freq tegra_freq_table[] = { 163 { 164 .freq = 12000000, 165 .enable_delay = 0x02, 166 .stable_count = 0x2F, 167 .active_delay = 0x04, 168 .xtal_freq_count = 0x76, 169 .debounce = 0x7530, 170 }, 171 { 172 .freq = 13000000, 173 .enable_delay = 0x02, 174 .stable_count = 0x33, 175 .active_delay = 0x05, 176 .xtal_freq_count = 0x7F, 177 .debounce = 0x7EF4, 178 }, 179 { 180 .freq = 19200000, 181 .enable_delay = 0x03, 182 .stable_count = 0x4B, 183 .active_delay = 0x06, 184 .xtal_freq_count = 0xBB, 185 .debounce = 0xBB80, 186 }, 187 { 188 .freq = 26000000, 189 .enable_delay = 0x04, 190 .stable_count = 0x66, 191 .active_delay = 0x09, 192 .xtal_freq_count = 0xFE, 193 .debounce = 0xFDE8, 194 }, 195 }; 196 197 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val) 198 { 199 void __iomem *base = phy->regs; 200 unsigned long val; 201 202 if (phy->soc_config->has_hostpc) { 203 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); 204 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); 205 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); 206 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); 207 } else { 208 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; 209 val &= ~TEGRA_USB_PORTSC1_PTS(~0); 210 val |= TEGRA_USB_PORTSC1_PTS(pts_val); 211 writel(val, base + TEGRA_USB_PORTSC1); 212 } 213 } 214 215 static void set_phcd(struct tegra_usb_phy *phy, bool enable) 216 { 217 void __iomem *base = phy->regs; 218 unsigned long val; 219 220 if (phy->soc_config->has_hostpc) { 221 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); 222 if (enable) 223 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD; 224 else 225 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD; 226 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); 227 } else { 228 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; 229 if (enable) 230 val |= TEGRA_USB_PORTSC1_PHCD; 231 else 232 val &= ~TEGRA_USB_PORTSC1_PHCD; 233 writel(val, base + TEGRA_USB_PORTSC1); 234 } 235 } 236 237 static int utmip_pad_open(struct tegra_usb_phy *phy) 238 { 239 phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads"); 240 if (IS_ERR(phy->pad_clk)) { 241 pr_err("%s: can't get utmip pad clock\n", __func__); 242 return PTR_ERR(phy->pad_clk); 243 } 244 245 return 0; 246 } 247 248 static void utmip_pad_power_on(struct tegra_usb_phy *phy) 249 { 250 unsigned long val, flags; 251 void __iomem *base = phy->pad_regs; 252 struct tegra_utmip_config *config = phy->config; 253 254 clk_prepare_enable(phy->pad_clk); 255 256 spin_lock_irqsave(&utmip_pad_lock, flags); 257 258 if (utmip_pad_count++ == 0) { 259 val = readl(base + UTMIP_BIAS_CFG0); 260 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); 261 262 if (phy->soc_config->requires_extra_tuning_parameters) { 263 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | 264 UTMIP_HSDISCON_LEVEL(~0) | 265 UTMIP_HSDISCON_LEVEL_MSB(~0)); 266 267 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level); 268 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level); 269 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level); 270 } 271 writel(val, base + UTMIP_BIAS_CFG0); 272 } 273 274 spin_unlock_irqrestore(&utmip_pad_lock, flags); 275 276 clk_disable_unprepare(phy->pad_clk); 277 } 278 279 static int utmip_pad_power_off(struct tegra_usb_phy *phy) 280 { 281 unsigned long val, flags; 282 void __iomem *base = phy->pad_regs; 283 284 if (!utmip_pad_count) { 285 pr_err("%s: utmip pad already powered off\n", __func__); 286 return -EINVAL; 287 } 288 289 clk_prepare_enable(phy->pad_clk); 290 291 spin_lock_irqsave(&utmip_pad_lock, flags); 292 293 if (--utmip_pad_count == 0) { 294 val = readl(base + UTMIP_BIAS_CFG0); 295 val |= UTMIP_OTGPD | UTMIP_BIASPD; 296 writel(val, base + UTMIP_BIAS_CFG0); 297 } 298 299 spin_unlock_irqrestore(&utmip_pad_lock, flags); 300 301 clk_disable_unprepare(phy->pad_clk); 302 303 return 0; 304 } 305 306 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) 307 { 308 u32 tmp; 309 310 return readl_poll_timeout(reg, tmp, (tmp & mask) == result, 311 2000, 6000); 312 } 313 314 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy) 315 { 316 unsigned long val; 317 void __iomem *base = phy->regs; 318 319 /* 320 * The USB driver may have already initiated the phy clock 321 * disable so wait to see if the clock turns off and if not 322 * then proceed with gating the clock. 323 */ 324 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0) 325 return; 326 327 if (phy->is_legacy_phy) { 328 val = readl(base + USB_SUSP_CTRL); 329 val |= USB_SUSP_SET; 330 writel(val, base + USB_SUSP_CTRL); 331 332 udelay(10); 333 334 val = readl(base + USB_SUSP_CTRL); 335 val &= ~USB_SUSP_SET; 336 writel(val, base + USB_SUSP_CTRL); 337 } else 338 set_phcd(phy, true); 339 340 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0) 341 pr_err("%s: timeout waiting for phy to stabilize\n", __func__); 342 } 343 344 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy) 345 { 346 unsigned long val; 347 void __iomem *base = phy->regs; 348 349 /* 350 * The USB driver may have already initiated the phy clock 351 * enable so wait to see if the clock turns on and if not 352 * then proceed with ungating the clock. 353 */ 354 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 355 USB_PHY_CLK_VALID) == 0) 356 return; 357 358 if (phy->is_legacy_phy) { 359 val = readl(base + USB_SUSP_CTRL); 360 val |= USB_SUSP_CLR; 361 writel(val, base + USB_SUSP_CTRL); 362 363 udelay(10); 364 365 val = readl(base + USB_SUSP_CTRL); 366 val &= ~USB_SUSP_CLR; 367 writel(val, base + USB_SUSP_CTRL); 368 } else 369 set_phcd(phy, false); 370 371 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 372 USB_PHY_CLK_VALID)) 373 pr_err("%s: timeout waiting for phy to stabilize\n", __func__); 374 } 375 376 static int utmi_phy_power_on(struct tegra_usb_phy *phy) 377 { 378 unsigned long val; 379 void __iomem *base = phy->regs; 380 struct tegra_utmip_config *config = phy->config; 381 382 val = readl(base + USB_SUSP_CTRL); 383 val |= UTMIP_RESET; 384 writel(val, base + USB_SUSP_CTRL); 385 386 if (phy->is_legacy_phy) { 387 val = readl(base + USB1_LEGACY_CTRL); 388 val |= USB1_NO_LEGACY_MODE; 389 writel(val, base + USB1_LEGACY_CTRL); 390 } 391 392 val = readl(base + UTMIP_TX_CFG0); 393 val |= UTMIP_FS_PREABMLE_J; 394 writel(val, base + UTMIP_TX_CFG0); 395 396 val = readl(base + UTMIP_HSRX_CFG0); 397 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); 398 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); 399 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); 400 writel(val, base + UTMIP_HSRX_CFG0); 401 402 val = readl(base + UTMIP_HSRX_CFG1); 403 val &= ~UTMIP_HS_SYNC_START_DLY(~0); 404 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); 405 writel(val, base + UTMIP_HSRX_CFG1); 406 407 val = readl(base + UTMIP_DEBOUNCE_CFG0); 408 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); 409 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); 410 writel(val, base + UTMIP_DEBOUNCE_CFG0); 411 412 val = readl(base + UTMIP_MISC_CFG0); 413 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; 414 writel(val, base + UTMIP_MISC_CFG0); 415 416 if (!phy->soc_config->utmi_pll_config_in_car_module) { 417 val = readl(base + UTMIP_MISC_CFG1); 418 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | 419 UTMIP_PLLU_STABLE_COUNT(~0)); 420 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | 421 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count); 422 writel(val, base + UTMIP_MISC_CFG1); 423 424 val = readl(base + UTMIP_PLL_CFG1); 425 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | 426 UTMIP_PLLU_ENABLE_DLY_COUNT(~0)); 427 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | 428 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay); 429 writel(val, base + UTMIP_PLL_CFG1); 430 } 431 432 if (phy->mode == USB_DR_MODE_PERIPHERAL) { 433 val = readl(base + USB_SUSP_CTRL); 434 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); 435 writel(val, base + USB_SUSP_CTRL); 436 437 val = readl(base + UTMIP_BAT_CHRG_CFG0); 438 val &= ~UTMIP_PD_CHRG; 439 writel(val, base + UTMIP_BAT_CHRG_CFG0); 440 } else { 441 val = readl(base + UTMIP_BAT_CHRG_CFG0); 442 val |= UTMIP_PD_CHRG; 443 writel(val, base + UTMIP_BAT_CHRG_CFG0); 444 } 445 446 utmip_pad_power_on(phy); 447 448 val = readl(base + UTMIP_XCVR_CFG0); 449 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | 450 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL | 451 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) | 452 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0)); 453 454 if (!config->xcvr_setup_use_fuses) { 455 val |= UTMIP_XCVR_SETUP(config->xcvr_setup); 456 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup); 457 } 458 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); 459 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); 460 461 if (phy->soc_config->requires_extra_tuning_parameters) { 462 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0)); 463 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew); 464 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew); 465 } 466 writel(val, base + UTMIP_XCVR_CFG0); 467 468 val = readl(base + UTMIP_XCVR_CFG1); 469 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | 470 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0)); 471 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); 472 writel(val, base + UTMIP_XCVR_CFG1); 473 474 val = readl(base + UTMIP_BIAS_CFG1); 475 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); 476 val |= UTMIP_BIAS_PDTRK_COUNT(0x5); 477 writel(val, base + UTMIP_BIAS_CFG1); 478 479 val = readl(base + UTMIP_SPARE_CFG0); 480 if (config->xcvr_setup_use_fuses) 481 val |= FUSE_SETUP_SEL; 482 else 483 val &= ~FUSE_SETUP_SEL; 484 writel(val, base + UTMIP_SPARE_CFG0); 485 486 if (!phy->is_legacy_phy) { 487 val = readl(base + USB_SUSP_CTRL); 488 val |= UTMIP_PHY_ENABLE; 489 writel(val, base + USB_SUSP_CTRL); 490 } 491 492 val = readl(base + USB_SUSP_CTRL); 493 val &= ~UTMIP_RESET; 494 writel(val, base + USB_SUSP_CTRL); 495 496 if (phy->is_legacy_phy) { 497 val = readl(base + USB1_LEGACY_CTRL); 498 val &= ~USB1_VBUS_SENSE_CTL_MASK; 499 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; 500 writel(val, base + USB1_LEGACY_CTRL); 501 502 val = readl(base + USB_SUSP_CTRL); 503 val &= ~USB_SUSP_SET; 504 writel(val, base + USB_SUSP_CTRL); 505 } 506 507 utmi_phy_clk_enable(phy); 508 509 if (phy->soc_config->requires_usbmode_setup) { 510 val = readl(base + USB_USBMODE); 511 val &= ~USB_USBMODE_MASK; 512 if (phy->mode == USB_DR_MODE_HOST) 513 val |= USB_USBMODE_HOST; 514 else 515 val |= USB_USBMODE_DEVICE; 516 writel(val, base + USB_USBMODE); 517 } 518 519 if (!phy->is_legacy_phy) 520 set_pts(phy, 0); 521 522 return 0; 523 } 524 525 static int utmi_phy_power_off(struct tegra_usb_phy *phy) 526 { 527 unsigned long val; 528 void __iomem *base = phy->regs; 529 530 utmi_phy_clk_disable(phy); 531 532 if (phy->mode == USB_DR_MODE_PERIPHERAL) { 533 val = readl(base + USB_SUSP_CTRL); 534 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); 535 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); 536 writel(val, base + USB_SUSP_CTRL); 537 } 538 539 val = readl(base + USB_SUSP_CTRL); 540 val |= UTMIP_RESET; 541 writel(val, base + USB_SUSP_CTRL); 542 543 val = readl(base + UTMIP_BAT_CHRG_CFG0); 544 val |= UTMIP_PD_CHRG; 545 writel(val, base + UTMIP_BAT_CHRG_CFG0); 546 547 val = readl(base + UTMIP_XCVR_CFG0); 548 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | 549 UTMIP_FORCE_PDZI_POWERDOWN; 550 writel(val, base + UTMIP_XCVR_CFG0); 551 552 val = readl(base + UTMIP_XCVR_CFG1); 553 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | 554 UTMIP_FORCE_PDDR_POWERDOWN; 555 writel(val, base + UTMIP_XCVR_CFG1); 556 557 return utmip_pad_power_off(phy); 558 } 559 560 static void utmi_phy_preresume(struct tegra_usb_phy *phy) 561 { 562 unsigned long val; 563 void __iomem *base = phy->regs; 564 565 val = readl(base + UTMIP_TX_CFG0); 566 val |= UTMIP_HS_DISCON_DISABLE; 567 writel(val, base + UTMIP_TX_CFG0); 568 } 569 570 static void utmi_phy_postresume(struct tegra_usb_phy *phy) 571 { 572 unsigned long val; 573 void __iomem *base = phy->regs; 574 575 val = readl(base + UTMIP_TX_CFG0); 576 val &= ~UTMIP_HS_DISCON_DISABLE; 577 writel(val, base + UTMIP_TX_CFG0); 578 } 579 580 static void utmi_phy_restore_start(struct tegra_usb_phy *phy, 581 enum tegra_usb_phy_port_speed port_speed) 582 { 583 unsigned long val; 584 void __iomem *base = phy->regs; 585 586 val = readl(base + UTMIP_MISC_CFG0); 587 val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); 588 if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) 589 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; 590 else 591 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; 592 writel(val, base + UTMIP_MISC_CFG0); 593 udelay(1); 594 595 val = readl(base + UTMIP_MISC_CFG0); 596 val |= UTMIP_DPDM_OBSERVE; 597 writel(val, base + UTMIP_MISC_CFG0); 598 udelay(10); 599 } 600 601 static void utmi_phy_restore_end(struct tegra_usb_phy *phy) 602 { 603 unsigned long val; 604 void __iomem *base = phy->regs; 605 606 val = readl(base + UTMIP_MISC_CFG0); 607 val &= ~UTMIP_DPDM_OBSERVE; 608 writel(val, base + UTMIP_MISC_CFG0); 609 udelay(10); 610 } 611 612 static int ulpi_phy_power_on(struct tegra_usb_phy *phy) 613 { 614 int ret; 615 unsigned long val; 616 void __iomem *base = phy->regs; 617 618 ret = gpio_direction_output(phy->reset_gpio, 0); 619 if (ret < 0) { 620 dev_err(phy->u_phy.dev, "gpio %d not set to 0\n", 621 phy->reset_gpio); 622 return ret; 623 } 624 msleep(5); 625 ret = gpio_direction_output(phy->reset_gpio, 1); 626 if (ret < 0) { 627 dev_err(phy->u_phy.dev, "gpio %d not set to 1\n", 628 phy->reset_gpio); 629 return ret; 630 } 631 632 clk_prepare_enable(phy->clk); 633 msleep(1); 634 635 val = readl(base + USB_SUSP_CTRL); 636 val |= UHSIC_RESET; 637 writel(val, base + USB_SUSP_CTRL); 638 639 val = readl(base + ULPI_TIMING_CTRL_0); 640 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; 641 writel(val, base + ULPI_TIMING_CTRL_0); 642 643 val = readl(base + USB_SUSP_CTRL); 644 val |= ULPI_PHY_ENABLE; 645 writel(val, base + USB_SUSP_CTRL); 646 647 val = 0; 648 writel(val, base + ULPI_TIMING_CTRL_1); 649 650 val |= ULPI_DATA_TRIMMER_SEL(4); 651 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); 652 val |= ULPI_DIR_TRIMMER_SEL(4); 653 writel(val, base + ULPI_TIMING_CTRL_1); 654 udelay(10); 655 656 val |= ULPI_DATA_TRIMMER_LOAD; 657 val |= ULPI_STPDIRNXT_TRIMMER_LOAD; 658 val |= ULPI_DIR_TRIMMER_LOAD; 659 writel(val, base + ULPI_TIMING_CTRL_1); 660 661 /* Fix VbusInvalid due to floating VBUS */ 662 ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08); 663 if (ret) { 664 pr_err("%s: ulpi write failed\n", __func__); 665 return ret; 666 } 667 668 ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B); 669 if (ret) { 670 pr_err("%s: ulpi write failed\n", __func__); 671 return ret; 672 } 673 674 val = readl(base + USB_SUSP_CTRL); 675 val |= USB_SUSP_CLR; 676 writel(val, base + USB_SUSP_CTRL); 677 udelay(100); 678 679 val = readl(base + USB_SUSP_CTRL); 680 val &= ~USB_SUSP_CLR; 681 writel(val, base + USB_SUSP_CTRL); 682 683 return 0; 684 } 685 686 static int ulpi_phy_power_off(struct tegra_usb_phy *phy) 687 { 688 clk_disable(phy->clk); 689 return gpio_direction_output(phy->reset_gpio, 0); 690 } 691 692 static void tegra_usb_phy_close(struct tegra_usb_phy *phy) 693 { 694 if (!IS_ERR(phy->vbus)) 695 regulator_disable(phy->vbus); 696 697 clk_disable_unprepare(phy->pll_u); 698 } 699 700 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) 701 { 702 if (phy->is_ulpi_phy) 703 return ulpi_phy_power_on(phy); 704 else 705 return utmi_phy_power_on(phy); 706 } 707 708 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) 709 { 710 if (phy->is_ulpi_phy) 711 return ulpi_phy_power_off(phy); 712 else 713 return utmi_phy_power_off(phy); 714 } 715 716 static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend) 717 { 718 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 719 if (suspend) 720 return tegra_usb_phy_power_off(phy); 721 else 722 return tegra_usb_phy_power_on(phy); 723 } 724 725 static int ulpi_open(struct tegra_usb_phy *phy) 726 { 727 int err; 728 729 phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link"); 730 if (IS_ERR(phy->clk)) { 731 pr_err("%s: can't get ulpi clock\n", __func__); 732 return PTR_ERR(phy->clk); 733 } 734 735 err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio, 736 "ulpi_phy_reset_b"); 737 if (err < 0) { 738 dev_err(phy->u_phy.dev, "request failed for gpio: %d\n", 739 phy->reset_gpio); 740 return err; 741 } 742 743 err = gpio_direction_output(phy->reset_gpio, 0); 744 if (err < 0) { 745 dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n", 746 phy->reset_gpio); 747 return err; 748 } 749 750 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); 751 if (!phy->ulpi) { 752 dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n"); 753 err = -ENOMEM; 754 return err; 755 } 756 757 phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT; 758 return 0; 759 } 760 761 static int tegra_usb_phy_init(struct tegra_usb_phy *phy) 762 { 763 unsigned long parent_rate; 764 int i; 765 int err; 766 767 phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u"); 768 if (IS_ERR(phy->pll_u)) { 769 pr_err("Can't get pll_u clock\n"); 770 return PTR_ERR(phy->pll_u); 771 } 772 773 err = clk_prepare_enable(phy->pll_u); 774 if (err) 775 return err; 776 777 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); 778 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { 779 if (tegra_freq_table[i].freq == parent_rate) { 780 phy->freq = &tegra_freq_table[i]; 781 break; 782 } 783 } 784 if (!phy->freq) { 785 pr_err("invalid pll_u parent rate %ld\n", parent_rate); 786 err = -EINVAL; 787 goto fail; 788 } 789 790 if (!IS_ERR(phy->vbus)) { 791 err = regulator_enable(phy->vbus); 792 if (err) { 793 dev_err(phy->u_phy.dev, 794 "failed to enable usb vbus regulator: %d\n", 795 err); 796 goto fail; 797 } 798 } 799 800 if (phy->is_ulpi_phy) 801 err = ulpi_open(phy); 802 else 803 err = utmip_pad_open(phy); 804 if (err < 0) 805 goto fail; 806 807 return 0; 808 809 fail: 810 clk_disable_unprepare(phy->pll_u); 811 return err; 812 } 813 814 void tegra_usb_phy_preresume(struct usb_phy *x) 815 { 816 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 817 818 if (!phy->is_ulpi_phy) 819 utmi_phy_preresume(phy); 820 } 821 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume); 822 823 void tegra_usb_phy_postresume(struct usb_phy *x) 824 { 825 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 826 827 if (!phy->is_ulpi_phy) 828 utmi_phy_postresume(phy); 829 } 830 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume); 831 832 void tegra_ehci_phy_restore_start(struct usb_phy *x, 833 enum tegra_usb_phy_port_speed port_speed) 834 { 835 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 836 837 if (!phy->is_ulpi_phy) 838 utmi_phy_restore_start(phy, port_speed); 839 } 840 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start); 841 842 void tegra_ehci_phy_restore_end(struct usb_phy *x) 843 { 844 struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); 845 846 if (!phy->is_ulpi_phy) 847 utmi_phy_restore_end(phy); 848 } 849 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end); 850 851 static int read_utmi_param(struct platform_device *pdev, const char *param, 852 u8 *dest) 853 { 854 u32 value; 855 int err = of_property_read_u32(pdev->dev.of_node, param, &value); 856 *dest = (u8)value; 857 if (err < 0) 858 dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n", 859 param, err); 860 return err; 861 } 862 863 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy, 864 struct platform_device *pdev) 865 { 866 struct resource *res; 867 int err; 868 struct tegra_utmip_config *config; 869 870 tegra_phy->is_ulpi_phy = false; 871 872 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 873 if (!res) { 874 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n"); 875 return -ENXIO; 876 } 877 878 tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start, 879 resource_size(res)); 880 if (!tegra_phy->pad_regs) { 881 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n"); 882 return -ENOMEM; 883 } 884 885 tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config), 886 GFP_KERNEL); 887 if (!tegra_phy->config) 888 return -ENOMEM; 889 890 config = tegra_phy->config; 891 892 err = read_utmi_param(pdev, "nvidia,hssync-start-delay", 893 &config->hssync_start_delay); 894 if (err < 0) 895 return err; 896 897 err = read_utmi_param(pdev, "nvidia,elastic-limit", 898 &config->elastic_limit); 899 if (err < 0) 900 return err; 901 902 err = read_utmi_param(pdev, "nvidia,idle-wait-delay", 903 &config->idle_wait_delay); 904 if (err < 0) 905 return err; 906 907 err = read_utmi_param(pdev, "nvidia,term-range-adj", 908 &config->term_range_adj); 909 if (err < 0) 910 return err; 911 912 err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew", 913 &config->xcvr_lsfslew); 914 if (err < 0) 915 return err; 916 917 err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew", 918 &config->xcvr_lsrslew); 919 if (err < 0) 920 return err; 921 922 if (tegra_phy->soc_config->requires_extra_tuning_parameters) { 923 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew", 924 &config->xcvr_hsslew); 925 if (err < 0) 926 return err; 927 928 err = read_utmi_param(pdev, "nvidia,hssquelch-level", 929 &config->hssquelch_level); 930 if (err < 0) 931 return err; 932 933 err = read_utmi_param(pdev, "nvidia,hsdiscon-level", 934 &config->hsdiscon_level); 935 if (err < 0) 936 return err; 937 } 938 939 config->xcvr_setup_use_fuses = of_property_read_bool( 940 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses"); 941 942 if (!config->xcvr_setup_use_fuses) { 943 err = read_utmi_param(pdev, "nvidia,xcvr-setup", 944 &config->xcvr_setup); 945 if (err < 0) 946 return err; 947 } 948 949 return 0; 950 } 951 952 static const struct tegra_phy_soc_config tegra20_soc_config = { 953 .utmi_pll_config_in_car_module = false, 954 .has_hostpc = false, 955 .requires_usbmode_setup = false, 956 .requires_extra_tuning_parameters = false, 957 }; 958 959 static const struct tegra_phy_soc_config tegra30_soc_config = { 960 .utmi_pll_config_in_car_module = true, 961 .has_hostpc = true, 962 .requires_usbmode_setup = true, 963 .requires_extra_tuning_parameters = true, 964 }; 965 966 static const struct of_device_id tegra_usb_phy_id_table[] = { 967 { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config }, 968 { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config }, 969 { }, 970 }; 971 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table); 972 973 static int tegra_usb_phy_probe(struct platform_device *pdev) 974 { 975 const struct of_device_id *match; 976 struct resource *res; 977 struct tegra_usb_phy *tegra_phy = NULL; 978 struct device_node *np = pdev->dev.of_node; 979 enum usb_phy_interface phy_type; 980 int err; 981 982 tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL); 983 if (!tegra_phy) 984 return -ENOMEM; 985 986 match = of_match_device(tegra_usb_phy_id_table, &pdev->dev); 987 if (!match) { 988 dev_err(&pdev->dev, "Error: No device match found\n"); 989 return -ENODEV; 990 } 991 tegra_phy->soc_config = match->data; 992 993 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 994 if (!res) { 995 dev_err(&pdev->dev, "Failed to get I/O memory\n"); 996 return -ENXIO; 997 } 998 999 tegra_phy->regs = devm_ioremap(&pdev->dev, res->start, 1000 resource_size(res)); 1001 if (!tegra_phy->regs) { 1002 dev_err(&pdev->dev, "Failed to remap I/O memory\n"); 1003 return -ENOMEM; 1004 } 1005 1006 tegra_phy->is_legacy_phy = 1007 of_property_read_bool(np, "nvidia,has-legacy-mode"); 1008 1009 phy_type = of_usb_get_phy_mode(np); 1010 switch (phy_type) { 1011 case USBPHY_INTERFACE_MODE_UTMI: 1012 err = utmi_phy_probe(tegra_phy, pdev); 1013 if (err < 0) 1014 return err; 1015 break; 1016 1017 case USBPHY_INTERFACE_MODE_ULPI: 1018 tegra_phy->is_ulpi_phy = true; 1019 1020 tegra_phy->reset_gpio = 1021 of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0); 1022 if (!gpio_is_valid(tegra_phy->reset_gpio)) { 1023 dev_err(&pdev->dev, "invalid gpio: %d\n", 1024 tegra_phy->reset_gpio); 1025 return tegra_phy->reset_gpio; 1026 } 1027 tegra_phy->config = NULL; 1028 break; 1029 1030 default: 1031 dev_err(&pdev->dev, "phy_type is invalid or unsupported\n"); 1032 return -EINVAL; 1033 } 1034 1035 if (of_find_property(np, "dr_mode", NULL)) 1036 tegra_phy->mode = usb_get_dr_mode(&pdev->dev); 1037 else 1038 tegra_phy->mode = USB_DR_MODE_HOST; 1039 1040 if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) { 1041 dev_err(&pdev->dev, "dr_mode is invalid\n"); 1042 return -EINVAL; 1043 } 1044 1045 /* On some boards, the VBUS regulator doesn't need to be controlled */ 1046 if (of_find_property(np, "vbus-supply", NULL)) { 1047 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus"); 1048 if (IS_ERR(tegra_phy->vbus)) 1049 return PTR_ERR(tegra_phy->vbus); 1050 } else { 1051 dev_notice(&pdev->dev, "no vbus regulator"); 1052 tegra_phy->vbus = ERR_PTR(-ENODEV); 1053 } 1054 1055 tegra_phy->u_phy.dev = &pdev->dev; 1056 err = tegra_usb_phy_init(tegra_phy); 1057 if (err < 0) 1058 return err; 1059 1060 tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend; 1061 1062 platform_set_drvdata(pdev, tegra_phy); 1063 1064 err = usb_add_phy_dev(&tegra_phy->u_phy); 1065 if (err < 0) { 1066 tegra_usb_phy_close(tegra_phy); 1067 return err; 1068 } 1069 1070 return 0; 1071 } 1072 1073 static int tegra_usb_phy_remove(struct platform_device *pdev) 1074 { 1075 struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev); 1076 1077 usb_remove_phy(&tegra_phy->u_phy); 1078 tegra_usb_phy_close(tegra_phy); 1079 1080 return 0; 1081 } 1082 1083 static struct platform_driver tegra_usb_phy_driver = { 1084 .probe = tegra_usb_phy_probe, 1085 .remove = tegra_usb_phy_remove, 1086 .driver = { 1087 .name = "tegra-phy", 1088 .of_match_table = tegra_usb_phy_id_table, 1089 }, 1090 }; 1091 module_platform_driver(tegra_usb_phy_driver); 1092 1093 MODULE_DESCRIPTION("Tegra USB PHY driver"); 1094 MODULE_LICENSE("GPL v2"); 1095