1 /* 2 * Copyright 2012-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2012 Marek Vasut <marex@denx.de> 4 * on behalf of DENX Software Engineering GmbH 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 * http://www.opensource.org/licenses/gpl-license.html 11 * http://www.gnu.org/copyleft/gpl.html 12 */ 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/platform_device.h> 17 #include <linux/clk.h> 18 #include <linux/usb/otg.h> 19 #include <linux/stmp_device.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/io.h> 23 #include <linux/of_device.h> 24 #include <linux/regmap.h> 25 #include <linux/mfd/syscon.h> 26 27 #define DRIVER_NAME "mxs_phy" 28 29 #define HW_USBPHY_PWD 0x00 30 #define HW_USBPHY_CTRL 0x30 31 #define HW_USBPHY_CTRL_SET 0x34 32 #define HW_USBPHY_CTRL_CLR 0x38 33 34 #define BM_USBPHY_CTRL_SFTRST BIT(31) 35 #define BM_USBPHY_CTRL_CLKGATE BIT(30) 36 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26) 37 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25) 38 #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20) 39 #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19) 40 #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18) 41 #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15) 42 #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14) 43 #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1) 44 45 #define to_mxs_phy(p) container_of((p), struct mxs_phy, phy) 46 47 /* Do disconnection between PHY and controller without vbus */ 48 #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0) 49 50 /* 51 * The PHY will be in messy if there is a wakeup after putting 52 * bus to suspend (set portsc.suspendM) but before setting PHY to low 53 * power mode (set portsc.phcd). 54 */ 55 #define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1) 56 57 /* 58 * The SOF sends too fast after resuming, it will cause disconnection 59 * between host and high speed device. 60 */ 61 #define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2) 62 63 struct mxs_phy_data { 64 unsigned int flags; 65 }; 66 67 static const struct mxs_phy_data imx23_phy_data = { 68 .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST, 69 }; 70 71 static const struct mxs_phy_data imx6q_phy_data = { 72 .flags = MXS_PHY_SENDING_SOF_TOO_FAST | 73 MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS, 74 }; 75 76 static const struct mxs_phy_data imx6sl_phy_data = { 77 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS, 78 }; 79 80 static const struct of_device_id mxs_phy_dt_ids[] = { 81 { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, }, 82 { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, }, 83 { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, }, 84 { /* sentinel */ } 85 }; 86 MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids); 87 88 struct mxs_phy { 89 struct usb_phy phy; 90 struct clk *clk; 91 const struct mxs_phy_data *data; 92 struct regmap *regmap_anatop; 93 }; 94 95 static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) 96 { 97 int ret; 98 void __iomem *base = mxs_phy->phy.io_priv; 99 100 ret = stmp_reset_block(base + HW_USBPHY_CTRL); 101 if (ret) 102 return ret; 103 104 /* Power up the PHY */ 105 writel(0, base + HW_USBPHY_PWD); 106 107 /* 108 * USB PHY Ctrl Setting 109 * - Auto clock/power on 110 * - Enable full/low speed support 111 */ 112 writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | 113 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | 114 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | 115 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | 116 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL | 117 BM_USBPHY_CTRL_ENUTMILEVEL2 | 118 BM_USBPHY_CTRL_ENUTMILEVEL3, 119 base + HW_USBPHY_CTRL_SET); 120 121 return 0; 122 } 123 124 static int mxs_phy_init(struct usb_phy *phy) 125 { 126 int ret; 127 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 128 129 ret = clk_prepare_enable(mxs_phy->clk); 130 if (ret) 131 return ret; 132 133 return mxs_phy_hw_init(mxs_phy); 134 } 135 136 static void mxs_phy_shutdown(struct usb_phy *phy) 137 { 138 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 139 140 writel(BM_USBPHY_CTRL_CLKGATE, 141 phy->io_priv + HW_USBPHY_CTRL_SET); 142 143 clk_disable_unprepare(mxs_phy->clk); 144 } 145 146 static int mxs_phy_suspend(struct usb_phy *x, int suspend) 147 { 148 int ret; 149 struct mxs_phy *mxs_phy = to_mxs_phy(x); 150 151 if (suspend) { 152 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD); 153 writel(BM_USBPHY_CTRL_CLKGATE, 154 x->io_priv + HW_USBPHY_CTRL_SET); 155 clk_disable_unprepare(mxs_phy->clk); 156 } else { 157 ret = clk_prepare_enable(mxs_phy->clk); 158 if (ret) 159 return ret; 160 writel(BM_USBPHY_CTRL_CLKGATE, 161 x->io_priv + HW_USBPHY_CTRL_CLR); 162 writel(0, x->io_priv + HW_USBPHY_PWD); 163 } 164 165 return 0; 166 } 167 168 static int mxs_phy_on_connect(struct usb_phy *phy, 169 enum usb_device_speed speed) 170 { 171 dev_dbg(phy->dev, "%s device has connected\n", 172 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); 173 174 if (speed == USB_SPEED_HIGH) 175 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, 176 phy->io_priv + HW_USBPHY_CTRL_SET); 177 178 return 0; 179 } 180 181 static int mxs_phy_on_disconnect(struct usb_phy *phy, 182 enum usb_device_speed speed) 183 { 184 dev_dbg(phy->dev, "%s device has disconnected\n", 185 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); 186 187 if (speed == USB_SPEED_HIGH) 188 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, 189 phy->io_priv + HW_USBPHY_CTRL_CLR); 190 191 return 0; 192 } 193 194 static int mxs_phy_probe(struct platform_device *pdev) 195 { 196 struct resource *res; 197 void __iomem *base; 198 struct clk *clk; 199 struct mxs_phy *mxs_phy; 200 int ret; 201 const struct of_device_id *of_id = 202 of_match_device(mxs_phy_dt_ids, &pdev->dev); 203 struct device_node *np = pdev->dev.of_node; 204 205 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 206 base = devm_ioremap_resource(&pdev->dev, res); 207 if (IS_ERR(base)) 208 return PTR_ERR(base); 209 210 clk = devm_clk_get(&pdev->dev, NULL); 211 if (IS_ERR(clk)) { 212 dev_err(&pdev->dev, 213 "can't get the clock, err=%ld", PTR_ERR(clk)); 214 return PTR_ERR(clk); 215 } 216 217 mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL); 218 if (!mxs_phy) { 219 dev_err(&pdev->dev, "Failed to allocate USB PHY structure!\n"); 220 return -ENOMEM; 221 } 222 223 /* Some SoCs don't have anatop registers */ 224 if (of_get_property(np, "fsl,anatop", NULL)) { 225 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle 226 (np, "fsl,anatop"); 227 if (IS_ERR(mxs_phy->regmap_anatop)) { 228 dev_dbg(&pdev->dev, 229 "failed to find regmap for anatop\n"); 230 return PTR_ERR(mxs_phy->regmap_anatop); 231 } 232 } 233 234 mxs_phy->phy.io_priv = base; 235 mxs_phy->phy.dev = &pdev->dev; 236 mxs_phy->phy.label = DRIVER_NAME; 237 mxs_phy->phy.init = mxs_phy_init; 238 mxs_phy->phy.shutdown = mxs_phy_shutdown; 239 mxs_phy->phy.set_suspend = mxs_phy_suspend; 240 mxs_phy->phy.notify_connect = mxs_phy_on_connect; 241 mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect; 242 mxs_phy->phy.type = USB_PHY_TYPE_USB2; 243 244 mxs_phy->clk = clk; 245 mxs_phy->data = of_id->data; 246 247 platform_set_drvdata(pdev, mxs_phy); 248 249 ret = usb_add_phy_dev(&mxs_phy->phy); 250 if (ret) 251 return ret; 252 253 return 0; 254 } 255 256 static int mxs_phy_remove(struct platform_device *pdev) 257 { 258 struct mxs_phy *mxs_phy = platform_get_drvdata(pdev); 259 260 usb_remove_phy(&mxs_phy->phy); 261 262 return 0; 263 } 264 265 static struct platform_driver mxs_phy_driver = { 266 .probe = mxs_phy_probe, 267 .remove = mxs_phy_remove, 268 .driver = { 269 .name = DRIVER_NAME, 270 .owner = THIS_MODULE, 271 .of_match_table = mxs_phy_dt_ids, 272 }, 273 }; 274 275 static int __init mxs_phy_module_init(void) 276 { 277 return platform_driver_register(&mxs_phy_driver); 278 } 279 postcore_initcall(mxs_phy_module_init); 280 281 static void __exit mxs_phy_module_exit(void) 282 { 283 platform_driver_unregister(&mxs_phy_driver); 284 } 285 module_exit(mxs_phy_module_exit); 286 287 MODULE_ALIAS("platform:mxs-usb-phy"); 288 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 289 MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>"); 290 MODULE_DESCRIPTION("Freescale MXS USB PHY driver"); 291 MODULE_LICENSE("GPL"); 292