1 /* 2 * Copyright 2012-2014 Freescale Semiconductor, Inc. 3 * Copyright (C) 2012 Marek Vasut <marex@denx.de> 4 * on behalf of DENX Software Engineering GmbH 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 * http://www.opensource.org/licenses/gpl-license.html 11 * http://www.gnu.org/copyleft/gpl.html 12 */ 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/platform_device.h> 17 #include <linux/clk.h> 18 #include <linux/usb/otg.h> 19 #include <linux/stmp_device.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/io.h> 23 #include <linux/of_device.h> 24 #include <linux/regmap.h> 25 #include <linux/mfd/syscon.h> 26 27 #define DRIVER_NAME "mxs_phy" 28 29 #define HW_USBPHY_PWD 0x00 30 #define HW_USBPHY_CTRL 0x30 31 #define HW_USBPHY_CTRL_SET 0x34 32 #define HW_USBPHY_CTRL_CLR 0x38 33 34 #define HW_USBPHY_DEBUG_SET 0x54 35 #define HW_USBPHY_DEBUG_CLR 0x58 36 37 #define HW_USBPHY_IP 0x90 38 #define HW_USBPHY_IP_SET 0x94 39 #define HW_USBPHY_IP_CLR 0x98 40 41 #define BM_USBPHY_CTRL_SFTRST BIT(31) 42 #define BM_USBPHY_CTRL_CLKGATE BIT(30) 43 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26) 44 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25) 45 #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23) 46 #define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22) 47 #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21) 48 #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20) 49 #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19) 50 #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18) 51 #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15) 52 #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14) 53 #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1) 54 55 #define BM_USBPHY_IP_FIX (BIT(17) | BIT(18)) 56 57 #define BM_USBPHY_DEBUG_CLKGATE BIT(30) 58 59 /* Anatop Registers */ 60 #define ANADIG_ANA_MISC0 0x150 61 #define ANADIG_ANA_MISC0_SET 0x154 62 #define ANADIG_ANA_MISC0_CLR 0x158 63 64 #define ANADIG_USB1_VBUS_DET_STAT 0x1c0 65 #define ANADIG_USB2_VBUS_DET_STAT 0x220 66 67 #define ANADIG_USB1_LOOPBACK_SET 0x1e4 68 #define ANADIG_USB1_LOOPBACK_CLR 0x1e8 69 #define ANADIG_USB2_LOOPBACK_SET 0x244 70 #define ANADIG_USB2_LOOPBACK_CLR 0x248 71 72 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12) 73 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11) 74 75 #define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) 76 #define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3) 77 78 #define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2) 79 #define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5) 80 #define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2) 81 #define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5) 82 83 #define to_mxs_phy(p) container_of((p), struct mxs_phy, phy) 84 85 /* Do disconnection between PHY and controller without vbus */ 86 #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0) 87 88 /* 89 * The PHY will be in messy if there is a wakeup after putting 90 * bus to suspend (set portsc.suspendM) but before setting PHY to low 91 * power mode (set portsc.phcd). 92 */ 93 #define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1) 94 95 /* 96 * The SOF sends too fast after resuming, it will cause disconnection 97 * between host and high speed device. 98 */ 99 #define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2) 100 101 /* 102 * IC has bug fixes logic, they include 103 * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST 104 * which are described at above flags, the RTL will handle it 105 * according to different versions. 106 */ 107 #define MXS_PHY_NEED_IP_FIX BIT(3) 108 109 struct mxs_phy_data { 110 unsigned int flags; 111 }; 112 113 static const struct mxs_phy_data imx23_phy_data = { 114 .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST, 115 }; 116 117 static const struct mxs_phy_data imx6q_phy_data = { 118 .flags = MXS_PHY_SENDING_SOF_TOO_FAST | 119 MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 120 MXS_PHY_NEED_IP_FIX, 121 }; 122 123 static const struct mxs_phy_data imx6sl_phy_data = { 124 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 125 MXS_PHY_NEED_IP_FIX, 126 }; 127 128 static const struct mxs_phy_data vf610_phy_data = { 129 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 130 MXS_PHY_NEED_IP_FIX, 131 }; 132 133 static const struct mxs_phy_data imx6sx_phy_data = { 134 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS, 135 }; 136 137 static const struct of_device_id mxs_phy_dt_ids[] = { 138 { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, }, 139 { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, }, 140 { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, }, 141 { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, }, 142 { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, }, 143 { /* sentinel */ } 144 }; 145 MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids); 146 147 struct mxs_phy { 148 struct usb_phy phy; 149 struct clk *clk; 150 const struct mxs_phy_data *data; 151 struct regmap *regmap_anatop; 152 int port_id; 153 }; 154 155 static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy) 156 { 157 return mxs_phy->data == &imx6q_phy_data; 158 } 159 160 static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy) 161 { 162 return mxs_phy->data == &imx6sl_phy_data; 163 } 164 165 /* 166 * PHY needs some 32K cycles to switch from 32K clock to 167 * bus (such as AHB/AXI, etc) clock. 168 */ 169 static void mxs_phy_clock_switch_delay(void) 170 { 171 usleep_range(300, 400); 172 } 173 174 static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) 175 { 176 int ret; 177 void __iomem *base = mxs_phy->phy.io_priv; 178 179 ret = stmp_reset_block(base + HW_USBPHY_CTRL); 180 if (ret) 181 return ret; 182 183 /* Power up the PHY */ 184 writel(0, base + HW_USBPHY_PWD); 185 186 /* 187 * USB PHY Ctrl Setting 188 * - Auto clock/power on 189 * - Enable full/low speed support 190 */ 191 writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | 192 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | 193 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | 194 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | 195 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL | 196 BM_USBPHY_CTRL_ENUTMILEVEL2 | 197 BM_USBPHY_CTRL_ENUTMILEVEL3, 198 base + HW_USBPHY_CTRL_SET); 199 200 if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX) 201 writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET); 202 203 return 0; 204 } 205 206 /* Return true if the vbus is there */ 207 static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy) 208 { 209 unsigned int vbus_value; 210 211 if (mxs_phy->port_id == 0) 212 regmap_read(mxs_phy->regmap_anatop, 213 ANADIG_USB1_VBUS_DET_STAT, 214 &vbus_value); 215 else if (mxs_phy->port_id == 1) 216 regmap_read(mxs_phy->regmap_anatop, 217 ANADIG_USB2_VBUS_DET_STAT, 218 &vbus_value); 219 220 if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID) 221 return true; 222 else 223 return false; 224 } 225 226 static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect) 227 { 228 void __iomem *base = mxs_phy->phy.io_priv; 229 u32 reg; 230 231 if (disconnect) 232 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 233 base + HW_USBPHY_DEBUG_CLR); 234 235 if (mxs_phy->port_id == 0) { 236 reg = disconnect ? ANADIG_USB1_LOOPBACK_SET 237 : ANADIG_USB1_LOOPBACK_CLR; 238 regmap_write(mxs_phy->regmap_anatop, reg, 239 BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 | 240 BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN); 241 } else if (mxs_phy->port_id == 1) { 242 reg = disconnect ? ANADIG_USB2_LOOPBACK_SET 243 : ANADIG_USB2_LOOPBACK_CLR; 244 regmap_write(mxs_phy->regmap_anatop, reg, 245 BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 | 246 BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN); 247 } 248 249 if (!disconnect) 250 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 251 base + HW_USBPHY_DEBUG_SET); 252 253 /* Delay some time, and let Linestate be SE0 for controller */ 254 if (disconnect) 255 usleep_range(500, 1000); 256 } 257 258 static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on) 259 { 260 bool vbus_is_on = false; 261 262 /* If the SoCs don't need to disconnect line without vbus, quit */ 263 if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS)) 264 return; 265 266 /* If the SoCs don't have anatop, quit */ 267 if (!mxs_phy->regmap_anatop) 268 return; 269 270 vbus_is_on = mxs_phy_get_vbus_status(mxs_phy); 271 272 if (on && !vbus_is_on) 273 __mxs_phy_disconnect_line(mxs_phy, true); 274 else 275 __mxs_phy_disconnect_line(mxs_phy, false); 276 277 } 278 279 static int mxs_phy_init(struct usb_phy *phy) 280 { 281 int ret; 282 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 283 284 mxs_phy_clock_switch_delay(); 285 ret = clk_prepare_enable(mxs_phy->clk); 286 if (ret) 287 return ret; 288 289 return mxs_phy_hw_init(mxs_phy); 290 } 291 292 static void mxs_phy_shutdown(struct usb_phy *phy) 293 { 294 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 295 u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | 296 BM_USBPHY_CTRL_ENDPDMCHG_WKUP | 297 BM_USBPHY_CTRL_ENIDCHG_WKUP | 298 BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | 299 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | 300 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | 301 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | 302 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL; 303 304 writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR); 305 writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD); 306 307 writel(BM_USBPHY_CTRL_CLKGATE, 308 phy->io_priv + HW_USBPHY_CTRL_SET); 309 310 clk_disable_unprepare(mxs_phy->clk); 311 } 312 313 static int mxs_phy_suspend(struct usb_phy *x, int suspend) 314 { 315 int ret; 316 struct mxs_phy *mxs_phy = to_mxs_phy(x); 317 318 if (suspend) { 319 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD); 320 writel(BM_USBPHY_CTRL_CLKGATE, 321 x->io_priv + HW_USBPHY_CTRL_SET); 322 clk_disable_unprepare(mxs_phy->clk); 323 } else { 324 mxs_phy_clock_switch_delay(); 325 ret = clk_prepare_enable(mxs_phy->clk); 326 if (ret) 327 return ret; 328 writel(BM_USBPHY_CTRL_CLKGATE, 329 x->io_priv + HW_USBPHY_CTRL_CLR); 330 writel(0, x->io_priv + HW_USBPHY_PWD); 331 } 332 333 return 0; 334 } 335 336 static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled) 337 { 338 struct mxs_phy *mxs_phy = to_mxs_phy(x); 339 u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | 340 BM_USBPHY_CTRL_ENDPDMCHG_WKUP | 341 BM_USBPHY_CTRL_ENIDCHG_WKUP; 342 if (enabled) { 343 mxs_phy_disconnect_line(mxs_phy, true); 344 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET); 345 } else { 346 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR); 347 mxs_phy_disconnect_line(mxs_phy, false); 348 } 349 350 return 0; 351 } 352 353 static int mxs_phy_on_connect(struct usb_phy *phy, 354 enum usb_device_speed speed) 355 { 356 dev_dbg(phy->dev, "%s device has connected\n", 357 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); 358 359 if (speed == USB_SPEED_HIGH) 360 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, 361 phy->io_priv + HW_USBPHY_CTRL_SET); 362 363 return 0; 364 } 365 366 static int mxs_phy_on_disconnect(struct usb_phy *phy, 367 enum usb_device_speed speed) 368 { 369 dev_dbg(phy->dev, "%s device has disconnected\n", 370 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); 371 372 /* Sometimes, the speed is not high speed when the error occurs */ 373 if (readl(phy->io_priv + HW_USBPHY_CTRL) & 374 BM_USBPHY_CTRL_ENHOSTDISCONDETECT) 375 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, 376 phy->io_priv + HW_USBPHY_CTRL_CLR); 377 378 return 0; 379 } 380 381 static int mxs_phy_probe(struct platform_device *pdev) 382 { 383 struct resource *res; 384 void __iomem *base; 385 struct clk *clk; 386 struct mxs_phy *mxs_phy; 387 int ret; 388 const struct of_device_id *of_id = 389 of_match_device(mxs_phy_dt_ids, &pdev->dev); 390 struct device_node *np = pdev->dev.of_node; 391 392 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 393 base = devm_ioremap_resource(&pdev->dev, res); 394 if (IS_ERR(base)) 395 return PTR_ERR(base); 396 397 clk = devm_clk_get(&pdev->dev, NULL); 398 if (IS_ERR(clk)) { 399 dev_err(&pdev->dev, 400 "can't get the clock, err=%ld", PTR_ERR(clk)); 401 return PTR_ERR(clk); 402 } 403 404 mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL); 405 if (!mxs_phy) 406 return -ENOMEM; 407 408 /* Some SoCs don't have anatop registers */ 409 if (of_get_property(np, "fsl,anatop", NULL)) { 410 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle 411 (np, "fsl,anatop"); 412 if (IS_ERR(mxs_phy->regmap_anatop)) { 413 dev_dbg(&pdev->dev, 414 "failed to find regmap for anatop\n"); 415 return PTR_ERR(mxs_phy->regmap_anatop); 416 } 417 } 418 419 ret = of_alias_get_id(np, "usbphy"); 420 if (ret < 0) 421 dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret); 422 mxs_phy->port_id = ret; 423 424 mxs_phy->phy.io_priv = base; 425 mxs_phy->phy.dev = &pdev->dev; 426 mxs_phy->phy.label = DRIVER_NAME; 427 mxs_phy->phy.init = mxs_phy_init; 428 mxs_phy->phy.shutdown = mxs_phy_shutdown; 429 mxs_phy->phy.set_suspend = mxs_phy_suspend; 430 mxs_phy->phy.notify_connect = mxs_phy_on_connect; 431 mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect; 432 mxs_phy->phy.type = USB_PHY_TYPE_USB2; 433 mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup; 434 435 mxs_phy->clk = clk; 436 mxs_phy->data = of_id->data; 437 438 platform_set_drvdata(pdev, mxs_phy); 439 440 device_set_wakeup_capable(&pdev->dev, true); 441 442 ret = usb_add_phy_dev(&mxs_phy->phy); 443 if (ret) 444 return ret; 445 446 return 0; 447 } 448 449 static int mxs_phy_remove(struct platform_device *pdev) 450 { 451 struct mxs_phy *mxs_phy = platform_get_drvdata(pdev); 452 453 usb_remove_phy(&mxs_phy->phy); 454 455 return 0; 456 } 457 458 #ifdef CONFIG_PM_SLEEP 459 static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on) 460 { 461 unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR; 462 463 /* If the SoCs don't have anatop, quit */ 464 if (!mxs_phy->regmap_anatop) 465 return; 466 467 if (is_imx6q_phy(mxs_phy)) 468 regmap_write(mxs_phy->regmap_anatop, reg, 469 BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG); 470 else if (is_imx6sl_phy(mxs_phy)) 471 regmap_write(mxs_phy->regmap_anatop, 472 reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL); 473 } 474 475 static int mxs_phy_system_suspend(struct device *dev) 476 { 477 struct mxs_phy *mxs_phy = dev_get_drvdata(dev); 478 479 if (device_may_wakeup(dev)) 480 mxs_phy_enable_ldo_in_suspend(mxs_phy, true); 481 482 return 0; 483 } 484 485 static int mxs_phy_system_resume(struct device *dev) 486 { 487 struct mxs_phy *mxs_phy = dev_get_drvdata(dev); 488 489 if (device_may_wakeup(dev)) 490 mxs_phy_enable_ldo_in_suspend(mxs_phy, false); 491 492 return 0; 493 } 494 #endif /* CONFIG_PM_SLEEP */ 495 496 static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend, 497 mxs_phy_system_resume); 498 499 static struct platform_driver mxs_phy_driver = { 500 .probe = mxs_phy_probe, 501 .remove = mxs_phy_remove, 502 .driver = { 503 .name = DRIVER_NAME, 504 .of_match_table = mxs_phy_dt_ids, 505 .pm = &mxs_phy_pm, 506 }, 507 }; 508 509 static int __init mxs_phy_module_init(void) 510 { 511 return platform_driver_register(&mxs_phy_driver); 512 } 513 postcore_initcall(mxs_phy_module_init); 514 515 static void __exit mxs_phy_module_exit(void) 516 { 517 platform_driver_unregister(&mxs_phy_driver); 518 } 519 module_exit(mxs_phy_module_exit); 520 521 MODULE_ALIAS("platform:mxs-usb-phy"); 522 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 523 MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>"); 524 MODULE_DESCRIPTION("Freescale MXS USB PHY driver"); 525 MODULE_LICENSE("GPL"); 526