1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2012-2014 Freescale Semiconductor, Inc. 4 * Copyright (C) 2012 Marek Vasut <marex@denx.de> 5 * on behalf of DENX Software Engineering GmbH 6 * 7 * The code contained herein is licensed under the GNU General Public 8 * License. You may obtain a copy of the GNU General Public License 9 * Version 2 or later at the following locations: 10 * 11 * http://www.opensource.org/licenses/gpl-license.html 12 * http://www.gnu.org/copyleft/gpl.html 13 */ 14 15 #include <linux/module.h> 16 #include <linux/kernel.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/usb/otg.h> 20 #include <linux/stmp_device.h> 21 #include <linux/delay.h> 22 #include <linux/err.h> 23 #include <linux/io.h> 24 #include <linux/of_device.h> 25 #include <linux/regmap.h> 26 #include <linux/mfd/syscon.h> 27 28 #define DRIVER_NAME "mxs_phy" 29 30 #define HW_USBPHY_PWD 0x00 31 #define HW_USBPHY_TX 0x10 32 #define HW_USBPHY_CTRL 0x30 33 #define HW_USBPHY_CTRL_SET 0x34 34 #define HW_USBPHY_CTRL_CLR 0x38 35 36 #define HW_USBPHY_DEBUG_SET 0x54 37 #define HW_USBPHY_DEBUG_CLR 0x58 38 39 #define HW_USBPHY_IP 0x90 40 #define HW_USBPHY_IP_SET 0x94 41 #define HW_USBPHY_IP_CLR 0x98 42 43 #define GM_USBPHY_TX_TXCAL45DP(x) (((x) & 0xf) << 16) 44 #define GM_USBPHY_TX_TXCAL45DN(x) (((x) & 0xf) << 8) 45 #define GM_USBPHY_TX_D_CAL(x) (((x) & 0xf) << 0) 46 47 #define BM_USBPHY_CTRL_SFTRST BIT(31) 48 #define BM_USBPHY_CTRL_CLKGATE BIT(30) 49 #define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27) 50 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26) 51 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25) 52 #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23) 53 #define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22) 54 #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21) 55 #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20) 56 #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19) 57 #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18) 58 #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15) 59 #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14) 60 #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1) 61 62 #define BM_USBPHY_IP_FIX (BIT(17) | BIT(18)) 63 64 #define BM_USBPHY_DEBUG_CLKGATE BIT(30) 65 66 /* Anatop Registers */ 67 #define ANADIG_ANA_MISC0 0x150 68 #define ANADIG_ANA_MISC0_SET 0x154 69 #define ANADIG_ANA_MISC0_CLR 0x158 70 71 #define ANADIG_USB1_CHRG_DETECT_SET 0x1b4 72 #define ANADIG_USB1_CHRG_DETECT_CLR 0x1b8 73 #define ANADIG_USB1_CHRG_DETECT_EN_B BIT(20) 74 #define ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B BIT(19) 75 #define ANADIG_USB1_CHRG_DETECT_CHK_CONTACT BIT(18) 76 77 #define ANADIG_USB1_VBUS_DET_STAT 0x1c0 78 #define ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) 79 80 #define ANADIG_USB1_CHRG_DET_STAT 0x1d0 81 #define ANADIG_USB1_CHRG_DET_STAT_DM_STATE BIT(2) 82 #define ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED BIT(1) 83 #define ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT BIT(0) 84 85 #define ANADIG_USB2_VBUS_DET_STAT 0x220 86 87 #define ANADIG_USB1_LOOPBACK_SET 0x1e4 88 #define ANADIG_USB1_LOOPBACK_CLR 0x1e8 89 #define ANADIG_USB1_LOOPBACK_UTMI_TESTSTART BIT(0) 90 91 #define ANADIG_USB2_LOOPBACK_SET 0x244 92 #define ANADIG_USB2_LOOPBACK_CLR 0x248 93 94 #define ANADIG_USB1_MISC 0x1f0 95 #define ANADIG_USB2_MISC 0x250 96 97 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12) 98 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11) 99 100 #define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) 101 #define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3) 102 103 #define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2) 104 #define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5) 105 #define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2) 106 #define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5) 107 108 #define BM_ANADIG_USB1_MISC_RX_VPIN_FS BIT(29) 109 #define BM_ANADIG_USB1_MISC_RX_VMIN_FS BIT(28) 110 #define BM_ANADIG_USB2_MISC_RX_VPIN_FS BIT(29) 111 #define BM_ANADIG_USB2_MISC_RX_VMIN_FS BIT(28) 112 113 #define to_mxs_phy(p) container_of((p), struct mxs_phy, phy) 114 115 /* Do disconnection between PHY and controller without vbus */ 116 #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0) 117 118 /* 119 * The PHY will be in messy if there is a wakeup after putting 120 * bus to suspend (set portsc.suspendM) but before setting PHY to low 121 * power mode (set portsc.phcd). 122 */ 123 #define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1) 124 125 /* 126 * The SOF sends too fast after resuming, it will cause disconnection 127 * between host and high speed device. 128 */ 129 #define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2) 130 131 /* 132 * IC has bug fixes logic, they include 133 * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST 134 * which are described at above flags, the RTL will handle it 135 * according to different versions. 136 */ 137 #define MXS_PHY_NEED_IP_FIX BIT(3) 138 139 /* Minimum and maximum values for device tree entries */ 140 #define MXS_PHY_TX_CAL45_MIN 30 141 #define MXS_PHY_TX_CAL45_MAX 55 142 #define MXS_PHY_TX_D_CAL_MIN 79 143 #define MXS_PHY_TX_D_CAL_MAX 119 144 145 struct mxs_phy_data { 146 unsigned int flags; 147 }; 148 149 static const struct mxs_phy_data imx23_phy_data = { 150 .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST, 151 }; 152 153 static const struct mxs_phy_data imx6q_phy_data = { 154 .flags = MXS_PHY_SENDING_SOF_TOO_FAST | 155 MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 156 MXS_PHY_NEED_IP_FIX, 157 }; 158 159 static const struct mxs_phy_data imx6sl_phy_data = { 160 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 161 MXS_PHY_NEED_IP_FIX, 162 }; 163 164 static const struct mxs_phy_data vf610_phy_data = { 165 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 166 MXS_PHY_NEED_IP_FIX, 167 }; 168 169 static const struct mxs_phy_data imx6sx_phy_data = { 170 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS, 171 }; 172 173 static const struct mxs_phy_data imx6ul_phy_data = { 174 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS, 175 }; 176 177 static const struct of_device_id mxs_phy_dt_ids[] = { 178 { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, }, 179 { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, }, 180 { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, }, 181 { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, }, 182 { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, }, 183 { .compatible = "fsl,imx6ul-usbphy", .data = &imx6ul_phy_data, }, 184 { /* sentinel */ } 185 }; 186 MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids); 187 188 struct mxs_phy { 189 struct usb_phy phy; 190 struct clk *clk; 191 const struct mxs_phy_data *data; 192 struct regmap *regmap_anatop; 193 int port_id; 194 u32 tx_reg_set; 195 u32 tx_reg_mask; 196 }; 197 198 static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy) 199 { 200 return mxs_phy->data == &imx6q_phy_data; 201 } 202 203 static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy) 204 { 205 return mxs_phy->data == &imx6sl_phy_data; 206 } 207 208 /* 209 * PHY needs some 32K cycles to switch from 32K clock to 210 * bus (such as AHB/AXI, etc) clock. 211 */ 212 static void mxs_phy_clock_switch_delay(void) 213 { 214 usleep_range(300, 400); 215 } 216 217 static void mxs_phy_tx_init(struct mxs_phy *mxs_phy) 218 { 219 void __iomem *base = mxs_phy->phy.io_priv; 220 u32 phytx; 221 222 /* Update TX register if there is anything to write */ 223 if (mxs_phy->tx_reg_mask) { 224 phytx = readl(base + HW_USBPHY_TX); 225 phytx &= ~mxs_phy->tx_reg_mask; 226 phytx |= mxs_phy->tx_reg_set; 227 writel(phytx, base + HW_USBPHY_TX); 228 } 229 } 230 231 static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) 232 { 233 int ret; 234 void __iomem *base = mxs_phy->phy.io_priv; 235 236 ret = stmp_reset_block(base + HW_USBPHY_CTRL); 237 if (ret) 238 return ret; 239 240 /* Power up the PHY */ 241 writel(0, base + HW_USBPHY_PWD); 242 243 /* 244 * USB PHY Ctrl Setting 245 * - Auto clock/power on 246 * - Enable full/low speed support 247 */ 248 writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | 249 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | 250 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | 251 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | 252 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL | 253 BM_USBPHY_CTRL_ENUTMILEVEL2 | 254 BM_USBPHY_CTRL_ENUTMILEVEL3, 255 base + HW_USBPHY_CTRL_SET); 256 257 if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX) 258 writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET); 259 260 mxs_phy_tx_init(mxs_phy); 261 262 return 0; 263 } 264 265 /* Return true if the vbus is there */ 266 static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy) 267 { 268 unsigned int vbus_value = 0; 269 270 if (!mxs_phy->regmap_anatop) 271 return false; 272 273 if (mxs_phy->port_id == 0) 274 regmap_read(mxs_phy->regmap_anatop, 275 ANADIG_USB1_VBUS_DET_STAT, 276 &vbus_value); 277 else if (mxs_phy->port_id == 1) 278 regmap_read(mxs_phy->regmap_anatop, 279 ANADIG_USB2_VBUS_DET_STAT, 280 &vbus_value); 281 282 if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID) 283 return true; 284 else 285 return false; 286 } 287 288 static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect) 289 { 290 void __iomem *base = mxs_phy->phy.io_priv; 291 u32 reg; 292 293 if (disconnect) 294 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 295 base + HW_USBPHY_DEBUG_CLR); 296 297 if (mxs_phy->port_id == 0) { 298 reg = disconnect ? ANADIG_USB1_LOOPBACK_SET 299 : ANADIG_USB1_LOOPBACK_CLR; 300 regmap_write(mxs_phy->regmap_anatop, reg, 301 BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 | 302 BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN); 303 } else if (mxs_phy->port_id == 1) { 304 reg = disconnect ? ANADIG_USB2_LOOPBACK_SET 305 : ANADIG_USB2_LOOPBACK_CLR; 306 regmap_write(mxs_phy->regmap_anatop, reg, 307 BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 | 308 BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN); 309 } 310 311 if (!disconnect) 312 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 313 base + HW_USBPHY_DEBUG_SET); 314 315 /* Delay some time, and let Linestate be SE0 for controller */ 316 if (disconnect) 317 usleep_range(500, 1000); 318 } 319 320 static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy) 321 { 322 void __iomem *base = mxs_phy->phy.io_priv; 323 u32 phyctrl = readl(base + HW_USBPHY_CTRL); 324 325 if (IS_ENABLED(CONFIG_USB_OTG) && 326 !(phyctrl & BM_USBPHY_CTRL_OTG_ID_VALUE)) 327 return true; 328 329 return false; 330 } 331 332 static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on) 333 { 334 bool vbus_is_on = false; 335 336 /* If the SoCs don't need to disconnect line without vbus, quit */ 337 if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS)) 338 return; 339 340 /* If the SoCs don't have anatop, quit */ 341 if (!mxs_phy->regmap_anatop) 342 return; 343 344 vbus_is_on = mxs_phy_get_vbus_status(mxs_phy); 345 346 if (on && !vbus_is_on && !mxs_phy_is_otg_host(mxs_phy)) 347 __mxs_phy_disconnect_line(mxs_phy, true); 348 else 349 __mxs_phy_disconnect_line(mxs_phy, false); 350 351 } 352 353 static int mxs_phy_init(struct usb_phy *phy) 354 { 355 int ret; 356 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 357 358 mxs_phy_clock_switch_delay(); 359 ret = clk_prepare_enable(mxs_phy->clk); 360 if (ret) 361 return ret; 362 363 return mxs_phy_hw_init(mxs_phy); 364 } 365 366 static void mxs_phy_shutdown(struct usb_phy *phy) 367 { 368 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 369 u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | 370 BM_USBPHY_CTRL_ENDPDMCHG_WKUP | 371 BM_USBPHY_CTRL_ENIDCHG_WKUP | 372 BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | 373 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | 374 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | 375 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | 376 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL; 377 378 writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR); 379 writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD); 380 381 writel(BM_USBPHY_CTRL_CLKGATE, 382 phy->io_priv + HW_USBPHY_CTRL_SET); 383 384 clk_disable_unprepare(mxs_phy->clk); 385 } 386 387 static bool mxs_phy_is_low_speed_connection(struct mxs_phy *mxs_phy) 388 { 389 unsigned int line_state; 390 /* bit definition is the same for all controllers */ 391 unsigned int dp_bit = BM_ANADIG_USB1_MISC_RX_VPIN_FS, 392 dm_bit = BM_ANADIG_USB1_MISC_RX_VMIN_FS; 393 unsigned int reg = ANADIG_USB1_MISC; 394 395 /* If the SoCs don't have anatop, quit */ 396 if (!mxs_phy->regmap_anatop) 397 return false; 398 399 if (mxs_phy->port_id == 0) 400 reg = ANADIG_USB1_MISC; 401 else if (mxs_phy->port_id == 1) 402 reg = ANADIG_USB2_MISC; 403 404 regmap_read(mxs_phy->regmap_anatop, reg, &line_state); 405 406 if ((line_state & (dp_bit | dm_bit)) == dm_bit) 407 return true; 408 else 409 return false; 410 } 411 412 static int mxs_phy_suspend(struct usb_phy *x, int suspend) 413 { 414 int ret; 415 struct mxs_phy *mxs_phy = to_mxs_phy(x); 416 bool low_speed_connection, vbus_is_on; 417 418 low_speed_connection = mxs_phy_is_low_speed_connection(mxs_phy); 419 vbus_is_on = mxs_phy_get_vbus_status(mxs_phy); 420 421 if (suspend) { 422 /* 423 * FIXME: Do not power down RXPWD1PT1 bit for low speed 424 * connect. The low speed connection will have problem at 425 * very rare cases during usb suspend and resume process. 426 */ 427 if (low_speed_connection & vbus_is_on) { 428 /* 429 * If value to be set as pwd value is not 0xffffffff, 430 * several 32Khz cycles are needed. 431 */ 432 mxs_phy_clock_switch_delay(); 433 writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD); 434 } else { 435 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD); 436 } 437 writel(BM_USBPHY_CTRL_CLKGATE, 438 x->io_priv + HW_USBPHY_CTRL_SET); 439 clk_disable_unprepare(mxs_phy->clk); 440 } else { 441 mxs_phy_clock_switch_delay(); 442 ret = clk_prepare_enable(mxs_phy->clk); 443 if (ret) 444 return ret; 445 writel(BM_USBPHY_CTRL_CLKGATE, 446 x->io_priv + HW_USBPHY_CTRL_CLR); 447 writel(0, x->io_priv + HW_USBPHY_PWD); 448 } 449 450 return 0; 451 } 452 453 static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled) 454 { 455 struct mxs_phy *mxs_phy = to_mxs_phy(x); 456 u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | 457 BM_USBPHY_CTRL_ENDPDMCHG_WKUP | 458 BM_USBPHY_CTRL_ENIDCHG_WKUP; 459 if (enabled) { 460 mxs_phy_disconnect_line(mxs_phy, true); 461 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET); 462 } else { 463 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR); 464 mxs_phy_disconnect_line(mxs_phy, false); 465 } 466 467 return 0; 468 } 469 470 static int mxs_phy_on_connect(struct usb_phy *phy, 471 enum usb_device_speed speed) 472 { 473 dev_dbg(phy->dev, "%s device has connected\n", 474 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); 475 476 if (speed == USB_SPEED_HIGH) 477 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, 478 phy->io_priv + HW_USBPHY_CTRL_SET); 479 480 return 0; 481 } 482 483 static int mxs_phy_on_disconnect(struct usb_phy *phy, 484 enum usb_device_speed speed) 485 { 486 dev_dbg(phy->dev, "%s device has disconnected\n", 487 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); 488 489 /* Sometimes, the speed is not high speed when the error occurs */ 490 if (readl(phy->io_priv + HW_USBPHY_CTRL) & 491 BM_USBPHY_CTRL_ENHOSTDISCONDETECT) 492 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, 493 phy->io_priv + HW_USBPHY_CTRL_CLR); 494 495 return 0; 496 } 497 498 #define MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT 100 499 static int mxs_charger_data_contact_detect(struct mxs_phy *x) 500 { 501 struct regmap *regmap = x->regmap_anatop; 502 int i, stable_contact_count = 0; 503 u32 val; 504 505 /* Check if vbus is valid */ 506 regmap_read(regmap, ANADIG_USB1_VBUS_DET_STAT, &val); 507 if (!(val & ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)) { 508 dev_err(x->phy.dev, "vbus is not valid\n"); 509 return -EINVAL; 510 } 511 512 /* Enable charger detector */ 513 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_CLR, 514 ANADIG_USB1_CHRG_DETECT_EN_B); 515 /* 516 * - Do not check whether a charger is connected to the USB port 517 * - Check whether the USB plug has been in contact with each other 518 */ 519 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET, 520 ANADIG_USB1_CHRG_DETECT_CHK_CONTACT | 521 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 522 523 /* Check if plug is connected */ 524 for (i = 0; i < MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT; i++) { 525 regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); 526 if (val & ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT) { 527 stable_contact_count++; 528 if (stable_contact_count > 5) 529 /* Data pin makes contact */ 530 break; 531 else 532 usleep_range(5000, 10000); 533 } else { 534 stable_contact_count = 0; 535 usleep_range(5000, 6000); 536 } 537 } 538 539 if (i == MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT) { 540 dev_err(x->phy.dev, 541 "Data pin can't make good contact.\n"); 542 /* Disable charger detector */ 543 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET, 544 ANADIG_USB1_CHRG_DETECT_EN_B | 545 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 546 return -ENXIO; 547 } 548 549 return 0; 550 } 551 552 static enum usb_charger_type mxs_charger_primary_detection(struct mxs_phy *x) 553 { 554 struct regmap *regmap = x->regmap_anatop; 555 enum usb_charger_type chgr_type = UNKNOWN_TYPE; 556 u32 val; 557 558 /* 559 * - Do check whether a charger is connected to the USB port 560 * - Do not Check whether the USB plug has been in contact with 561 * each other 562 */ 563 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_CLR, 564 ANADIG_USB1_CHRG_DETECT_CHK_CONTACT | 565 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 566 567 msleep(100); 568 569 /* Check if it is a charger */ 570 regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); 571 if (!(val & ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED)) { 572 chgr_type = SDP_TYPE; 573 dev_dbg(x->phy.dev, "It is a stardard downstream port\n"); 574 } 575 576 /* Disable charger detector */ 577 regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET, 578 ANADIG_USB1_CHRG_DETECT_EN_B | 579 ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); 580 581 return chgr_type; 582 } 583 584 /* 585 * It must be called after DP is pulled up, which is used to 586 * differentiate DCP and CDP. 587 */ 588 enum usb_charger_type mxs_charger_secondary_detection(struct mxs_phy *x) 589 { 590 struct regmap *regmap = x->regmap_anatop; 591 int val; 592 593 msleep(80); 594 595 regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); 596 if (val & ANADIG_USB1_CHRG_DET_STAT_DM_STATE) { 597 dev_dbg(x->phy.dev, "It is a dedicate charging port\n"); 598 return DCP_TYPE; 599 } else { 600 dev_dbg(x->phy.dev, "It is a charging downstream port\n"); 601 return CDP_TYPE; 602 } 603 } 604 605 static enum usb_charger_type mxs_phy_charger_detect(struct usb_phy *phy) 606 { 607 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 608 struct regmap *regmap = mxs_phy->regmap_anatop; 609 void __iomem *base = phy->io_priv; 610 enum usb_charger_type chgr_type = UNKNOWN_TYPE; 611 612 if (mxs_charger_data_contact_detect(mxs_phy)) 613 return chgr_type; 614 615 chgr_type = mxs_charger_primary_detection(mxs_phy); 616 617 if (chgr_type != SDP_TYPE) { 618 /* Pull up DP via test */ 619 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 620 base + HW_USBPHY_DEBUG_CLR); 621 regmap_write(regmap, ANADIG_USB1_LOOPBACK_SET, 622 ANADIG_USB1_LOOPBACK_UTMI_TESTSTART); 623 624 chgr_type = mxs_charger_secondary_detection(mxs_phy); 625 626 /* Stop the test */ 627 regmap_write(regmap, ANADIG_USB1_LOOPBACK_CLR, 628 ANADIG_USB1_LOOPBACK_UTMI_TESTSTART); 629 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 630 base + HW_USBPHY_DEBUG_SET); 631 } 632 633 return chgr_type; 634 } 635 636 static int mxs_phy_probe(struct platform_device *pdev) 637 { 638 struct resource *res; 639 void __iomem *base; 640 struct clk *clk; 641 struct mxs_phy *mxs_phy; 642 int ret; 643 const struct of_device_id *of_id; 644 struct device_node *np = pdev->dev.of_node; 645 u32 val; 646 647 of_id = of_match_device(mxs_phy_dt_ids, &pdev->dev); 648 if (!of_id) 649 return -ENODEV; 650 651 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 652 base = devm_ioremap_resource(&pdev->dev, res); 653 if (IS_ERR(base)) 654 return PTR_ERR(base); 655 656 clk = devm_clk_get(&pdev->dev, NULL); 657 if (IS_ERR(clk)) { 658 dev_err(&pdev->dev, 659 "can't get the clock, err=%ld", PTR_ERR(clk)); 660 return PTR_ERR(clk); 661 } 662 663 mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL); 664 if (!mxs_phy) 665 return -ENOMEM; 666 667 /* Some SoCs don't have anatop registers */ 668 if (of_get_property(np, "fsl,anatop", NULL)) { 669 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle 670 (np, "fsl,anatop"); 671 if (IS_ERR(mxs_phy->regmap_anatop)) { 672 dev_dbg(&pdev->dev, 673 "failed to find regmap for anatop\n"); 674 return PTR_ERR(mxs_phy->regmap_anatop); 675 } 676 } 677 678 /* Precompute which bits of the TX register are to be updated, if any */ 679 if (!of_property_read_u32(np, "fsl,tx-cal-45-dn-ohms", &val) && 680 val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) { 681 /* Scale to a 4-bit value */ 682 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF 683 / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN); 684 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DN(~0); 685 mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DN(val); 686 } 687 688 if (!of_property_read_u32(np, "fsl,tx-cal-45-dp-ohms", &val) && 689 val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) { 690 /* Scale to a 4-bit value. */ 691 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF 692 / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN); 693 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DP(~0); 694 mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DP(val); 695 } 696 697 if (!of_property_read_u32(np, "fsl,tx-d-cal", &val) && 698 val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) { 699 /* Scale to a 4-bit value. Round up the values and heavily 700 * weight the rounding by adding 2/3 of the denominator. 701 */ 702 val = ((MXS_PHY_TX_D_CAL_MAX - val) * 0xF 703 + (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN) * 2/3) 704 / (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN); 705 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0); 706 mxs_phy->tx_reg_set |= GM_USBPHY_TX_D_CAL(val); 707 } 708 709 ret = of_alias_get_id(np, "usbphy"); 710 if (ret < 0) 711 dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret); 712 mxs_phy->port_id = ret; 713 714 mxs_phy->phy.io_priv = base; 715 mxs_phy->phy.dev = &pdev->dev; 716 mxs_phy->phy.label = DRIVER_NAME; 717 mxs_phy->phy.init = mxs_phy_init; 718 mxs_phy->phy.shutdown = mxs_phy_shutdown; 719 mxs_phy->phy.set_suspend = mxs_phy_suspend; 720 mxs_phy->phy.notify_connect = mxs_phy_on_connect; 721 mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect; 722 mxs_phy->phy.type = USB_PHY_TYPE_USB2; 723 mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup; 724 mxs_phy->phy.charger_detect = mxs_phy_charger_detect; 725 726 mxs_phy->clk = clk; 727 mxs_phy->data = of_id->data; 728 729 platform_set_drvdata(pdev, mxs_phy); 730 731 device_set_wakeup_capable(&pdev->dev, true); 732 733 return usb_add_phy_dev(&mxs_phy->phy); 734 } 735 736 static int mxs_phy_remove(struct platform_device *pdev) 737 { 738 struct mxs_phy *mxs_phy = platform_get_drvdata(pdev); 739 740 usb_remove_phy(&mxs_phy->phy); 741 742 return 0; 743 } 744 745 #ifdef CONFIG_PM_SLEEP 746 static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on) 747 { 748 unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR; 749 750 /* If the SoCs don't have anatop, quit */ 751 if (!mxs_phy->regmap_anatop) 752 return; 753 754 if (is_imx6q_phy(mxs_phy)) 755 regmap_write(mxs_phy->regmap_anatop, reg, 756 BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG); 757 else if (is_imx6sl_phy(mxs_phy)) 758 regmap_write(mxs_phy->regmap_anatop, 759 reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL); 760 } 761 762 static int mxs_phy_system_suspend(struct device *dev) 763 { 764 struct mxs_phy *mxs_phy = dev_get_drvdata(dev); 765 766 if (device_may_wakeup(dev)) 767 mxs_phy_enable_ldo_in_suspend(mxs_phy, true); 768 769 return 0; 770 } 771 772 static int mxs_phy_system_resume(struct device *dev) 773 { 774 struct mxs_phy *mxs_phy = dev_get_drvdata(dev); 775 776 if (device_may_wakeup(dev)) 777 mxs_phy_enable_ldo_in_suspend(mxs_phy, false); 778 779 return 0; 780 } 781 #endif /* CONFIG_PM_SLEEP */ 782 783 static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend, 784 mxs_phy_system_resume); 785 786 static struct platform_driver mxs_phy_driver = { 787 .probe = mxs_phy_probe, 788 .remove = mxs_phy_remove, 789 .driver = { 790 .name = DRIVER_NAME, 791 .of_match_table = mxs_phy_dt_ids, 792 .pm = &mxs_phy_pm, 793 }, 794 }; 795 796 static int __init mxs_phy_module_init(void) 797 { 798 return platform_driver_register(&mxs_phy_driver); 799 } 800 postcore_initcall(mxs_phy_module_init); 801 802 static void __exit mxs_phy_module_exit(void) 803 { 804 platform_driver_unregister(&mxs_phy_driver); 805 } 806 module_exit(mxs_phy_module_exit); 807 808 MODULE_ALIAS("platform:mxs-usb-phy"); 809 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 810 MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>"); 811 MODULE_DESCRIPTION("Freescale MXS USB PHY driver"); 812 MODULE_LICENSE("GPL"); 813