1 /* 2 * Copyright 2012-2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2012 Marek Vasut <marex@denx.de> 4 * on behalf of DENX Software Engineering GmbH 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 * http://www.opensource.org/licenses/gpl-license.html 11 * http://www.gnu.org/copyleft/gpl.html 12 */ 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/platform_device.h> 17 #include <linux/clk.h> 18 #include <linux/usb/otg.h> 19 #include <linux/stmp_device.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 #include <linux/io.h> 23 #include <linux/of_device.h> 24 #include <linux/regmap.h> 25 #include <linux/mfd/syscon.h> 26 27 #define DRIVER_NAME "mxs_phy" 28 29 #define HW_USBPHY_PWD 0x00 30 #define HW_USBPHY_CTRL 0x30 31 #define HW_USBPHY_CTRL_SET 0x34 32 #define HW_USBPHY_CTRL_CLR 0x38 33 34 #define HW_USBPHY_DEBUG_SET 0x54 35 #define HW_USBPHY_DEBUG_CLR 0x58 36 37 #define HW_USBPHY_IP 0x90 38 #define HW_USBPHY_IP_SET 0x94 39 #define HW_USBPHY_IP_CLR 0x98 40 41 #define BM_USBPHY_CTRL_SFTRST BIT(31) 42 #define BM_USBPHY_CTRL_CLKGATE BIT(30) 43 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26) 44 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25) 45 #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23) 46 #define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22) 47 #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21) 48 #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20) 49 #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19) 50 #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18) 51 #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15) 52 #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14) 53 #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1) 54 55 #define BM_USBPHY_IP_FIX (BIT(17) | BIT(18)) 56 57 #define BM_USBPHY_DEBUG_CLKGATE BIT(30) 58 59 /* Anatop Registers */ 60 #define ANADIG_ANA_MISC0 0x150 61 #define ANADIG_ANA_MISC0_SET 0x154 62 #define ANADIG_ANA_MISC0_CLR 0x158 63 64 #define ANADIG_USB1_VBUS_DET_STAT 0x1c0 65 #define ANADIG_USB2_VBUS_DET_STAT 0x220 66 67 #define ANADIG_USB1_LOOPBACK_SET 0x1e4 68 #define ANADIG_USB1_LOOPBACK_CLR 0x1e8 69 #define ANADIG_USB2_LOOPBACK_SET 0x244 70 #define ANADIG_USB2_LOOPBACK_CLR 0x248 71 72 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12) 73 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11) 74 75 #define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) 76 #define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3) 77 78 #define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2) 79 #define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5) 80 #define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2) 81 #define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5) 82 83 #define to_mxs_phy(p) container_of((p), struct mxs_phy, phy) 84 85 /* Do disconnection between PHY and controller without vbus */ 86 #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0) 87 88 /* 89 * The PHY will be in messy if there is a wakeup after putting 90 * bus to suspend (set portsc.suspendM) but before setting PHY to low 91 * power mode (set portsc.phcd). 92 */ 93 #define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1) 94 95 /* 96 * The SOF sends too fast after resuming, it will cause disconnection 97 * between host and high speed device. 98 */ 99 #define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2) 100 101 /* 102 * IC has bug fixes logic, they include 103 * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST 104 * which are described at above flags, the RTL will handle it 105 * according to different versions. 106 */ 107 #define MXS_PHY_NEED_IP_FIX BIT(3) 108 109 struct mxs_phy_data { 110 unsigned int flags; 111 }; 112 113 static const struct mxs_phy_data imx23_phy_data = { 114 .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST, 115 }; 116 117 static const struct mxs_phy_data imx6q_phy_data = { 118 .flags = MXS_PHY_SENDING_SOF_TOO_FAST | 119 MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 120 MXS_PHY_NEED_IP_FIX, 121 }; 122 123 static const struct mxs_phy_data imx6sl_phy_data = { 124 .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | 125 MXS_PHY_NEED_IP_FIX, 126 }; 127 128 static const struct of_device_id mxs_phy_dt_ids[] = { 129 { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, }, 130 { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, }, 131 { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, }, 132 { /* sentinel */ } 133 }; 134 MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids); 135 136 struct mxs_phy { 137 struct usb_phy phy; 138 struct clk *clk; 139 const struct mxs_phy_data *data; 140 struct regmap *regmap_anatop; 141 int port_id; 142 }; 143 144 static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy) 145 { 146 return mxs_phy->data == &imx6q_phy_data; 147 } 148 149 static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy) 150 { 151 return mxs_phy->data == &imx6sl_phy_data; 152 } 153 154 /* 155 * PHY needs some 32K cycles to switch from 32K clock to 156 * bus (such as AHB/AXI, etc) clock. 157 */ 158 static void mxs_phy_clock_switch_delay(void) 159 { 160 usleep_range(300, 400); 161 } 162 163 static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) 164 { 165 int ret; 166 void __iomem *base = mxs_phy->phy.io_priv; 167 168 ret = stmp_reset_block(base + HW_USBPHY_CTRL); 169 if (ret) 170 return ret; 171 172 /* Power up the PHY */ 173 writel(0, base + HW_USBPHY_PWD); 174 175 /* 176 * USB PHY Ctrl Setting 177 * - Auto clock/power on 178 * - Enable full/low speed support 179 */ 180 writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | 181 BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | 182 BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | 183 BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | 184 BM_USBPHY_CTRL_ENAUTO_PWRON_PLL | 185 BM_USBPHY_CTRL_ENUTMILEVEL2 | 186 BM_USBPHY_CTRL_ENUTMILEVEL3, 187 base + HW_USBPHY_CTRL_SET); 188 189 if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX) 190 writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET); 191 192 return 0; 193 } 194 195 /* Return true if the vbus is there */ 196 static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy) 197 { 198 unsigned int vbus_value; 199 200 if (mxs_phy->port_id == 0) 201 regmap_read(mxs_phy->regmap_anatop, 202 ANADIG_USB1_VBUS_DET_STAT, 203 &vbus_value); 204 else if (mxs_phy->port_id == 1) 205 regmap_read(mxs_phy->regmap_anatop, 206 ANADIG_USB2_VBUS_DET_STAT, 207 &vbus_value); 208 209 if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID) 210 return true; 211 else 212 return false; 213 } 214 215 static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect) 216 { 217 void __iomem *base = mxs_phy->phy.io_priv; 218 u32 reg; 219 220 if (disconnect) 221 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 222 base + HW_USBPHY_DEBUG_CLR); 223 224 if (mxs_phy->port_id == 0) { 225 reg = disconnect ? ANADIG_USB1_LOOPBACK_SET 226 : ANADIG_USB1_LOOPBACK_CLR; 227 regmap_write(mxs_phy->regmap_anatop, reg, 228 BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 | 229 BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN); 230 } else if (mxs_phy->port_id == 1) { 231 reg = disconnect ? ANADIG_USB2_LOOPBACK_SET 232 : ANADIG_USB2_LOOPBACK_CLR; 233 regmap_write(mxs_phy->regmap_anatop, reg, 234 BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 | 235 BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN); 236 } 237 238 if (!disconnect) 239 writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, 240 base + HW_USBPHY_DEBUG_SET); 241 242 /* Delay some time, and let Linestate be SE0 for controller */ 243 if (disconnect) 244 usleep_range(500, 1000); 245 } 246 247 static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on) 248 { 249 bool vbus_is_on = false; 250 251 /* If the SoCs don't need to disconnect line without vbus, quit */ 252 if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS)) 253 return; 254 255 /* If the SoCs don't have anatop, quit */ 256 if (!mxs_phy->regmap_anatop) 257 return; 258 259 vbus_is_on = mxs_phy_get_vbus_status(mxs_phy); 260 261 if (on && !vbus_is_on) 262 __mxs_phy_disconnect_line(mxs_phy, true); 263 else 264 __mxs_phy_disconnect_line(mxs_phy, false); 265 266 } 267 268 static int mxs_phy_init(struct usb_phy *phy) 269 { 270 int ret; 271 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 272 273 mxs_phy_clock_switch_delay(); 274 ret = clk_prepare_enable(mxs_phy->clk); 275 if (ret) 276 return ret; 277 278 return mxs_phy_hw_init(mxs_phy); 279 } 280 281 static void mxs_phy_shutdown(struct usb_phy *phy) 282 { 283 struct mxs_phy *mxs_phy = to_mxs_phy(phy); 284 285 writel(BM_USBPHY_CTRL_CLKGATE, 286 phy->io_priv + HW_USBPHY_CTRL_SET); 287 288 clk_disable_unprepare(mxs_phy->clk); 289 } 290 291 static int mxs_phy_suspend(struct usb_phy *x, int suspend) 292 { 293 int ret; 294 struct mxs_phy *mxs_phy = to_mxs_phy(x); 295 296 if (suspend) { 297 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD); 298 writel(BM_USBPHY_CTRL_CLKGATE, 299 x->io_priv + HW_USBPHY_CTRL_SET); 300 clk_disable_unprepare(mxs_phy->clk); 301 } else { 302 mxs_phy_clock_switch_delay(); 303 ret = clk_prepare_enable(mxs_phy->clk); 304 if (ret) 305 return ret; 306 writel(BM_USBPHY_CTRL_CLKGATE, 307 x->io_priv + HW_USBPHY_CTRL_CLR); 308 writel(0, x->io_priv + HW_USBPHY_PWD); 309 } 310 311 return 0; 312 } 313 314 static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled) 315 { 316 struct mxs_phy *mxs_phy = to_mxs_phy(x); 317 u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | 318 BM_USBPHY_CTRL_ENDPDMCHG_WKUP | 319 BM_USBPHY_CTRL_ENIDCHG_WKUP; 320 if (enabled) { 321 mxs_phy_disconnect_line(mxs_phy, true); 322 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET); 323 } else { 324 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR); 325 mxs_phy_disconnect_line(mxs_phy, false); 326 } 327 328 return 0; 329 } 330 331 static int mxs_phy_on_connect(struct usb_phy *phy, 332 enum usb_device_speed speed) 333 { 334 dev_dbg(phy->dev, "%s device has connected\n", 335 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); 336 337 if (speed == USB_SPEED_HIGH) 338 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, 339 phy->io_priv + HW_USBPHY_CTRL_SET); 340 341 return 0; 342 } 343 344 static int mxs_phy_on_disconnect(struct usb_phy *phy, 345 enum usb_device_speed speed) 346 { 347 dev_dbg(phy->dev, "%s device has disconnected\n", 348 (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); 349 350 if (speed == USB_SPEED_HIGH) 351 writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, 352 phy->io_priv + HW_USBPHY_CTRL_CLR); 353 354 return 0; 355 } 356 357 static int mxs_phy_probe(struct platform_device *pdev) 358 { 359 struct resource *res; 360 void __iomem *base; 361 struct clk *clk; 362 struct mxs_phy *mxs_phy; 363 int ret; 364 const struct of_device_id *of_id = 365 of_match_device(mxs_phy_dt_ids, &pdev->dev); 366 struct device_node *np = pdev->dev.of_node; 367 368 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 369 base = devm_ioremap_resource(&pdev->dev, res); 370 if (IS_ERR(base)) 371 return PTR_ERR(base); 372 373 clk = devm_clk_get(&pdev->dev, NULL); 374 if (IS_ERR(clk)) { 375 dev_err(&pdev->dev, 376 "can't get the clock, err=%ld", PTR_ERR(clk)); 377 return PTR_ERR(clk); 378 } 379 380 mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL); 381 if (!mxs_phy) { 382 dev_err(&pdev->dev, "Failed to allocate USB PHY structure!\n"); 383 return -ENOMEM; 384 } 385 386 /* Some SoCs don't have anatop registers */ 387 if (of_get_property(np, "fsl,anatop", NULL)) { 388 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle 389 (np, "fsl,anatop"); 390 if (IS_ERR(mxs_phy->regmap_anatop)) { 391 dev_dbg(&pdev->dev, 392 "failed to find regmap for anatop\n"); 393 return PTR_ERR(mxs_phy->regmap_anatop); 394 } 395 } 396 397 ret = of_alias_get_id(np, "usbphy"); 398 if (ret < 0) 399 dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret); 400 mxs_phy->port_id = ret; 401 402 mxs_phy->phy.io_priv = base; 403 mxs_phy->phy.dev = &pdev->dev; 404 mxs_phy->phy.label = DRIVER_NAME; 405 mxs_phy->phy.init = mxs_phy_init; 406 mxs_phy->phy.shutdown = mxs_phy_shutdown; 407 mxs_phy->phy.set_suspend = mxs_phy_suspend; 408 mxs_phy->phy.notify_connect = mxs_phy_on_connect; 409 mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect; 410 mxs_phy->phy.type = USB_PHY_TYPE_USB2; 411 mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup; 412 413 mxs_phy->clk = clk; 414 mxs_phy->data = of_id->data; 415 416 platform_set_drvdata(pdev, mxs_phy); 417 418 device_set_wakeup_capable(&pdev->dev, true); 419 420 ret = usb_add_phy_dev(&mxs_phy->phy); 421 if (ret) 422 return ret; 423 424 return 0; 425 } 426 427 static int mxs_phy_remove(struct platform_device *pdev) 428 { 429 struct mxs_phy *mxs_phy = platform_get_drvdata(pdev); 430 431 usb_remove_phy(&mxs_phy->phy); 432 433 return 0; 434 } 435 436 #ifdef CONFIG_PM_SLEEP 437 static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on) 438 { 439 unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR; 440 441 /* If the SoCs don't have anatop, quit */ 442 if (!mxs_phy->regmap_anatop) 443 return; 444 445 if (is_imx6q_phy(mxs_phy)) 446 regmap_write(mxs_phy->regmap_anatop, reg, 447 BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG); 448 else if (is_imx6sl_phy(mxs_phy)) 449 regmap_write(mxs_phy->regmap_anatop, 450 reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL); 451 } 452 453 static int mxs_phy_system_suspend(struct device *dev) 454 { 455 struct mxs_phy *mxs_phy = dev_get_drvdata(dev); 456 457 if (device_may_wakeup(dev)) 458 mxs_phy_enable_ldo_in_suspend(mxs_phy, true); 459 460 return 0; 461 } 462 463 static int mxs_phy_system_resume(struct device *dev) 464 { 465 struct mxs_phy *mxs_phy = dev_get_drvdata(dev); 466 467 if (device_may_wakeup(dev)) 468 mxs_phy_enable_ldo_in_suspend(mxs_phy, false); 469 470 return 0; 471 } 472 #endif /* CONFIG_PM_SLEEP */ 473 474 static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend, 475 mxs_phy_system_resume); 476 477 static struct platform_driver mxs_phy_driver = { 478 .probe = mxs_phy_probe, 479 .remove = mxs_phy_remove, 480 .driver = { 481 .name = DRIVER_NAME, 482 .owner = THIS_MODULE, 483 .of_match_table = mxs_phy_dt_ids, 484 .pm = &mxs_phy_pm, 485 }, 486 }; 487 488 static int __init mxs_phy_module_init(void) 489 { 490 return platform_driver_register(&mxs_phy_driver); 491 } 492 postcore_initcall(mxs_phy_module_init); 493 494 static void __exit mxs_phy_module_exit(void) 495 { 496 platform_driver_unregister(&mxs_phy_driver); 497 } 498 module_exit(mxs_phy_module_exit); 499 500 MODULE_ALIAS("platform:mxs-usb-phy"); 501 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 502 MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>"); 503 MODULE_DESCRIPTION("Freescale MXS USB PHY driver"); 504 MODULE_LICENSE("GPL"); 505