194ae9843SFelipe Balbi /* Copyright (C) 2007,2008 Freescale Semiconductor, Inc. 294ae9843SFelipe Balbi * 394ae9843SFelipe Balbi * This program is free software; you can redistribute it and/or modify it 494ae9843SFelipe Balbi * under the terms of the GNU General Public License as published by the 594ae9843SFelipe Balbi * Free Software Foundation; either version 2 of the License, or (at your 694ae9843SFelipe Balbi * option) any later version. 794ae9843SFelipe Balbi * 894ae9843SFelipe Balbi * This program is distributed in the hope that it will be useful, but 994ae9843SFelipe Balbi * WITHOUT ANY WARRANTY; without even the implied warranty of 1094ae9843SFelipe Balbi * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1194ae9843SFelipe Balbi * General Public License for more details. 1294ae9843SFelipe Balbi * 1394ae9843SFelipe Balbi * You should have received a copy of the GNU General Public License along 1494ae9843SFelipe Balbi * with this program; if not, write to the Free Software Foundation, Inc., 1594ae9843SFelipe Balbi * 675 Mass Ave, Cambridge, MA 02139, USA. 1694ae9843SFelipe Balbi */ 1794ae9843SFelipe Balbi 185653668cSAnton Tikhomirov #include <linux/usb/otg-fsm.h> 1994ae9843SFelipe Balbi #include <linux/usb/otg.h> 2094ae9843SFelipe Balbi #include <linux/ioctl.h> 2194ae9843SFelipe Balbi 2294ae9843SFelipe Balbi /* USB Command Register Bit Masks */ 2394ae9843SFelipe Balbi #define USB_CMD_RUN_STOP (0x1<<0) 2494ae9843SFelipe Balbi #define USB_CMD_CTRL_RESET (0x1<<1) 2594ae9843SFelipe Balbi #define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4) 2694ae9843SFelipe Balbi #define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5) 2794ae9843SFelipe Balbi #define USB_CMD_INT_AA_DOORBELL (0x1<<6) 2894ae9843SFelipe Balbi #define USB_CMD_ASP (0x3<<8) 2994ae9843SFelipe Balbi #define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11) 3094ae9843SFelipe Balbi #define USB_CMD_SUTW (0x1<<13) 3194ae9843SFelipe Balbi #define USB_CMD_ATDTW (0x1<<14) 3294ae9843SFelipe Balbi #define USB_CMD_ITC (0xFF<<16) 3394ae9843SFelipe Balbi 3494ae9843SFelipe Balbi /* bit 15,3,2 are frame list size */ 3594ae9843SFelipe Balbi #define USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2) 3694ae9843SFelipe Balbi #define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2) 3794ae9843SFelipe Balbi #define USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2) 3894ae9843SFelipe Balbi #define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2) 3994ae9843SFelipe Balbi #define USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2) 4094ae9843SFelipe Balbi #define USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2) 4194ae9843SFelipe Balbi #define USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2) 4294ae9843SFelipe Balbi #define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2) 4394ae9843SFelipe Balbi 4494ae9843SFelipe Balbi /* bit 9-8 are async schedule park mode count */ 4594ae9843SFelipe Balbi #define USB_CMD_ASP_00 (0x0<<8) 4694ae9843SFelipe Balbi #define USB_CMD_ASP_01 (0x1<<8) 4794ae9843SFelipe Balbi #define USB_CMD_ASP_10 (0x2<<8) 4894ae9843SFelipe Balbi #define USB_CMD_ASP_11 (0x3<<8) 4994ae9843SFelipe Balbi #define USB_CMD_ASP_BIT_POS (8) 5094ae9843SFelipe Balbi 5194ae9843SFelipe Balbi /* bit 23-16 are interrupt threshold control */ 5294ae9843SFelipe Balbi #define USB_CMD_ITC_NO_THRESHOLD (0x00<<16) 5394ae9843SFelipe Balbi #define USB_CMD_ITC_1_MICRO_FRM (0x01<<16) 5494ae9843SFelipe Balbi #define USB_CMD_ITC_2_MICRO_FRM (0x02<<16) 5594ae9843SFelipe Balbi #define USB_CMD_ITC_4_MICRO_FRM (0x04<<16) 5694ae9843SFelipe Balbi #define USB_CMD_ITC_8_MICRO_FRM (0x08<<16) 5794ae9843SFelipe Balbi #define USB_CMD_ITC_16_MICRO_FRM (0x10<<16) 5894ae9843SFelipe Balbi #define USB_CMD_ITC_32_MICRO_FRM (0x20<<16) 5994ae9843SFelipe Balbi #define USB_CMD_ITC_64_MICRO_FRM (0x40<<16) 6094ae9843SFelipe Balbi #define USB_CMD_ITC_BIT_POS (16) 6194ae9843SFelipe Balbi 6294ae9843SFelipe Balbi /* USB Status Register Bit Masks */ 6394ae9843SFelipe Balbi #define USB_STS_INT (0x1<<0) 6494ae9843SFelipe Balbi #define USB_STS_ERR (0x1<<1) 6594ae9843SFelipe Balbi #define USB_STS_PORT_CHANGE (0x1<<2) 6694ae9843SFelipe Balbi #define USB_STS_FRM_LST_ROLL (0x1<<3) 6794ae9843SFelipe Balbi #define USB_STS_SYS_ERR (0x1<<4) 6894ae9843SFelipe Balbi #define USB_STS_IAA (0x1<<5) 6994ae9843SFelipe Balbi #define USB_STS_RESET_RECEIVED (0x1<<6) 7094ae9843SFelipe Balbi #define USB_STS_SOF (0x1<<7) 7194ae9843SFelipe Balbi #define USB_STS_DCSUSPEND (0x1<<8) 7294ae9843SFelipe Balbi #define USB_STS_HC_HALTED (0x1<<12) 7394ae9843SFelipe Balbi #define USB_STS_RCL (0x1<<13) 7494ae9843SFelipe Balbi #define USB_STS_PERIODIC_SCHEDULE (0x1<<14) 7594ae9843SFelipe Balbi #define USB_STS_ASYNC_SCHEDULE (0x1<<15) 7694ae9843SFelipe Balbi 7794ae9843SFelipe Balbi /* USB Interrupt Enable Register Bit Masks */ 7894ae9843SFelipe Balbi #define USB_INTR_INT_EN (0x1<<0) 7994ae9843SFelipe Balbi #define USB_INTR_ERR_INT_EN (0x1<<1) 8094ae9843SFelipe Balbi #define USB_INTR_PC_DETECT_EN (0x1<<2) 8194ae9843SFelipe Balbi #define USB_INTR_FRM_LST_ROLL_EN (0x1<<3) 8294ae9843SFelipe Balbi #define USB_INTR_SYS_ERR_EN (0x1<<4) 8394ae9843SFelipe Balbi #define USB_INTR_ASYN_ADV_EN (0x1<<5) 8494ae9843SFelipe Balbi #define USB_INTR_RESET_EN (0x1<<6) 8594ae9843SFelipe Balbi #define USB_INTR_SOF_EN (0x1<<7) 8694ae9843SFelipe Balbi #define USB_INTR_DEVICE_SUSPEND (0x1<<8) 8794ae9843SFelipe Balbi 8894ae9843SFelipe Balbi /* Device Address bit masks */ 8994ae9843SFelipe Balbi #define USB_DEVICE_ADDRESS_MASK (0x7F<<25) 9094ae9843SFelipe Balbi #define USB_DEVICE_ADDRESS_BIT_POS (25) 9194ae9843SFelipe Balbi /* PORTSC Register Bit Masks,Only one PORT in OTG mode*/ 9294ae9843SFelipe Balbi #define PORTSC_CURRENT_CONNECT_STATUS (0x1<<0) 9394ae9843SFelipe Balbi #define PORTSC_CONNECT_STATUS_CHANGE (0x1<<1) 9494ae9843SFelipe Balbi #define PORTSC_PORT_ENABLE (0x1<<2) 9594ae9843SFelipe Balbi #define PORTSC_PORT_EN_DIS_CHANGE (0x1<<3) 9694ae9843SFelipe Balbi #define PORTSC_OVER_CURRENT_ACT (0x1<<4) 9794ae9843SFelipe Balbi #define PORTSC_OVER_CUURENT_CHG (0x1<<5) 9894ae9843SFelipe Balbi #define PORTSC_PORT_FORCE_RESUME (0x1<<6) 9994ae9843SFelipe Balbi #define PORTSC_PORT_SUSPEND (0x1<<7) 10094ae9843SFelipe Balbi #define PORTSC_PORT_RESET (0x1<<8) 10194ae9843SFelipe Balbi #define PORTSC_LINE_STATUS_BITS (0x3<<10) 10294ae9843SFelipe Balbi #define PORTSC_PORT_POWER (0x1<<12) 10394ae9843SFelipe Balbi #define PORTSC_PORT_INDICTOR_CTRL (0x3<<14) 10494ae9843SFelipe Balbi #define PORTSC_PORT_TEST_CTRL (0xF<<16) 10594ae9843SFelipe Balbi #define PORTSC_WAKE_ON_CONNECT_EN (0x1<<20) 10694ae9843SFelipe Balbi #define PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21) 10794ae9843SFelipe Balbi #define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22) 10894ae9843SFelipe Balbi #define PORTSC_PHY_LOW_POWER_SPD (0x1<<23) 10994ae9843SFelipe Balbi #define PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24) 11094ae9843SFelipe Balbi #define PORTSC_PORT_SPEED_MASK (0x3<<26) 11194ae9843SFelipe Balbi #define PORTSC_TRANSCEIVER_WIDTH (0x1<<28) 11294ae9843SFelipe Balbi #define PORTSC_PHY_TYPE_SEL (0x3<<30) 11394ae9843SFelipe Balbi /* bit 11-10 are line status */ 11494ae9843SFelipe Balbi #define PORTSC_LINE_STATUS_SE0 (0x0<<10) 11594ae9843SFelipe Balbi #define PORTSC_LINE_STATUS_JSTATE (0x1<<10) 11694ae9843SFelipe Balbi #define PORTSC_LINE_STATUS_KSTATE (0x2<<10) 11794ae9843SFelipe Balbi #define PORTSC_LINE_STATUS_UNDEF (0x3<<10) 11894ae9843SFelipe Balbi #define PORTSC_LINE_STATUS_BIT_POS (10) 11994ae9843SFelipe Balbi 12094ae9843SFelipe Balbi /* bit 15-14 are port indicator control */ 12194ae9843SFelipe Balbi #define PORTSC_PIC_OFF (0x0<<14) 12294ae9843SFelipe Balbi #define PORTSC_PIC_AMBER (0x1<<14) 12394ae9843SFelipe Balbi #define PORTSC_PIC_GREEN (0x2<<14) 12494ae9843SFelipe Balbi #define PORTSC_PIC_UNDEF (0x3<<14) 12594ae9843SFelipe Balbi #define PORTSC_PIC_BIT_POS (14) 12694ae9843SFelipe Balbi 12794ae9843SFelipe Balbi /* bit 19-16 are port test control */ 12894ae9843SFelipe Balbi #define PORTSC_PTC_DISABLE (0x0<<16) 12994ae9843SFelipe Balbi #define PORTSC_PTC_JSTATE (0x1<<16) 13094ae9843SFelipe Balbi #define PORTSC_PTC_KSTATE (0x2<<16) 13194ae9843SFelipe Balbi #define PORTSC_PTC_SEQNAK (0x3<<16) 13294ae9843SFelipe Balbi #define PORTSC_PTC_PACKET (0x4<<16) 13394ae9843SFelipe Balbi #define PORTSC_PTC_FORCE_EN (0x5<<16) 13494ae9843SFelipe Balbi #define PORTSC_PTC_BIT_POS (16) 13594ae9843SFelipe Balbi 13694ae9843SFelipe Balbi /* bit 27-26 are port speed */ 13794ae9843SFelipe Balbi #define PORTSC_PORT_SPEED_FULL (0x0<<26) 13894ae9843SFelipe Balbi #define PORTSC_PORT_SPEED_LOW (0x1<<26) 13994ae9843SFelipe Balbi #define PORTSC_PORT_SPEED_HIGH (0x2<<26) 14094ae9843SFelipe Balbi #define PORTSC_PORT_SPEED_UNDEF (0x3<<26) 14194ae9843SFelipe Balbi #define PORTSC_SPEED_BIT_POS (26) 14294ae9843SFelipe Balbi 14394ae9843SFelipe Balbi /* bit 28 is parallel transceiver width for UTMI interface */ 14494ae9843SFelipe Balbi #define PORTSC_PTW (0x1<<28) 14594ae9843SFelipe Balbi #define PORTSC_PTW_8BIT (0x0<<28) 14694ae9843SFelipe Balbi #define PORTSC_PTW_16BIT (0x1<<28) 14794ae9843SFelipe Balbi 14894ae9843SFelipe Balbi /* bit 31-30 are port transceiver select */ 14994ae9843SFelipe Balbi #define PORTSC_PTS_UTMI (0x0<<30) 15094ae9843SFelipe Balbi #define PORTSC_PTS_ULPI (0x2<<30) 15194ae9843SFelipe Balbi #define PORTSC_PTS_FSLS_SERIAL (0x3<<30) 15294ae9843SFelipe Balbi #define PORTSC_PTS_BIT_POS (30) 15394ae9843SFelipe Balbi 15494ae9843SFelipe Balbi #define PORTSC_W1C_BITS \ 15594ae9843SFelipe Balbi (PORTSC_CONNECT_STATUS_CHANGE | \ 15694ae9843SFelipe Balbi PORTSC_PORT_EN_DIS_CHANGE | \ 15794ae9843SFelipe Balbi PORTSC_OVER_CUURENT_CHG) 15894ae9843SFelipe Balbi 15994ae9843SFelipe Balbi /* OTG Status Control Register Bit Masks */ 16094ae9843SFelipe Balbi #define OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0) 16194ae9843SFelipe Balbi #define OTGSC_CTRL_VBUS_CHARGE (0x1<<1) 16294ae9843SFelipe Balbi #define OTGSC_CTRL_OTG_TERMINATION (0x1<<3) 16394ae9843SFelipe Balbi #define OTGSC_CTRL_DATA_PULSING (0x1<<4) 16494ae9843SFelipe Balbi #define OTGSC_CTRL_ID_PULL_EN (0x1<<5) 16594ae9843SFelipe Balbi #define OTGSC_HA_DATA_PULSE (0x1<<6) 16694ae9843SFelipe Balbi #define OTGSC_HA_BA (0x1<<7) 16794ae9843SFelipe Balbi #define OTGSC_STS_USB_ID (0x1<<8) 16894ae9843SFelipe Balbi #define OTGSC_STS_A_VBUS_VALID (0x1<<9) 16994ae9843SFelipe Balbi #define OTGSC_STS_A_SESSION_VALID (0x1<<10) 17094ae9843SFelipe Balbi #define OTGSC_STS_B_SESSION_VALID (0x1<<11) 17194ae9843SFelipe Balbi #define OTGSC_STS_B_SESSION_END (0x1<<12) 17294ae9843SFelipe Balbi #define OTGSC_STS_1MS_TOGGLE (0x1<<13) 17394ae9843SFelipe Balbi #define OTGSC_STS_DATA_PULSING (0x1<<14) 17494ae9843SFelipe Balbi #define OTGSC_INTSTS_USB_ID (0x1<<16) 17594ae9843SFelipe Balbi #define OTGSC_INTSTS_A_VBUS_VALID (0x1<<17) 17694ae9843SFelipe Balbi #define OTGSC_INTSTS_A_SESSION_VALID (0x1<<18) 17794ae9843SFelipe Balbi #define OTGSC_INTSTS_B_SESSION_VALID (0x1<<19) 17894ae9843SFelipe Balbi #define OTGSC_INTSTS_B_SESSION_END (0x1<<20) 17994ae9843SFelipe Balbi #define OTGSC_INTSTS_1MS (0x1<<21) 18094ae9843SFelipe Balbi #define OTGSC_INTSTS_DATA_PULSING (0x1<<22) 18194ae9843SFelipe Balbi #define OTGSC_INTR_USB_ID_EN (0x1<<24) 18294ae9843SFelipe Balbi #define OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25) 18394ae9843SFelipe Balbi #define OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26) 18494ae9843SFelipe Balbi #define OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27) 18594ae9843SFelipe Balbi #define OTGSC_INTR_B_SESSION_END_EN (0x1<<28) 18694ae9843SFelipe Balbi #define OTGSC_INTR_1MS_TIMER_EN (0x1<<29) 18794ae9843SFelipe Balbi #define OTGSC_INTR_DATA_PULSING_EN (0x1<<30) 18894ae9843SFelipe Balbi #define OTGSC_INTSTS_MASK (0x00ff0000) 18994ae9843SFelipe Balbi 19094ae9843SFelipe Balbi /* USB MODE Register Bit Masks */ 19194ae9843SFelipe Balbi #define USB_MODE_CTRL_MODE_IDLE (0x0<<0) 19294ae9843SFelipe Balbi #define USB_MODE_CTRL_MODE_DEVICE (0x2<<0) 19394ae9843SFelipe Balbi #define USB_MODE_CTRL_MODE_HOST (0x3<<0) 19494ae9843SFelipe Balbi #define USB_MODE_CTRL_MODE_RSV (0x1<<0) 19594ae9843SFelipe Balbi #define USB_MODE_SETUP_LOCK_OFF (0x1<<3) 19694ae9843SFelipe Balbi #define USB_MODE_STREAM_DISABLE (0x1<<4) 19794ae9843SFelipe Balbi #define USB_MODE_ES (0x1<<2) /* Endian Select */ 19894ae9843SFelipe Balbi 19994ae9843SFelipe Balbi /* control Register Bit Masks */ 20094ae9843SFelipe Balbi #define USB_CTRL_IOENB (0x1<<2) 20194ae9843SFelipe Balbi #define USB_CTRL_ULPI_INT0EN (0x1<<0) 20294ae9843SFelipe Balbi 20394ae9843SFelipe Balbi /* BCSR5 */ 20494ae9843SFelipe Balbi #define BCSR5_INT_USB (0x02) 20594ae9843SFelipe Balbi 20694ae9843SFelipe Balbi /* USB module clk cfg */ 20794ae9843SFelipe Balbi #define SCCR_OFFS (0xA08) 20894ae9843SFelipe Balbi #define SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */ 20994ae9843SFelipe Balbi #define SCCR_USB_MPHCM_11 (0x00c00000) 21094ae9843SFelipe Balbi #define SCCR_USB_MPHCM_01 (0x00400000) 21194ae9843SFelipe Balbi #define SCCR_USB_MPHCM_10 (0x00800000) 21294ae9843SFelipe Balbi #define SCCR_USB_DRCM_11 (0x00300000) 21394ae9843SFelipe Balbi #define SCCR_USB_DRCM_01 (0x00100000) 21494ae9843SFelipe Balbi #define SCCR_USB_DRCM_10 (0x00200000) 21594ae9843SFelipe Balbi 21694ae9843SFelipe Balbi #define SICRL_OFFS (0x114) 21794ae9843SFelipe Balbi #define SICRL_USB0 (0x40000000) 21894ae9843SFelipe Balbi #define SICRL_USB1 (0x20000000) 21994ae9843SFelipe Balbi 22094ae9843SFelipe Balbi #define SICRH_OFFS (0x118) 22194ae9843SFelipe Balbi #define SICRH_USB_UTMI (0x00020000) 22294ae9843SFelipe Balbi 22394ae9843SFelipe Balbi /* OTG interrupt enable bit masks */ 22494ae9843SFelipe Balbi #define OTGSC_INTERRUPT_ENABLE_BITS_MASK \ 22594ae9843SFelipe Balbi (OTGSC_INTR_USB_ID_EN | \ 22694ae9843SFelipe Balbi OTGSC_INTR_1MS_TIMER_EN | \ 22794ae9843SFelipe Balbi OTGSC_INTR_A_VBUS_VALID_EN | \ 22894ae9843SFelipe Balbi OTGSC_INTR_A_SESSION_VALID_EN | \ 22994ae9843SFelipe Balbi OTGSC_INTR_B_SESSION_VALID_EN | \ 23094ae9843SFelipe Balbi OTGSC_INTR_B_SESSION_END_EN | \ 23194ae9843SFelipe Balbi OTGSC_INTR_DATA_PULSING_EN) 23294ae9843SFelipe Balbi 23394ae9843SFelipe Balbi /* OTG interrupt status bit masks */ 23494ae9843SFelipe Balbi #define OTGSC_INTERRUPT_STATUS_BITS_MASK \ 23594ae9843SFelipe Balbi (OTGSC_INTSTS_USB_ID | \ 23694ae9843SFelipe Balbi OTGSC_INTR_1MS_TIMER_EN | \ 23794ae9843SFelipe Balbi OTGSC_INTSTS_A_VBUS_VALID | \ 23894ae9843SFelipe Balbi OTGSC_INTSTS_A_SESSION_VALID | \ 23994ae9843SFelipe Balbi OTGSC_INTSTS_B_SESSION_VALID | \ 24094ae9843SFelipe Balbi OTGSC_INTSTS_B_SESSION_END | \ 24194ae9843SFelipe Balbi OTGSC_INTSTS_DATA_PULSING) 24294ae9843SFelipe Balbi 24394ae9843SFelipe Balbi /* 24494ae9843SFelipe Balbi * A-DEVICE timing constants 24594ae9843SFelipe Balbi */ 24694ae9843SFelipe Balbi 24794ae9843SFelipe Balbi /* Wait for VBUS Rise */ 24894ae9843SFelipe Balbi #define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */ 24994ae9843SFelipe Balbi 25094ae9843SFelipe Balbi /* Wait for B-Connect */ 25194ae9843SFelipe Balbi #define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2 25294ae9843SFelipe Balbi * This is only used to get out of 25394ae9843SFelipe Balbi * OTG_STATE_A_WAIT_BCON state if there was 25494ae9843SFelipe Balbi * no connection for these many milliseconds 25594ae9843SFelipe Balbi */ 25694ae9843SFelipe Balbi 25794ae9843SFelipe Balbi /* A-Idle to B-Disconnect */ 25894ae9843SFelipe Balbi /* It is necessary for this timer to be more than 750 ms because of a bug in OPT 25994ae9843SFelipe Balbi * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated 26094ae9843SFelipe Balbi * in the test description 26194ae9843SFelipe Balbi */ 26294ae9843SFelipe Balbi #define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */ 26394ae9843SFelipe Balbi 26494ae9843SFelipe Balbi /* B-Idle to A-Disconnect */ 26594ae9843SFelipe Balbi #define TA_BIDL_ADIS (12) /* 3 to 200 ms */ 26694ae9843SFelipe Balbi 26794ae9843SFelipe Balbi /* B-device timing constants */ 26894ae9843SFelipe Balbi 26994ae9843SFelipe Balbi 27094ae9843SFelipe Balbi /* Data-Line Pulse Time*/ 27194ae9843SFelipe Balbi #define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */ 27294ae9843SFelipe Balbi #define TB_DATA_PLS_MIN (5) /* minimum 5 ms */ 27394ae9843SFelipe Balbi #define TB_DATA_PLS_MAX (10) /* maximum 10 ms */ 27494ae9843SFelipe Balbi 27594ae9843SFelipe Balbi /* SRP Initiate Time */ 27694ae9843SFelipe Balbi #define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */ 27794ae9843SFelipe Balbi 27894ae9843SFelipe Balbi /* SRP Fail Time */ 27994ae9843SFelipe Balbi #define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/ 28094ae9843SFelipe Balbi 28194ae9843SFelipe Balbi /* SRP result wait time */ 28294ae9843SFelipe Balbi #define TB_SRP_WAIT (60) 28394ae9843SFelipe Balbi 28494ae9843SFelipe Balbi /* VBus time */ 28594ae9843SFelipe Balbi #define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */ 28694ae9843SFelipe Balbi 28794ae9843SFelipe Balbi /* Discharge time */ 28894ae9843SFelipe Balbi /* This time should be less than 10ms. It varies from system to system. */ 28994ae9843SFelipe Balbi #define TB_VBUS_DSCHRG (8) 29094ae9843SFelipe Balbi 29194ae9843SFelipe Balbi /* A-SE0 to B-Reset */ 29294ae9843SFelipe Balbi #define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */ 29394ae9843SFelipe Balbi 29494ae9843SFelipe Balbi /* A bus suspend timer before we can switch to b_wait_aconn */ 29594ae9843SFelipe Balbi #define TB_A_SUSPEND (7) 29694ae9843SFelipe Balbi #define TB_BUS_RESUME (12) 29794ae9843SFelipe Balbi 29894ae9843SFelipe Balbi /* SE0 Time Before SRP */ 29994ae9843SFelipe Balbi #define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */ 30094ae9843SFelipe Balbi 30194ae9843SFelipe Balbi #define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate) 30294ae9843SFelipe Balbi 30394ae9843SFelipe Balbi struct usb_dr_mmap { 30494ae9843SFelipe Balbi /* Capability register */ 30594ae9843SFelipe Balbi u8 res1[256]; 30694ae9843SFelipe Balbi u16 caplength; /* Capability Register Length */ 30794ae9843SFelipe Balbi u16 hciversion; /* Host Controller Interface Version */ 30894ae9843SFelipe Balbi u32 hcsparams; /* Host Controller Structual Parameters */ 30994ae9843SFelipe Balbi u32 hccparams; /* Host Controller Capability Parameters */ 31094ae9843SFelipe Balbi u8 res2[20]; 31194ae9843SFelipe Balbi u32 dciversion; /* Device Controller Interface Version */ 31294ae9843SFelipe Balbi u32 dccparams; /* Device Controller Capability Parameters */ 31394ae9843SFelipe Balbi u8 res3[24]; 31494ae9843SFelipe Balbi /* Operation register */ 31594ae9843SFelipe Balbi u32 usbcmd; /* USB Command Register */ 31694ae9843SFelipe Balbi u32 usbsts; /* USB Status Register */ 31794ae9843SFelipe Balbi u32 usbintr; /* USB Interrupt Enable Register */ 31894ae9843SFelipe Balbi u32 frindex; /* Frame Index Register */ 31994ae9843SFelipe Balbi u8 res4[4]; 32094ae9843SFelipe Balbi u32 deviceaddr; /* Device Address */ 32194ae9843SFelipe Balbi u32 endpointlistaddr; /* Endpoint List Address Register */ 32294ae9843SFelipe Balbi u8 res5[4]; 32394ae9843SFelipe Balbi u32 burstsize; /* Master Interface Data Burst Size Register */ 32494ae9843SFelipe Balbi u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ 32594ae9843SFelipe Balbi u8 res6[8]; 32694ae9843SFelipe Balbi u32 ulpiview; /* ULPI register access */ 32794ae9843SFelipe Balbi u8 res7[12]; 32894ae9843SFelipe Balbi u32 configflag; /* Configure Flag Register */ 32994ae9843SFelipe Balbi u32 portsc; /* Port 1 Status and Control Register */ 33094ae9843SFelipe Balbi u8 res8[28]; 33194ae9843SFelipe Balbi u32 otgsc; /* On-The-Go Status and Control */ 33294ae9843SFelipe Balbi u32 usbmode; /* USB Mode Register */ 33394ae9843SFelipe Balbi u32 endptsetupstat; /* Endpoint Setup Status Register */ 33494ae9843SFelipe Balbi u32 endpointprime; /* Endpoint Initialization Register */ 33594ae9843SFelipe Balbi u32 endptflush; /* Endpoint Flush Register */ 33694ae9843SFelipe Balbi u32 endptstatus; /* Endpoint Status Register */ 33794ae9843SFelipe Balbi u32 endptcomplete; /* Endpoint Complete Register */ 33894ae9843SFelipe Balbi u32 endptctrl[6]; /* Endpoint Control Registers */ 33994ae9843SFelipe Balbi u8 res9[552]; 34094ae9843SFelipe Balbi u32 snoop1; 34194ae9843SFelipe Balbi u32 snoop2; 34294ae9843SFelipe Balbi u32 age_cnt_thresh; /* Age Count Threshold Register */ 34394ae9843SFelipe Balbi u32 pri_ctrl; /* Priority Control Register */ 34494ae9843SFelipe Balbi u32 si_ctrl; /* System Interface Control Register */ 34594ae9843SFelipe Balbi u8 res10[236]; 34694ae9843SFelipe Balbi u32 control; /* General Purpose Control Register */ 34794ae9843SFelipe Balbi }; 34894ae9843SFelipe Balbi 34994ae9843SFelipe Balbi struct fsl_otg_timer { 35094ae9843SFelipe Balbi unsigned long expires; /* Number of count increase to timeout */ 35194ae9843SFelipe Balbi unsigned long count; /* Tick counter */ 35294ae9843SFelipe Balbi void (*function)(unsigned long); /* Timeout function */ 35394ae9843SFelipe Balbi unsigned long data; /* Data passed to function */ 35494ae9843SFelipe Balbi struct list_head list; 35594ae9843SFelipe Balbi }; 35694ae9843SFelipe Balbi 35794ae9843SFelipe Balbi inline struct fsl_otg_timer *otg_timer_initializer 35894ae9843SFelipe Balbi (void (*function)(unsigned long), unsigned long expires, unsigned long data) 35994ae9843SFelipe Balbi { 36094ae9843SFelipe Balbi struct fsl_otg_timer *timer; 36194ae9843SFelipe Balbi 36294ae9843SFelipe Balbi timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL); 36394ae9843SFelipe Balbi if (!timer) 36494ae9843SFelipe Balbi return NULL; 36594ae9843SFelipe Balbi timer->function = function; 36694ae9843SFelipe Balbi timer->expires = expires; 36794ae9843SFelipe Balbi timer->data = data; 36894ae9843SFelipe Balbi return timer; 36994ae9843SFelipe Balbi } 37094ae9843SFelipe Balbi 37194ae9843SFelipe Balbi struct fsl_otg { 37294ae9843SFelipe Balbi struct usb_phy phy; 37394ae9843SFelipe Balbi struct otg_fsm fsm; 37494ae9843SFelipe Balbi struct usb_dr_mmap *dr_mem_map; 37594ae9843SFelipe Balbi struct delayed_work otg_event; 37694ae9843SFelipe Balbi 37794ae9843SFelipe Balbi /* used for usb host */ 37894ae9843SFelipe Balbi struct work_struct work_wq; 37994ae9843SFelipe Balbi u8 host_working; 38094ae9843SFelipe Balbi 38194ae9843SFelipe Balbi int irq; 38294ae9843SFelipe Balbi }; 38394ae9843SFelipe Balbi 38494ae9843SFelipe Balbi struct fsl_otg_config { 38594ae9843SFelipe Balbi u8 otg_port; 38694ae9843SFelipe Balbi }; 38794ae9843SFelipe Balbi 38894ae9843SFelipe Balbi /* For SRP and HNP handle */ 38994ae9843SFelipe Balbi #define FSL_OTG_MAJOR 240 39094ae9843SFelipe Balbi #define FSL_OTG_NAME "fsl-usb2-otg" 39194ae9843SFelipe Balbi /* Command to OTG driver ioctl */ 39294ae9843SFelipe Balbi #define OTG_IOCTL_MAGIC FSL_OTG_MAJOR 39394ae9843SFelipe Balbi /* if otg work as host, it should return 1, otherwise return 0 */ 39494ae9843SFelipe Balbi #define GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int) 39594ae9843SFelipe Balbi #define SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int) 39694ae9843SFelipe Balbi #define SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int) 39794ae9843SFelipe Balbi #define SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int) 39894ae9843SFelipe Balbi #define SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int) 39994ae9843SFelipe Balbi #define GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int) 40094ae9843SFelipe Balbi #define GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int) 40194ae9843SFelipe Balbi #define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int) 40294ae9843SFelipe Balbi #define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int) 40394ae9843SFelipe Balbi 404da8cc167SAnton Tikhomirov void fsl_otg_add_timer(struct otg_fsm *fsm, void *timer); 405da8cc167SAnton Tikhomirov void fsl_otg_del_timer(struct otg_fsm *fsm, void *timer); 40694ae9843SFelipe Balbi void fsl_otg_pulse_vbus(void); 407