1 /* 2 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface 3 * 4 * Copyright (C) 2006 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/errno.h> 14 #include <linux/init.h> 15 #include <linux/usb.h> 16 #include <linux/platform_device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/omap-dma.h> 20 21 #include "musb_core.h" 22 #include "tusb6010.h" 23 24 #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data) 25 26 #define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */ 27 28 #define OMAP24XX_DMA_EXT_DMAREQ0 2 29 #define OMAP24XX_DMA_EXT_DMAREQ1 3 30 #define OMAP242X_DMA_EXT_DMAREQ2 14 31 #define OMAP242X_DMA_EXT_DMAREQ3 15 32 #define OMAP242X_DMA_EXT_DMAREQ4 16 33 #define OMAP242X_DMA_EXT_DMAREQ5 64 34 35 struct tusb_omap_dma_ch { 36 struct musb *musb; 37 void __iomem *tbase; 38 unsigned long phys_offset; 39 int epnum; 40 u8 tx; 41 struct musb_hw_ep *hw_ep; 42 43 int ch; 44 s8 dmareq; 45 s8 sync_dev; 46 47 struct tusb_omap_dma *tusb_dma; 48 49 dma_addr_t dma_addr; 50 51 u32 len; 52 u16 packet_sz; 53 u16 transfer_packet_sz; 54 u32 transfer_len; 55 u32 completed_len; 56 }; 57 58 struct tusb_omap_dma { 59 struct dma_controller controller; 60 struct musb *musb; 61 void __iomem *tbase; 62 63 int ch; 64 s8 dmareq; 65 s8 sync_dev; 66 unsigned multichannel:1; 67 }; 68 69 /* 70 * Allocate dmareq0 to the current channel unless it's already taken 71 */ 72 static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat) 73 { 74 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 75 76 if (reg != 0) { 77 dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n", 78 chdat->epnum, reg & 0xf); 79 return -EAGAIN; 80 } 81 82 if (chdat->tx) 83 reg = (1 << 4) | chdat->epnum; 84 else 85 reg = chdat->epnum; 86 87 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 88 89 return 0; 90 } 91 92 static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat) 93 { 94 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 95 96 if ((reg & 0xf) != chdat->epnum) { 97 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n", 98 chdat->epnum, reg & 0xf); 99 return; 100 } 101 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0); 102 } 103 104 /* 105 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in 106 * musb_gadget.c. 107 */ 108 static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data) 109 { 110 struct dma_channel *channel = (struct dma_channel *)data; 111 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 112 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 113 struct musb *musb = chdat->musb; 114 struct device *dev = musb->controller; 115 struct musb_hw_ep *hw_ep = chdat->hw_ep; 116 void __iomem *ep_conf = hw_ep->conf; 117 void __iomem *mbase = musb->mregs; 118 unsigned long remaining, flags, pio; 119 int ch; 120 121 spin_lock_irqsave(&musb->lock, flags); 122 123 if (tusb_dma->multichannel) 124 ch = chdat->ch; 125 else 126 ch = tusb_dma->ch; 127 128 if (ch_status != OMAP_DMA_BLOCK_IRQ) 129 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status); 130 131 dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n", 132 chdat->epnum, chdat->tx ? "tx" : "rx", 133 ch, ch_status); 134 135 if (chdat->tx) 136 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); 137 else 138 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); 139 140 remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining); 141 142 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */ 143 if (unlikely(remaining > chdat->transfer_len)) { 144 dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n", 145 chdat->tx ? "tx" : "rx", chdat->ch, 146 remaining); 147 remaining = 0; 148 } 149 150 channel->actual_len = chdat->transfer_len - remaining; 151 pio = chdat->len - channel->actual_len; 152 153 dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len); 154 155 /* Transfer remaining 1 - 31 bytes */ 156 if (pio > 0 && pio < 32) { 157 u8 *buf; 158 159 dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio); 160 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len; 161 if (chdat->tx) { 162 dma_unmap_single(dev, chdat->dma_addr, 163 chdat->transfer_len, 164 DMA_TO_DEVICE); 165 musb_write_fifo(hw_ep, pio, buf); 166 } else { 167 dma_unmap_single(dev, chdat->dma_addr, 168 chdat->transfer_len, 169 DMA_FROM_DEVICE); 170 musb_read_fifo(hw_ep, pio, buf); 171 } 172 channel->actual_len += pio; 173 } 174 175 if (!tusb_dma->multichannel) 176 tusb_omap_free_shared_dmareq(chdat); 177 178 channel->status = MUSB_DMA_STATUS_FREE; 179 180 /* Handle only RX callbacks here. TX callbacks must be handled based 181 * on the TUSB DMA status interrupt. 182 * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback 183 * interrupt for RX and TX. 184 */ 185 if (!chdat->tx) 186 musb_dma_completion(musb, chdat->epnum, chdat->tx); 187 188 /* We must terminate short tx transfers manually by setting TXPKTRDY. 189 * REVISIT: This same problem may occur with other MUSB dma as well. 190 * Easy to test with g_ether by pinging the MUSB board with ping -s54. 191 */ 192 if ((chdat->transfer_len < chdat->packet_sz) 193 || (chdat->transfer_len % chdat->packet_sz != 0)) { 194 u16 csr; 195 196 if (chdat->tx) { 197 dev_dbg(musb->controller, "terminating short tx packet\n"); 198 musb_ep_select(mbase, chdat->epnum); 199 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 200 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY 201 | MUSB_TXCSR_P_WZC_BITS; 202 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); 203 } 204 } 205 206 spin_unlock_irqrestore(&musb->lock, flags); 207 } 208 209 static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz, 210 u8 rndis_mode, dma_addr_t dma_addr, u32 len) 211 { 212 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 213 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 214 struct musb *musb = chdat->musb; 215 struct device *dev = musb->controller; 216 struct musb_hw_ep *hw_ep = chdat->hw_ep; 217 void __iomem *mbase = musb->mregs; 218 void __iomem *ep_conf = hw_ep->conf; 219 dma_addr_t fifo = hw_ep->fifo_sync; 220 struct omap_dma_channel_params dma_params; 221 u32 dma_remaining; 222 int src_burst, dst_burst; 223 u16 csr; 224 int ch; 225 s8 dmareq; 226 s8 sync_dev; 227 228 if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz)) 229 return false; 230 231 /* 232 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE 233 * register which will cause missed DMA interrupt. We could try to 234 * use a timer for the callback, but it is unsafe as the XFR_SIZE 235 * register is corrupt, and we won't know if the DMA worked. 236 */ 237 if (dma_addr & 0x2) 238 return false; 239 240 /* 241 * Because of HW issue #10, it seems like mixing sync DMA and async 242 * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before 243 * using the channel for DMA. 244 */ 245 if (chdat->tx) 246 dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); 247 else 248 dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); 249 250 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining); 251 if (dma_remaining) { 252 dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n", 253 chdat->tx ? "tx" : "rx", chdat->ch, 254 dma_remaining); 255 return false; 256 } 257 258 chdat->transfer_len = len & ~0x1f; 259 260 if (len < packet_sz) 261 chdat->transfer_packet_sz = chdat->transfer_len; 262 else 263 chdat->transfer_packet_sz = packet_sz; 264 265 if (tusb_dma->multichannel) { 266 ch = chdat->ch; 267 dmareq = chdat->dmareq; 268 sync_dev = chdat->sync_dev; 269 } else { 270 if (tusb_omap_use_shared_dmareq(chdat) != 0) { 271 dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum); 272 return false; 273 } 274 if (tusb_dma->ch < 0) { 275 /* REVISIT: This should get blocked earlier, happens 276 * with MSC ErrorRecoveryTest 277 */ 278 WARN_ON(1); 279 return false; 280 } 281 282 ch = tusb_dma->ch; 283 dmareq = tusb_dma->dmareq; 284 sync_dev = tusb_dma->sync_dev; 285 omap_set_dma_callback(ch, tusb_omap_dma_cb, channel); 286 } 287 288 chdat->packet_sz = packet_sz; 289 chdat->len = len; 290 channel->actual_len = 0; 291 chdat->dma_addr = dma_addr; 292 channel->status = MUSB_DMA_STATUS_BUSY; 293 294 /* Since we're recycling dma areas, we need to clean or invalidate */ 295 if (chdat->tx) 296 dma_map_single(dev, phys_to_virt(dma_addr), len, 297 DMA_TO_DEVICE); 298 else 299 dma_map_single(dev, phys_to_virt(dma_addr), len, 300 DMA_FROM_DEVICE); 301 302 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */ 303 if ((dma_addr & 0x3) == 0) { 304 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32; 305 dma_params.elem_count = 8; /* Elements in frame */ 306 } else { 307 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16; 308 dma_params.elem_count = 16; /* Elements in frame */ 309 fifo = hw_ep->fifo_async; 310 } 311 312 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */ 313 314 dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n", 315 chdat->epnum, chdat->tx ? "tx" : "rx", 316 ch, dma_addr, chdat->transfer_len, len, 317 chdat->transfer_packet_sz, packet_sz); 318 319 /* 320 * Prepare omap DMA for transfer 321 */ 322 if (chdat->tx) { 323 dma_params.src_amode = OMAP_DMA_AMODE_POST_INC; 324 dma_params.src_start = (unsigned long)dma_addr; 325 dma_params.src_ei = 0; 326 dma_params.src_fi = 0; 327 328 dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX; 329 dma_params.dst_start = (unsigned long)fifo; 330 dma_params.dst_ei = 1; 331 dma_params.dst_fi = -31; /* Loop 32 byte window */ 332 333 dma_params.trigger = sync_dev; 334 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; 335 dma_params.src_or_dst_synch = 0; /* Dest sync */ 336 337 src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */ 338 dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */ 339 } else { 340 dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX; 341 dma_params.src_start = (unsigned long)fifo; 342 dma_params.src_ei = 1; 343 dma_params.src_fi = -31; /* Loop 32 byte window */ 344 345 dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC; 346 dma_params.dst_start = (unsigned long)dma_addr; 347 dma_params.dst_ei = 0; 348 dma_params.dst_fi = 0; 349 350 dma_params.trigger = sync_dev; 351 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; 352 dma_params.src_or_dst_synch = 1; /* Source sync */ 353 354 src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */ 355 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */ 356 } 357 358 dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n", 359 chdat->epnum, chdat->tx ? "tx" : "rx", 360 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16, 361 ((dma_addr & 0x3) == 0) ? "sync" : "async", 362 dma_params.src_start, dma_params.dst_start); 363 364 omap_set_dma_params(ch, &dma_params); 365 omap_set_dma_src_burst_mode(ch, src_burst); 366 omap_set_dma_dest_burst_mode(ch, dst_burst); 367 omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED); 368 369 /* 370 * Prepare MUSB for DMA transfer 371 */ 372 if (chdat->tx) { 373 musb_ep_select(mbase, chdat->epnum); 374 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 375 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB 376 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE); 377 csr &= ~MUSB_TXCSR_P_UNDERRUN; 378 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); 379 } else { 380 musb_ep_select(mbase, chdat->epnum); 381 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 382 csr |= MUSB_RXCSR_DMAENAB; 383 csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE); 384 musb_writew(hw_ep->regs, MUSB_RXCSR, 385 csr | MUSB_RXCSR_P_WZC_BITS); 386 } 387 388 /* 389 * Start DMA transfer 390 */ 391 omap_start_dma(ch); 392 393 if (chdat->tx) { 394 /* Send transfer_packet_sz packets at a time */ 395 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, 396 chdat->transfer_packet_sz); 397 398 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 399 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); 400 } else { 401 /* Receive transfer_packet_sz packets at a time */ 402 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, 403 chdat->transfer_packet_sz << 16); 404 405 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 406 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); 407 } 408 409 return true; 410 } 411 412 static int tusb_omap_dma_abort(struct dma_channel *channel) 413 { 414 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 415 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 416 417 if (!tusb_dma->multichannel) { 418 if (tusb_dma->ch >= 0) { 419 omap_stop_dma(tusb_dma->ch); 420 omap_free_dma(tusb_dma->ch); 421 tusb_dma->ch = -1; 422 } 423 424 tusb_dma->dmareq = -1; 425 tusb_dma->sync_dev = -1; 426 } 427 428 channel->status = MUSB_DMA_STATUS_FREE; 429 430 return 0; 431 } 432 433 static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat) 434 { 435 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 436 int i, dmareq_nr = -1; 437 438 const int sync_dev[6] = { 439 OMAP24XX_DMA_EXT_DMAREQ0, 440 OMAP24XX_DMA_EXT_DMAREQ1, 441 OMAP242X_DMA_EXT_DMAREQ2, 442 OMAP242X_DMA_EXT_DMAREQ3, 443 OMAP242X_DMA_EXT_DMAREQ4, 444 OMAP242X_DMA_EXT_DMAREQ5, 445 }; 446 447 for (i = 0; i < MAX_DMAREQ; i++) { 448 int cur = (reg & (0xf << (i * 5))) >> (i * 5); 449 if (cur == 0) { 450 dmareq_nr = i; 451 break; 452 } 453 } 454 455 if (dmareq_nr == -1) 456 return -EAGAIN; 457 458 reg |= (chdat->epnum << (dmareq_nr * 5)); 459 if (chdat->tx) 460 reg |= ((1 << 4) << (dmareq_nr * 5)); 461 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 462 463 chdat->dmareq = dmareq_nr; 464 chdat->sync_dev = sync_dev[chdat->dmareq]; 465 466 return 0; 467 } 468 469 static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat) 470 { 471 u32 reg; 472 473 if (!chdat || chdat->dmareq < 0) 474 return; 475 476 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 477 reg &= ~(0x1f << (chdat->dmareq * 5)); 478 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 479 480 chdat->dmareq = -1; 481 chdat->sync_dev = -1; 482 } 483 484 static struct dma_channel *dma_channel_pool[MAX_DMAREQ]; 485 486 static struct dma_channel * 487 tusb_omap_dma_allocate(struct dma_controller *c, 488 struct musb_hw_ep *hw_ep, 489 u8 tx) 490 { 491 int ret, i; 492 const char *dev_name; 493 struct tusb_omap_dma *tusb_dma; 494 struct musb *musb; 495 void __iomem *tbase; 496 struct dma_channel *channel = NULL; 497 struct tusb_omap_dma_ch *chdat = NULL; 498 u32 reg; 499 500 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 501 musb = tusb_dma->musb; 502 tbase = musb->ctrl_base; 503 504 reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 505 if (tx) 506 reg &= ~(1 << hw_ep->epnum); 507 else 508 reg &= ~(1 << (hw_ep->epnum + 15)); 509 musb_writel(tbase, TUSB_DMA_INT_MASK, reg); 510 511 /* REVISIT: Why does dmareq5 not work? */ 512 if (hw_ep->epnum == 0) { 513 dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx"); 514 return NULL; 515 } 516 517 for (i = 0; i < MAX_DMAREQ; i++) { 518 struct dma_channel *ch = dma_channel_pool[i]; 519 if (ch->status == MUSB_DMA_STATUS_UNKNOWN) { 520 ch->status = MUSB_DMA_STATUS_FREE; 521 channel = ch; 522 chdat = ch->private_data; 523 break; 524 } 525 } 526 527 if (!channel) 528 return NULL; 529 530 if (tx) { 531 chdat->tx = 1; 532 dev_name = "TUSB transmit"; 533 } else { 534 chdat->tx = 0; 535 dev_name = "TUSB receive"; 536 } 537 538 chdat->musb = tusb_dma->musb; 539 chdat->tbase = tusb_dma->tbase; 540 chdat->hw_ep = hw_ep; 541 chdat->epnum = hw_ep->epnum; 542 chdat->dmareq = -1; 543 chdat->completed_len = 0; 544 chdat->tusb_dma = tusb_dma; 545 546 channel->max_len = 0x7fffffff; 547 channel->desired_mode = 0; 548 channel->actual_len = 0; 549 550 if (tusb_dma->multichannel) { 551 ret = tusb_omap_dma_allocate_dmareq(chdat); 552 if (ret != 0) 553 goto free_dmareq; 554 555 ret = omap_request_dma(chdat->sync_dev, dev_name, 556 tusb_omap_dma_cb, channel, &chdat->ch); 557 if (ret != 0) 558 goto free_dmareq; 559 } else if (tusb_dma->ch == -1) { 560 tusb_dma->dmareq = 0; 561 tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0; 562 563 /* Callback data gets set later in the shared dmareq case */ 564 ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared", 565 tusb_omap_dma_cb, NULL, &tusb_dma->ch); 566 if (ret != 0) 567 goto free_dmareq; 568 569 chdat->dmareq = -1; 570 chdat->ch = -1; 571 } 572 573 dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n", 574 chdat->epnum, 575 chdat->tx ? "tx" : "rx", 576 chdat->ch >= 0 ? "dedicated" : "shared", 577 chdat->ch >= 0 ? chdat->ch : tusb_dma->ch, 578 chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq, 579 chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev); 580 581 return channel; 582 583 free_dmareq: 584 tusb_omap_dma_free_dmareq(chdat); 585 586 dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum); 587 channel->status = MUSB_DMA_STATUS_UNKNOWN; 588 589 return NULL; 590 } 591 592 static void tusb_omap_dma_release(struct dma_channel *channel) 593 { 594 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 595 struct musb *musb = chdat->musb; 596 void __iomem *tbase = musb->ctrl_base; 597 u32 reg; 598 599 dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch); 600 601 reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 602 if (chdat->tx) 603 reg |= (1 << chdat->epnum); 604 else 605 reg |= (1 << (chdat->epnum + 15)); 606 musb_writel(tbase, TUSB_DMA_INT_MASK, reg); 607 608 reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR); 609 if (chdat->tx) 610 reg |= (1 << chdat->epnum); 611 else 612 reg |= (1 << (chdat->epnum + 15)); 613 musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg); 614 615 channel->status = MUSB_DMA_STATUS_UNKNOWN; 616 617 if (chdat->ch >= 0) { 618 omap_stop_dma(chdat->ch); 619 omap_free_dma(chdat->ch); 620 chdat->ch = -1; 621 } 622 623 if (chdat->dmareq >= 0) 624 tusb_omap_dma_free_dmareq(chdat); 625 626 channel = NULL; 627 } 628 629 void dma_controller_destroy(struct dma_controller *c) 630 { 631 struct tusb_omap_dma *tusb_dma; 632 int i; 633 634 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 635 for (i = 0; i < MAX_DMAREQ; i++) { 636 struct dma_channel *ch = dma_channel_pool[i]; 637 if (ch) { 638 kfree(ch->private_data); 639 kfree(ch); 640 } 641 } 642 643 if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0) 644 omap_free_dma(tusb_dma->ch); 645 646 kfree(tusb_dma); 647 } 648 649 struct dma_controller *dma_controller_create(struct musb *musb, void __iomem *base) 650 { 651 void __iomem *tbase = musb->ctrl_base; 652 struct tusb_omap_dma *tusb_dma; 653 int i; 654 655 /* REVISIT: Get dmareq lines used from board-*.c */ 656 657 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff); 658 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0); 659 660 musb_writel(tbase, TUSB_DMA_REQ_CONF, 661 TUSB_DMA_REQ_CONF_BURST_SIZE(2) 662 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) 663 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 664 665 tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL); 666 if (!tusb_dma) 667 goto out; 668 669 tusb_dma->musb = musb; 670 tusb_dma->tbase = musb->ctrl_base; 671 672 tusb_dma->ch = -1; 673 tusb_dma->dmareq = -1; 674 tusb_dma->sync_dev = -1; 675 676 tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate; 677 tusb_dma->controller.channel_release = tusb_omap_dma_release; 678 tusb_dma->controller.channel_program = tusb_omap_dma_program; 679 tusb_dma->controller.channel_abort = tusb_omap_dma_abort; 680 681 if (tusb_get_revision(musb) >= TUSB_REV_30) 682 tusb_dma->multichannel = 1; 683 684 for (i = 0; i < MAX_DMAREQ; i++) { 685 struct dma_channel *ch; 686 struct tusb_omap_dma_ch *chdat; 687 688 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL); 689 if (!ch) 690 goto cleanup; 691 692 dma_channel_pool[i] = ch; 693 694 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL); 695 if (!chdat) 696 goto cleanup; 697 698 ch->status = MUSB_DMA_STATUS_UNKNOWN; 699 ch->private_data = chdat; 700 } 701 702 return &tusb_dma->controller; 703 704 cleanup: 705 dma_controller_destroy(&tusb_dma->controller); 706 out: 707 return NULL; 708 } 709