1 /* 2 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface 3 * 4 * Copyright (C) 2006 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/errno.h> 14 #include <linux/usb.h> 15 #include <linux/platform_device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/slab.h> 18 #include <linux/omap-dma.h> 19 20 #include "musb_core.h" 21 #include "tusb6010.h" 22 23 #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data) 24 25 #define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */ 26 27 #define OMAP24XX_DMA_EXT_DMAREQ0 2 28 #define OMAP24XX_DMA_EXT_DMAREQ1 3 29 #define OMAP242X_DMA_EXT_DMAREQ2 14 30 #define OMAP242X_DMA_EXT_DMAREQ3 15 31 #define OMAP242X_DMA_EXT_DMAREQ4 16 32 #define OMAP242X_DMA_EXT_DMAREQ5 64 33 34 struct tusb_omap_dma_ch { 35 struct musb *musb; 36 void __iomem *tbase; 37 unsigned long phys_offset; 38 int epnum; 39 u8 tx; 40 struct musb_hw_ep *hw_ep; 41 42 int ch; 43 s8 dmareq; 44 s8 sync_dev; 45 46 struct tusb_omap_dma *tusb_dma; 47 48 dma_addr_t dma_addr; 49 50 u32 len; 51 u16 packet_sz; 52 u16 transfer_packet_sz; 53 u32 transfer_len; 54 u32 completed_len; 55 }; 56 57 struct tusb_omap_dma { 58 struct dma_controller controller; 59 void __iomem *tbase; 60 61 int ch; 62 s8 dmareq; 63 s8 sync_dev; 64 unsigned multichannel:1; 65 }; 66 67 /* 68 * Allocate dmareq0 to the current channel unless it's already taken 69 */ 70 static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat) 71 { 72 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 73 74 if (reg != 0) { 75 dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n", 76 chdat->epnum, reg & 0xf); 77 return -EAGAIN; 78 } 79 80 if (chdat->tx) 81 reg = (1 << 4) | chdat->epnum; 82 else 83 reg = chdat->epnum; 84 85 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 86 87 return 0; 88 } 89 90 static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat) 91 { 92 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 93 94 if ((reg & 0xf) != chdat->epnum) { 95 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n", 96 chdat->epnum, reg & 0xf); 97 return; 98 } 99 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0); 100 } 101 102 /* 103 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in 104 * musb_gadget.c. 105 */ 106 static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data) 107 { 108 struct dma_channel *channel = (struct dma_channel *)data; 109 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 110 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 111 struct musb *musb = chdat->musb; 112 struct device *dev = musb->controller; 113 struct musb_hw_ep *hw_ep = chdat->hw_ep; 114 void __iomem *ep_conf = hw_ep->conf; 115 void __iomem *mbase = musb->mregs; 116 unsigned long remaining, flags, pio; 117 int ch; 118 119 spin_lock_irqsave(&musb->lock, flags); 120 121 if (tusb_dma->multichannel) 122 ch = chdat->ch; 123 else 124 ch = tusb_dma->ch; 125 126 if (ch_status != OMAP_DMA_BLOCK_IRQ) 127 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status); 128 129 dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n", 130 chdat->epnum, chdat->tx ? "tx" : "rx", 131 ch, ch_status); 132 133 if (chdat->tx) 134 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); 135 else 136 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); 137 138 remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining); 139 140 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */ 141 if (unlikely(remaining > chdat->transfer_len)) { 142 dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n", 143 chdat->tx ? "tx" : "rx", chdat->ch, 144 remaining); 145 remaining = 0; 146 } 147 148 channel->actual_len = chdat->transfer_len - remaining; 149 pio = chdat->len - channel->actual_len; 150 151 dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len); 152 153 /* Transfer remaining 1 - 31 bytes */ 154 if (pio > 0 && pio < 32) { 155 u8 *buf; 156 157 dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio); 158 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len; 159 if (chdat->tx) { 160 dma_unmap_single(dev, chdat->dma_addr, 161 chdat->transfer_len, 162 DMA_TO_DEVICE); 163 musb_write_fifo(hw_ep, pio, buf); 164 } else { 165 dma_unmap_single(dev, chdat->dma_addr, 166 chdat->transfer_len, 167 DMA_FROM_DEVICE); 168 musb_read_fifo(hw_ep, pio, buf); 169 } 170 channel->actual_len += pio; 171 } 172 173 if (!tusb_dma->multichannel) 174 tusb_omap_free_shared_dmareq(chdat); 175 176 channel->status = MUSB_DMA_STATUS_FREE; 177 178 /* Handle only RX callbacks here. TX callbacks must be handled based 179 * on the TUSB DMA status interrupt. 180 * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback 181 * interrupt for RX and TX. 182 */ 183 if (!chdat->tx) 184 musb_dma_completion(musb, chdat->epnum, chdat->tx); 185 186 /* We must terminate short tx transfers manually by setting TXPKTRDY. 187 * REVISIT: This same problem may occur with other MUSB dma as well. 188 * Easy to test with g_ether by pinging the MUSB board with ping -s54. 189 */ 190 if ((chdat->transfer_len < chdat->packet_sz) 191 || (chdat->transfer_len % chdat->packet_sz != 0)) { 192 u16 csr; 193 194 if (chdat->tx) { 195 dev_dbg(musb->controller, "terminating short tx packet\n"); 196 musb_ep_select(mbase, chdat->epnum); 197 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 198 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY 199 | MUSB_TXCSR_P_WZC_BITS; 200 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); 201 } 202 } 203 204 spin_unlock_irqrestore(&musb->lock, flags); 205 } 206 207 static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz, 208 u8 rndis_mode, dma_addr_t dma_addr, u32 len) 209 { 210 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 211 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 212 struct musb *musb = chdat->musb; 213 struct device *dev = musb->controller; 214 struct musb_hw_ep *hw_ep = chdat->hw_ep; 215 void __iomem *mbase = musb->mregs; 216 void __iomem *ep_conf = hw_ep->conf; 217 dma_addr_t fifo = hw_ep->fifo_sync; 218 struct omap_dma_channel_params dma_params; 219 u32 dma_remaining; 220 int src_burst, dst_burst; 221 u16 csr; 222 int ch; 223 s8 dmareq; 224 s8 sync_dev; 225 226 if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz)) 227 return false; 228 229 /* 230 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE 231 * register which will cause missed DMA interrupt. We could try to 232 * use a timer for the callback, but it is unsafe as the XFR_SIZE 233 * register is corrupt, and we won't know if the DMA worked. 234 */ 235 if (dma_addr & 0x2) 236 return false; 237 238 /* 239 * Because of HW issue #10, it seems like mixing sync DMA and async 240 * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before 241 * using the channel for DMA. 242 */ 243 if (chdat->tx) 244 dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); 245 else 246 dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); 247 248 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining); 249 if (dma_remaining) { 250 dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n", 251 chdat->tx ? "tx" : "rx", chdat->ch, 252 dma_remaining); 253 return false; 254 } 255 256 chdat->transfer_len = len & ~0x1f; 257 258 if (len < packet_sz) 259 chdat->transfer_packet_sz = chdat->transfer_len; 260 else 261 chdat->transfer_packet_sz = packet_sz; 262 263 if (tusb_dma->multichannel) { 264 ch = chdat->ch; 265 dmareq = chdat->dmareq; 266 sync_dev = chdat->sync_dev; 267 } else { 268 if (tusb_omap_use_shared_dmareq(chdat) != 0) { 269 dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum); 270 return false; 271 } 272 if (tusb_dma->ch < 0) { 273 /* REVISIT: This should get blocked earlier, happens 274 * with MSC ErrorRecoveryTest 275 */ 276 WARN_ON(1); 277 return false; 278 } 279 280 ch = tusb_dma->ch; 281 dmareq = tusb_dma->dmareq; 282 sync_dev = tusb_dma->sync_dev; 283 omap_set_dma_callback(ch, tusb_omap_dma_cb, channel); 284 } 285 286 chdat->packet_sz = packet_sz; 287 chdat->len = len; 288 channel->actual_len = 0; 289 chdat->dma_addr = dma_addr; 290 channel->status = MUSB_DMA_STATUS_BUSY; 291 292 /* Since we're recycling dma areas, we need to clean or invalidate */ 293 if (chdat->tx) 294 dma_map_single(dev, phys_to_virt(dma_addr), len, 295 DMA_TO_DEVICE); 296 else 297 dma_map_single(dev, phys_to_virt(dma_addr), len, 298 DMA_FROM_DEVICE); 299 300 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */ 301 if ((dma_addr & 0x3) == 0) { 302 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32; 303 dma_params.elem_count = 8; /* Elements in frame */ 304 } else { 305 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16; 306 dma_params.elem_count = 16; /* Elements in frame */ 307 fifo = hw_ep->fifo_async; 308 } 309 310 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */ 311 312 dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %pad len: %u(%u) packet_sz: %i(%i)\n", 313 chdat->epnum, chdat->tx ? "tx" : "rx", 314 ch, &dma_addr, chdat->transfer_len, len, 315 chdat->transfer_packet_sz, packet_sz); 316 317 /* 318 * Prepare omap DMA for transfer 319 */ 320 if (chdat->tx) { 321 dma_params.src_amode = OMAP_DMA_AMODE_POST_INC; 322 dma_params.src_start = (unsigned long)dma_addr; 323 dma_params.src_ei = 0; 324 dma_params.src_fi = 0; 325 326 dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX; 327 dma_params.dst_start = (unsigned long)fifo; 328 dma_params.dst_ei = 1; 329 dma_params.dst_fi = -31; /* Loop 32 byte window */ 330 331 dma_params.trigger = sync_dev; 332 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; 333 dma_params.src_or_dst_synch = 0; /* Dest sync */ 334 335 src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */ 336 dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */ 337 } else { 338 dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX; 339 dma_params.src_start = (unsigned long)fifo; 340 dma_params.src_ei = 1; 341 dma_params.src_fi = -31; /* Loop 32 byte window */ 342 343 dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC; 344 dma_params.dst_start = (unsigned long)dma_addr; 345 dma_params.dst_ei = 0; 346 dma_params.dst_fi = 0; 347 348 dma_params.trigger = sync_dev; 349 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; 350 dma_params.src_or_dst_synch = 1; /* Source sync */ 351 352 src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */ 353 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */ 354 } 355 356 dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n", 357 chdat->epnum, chdat->tx ? "tx" : "rx", 358 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16, 359 ((dma_addr & 0x3) == 0) ? "sync" : "async", 360 dma_params.src_start, dma_params.dst_start); 361 362 omap_set_dma_params(ch, &dma_params); 363 omap_set_dma_src_burst_mode(ch, src_burst); 364 omap_set_dma_dest_burst_mode(ch, dst_burst); 365 omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED); 366 367 /* 368 * Prepare MUSB for DMA transfer 369 */ 370 if (chdat->tx) { 371 musb_ep_select(mbase, chdat->epnum); 372 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 373 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB 374 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE); 375 csr &= ~MUSB_TXCSR_P_UNDERRUN; 376 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); 377 } else { 378 musb_ep_select(mbase, chdat->epnum); 379 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 380 csr |= MUSB_RXCSR_DMAENAB; 381 csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE); 382 musb_writew(hw_ep->regs, MUSB_RXCSR, 383 csr | MUSB_RXCSR_P_WZC_BITS); 384 } 385 386 /* 387 * Start DMA transfer 388 */ 389 omap_start_dma(ch); 390 391 if (chdat->tx) { 392 /* Send transfer_packet_sz packets at a time */ 393 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, 394 chdat->transfer_packet_sz); 395 396 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 397 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); 398 } else { 399 /* Receive transfer_packet_sz packets at a time */ 400 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, 401 chdat->transfer_packet_sz << 16); 402 403 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 404 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); 405 } 406 407 return true; 408 } 409 410 static int tusb_omap_dma_abort(struct dma_channel *channel) 411 { 412 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 413 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 414 415 if (!tusb_dma->multichannel) { 416 if (tusb_dma->ch >= 0) { 417 omap_stop_dma(tusb_dma->ch); 418 omap_free_dma(tusb_dma->ch); 419 tusb_dma->ch = -1; 420 } 421 422 tusb_dma->dmareq = -1; 423 tusb_dma->sync_dev = -1; 424 } 425 426 channel->status = MUSB_DMA_STATUS_FREE; 427 428 return 0; 429 } 430 431 static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat) 432 { 433 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 434 int i, dmareq_nr = -1; 435 436 const int sync_dev[6] = { 437 OMAP24XX_DMA_EXT_DMAREQ0, 438 OMAP24XX_DMA_EXT_DMAREQ1, 439 OMAP242X_DMA_EXT_DMAREQ2, 440 OMAP242X_DMA_EXT_DMAREQ3, 441 OMAP242X_DMA_EXT_DMAREQ4, 442 OMAP242X_DMA_EXT_DMAREQ5, 443 }; 444 445 for (i = 0; i < MAX_DMAREQ; i++) { 446 int cur = (reg & (0xf << (i * 5))) >> (i * 5); 447 if (cur == 0) { 448 dmareq_nr = i; 449 break; 450 } 451 } 452 453 if (dmareq_nr == -1) 454 return -EAGAIN; 455 456 reg |= (chdat->epnum << (dmareq_nr * 5)); 457 if (chdat->tx) 458 reg |= ((1 << 4) << (dmareq_nr * 5)); 459 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 460 461 chdat->dmareq = dmareq_nr; 462 chdat->sync_dev = sync_dev[chdat->dmareq]; 463 464 return 0; 465 } 466 467 static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat) 468 { 469 u32 reg; 470 471 if (!chdat || chdat->dmareq < 0) 472 return; 473 474 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 475 reg &= ~(0x1f << (chdat->dmareq * 5)); 476 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 477 478 chdat->dmareq = -1; 479 chdat->sync_dev = -1; 480 } 481 482 static struct dma_channel *dma_channel_pool[MAX_DMAREQ]; 483 484 static struct dma_channel * 485 tusb_omap_dma_allocate(struct dma_controller *c, 486 struct musb_hw_ep *hw_ep, 487 u8 tx) 488 { 489 int ret, i; 490 const char *dev_name; 491 struct tusb_omap_dma *tusb_dma; 492 struct musb *musb; 493 void __iomem *tbase; 494 struct dma_channel *channel = NULL; 495 struct tusb_omap_dma_ch *chdat = NULL; 496 u32 reg; 497 498 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 499 musb = tusb_dma->controller.musb; 500 tbase = musb->ctrl_base; 501 502 reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 503 if (tx) 504 reg &= ~(1 << hw_ep->epnum); 505 else 506 reg &= ~(1 << (hw_ep->epnum + 15)); 507 musb_writel(tbase, TUSB_DMA_INT_MASK, reg); 508 509 /* REVISIT: Why does dmareq5 not work? */ 510 if (hw_ep->epnum == 0) { 511 dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx"); 512 return NULL; 513 } 514 515 for (i = 0; i < MAX_DMAREQ; i++) { 516 struct dma_channel *ch = dma_channel_pool[i]; 517 if (ch->status == MUSB_DMA_STATUS_UNKNOWN) { 518 ch->status = MUSB_DMA_STATUS_FREE; 519 channel = ch; 520 chdat = ch->private_data; 521 break; 522 } 523 } 524 525 if (!channel) 526 return NULL; 527 528 if (tx) { 529 chdat->tx = 1; 530 dev_name = "TUSB transmit"; 531 } else { 532 chdat->tx = 0; 533 dev_name = "TUSB receive"; 534 } 535 536 chdat->musb = tusb_dma->controller.musb; 537 chdat->tbase = tusb_dma->tbase; 538 chdat->hw_ep = hw_ep; 539 chdat->epnum = hw_ep->epnum; 540 chdat->dmareq = -1; 541 chdat->completed_len = 0; 542 chdat->tusb_dma = tusb_dma; 543 544 channel->max_len = 0x7fffffff; 545 channel->desired_mode = 0; 546 channel->actual_len = 0; 547 548 if (tusb_dma->multichannel) { 549 ret = tusb_omap_dma_allocate_dmareq(chdat); 550 if (ret != 0) 551 goto free_dmareq; 552 553 ret = omap_request_dma(chdat->sync_dev, dev_name, 554 tusb_omap_dma_cb, channel, &chdat->ch); 555 if (ret != 0) 556 goto free_dmareq; 557 } else if (tusb_dma->ch == -1) { 558 tusb_dma->dmareq = 0; 559 tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0; 560 561 /* Callback data gets set later in the shared dmareq case */ 562 ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared", 563 tusb_omap_dma_cb, NULL, &tusb_dma->ch); 564 if (ret != 0) 565 goto free_dmareq; 566 567 chdat->dmareq = -1; 568 chdat->ch = -1; 569 } 570 571 dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n", 572 chdat->epnum, 573 chdat->tx ? "tx" : "rx", 574 chdat->ch >= 0 ? "dedicated" : "shared", 575 chdat->ch >= 0 ? chdat->ch : tusb_dma->ch, 576 chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq, 577 chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev); 578 579 return channel; 580 581 free_dmareq: 582 tusb_omap_dma_free_dmareq(chdat); 583 584 dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum); 585 channel->status = MUSB_DMA_STATUS_UNKNOWN; 586 587 return NULL; 588 } 589 590 static void tusb_omap_dma_release(struct dma_channel *channel) 591 { 592 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 593 struct musb *musb = chdat->musb; 594 void __iomem *tbase = musb->ctrl_base; 595 u32 reg; 596 597 dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch); 598 599 reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 600 if (chdat->tx) 601 reg |= (1 << chdat->epnum); 602 else 603 reg |= (1 << (chdat->epnum + 15)); 604 musb_writel(tbase, TUSB_DMA_INT_MASK, reg); 605 606 reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR); 607 if (chdat->tx) 608 reg |= (1 << chdat->epnum); 609 else 610 reg |= (1 << (chdat->epnum + 15)); 611 musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg); 612 613 channel->status = MUSB_DMA_STATUS_UNKNOWN; 614 615 if (chdat->ch >= 0) { 616 omap_stop_dma(chdat->ch); 617 omap_free_dma(chdat->ch); 618 chdat->ch = -1; 619 } 620 621 if (chdat->dmareq >= 0) 622 tusb_omap_dma_free_dmareq(chdat); 623 624 channel = NULL; 625 } 626 627 void tusb_dma_controller_destroy(struct dma_controller *c) 628 { 629 struct tusb_omap_dma *tusb_dma; 630 int i; 631 632 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 633 for (i = 0; i < MAX_DMAREQ; i++) { 634 struct dma_channel *ch = dma_channel_pool[i]; 635 if (ch) { 636 kfree(ch->private_data); 637 kfree(ch); 638 } 639 } 640 641 if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0) 642 omap_free_dma(tusb_dma->ch); 643 644 kfree(tusb_dma); 645 } 646 EXPORT_SYMBOL_GPL(tusb_dma_controller_destroy); 647 648 struct dma_controller * 649 tusb_dma_controller_create(struct musb *musb, void __iomem *base) 650 { 651 void __iomem *tbase = musb->ctrl_base; 652 struct tusb_omap_dma *tusb_dma; 653 int i; 654 655 /* REVISIT: Get dmareq lines used from board-*.c */ 656 657 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff); 658 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0); 659 660 musb_writel(tbase, TUSB_DMA_REQ_CONF, 661 TUSB_DMA_REQ_CONF_BURST_SIZE(2) 662 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) 663 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 664 665 tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL); 666 if (!tusb_dma) 667 goto out; 668 669 tusb_dma->controller.musb = musb; 670 tusb_dma->tbase = musb->ctrl_base; 671 672 tusb_dma->ch = -1; 673 tusb_dma->dmareq = -1; 674 tusb_dma->sync_dev = -1; 675 676 tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate; 677 tusb_dma->controller.channel_release = tusb_omap_dma_release; 678 tusb_dma->controller.channel_program = tusb_omap_dma_program; 679 tusb_dma->controller.channel_abort = tusb_omap_dma_abort; 680 681 if (musb->tusb_revision >= TUSB_REV_30) 682 tusb_dma->multichannel = 1; 683 684 for (i = 0; i < MAX_DMAREQ; i++) { 685 struct dma_channel *ch; 686 struct tusb_omap_dma_ch *chdat; 687 688 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL); 689 if (!ch) 690 goto cleanup; 691 692 dma_channel_pool[i] = ch; 693 694 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL); 695 if (!chdat) 696 goto cleanup; 697 698 ch->status = MUSB_DMA_STATUS_UNKNOWN; 699 ch->private_data = chdat; 700 } 701 702 return &tusb_dma->controller; 703 704 cleanup: 705 musb_dma_controller_destroy(&tusb_dma->controller); 706 out: 707 return NULL; 708 } 709 EXPORT_SYMBOL_GPL(tusb_dma_controller_create); 710