1 /* 2 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface 3 * 4 * Copyright (C) 2006 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/errno.h> 14 #include <linux/usb.h> 15 #include <linux/platform_device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/slab.h> 18 #include <linux/omap-dma.h> 19 20 #include "musb_core.h" 21 #include "tusb6010.h" 22 23 #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data) 24 25 #define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */ 26 27 #define OMAP24XX_DMA_EXT_DMAREQ0 2 28 #define OMAP24XX_DMA_EXT_DMAREQ1 3 29 #define OMAP242X_DMA_EXT_DMAREQ2 14 30 #define OMAP242X_DMA_EXT_DMAREQ3 15 31 #define OMAP242X_DMA_EXT_DMAREQ4 16 32 #define OMAP242X_DMA_EXT_DMAREQ5 64 33 34 struct tusb_omap_dma_ch { 35 struct musb *musb; 36 void __iomem *tbase; 37 unsigned long phys_offset; 38 int epnum; 39 u8 tx; 40 struct musb_hw_ep *hw_ep; 41 42 int ch; 43 s8 dmareq; 44 s8 sync_dev; 45 46 struct tusb_omap_dma *tusb_dma; 47 48 dma_addr_t dma_addr; 49 50 u32 len; 51 u16 packet_sz; 52 u16 transfer_packet_sz; 53 u32 transfer_len; 54 u32 completed_len; 55 }; 56 57 struct tusb_omap_dma { 58 struct dma_controller controller; 59 struct musb *musb; 60 void __iomem *tbase; 61 62 int ch; 63 s8 dmareq; 64 s8 sync_dev; 65 unsigned multichannel:1; 66 }; 67 68 /* 69 * Allocate dmareq0 to the current channel unless it's already taken 70 */ 71 static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat) 72 { 73 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 74 75 if (reg != 0) { 76 dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n", 77 chdat->epnum, reg & 0xf); 78 return -EAGAIN; 79 } 80 81 if (chdat->tx) 82 reg = (1 << 4) | chdat->epnum; 83 else 84 reg = chdat->epnum; 85 86 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 87 88 return 0; 89 } 90 91 static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat) 92 { 93 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 94 95 if ((reg & 0xf) != chdat->epnum) { 96 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n", 97 chdat->epnum, reg & 0xf); 98 return; 99 } 100 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0); 101 } 102 103 /* 104 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in 105 * musb_gadget.c. 106 */ 107 static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data) 108 { 109 struct dma_channel *channel = (struct dma_channel *)data; 110 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 111 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 112 struct musb *musb = chdat->musb; 113 struct device *dev = musb->controller; 114 struct musb_hw_ep *hw_ep = chdat->hw_ep; 115 void __iomem *ep_conf = hw_ep->conf; 116 void __iomem *mbase = musb->mregs; 117 unsigned long remaining, flags, pio; 118 int ch; 119 120 spin_lock_irqsave(&musb->lock, flags); 121 122 if (tusb_dma->multichannel) 123 ch = chdat->ch; 124 else 125 ch = tusb_dma->ch; 126 127 if (ch_status != OMAP_DMA_BLOCK_IRQ) 128 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status); 129 130 dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n", 131 chdat->epnum, chdat->tx ? "tx" : "rx", 132 ch, ch_status); 133 134 if (chdat->tx) 135 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); 136 else 137 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); 138 139 remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining); 140 141 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */ 142 if (unlikely(remaining > chdat->transfer_len)) { 143 dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n", 144 chdat->tx ? "tx" : "rx", chdat->ch, 145 remaining); 146 remaining = 0; 147 } 148 149 channel->actual_len = chdat->transfer_len - remaining; 150 pio = chdat->len - channel->actual_len; 151 152 dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len); 153 154 /* Transfer remaining 1 - 31 bytes */ 155 if (pio > 0 && pio < 32) { 156 u8 *buf; 157 158 dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio); 159 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len; 160 if (chdat->tx) { 161 dma_unmap_single(dev, chdat->dma_addr, 162 chdat->transfer_len, 163 DMA_TO_DEVICE); 164 musb_write_fifo(hw_ep, pio, buf); 165 } else { 166 dma_unmap_single(dev, chdat->dma_addr, 167 chdat->transfer_len, 168 DMA_FROM_DEVICE); 169 musb_read_fifo(hw_ep, pio, buf); 170 } 171 channel->actual_len += pio; 172 } 173 174 if (!tusb_dma->multichannel) 175 tusb_omap_free_shared_dmareq(chdat); 176 177 channel->status = MUSB_DMA_STATUS_FREE; 178 179 /* Handle only RX callbacks here. TX callbacks must be handled based 180 * on the TUSB DMA status interrupt. 181 * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback 182 * interrupt for RX and TX. 183 */ 184 if (!chdat->tx) 185 musb_dma_completion(musb, chdat->epnum, chdat->tx); 186 187 /* We must terminate short tx transfers manually by setting TXPKTRDY. 188 * REVISIT: This same problem may occur with other MUSB dma as well. 189 * Easy to test with g_ether by pinging the MUSB board with ping -s54. 190 */ 191 if ((chdat->transfer_len < chdat->packet_sz) 192 || (chdat->transfer_len % chdat->packet_sz != 0)) { 193 u16 csr; 194 195 if (chdat->tx) { 196 dev_dbg(musb->controller, "terminating short tx packet\n"); 197 musb_ep_select(mbase, chdat->epnum); 198 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 199 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY 200 | MUSB_TXCSR_P_WZC_BITS; 201 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); 202 } 203 } 204 205 spin_unlock_irqrestore(&musb->lock, flags); 206 } 207 208 static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz, 209 u8 rndis_mode, dma_addr_t dma_addr, u32 len) 210 { 211 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 212 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 213 struct musb *musb = chdat->musb; 214 struct device *dev = musb->controller; 215 struct musb_hw_ep *hw_ep = chdat->hw_ep; 216 void __iomem *mbase = musb->mregs; 217 void __iomem *ep_conf = hw_ep->conf; 218 dma_addr_t fifo = hw_ep->fifo_sync; 219 struct omap_dma_channel_params dma_params; 220 u32 dma_remaining; 221 int src_burst, dst_burst; 222 u16 csr; 223 int ch; 224 s8 dmareq; 225 s8 sync_dev; 226 227 if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz)) 228 return false; 229 230 /* 231 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE 232 * register which will cause missed DMA interrupt. We could try to 233 * use a timer for the callback, but it is unsafe as the XFR_SIZE 234 * register is corrupt, and we won't know if the DMA worked. 235 */ 236 if (dma_addr & 0x2) 237 return false; 238 239 /* 240 * Because of HW issue #10, it seems like mixing sync DMA and async 241 * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before 242 * using the channel for DMA. 243 */ 244 if (chdat->tx) 245 dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); 246 else 247 dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); 248 249 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining); 250 if (dma_remaining) { 251 dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n", 252 chdat->tx ? "tx" : "rx", chdat->ch, 253 dma_remaining); 254 return false; 255 } 256 257 chdat->transfer_len = len & ~0x1f; 258 259 if (len < packet_sz) 260 chdat->transfer_packet_sz = chdat->transfer_len; 261 else 262 chdat->transfer_packet_sz = packet_sz; 263 264 if (tusb_dma->multichannel) { 265 ch = chdat->ch; 266 dmareq = chdat->dmareq; 267 sync_dev = chdat->sync_dev; 268 } else { 269 if (tusb_omap_use_shared_dmareq(chdat) != 0) { 270 dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum); 271 return false; 272 } 273 if (tusb_dma->ch < 0) { 274 /* REVISIT: This should get blocked earlier, happens 275 * with MSC ErrorRecoveryTest 276 */ 277 WARN_ON(1); 278 return false; 279 } 280 281 ch = tusb_dma->ch; 282 dmareq = tusb_dma->dmareq; 283 sync_dev = tusb_dma->sync_dev; 284 omap_set_dma_callback(ch, tusb_omap_dma_cb, channel); 285 } 286 287 chdat->packet_sz = packet_sz; 288 chdat->len = len; 289 channel->actual_len = 0; 290 chdat->dma_addr = dma_addr; 291 channel->status = MUSB_DMA_STATUS_BUSY; 292 293 /* Since we're recycling dma areas, we need to clean or invalidate */ 294 if (chdat->tx) 295 dma_map_single(dev, phys_to_virt(dma_addr), len, 296 DMA_TO_DEVICE); 297 else 298 dma_map_single(dev, phys_to_virt(dma_addr), len, 299 DMA_FROM_DEVICE); 300 301 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */ 302 if ((dma_addr & 0x3) == 0) { 303 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32; 304 dma_params.elem_count = 8; /* Elements in frame */ 305 } else { 306 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16; 307 dma_params.elem_count = 16; /* Elements in frame */ 308 fifo = hw_ep->fifo_async; 309 } 310 311 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */ 312 313 dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n", 314 chdat->epnum, chdat->tx ? "tx" : "rx", 315 ch, dma_addr, chdat->transfer_len, len, 316 chdat->transfer_packet_sz, packet_sz); 317 318 /* 319 * Prepare omap DMA for transfer 320 */ 321 if (chdat->tx) { 322 dma_params.src_amode = OMAP_DMA_AMODE_POST_INC; 323 dma_params.src_start = (unsigned long)dma_addr; 324 dma_params.src_ei = 0; 325 dma_params.src_fi = 0; 326 327 dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX; 328 dma_params.dst_start = (unsigned long)fifo; 329 dma_params.dst_ei = 1; 330 dma_params.dst_fi = -31; /* Loop 32 byte window */ 331 332 dma_params.trigger = sync_dev; 333 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; 334 dma_params.src_or_dst_synch = 0; /* Dest sync */ 335 336 src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */ 337 dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */ 338 } else { 339 dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX; 340 dma_params.src_start = (unsigned long)fifo; 341 dma_params.src_ei = 1; 342 dma_params.src_fi = -31; /* Loop 32 byte window */ 343 344 dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC; 345 dma_params.dst_start = (unsigned long)dma_addr; 346 dma_params.dst_ei = 0; 347 dma_params.dst_fi = 0; 348 349 dma_params.trigger = sync_dev; 350 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; 351 dma_params.src_or_dst_synch = 1; /* Source sync */ 352 353 src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */ 354 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */ 355 } 356 357 dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n", 358 chdat->epnum, chdat->tx ? "tx" : "rx", 359 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16, 360 ((dma_addr & 0x3) == 0) ? "sync" : "async", 361 dma_params.src_start, dma_params.dst_start); 362 363 omap_set_dma_params(ch, &dma_params); 364 omap_set_dma_src_burst_mode(ch, src_burst); 365 omap_set_dma_dest_burst_mode(ch, dst_burst); 366 omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED); 367 368 /* 369 * Prepare MUSB for DMA transfer 370 */ 371 if (chdat->tx) { 372 musb_ep_select(mbase, chdat->epnum); 373 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 374 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB 375 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE); 376 csr &= ~MUSB_TXCSR_P_UNDERRUN; 377 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); 378 } else { 379 musb_ep_select(mbase, chdat->epnum); 380 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 381 csr |= MUSB_RXCSR_DMAENAB; 382 csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE); 383 musb_writew(hw_ep->regs, MUSB_RXCSR, 384 csr | MUSB_RXCSR_P_WZC_BITS); 385 } 386 387 /* 388 * Start DMA transfer 389 */ 390 omap_start_dma(ch); 391 392 if (chdat->tx) { 393 /* Send transfer_packet_sz packets at a time */ 394 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, 395 chdat->transfer_packet_sz); 396 397 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 398 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); 399 } else { 400 /* Receive transfer_packet_sz packets at a time */ 401 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, 402 chdat->transfer_packet_sz << 16); 403 404 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 405 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); 406 } 407 408 return true; 409 } 410 411 static int tusb_omap_dma_abort(struct dma_channel *channel) 412 { 413 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 414 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 415 416 if (!tusb_dma->multichannel) { 417 if (tusb_dma->ch >= 0) { 418 omap_stop_dma(tusb_dma->ch); 419 omap_free_dma(tusb_dma->ch); 420 tusb_dma->ch = -1; 421 } 422 423 tusb_dma->dmareq = -1; 424 tusb_dma->sync_dev = -1; 425 } 426 427 channel->status = MUSB_DMA_STATUS_FREE; 428 429 return 0; 430 } 431 432 static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat) 433 { 434 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 435 int i, dmareq_nr = -1; 436 437 const int sync_dev[6] = { 438 OMAP24XX_DMA_EXT_DMAREQ0, 439 OMAP24XX_DMA_EXT_DMAREQ1, 440 OMAP242X_DMA_EXT_DMAREQ2, 441 OMAP242X_DMA_EXT_DMAREQ3, 442 OMAP242X_DMA_EXT_DMAREQ4, 443 OMAP242X_DMA_EXT_DMAREQ5, 444 }; 445 446 for (i = 0; i < MAX_DMAREQ; i++) { 447 int cur = (reg & (0xf << (i * 5))) >> (i * 5); 448 if (cur == 0) { 449 dmareq_nr = i; 450 break; 451 } 452 } 453 454 if (dmareq_nr == -1) 455 return -EAGAIN; 456 457 reg |= (chdat->epnum << (dmareq_nr * 5)); 458 if (chdat->tx) 459 reg |= ((1 << 4) << (dmareq_nr * 5)); 460 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 461 462 chdat->dmareq = dmareq_nr; 463 chdat->sync_dev = sync_dev[chdat->dmareq]; 464 465 return 0; 466 } 467 468 static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat) 469 { 470 u32 reg; 471 472 if (!chdat || chdat->dmareq < 0) 473 return; 474 475 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 476 reg &= ~(0x1f << (chdat->dmareq * 5)); 477 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 478 479 chdat->dmareq = -1; 480 chdat->sync_dev = -1; 481 } 482 483 static struct dma_channel *dma_channel_pool[MAX_DMAREQ]; 484 485 static struct dma_channel * 486 tusb_omap_dma_allocate(struct dma_controller *c, 487 struct musb_hw_ep *hw_ep, 488 u8 tx) 489 { 490 int ret, i; 491 const char *dev_name; 492 struct tusb_omap_dma *tusb_dma; 493 struct musb *musb; 494 void __iomem *tbase; 495 struct dma_channel *channel = NULL; 496 struct tusb_omap_dma_ch *chdat = NULL; 497 u32 reg; 498 499 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 500 musb = tusb_dma->musb; 501 tbase = musb->ctrl_base; 502 503 reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 504 if (tx) 505 reg &= ~(1 << hw_ep->epnum); 506 else 507 reg &= ~(1 << (hw_ep->epnum + 15)); 508 musb_writel(tbase, TUSB_DMA_INT_MASK, reg); 509 510 /* REVISIT: Why does dmareq5 not work? */ 511 if (hw_ep->epnum == 0) { 512 dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx"); 513 return NULL; 514 } 515 516 for (i = 0; i < MAX_DMAREQ; i++) { 517 struct dma_channel *ch = dma_channel_pool[i]; 518 if (ch->status == MUSB_DMA_STATUS_UNKNOWN) { 519 ch->status = MUSB_DMA_STATUS_FREE; 520 channel = ch; 521 chdat = ch->private_data; 522 break; 523 } 524 } 525 526 if (!channel) 527 return NULL; 528 529 if (tx) { 530 chdat->tx = 1; 531 dev_name = "TUSB transmit"; 532 } else { 533 chdat->tx = 0; 534 dev_name = "TUSB receive"; 535 } 536 537 chdat->musb = tusb_dma->musb; 538 chdat->tbase = tusb_dma->tbase; 539 chdat->hw_ep = hw_ep; 540 chdat->epnum = hw_ep->epnum; 541 chdat->dmareq = -1; 542 chdat->completed_len = 0; 543 chdat->tusb_dma = tusb_dma; 544 545 channel->max_len = 0x7fffffff; 546 channel->desired_mode = 0; 547 channel->actual_len = 0; 548 549 if (tusb_dma->multichannel) { 550 ret = tusb_omap_dma_allocate_dmareq(chdat); 551 if (ret != 0) 552 goto free_dmareq; 553 554 ret = omap_request_dma(chdat->sync_dev, dev_name, 555 tusb_omap_dma_cb, channel, &chdat->ch); 556 if (ret != 0) 557 goto free_dmareq; 558 } else if (tusb_dma->ch == -1) { 559 tusb_dma->dmareq = 0; 560 tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0; 561 562 /* Callback data gets set later in the shared dmareq case */ 563 ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared", 564 tusb_omap_dma_cb, NULL, &tusb_dma->ch); 565 if (ret != 0) 566 goto free_dmareq; 567 568 chdat->dmareq = -1; 569 chdat->ch = -1; 570 } 571 572 dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n", 573 chdat->epnum, 574 chdat->tx ? "tx" : "rx", 575 chdat->ch >= 0 ? "dedicated" : "shared", 576 chdat->ch >= 0 ? chdat->ch : tusb_dma->ch, 577 chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq, 578 chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev); 579 580 return channel; 581 582 free_dmareq: 583 tusb_omap_dma_free_dmareq(chdat); 584 585 dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum); 586 channel->status = MUSB_DMA_STATUS_UNKNOWN; 587 588 return NULL; 589 } 590 591 static void tusb_omap_dma_release(struct dma_channel *channel) 592 { 593 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 594 struct musb *musb = chdat->musb; 595 void __iomem *tbase = musb->ctrl_base; 596 u32 reg; 597 598 dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch); 599 600 reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 601 if (chdat->tx) 602 reg |= (1 << chdat->epnum); 603 else 604 reg |= (1 << (chdat->epnum + 15)); 605 musb_writel(tbase, TUSB_DMA_INT_MASK, reg); 606 607 reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR); 608 if (chdat->tx) 609 reg |= (1 << chdat->epnum); 610 else 611 reg |= (1 << (chdat->epnum + 15)); 612 musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg); 613 614 channel->status = MUSB_DMA_STATUS_UNKNOWN; 615 616 if (chdat->ch >= 0) { 617 omap_stop_dma(chdat->ch); 618 omap_free_dma(chdat->ch); 619 chdat->ch = -1; 620 } 621 622 if (chdat->dmareq >= 0) 623 tusb_omap_dma_free_dmareq(chdat); 624 625 channel = NULL; 626 } 627 628 void dma_controller_destroy(struct dma_controller *c) 629 { 630 struct tusb_omap_dma *tusb_dma; 631 int i; 632 633 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 634 for (i = 0; i < MAX_DMAREQ; i++) { 635 struct dma_channel *ch = dma_channel_pool[i]; 636 if (ch) { 637 kfree(ch->private_data); 638 kfree(ch); 639 } 640 } 641 642 if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0) 643 omap_free_dma(tusb_dma->ch); 644 645 kfree(tusb_dma); 646 } 647 648 struct dma_controller *dma_controller_create(struct musb *musb, void __iomem *base) 649 { 650 void __iomem *tbase = musb->ctrl_base; 651 struct tusb_omap_dma *tusb_dma; 652 int i; 653 654 /* REVISIT: Get dmareq lines used from board-*.c */ 655 656 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff); 657 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0); 658 659 musb_writel(tbase, TUSB_DMA_REQ_CONF, 660 TUSB_DMA_REQ_CONF_BURST_SIZE(2) 661 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) 662 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 663 664 tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL); 665 if (!tusb_dma) 666 goto out; 667 668 tusb_dma->musb = musb; 669 tusb_dma->tbase = musb->ctrl_base; 670 671 tusb_dma->ch = -1; 672 tusb_dma->dmareq = -1; 673 tusb_dma->sync_dev = -1; 674 675 tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate; 676 tusb_dma->controller.channel_release = tusb_omap_dma_release; 677 tusb_dma->controller.channel_program = tusb_omap_dma_program; 678 tusb_dma->controller.channel_abort = tusb_omap_dma_abort; 679 680 if (musb->tusb_revision >= TUSB_REV_30) 681 tusb_dma->multichannel = 1; 682 683 for (i = 0; i < MAX_DMAREQ; i++) { 684 struct dma_channel *ch; 685 struct tusb_omap_dma_ch *chdat; 686 687 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL); 688 if (!ch) 689 goto cleanup; 690 691 dma_channel_pool[i] = ch; 692 693 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL); 694 if (!chdat) 695 goto cleanup; 696 697 ch->status = MUSB_DMA_STATUS_UNKNOWN; 698 ch->private_data = chdat; 699 } 700 701 return &tusb_dma->controller; 702 703 cleanup: 704 dma_controller_destroy(&tusb_dma->controller); 705 out: 706 return NULL; 707 } 708