1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TUSB6010 USB 2.0 OTG Dual Role controller 4 * 5 * Copyright (C) 2006 Nokia Corporation 6 * Tony Lindgren <tony@atomide.com> 7 * 8 * Notes: 9 * - Driver assumes that interface to external host (main CPU) is 10 * configured for NOR FLASH interface instead of VLYNQ serial 11 * interface. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/errno.h> 17 #include <linux/err.h> 18 #include <linux/prefetch.h> 19 #include <linux/usb.h> 20 #include <linux/irq.h> 21 #include <linux/io.h> 22 #include <linux/device.h> 23 #include <linux/platform_device.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/usb/usb_phy_generic.h> 26 27 #include "musb_core.h" 28 29 struct tusb6010_glue { 30 struct device *dev; 31 struct platform_device *musb; 32 struct platform_device *phy; 33 }; 34 35 static void tusb_musb_set_vbus(struct musb *musb, int is_on); 36 37 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) 38 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) 39 40 /* 41 * Checks the revision. We need to use the DMA register as 3.0 does not 42 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. 43 */ 44 static u8 tusb_get_revision(struct musb *musb) 45 { 46 void __iomem *tbase = musb->ctrl_base; 47 u32 die_id; 48 u8 rev; 49 50 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff; 51 if (TUSB_REV_MAJOR(rev) == 3) { 52 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, 53 TUSB_DIDR1_HI)); 54 if (die_id >= TUSB_DIDR1_HI_REV_31) 55 rev |= 1; 56 } 57 58 return rev; 59 } 60 61 static void tusb_print_revision(struct musb *musb) 62 { 63 void __iomem *tbase = musb->ctrl_base; 64 u8 rev; 65 66 rev = musb->tusb_revision; 67 68 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n", 69 "prcm", 70 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)), 71 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)), 72 "int", 73 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 74 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 75 "gpio", 76 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)), 77 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)), 78 "dma", 79 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 80 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 81 "dieid", 82 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)), 83 "rev", 84 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev)); 85 } 86 87 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \ 88 | TUSB_PHY_OTG_CTRL_TESTM0) 89 90 /* 91 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0. 92 * Disables power detection in PHY for the duration of idle. 93 */ 94 static void tusb_wbus_quirk(struct musb *musb, int enabled) 95 { 96 void __iomem *tbase = musb->ctrl_base; 97 static u32 phy_otg_ctrl, phy_otg_ena; 98 u32 tmp; 99 100 if (enabled) { 101 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 102 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 103 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT 104 | phy_otg_ena | WBUS_QUIRK_MASK; 105 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 109 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 110 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 113 & TUSB_PHY_OTG_CTRL_TESTM2) { 114 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl; 115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 118 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 119 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 121 phy_otg_ctrl = 0; 122 phy_otg_ena = 0; 123 } 124 } 125 126 static u32 tusb_fifo_offset(u8 epnum) 127 { 128 return 0x200 + (epnum * 0x20); 129 } 130 131 static u32 tusb_ep_offset(u8 epnum, u16 offset) 132 { 133 return 0x10 + offset; 134 } 135 136 /* TUSB mapping: "flat" plus ep0 special cases */ 137 static void tusb_ep_select(void __iomem *mbase, u8 epnum) 138 { 139 musb_writeb(mbase, MUSB_INDEX, epnum); 140 } 141 142 /* 143 * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum. 144 */ 145 static u8 tusb_readb(void __iomem *addr, u32 offset) 146 { 147 u16 tmp; 148 u8 val; 149 150 tmp = __raw_readw(addr + (offset & ~1)); 151 if (offset & 1) 152 val = (tmp >> 8); 153 else 154 val = tmp & 0xff; 155 156 return val; 157 } 158 159 static void tusb_writeb(void __iomem *addr, u32 offset, u8 data) 160 { 161 u16 tmp; 162 163 tmp = __raw_readw(addr + (offset & ~1)); 164 if (offset & 1) 165 tmp = (data << 8) | (tmp & 0xff); 166 else 167 tmp = (tmp & 0xff00) | data; 168 169 __raw_writew(tmp, addr + (offset & ~1)); 170 } 171 172 /* 173 * TUSB 6010 may use a parallel bus that doesn't support byte ops; 174 * so both loading and unloading FIFOs need explicit byte counts. 175 */ 176 177 static inline void 178 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len) 179 { 180 u32 val; 181 int i; 182 183 if (len > 4) { 184 for (i = 0; i < (len >> 2); i++) { 185 memcpy(&val, buf, 4); 186 musb_writel(fifo, 0, val); 187 buf += 4; 188 } 189 len %= 4; 190 } 191 if (len > 0) { 192 /* Write the rest 1 - 3 bytes to FIFO */ 193 val = 0; 194 memcpy(&val, buf, len); 195 musb_writel(fifo, 0, val); 196 } 197 } 198 199 static inline void tusb_fifo_read_unaligned(void __iomem *fifo, 200 void *buf, u16 len) 201 { 202 u32 val; 203 int i; 204 205 if (len > 4) { 206 for (i = 0; i < (len >> 2); i++) { 207 val = musb_readl(fifo, 0); 208 memcpy(buf, &val, 4); 209 buf += 4; 210 } 211 len %= 4; 212 } 213 if (len > 0) { 214 /* Read the rest 1 - 3 bytes from FIFO */ 215 val = musb_readl(fifo, 0); 216 memcpy(buf, &val, len); 217 } 218 } 219 220 static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) 221 { 222 struct musb *musb = hw_ep->musb; 223 void __iomem *ep_conf = hw_ep->conf; 224 void __iomem *fifo = hw_ep->fifo; 225 u8 epnum = hw_ep->epnum; 226 227 prefetch(buf); 228 229 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 230 'T', epnum, fifo, len, buf); 231 232 if (epnum) 233 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 234 TUSB_EP_CONFIG_XFR_SIZE(len)); 235 else 236 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX | 237 TUSB_EP0_CONFIG_XFR_SIZE(len)); 238 239 if (likely((0x01 & (unsigned long) buf) == 0)) { 240 241 /* Best case is 32bit-aligned destination address */ 242 if ((0x02 & (unsigned long) buf) == 0) { 243 if (len >= 4) { 244 iowrite32_rep(fifo, buf, len >> 2); 245 buf += (len & ~0x03); 246 len &= 0x03; 247 } 248 } else { 249 if (len >= 2) { 250 u32 val; 251 int i; 252 253 /* Cannot use writesw, fifo is 32-bit */ 254 for (i = 0; i < (len >> 2); i++) { 255 val = (u32)(*(u16 *)buf); 256 buf += 2; 257 val |= (*(u16 *)buf) << 16; 258 buf += 2; 259 musb_writel(fifo, 0, val); 260 } 261 len &= 0x03; 262 } 263 } 264 } 265 266 if (len > 0) 267 tusb_fifo_write_unaligned(fifo, buf, len); 268 } 269 270 static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) 271 { 272 struct musb *musb = hw_ep->musb; 273 void __iomem *ep_conf = hw_ep->conf; 274 void __iomem *fifo = hw_ep->fifo; 275 u8 epnum = hw_ep->epnum; 276 277 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 278 'R', epnum, fifo, len, buf); 279 280 if (epnum) 281 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 282 TUSB_EP_CONFIG_XFR_SIZE(len)); 283 else 284 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len)); 285 286 if (likely((0x01 & (unsigned long) buf) == 0)) { 287 288 /* Best case is 32bit-aligned destination address */ 289 if ((0x02 & (unsigned long) buf) == 0) { 290 if (len >= 4) { 291 ioread32_rep(fifo, buf, len >> 2); 292 buf += (len & ~0x03); 293 len &= 0x03; 294 } 295 } else { 296 if (len >= 2) { 297 u32 val; 298 int i; 299 300 /* Cannot use readsw, fifo is 32-bit */ 301 for (i = 0; i < (len >> 2); i++) { 302 val = musb_readl(fifo, 0); 303 *(u16 *)buf = (u16)(val & 0xffff); 304 buf += 2; 305 *(u16 *)buf = (u16)(val >> 16); 306 buf += 2; 307 } 308 len &= 0x03; 309 } 310 } 311 } 312 313 if (len > 0) 314 tusb_fifo_read_unaligned(fifo, buf, len); 315 } 316 317 static struct musb *the_musb; 318 319 /* This is used by gadget drivers, and OTG transceiver logic, allowing 320 * at most mA current to be drawn from VBUS during a Default-B session 321 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host 322 * mode), or low power Default-B sessions, something else supplies power. 323 * Caller must take care of locking. 324 */ 325 static int tusb_draw_power(struct usb_phy *x, unsigned mA) 326 { 327 struct musb *musb = the_musb; 328 void __iomem *tbase = musb->ctrl_base; 329 u32 reg; 330 331 /* tps65030 seems to consume max 100mA, with maybe 60mA available 332 * (measured on one board) for things other than tps and tusb. 333 * 334 * Boards sharing the CPU clock with CLKIN will need to prevent 335 * certain idle sleep states while the USB link is active. 336 * 337 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }. 338 * The actual current usage would be very board-specific. For now, 339 * it's simpler to just use an aggregate (also board-specific). 340 */ 341 if (x->otg->default_a || mA < (musb->min_power << 1)) 342 mA = 0; 343 344 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 345 if (mA) { 346 musb->is_bus_powered = 1; 347 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; 348 } else { 349 musb->is_bus_powered = 0; 350 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 351 } 352 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 353 354 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA); 355 return 0; 356 } 357 358 /* workaround for issue 13: change clock during chip idle 359 * (to be fixed in rev3 silicon) ... symptoms include disconnect 360 * or looping suspend/resume cycles 361 */ 362 static void tusb_set_clock_source(struct musb *musb, unsigned mode) 363 { 364 void __iomem *tbase = musb->ctrl_base; 365 u32 reg; 366 367 reg = musb_readl(tbase, TUSB_PRCM_CONF); 368 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); 369 370 /* 0 = refclk (clkin, XI) 371 * 1 = PHY 60 MHz (internal PLL) 372 * 2 = not supported 373 * 3 = what? 374 */ 375 if (mode > 0) 376 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); 377 378 musb_writel(tbase, TUSB_PRCM_CONF, reg); 379 380 /* FIXME tusb6010_platform_retime(mode == 0); */ 381 } 382 383 /* 384 * Idle TUSB6010 until next wake-up event; NOR access always wakes. 385 * Other code ensures that we idle unless we're connected _and_ the 386 * USB link is not suspended ... and tells us the relevant wakeup 387 * events. SW_EN for voltage is handled separately. 388 */ 389 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables) 390 { 391 void __iomem *tbase = musb->ctrl_base; 392 u32 reg; 393 394 if ((wakeup_enables & TUSB_PRCM_WBUS) 395 && (musb->tusb_revision == TUSB_REV_30)) 396 tusb_wbus_quirk(musb, 1); 397 398 tusb_set_clock_source(musb, 0); 399 400 wakeup_enables |= TUSB_PRCM_WNORCS; 401 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables); 402 403 /* REVISIT writeup of WID implies that if WID set and ID is grounded, 404 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared. 405 * Presumably that's mostly to save power, hence WID is immaterial ... 406 */ 407 408 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 409 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */ 410 if (is_host_active(musb)) { 411 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 412 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 413 } else { 414 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 415 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 416 } 417 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 418 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 419 420 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables); 421 } 422 423 /* 424 * Updates cable VBUS status. Caller must take care of locking. 425 */ 426 static int tusb_musb_vbus_status(struct musb *musb) 427 { 428 void __iomem *tbase = musb->ctrl_base; 429 u32 otg_stat, prcm_mngmt; 430 int ret = 0; 431 432 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 433 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT); 434 435 /* Temporarily enable VBUS detection if it was disabled for 436 * suspend mode. Unless it's enabled otg_stat and devctl will 437 * not show correct VBUS state. 438 */ 439 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) { 440 u32 tmp = prcm_mngmt; 441 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 442 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp); 443 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 444 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt); 445 } 446 447 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) 448 ret = 1; 449 450 return ret; 451 } 452 453 static void musb_do_idle(struct timer_list *t) 454 { 455 struct musb *musb = from_timer(musb, t, dev_timer); 456 unsigned long flags; 457 458 spin_lock_irqsave(&musb->lock, flags); 459 460 switch (musb->xceiv->otg->state) { 461 case OTG_STATE_A_WAIT_BCON: 462 if ((musb->a_wait_bcon != 0) 463 && (musb->idle_timeout == 0 464 || time_after(jiffies, musb->idle_timeout))) { 465 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n", 466 usb_otg_state_string(musb->xceiv->otg->state)); 467 } 468 fallthrough; 469 case OTG_STATE_A_IDLE: 470 tusb_musb_set_vbus(musb, 0); 471 break; 472 default: 473 break; 474 } 475 476 if (!musb->is_active) { 477 u32 wakeups; 478 479 /* wait until hub_wq handles port change status */ 480 if (is_host_active(musb) && (musb->port1_status >> 16)) 481 goto done; 482 483 if (!musb->gadget_driver) { 484 wakeups = 0; 485 } else { 486 wakeups = TUSB_PRCM_WHOSTDISCON 487 | TUSB_PRCM_WBUS 488 | TUSB_PRCM_WVBUS; 489 wakeups |= TUSB_PRCM_WID; 490 } 491 tusb_allow_idle(musb, wakeups); 492 } 493 done: 494 spin_unlock_irqrestore(&musb->lock, flags); 495 } 496 497 /* 498 * Maybe put TUSB6010 into idle mode depending on USB link status, 499 * like "disconnected" or "suspended". We'll be woken out of it by 500 * connect, resume, or disconnect. 501 * 502 * Needs to be called as the last function everywhere where there is 503 * register access to TUSB6010 because of NOR flash wake-up. 504 * Caller should own controller spinlock. 505 * 506 * Delay because peripheral enables D+ pullup 3msec after SE0, and 507 * we don't want to treat that full speed J as a wakeup event. 508 * ... peripherals must draw only suspend current after 10 msec. 509 */ 510 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout) 511 { 512 unsigned long default_timeout = jiffies + msecs_to_jiffies(3); 513 static unsigned long last_timer; 514 515 if (timeout == 0) 516 timeout = default_timeout; 517 518 /* Never idle if active, or when VBUS timeout is not set as host */ 519 if (musb->is_active || ((musb->a_wait_bcon == 0) 520 && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) { 521 dev_dbg(musb->controller, "%s active, deleting timer\n", 522 usb_otg_state_string(musb->xceiv->otg->state)); 523 del_timer(&musb->dev_timer); 524 last_timer = jiffies; 525 return; 526 } 527 528 if (time_after(last_timer, timeout)) { 529 if (!timer_pending(&musb->dev_timer)) 530 last_timer = timeout; 531 else { 532 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n"); 533 return; 534 } 535 } 536 last_timer = timeout; 537 538 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n", 539 usb_otg_state_string(musb->xceiv->otg->state), 540 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 541 mod_timer(&musb->dev_timer, timeout); 542 } 543 544 /* ticks of 60 MHz clock */ 545 #define DEVCLOCK 60000000 546 #define OTG_TIMER_MS(msecs) ((msecs) \ 547 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \ 548 | TUSB_DEV_OTG_TIMER_ENABLE) \ 549 : 0) 550 551 static void tusb_musb_set_vbus(struct musb *musb, int is_on) 552 { 553 void __iomem *tbase = musb->ctrl_base; 554 u32 conf, prcm, timer; 555 u8 devctl; 556 struct usb_otg *otg = musb->xceiv->otg; 557 558 /* HDRC controls CPEN, but beware current surges during device 559 * connect. They can trigger transient overcurrent conditions 560 * that must be ignored. 561 */ 562 563 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT); 564 conf = musb_readl(tbase, TUSB_DEV_CONF); 565 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 566 567 if (is_on) { 568 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); 569 otg->default_a = 1; 570 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 571 devctl |= MUSB_DEVCTL_SESSION; 572 573 conf |= TUSB_DEV_CONF_USB_HOST_MODE; 574 MUSB_HST_MODE(musb); 575 } else { 576 u32 otg_stat; 577 578 timer = 0; 579 580 /* If ID pin is grounded, we want to be a_idle */ 581 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 582 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { 583 switch (musb->xceiv->otg->state) { 584 case OTG_STATE_A_WAIT_VRISE: 585 case OTG_STATE_A_WAIT_BCON: 586 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; 587 break; 588 case OTG_STATE_A_WAIT_VFALL: 589 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 590 break; 591 default: 592 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 593 } 594 musb->is_active = 0; 595 otg->default_a = 1; 596 MUSB_HST_MODE(musb); 597 } else { 598 musb->is_active = 0; 599 otg->default_a = 0; 600 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 601 MUSB_DEV_MODE(musb); 602 } 603 604 devctl &= ~MUSB_DEVCTL_SESSION; 605 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE; 606 } 607 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 608 609 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm); 610 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer); 611 musb_writel(tbase, TUSB_DEV_CONF, conf); 612 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 613 614 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 615 usb_otg_state_string(musb->xceiv->otg->state), 616 musb_readb(musb->mregs, MUSB_DEVCTL), 617 musb_readl(tbase, TUSB_DEV_OTG_STAT), 618 conf, prcm); 619 } 620 621 /* 622 * Sets the mode to OTG, peripheral or host by changing the ID detection. 623 * Caller must take care of locking. 624 * 625 * Note that if a mini-A cable is plugged in the ID line will stay down as 626 * the weak ID pull-up is not able to pull the ID up. 627 */ 628 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode) 629 { 630 void __iomem *tbase = musb->ctrl_base; 631 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf; 632 633 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 634 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 635 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 636 dev_conf = musb_readl(tbase, TUSB_DEV_CONF); 637 638 switch (musb_mode) { 639 640 case MUSB_HOST: /* Disable PHY ID detect, ground ID */ 641 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 642 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 643 dev_conf |= TUSB_DEV_CONF_ID_SEL; 644 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID; 645 break; 646 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */ 647 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 648 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 649 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 650 break; 651 case MUSB_OTG: /* Use PHY ID detection */ 652 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 653 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 654 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 655 break; 656 657 default: 658 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode); 659 return -EINVAL; 660 } 661 662 musb_writel(tbase, TUSB_PHY_OTG_CTRL, 663 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl); 664 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, 665 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena); 666 musb_writel(tbase, TUSB_DEV_CONF, dev_conf); 667 668 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 669 if ((musb_mode == MUSB_PERIPHERAL) && 670 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) 671 INFO("Cannot be peripheral with mini-A cable " 672 "otg_stat: %08x\n", otg_stat); 673 674 return 0; 675 } 676 677 static inline unsigned long 678 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) 679 { 680 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 681 unsigned long idle_timeout = 0; 682 struct usb_otg *otg = musb->xceiv->otg; 683 684 /* ID pin */ 685 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) { 686 int default_a; 687 688 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 689 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B'); 690 otg->default_a = default_a; 691 tusb_musb_set_vbus(musb, default_a); 692 693 /* Don't allow idling immediately */ 694 if (default_a) 695 idle_timeout = jiffies + (HZ * 3); 696 } 697 698 /* VBUS state change */ 699 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { 700 701 /* B-dev state machine: no vbus ~= disconnect */ 702 if (!otg->default_a) { 703 /* ? musb_root_disconnect(musb); */ 704 musb->port1_status &= 705 ~(USB_PORT_STAT_CONNECTION 706 | USB_PORT_STAT_ENABLE 707 | USB_PORT_STAT_LOW_SPEED 708 | USB_PORT_STAT_HIGH_SPEED 709 | USB_PORT_STAT_TEST 710 ); 711 712 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 713 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n"); 714 if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) { 715 /* INTR_DISCONNECT can hide... */ 716 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 717 musb->int_usb |= MUSB_INTR_DISCONNECT; 718 } 719 musb->is_active = 0; 720 } 721 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", 722 usb_otg_state_string(musb->xceiv->otg->state), otg_stat); 723 idle_timeout = jiffies + (1 * HZ); 724 schedule_delayed_work(&musb->irq_work, 0); 725 726 } else /* A-dev state machine */ { 727 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", 728 usb_otg_state_string(musb->xceiv->otg->state), otg_stat); 729 730 switch (musb->xceiv->otg->state) { 731 case OTG_STATE_A_IDLE: 732 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n"); 733 musb_platform_set_vbus(musb, 1); 734 735 /* CONNECT can wake if a_wait_bcon is set */ 736 if (musb->a_wait_bcon != 0) 737 musb->is_active = 0; 738 else 739 musb->is_active = 1; 740 741 /* 742 * OPT FS A TD.4.6 needs few seconds for 743 * A_WAIT_VRISE 744 */ 745 idle_timeout = jiffies + (2 * HZ); 746 747 break; 748 case OTG_STATE_A_WAIT_VRISE: 749 /* ignore; A-session-valid < VBUS_VALID/2, 750 * we monitor this with the timer 751 */ 752 break; 753 case OTG_STATE_A_WAIT_VFALL: 754 /* REVISIT this irq triggers during short 755 * spikes caused by enumeration ... 756 */ 757 if (musb->vbuserr_retry) { 758 musb->vbuserr_retry--; 759 tusb_musb_set_vbus(musb, 1); 760 } else { 761 musb->vbuserr_retry 762 = VBUSERR_RETRY_COUNT; 763 tusb_musb_set_vbus(musb, 0); 764 } 765 break; 766 default: 767 break; 768 } 769 } 770 } 771 772 /* OTG timer expiration */ 773 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 774 u8 devctl; 775 776 dev_dbg(musb->controller, "%s timer, %03x\n", 777 usb_otg_state_string(musb->xceiv->otg->state), otg_stat); 778 779 switch (musb->xceiv->otg->state) { 780 case OTG_STATE_A_WAIT_VRISE: 781 /* VBUS has probably been valid for a while now, 782 * but may well have bounced out of range a bit 783 */ 784 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 785 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 786 if ((devctl & MUSB_DEVCTL_VBUS) 787 != MUSB_DEVCTL_VBUS) { 788 dev_dbg(musb->controller, "devctl %02x\n", devctl); 789 break; 790 } 791 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; 792 musb->is_active = 0; 793 idle_timeout = jiffies 794 + msecs_to_jiffies(musb->a_wait_bcon); 795 } else { 796 /* REVISIT report overcurrent to hub? */ 797 ERR("vbus too slow, devctl %02x\n", devctl); 798 tusb_musb_set_vbus(musb, 0); 799 } 800 break; 801 case OTG_STATE_A_WAIT_BCON: 802 if (musb->a_wait_bcon != 0) 803 idle_timeout = jiffies 804 + msecs_to_jiffies(musb->a_wait_bcon); 805 break; 806 case OTG_STATE_A_SUSPEND: 807 break; 808 case OTG_STATE_B_WAIT_ACON: 809 break; 810 default: 811 break; 812 } 813 } 814 schedule_delayed_work(&musb->irq_work, 0); 815 816 return idle_timeout; 817 } 818 819 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci) 820 { 821 struct musb *musb = __hci; 822 void __iomem *tbase = musb->ctrl_base; 823 unsigned long flags, idle_timeout = 0; 824 u32 int_mask, int_src; 825 826 spin_lock_irqsave(&musb->lock, flags); 827 828 /* Mask all interrupts to allow using both edge and level GPIO irq */ 829 int_mask = musb_readl(tbase, TUSB_INT_MASK); 830 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 831 832 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 833 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src); 834 835 musb->int_usb = (u8) int_src; 836 837 /* Acknowledge wake-up source interrupts */ 838 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) { 839 u32 reg; 840 u32 i; 841 842 if (musb->tusb_revision == TUSB_REV_30) 843 tusb_wbus_quirk(musb, 0); 844 845 /* there are issues re-locking the PLL on wakeup ... */ 846 847 /* work around issue 8 */ 848 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) { 849 musb_writel(tbase, TUSB_SCRATCH_PAD, 0); 850 musb_writel(tbase, TUSB_SCRATCH_PAD, i); 851 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 852 if (reg == i) 853 break; 854 dev_dbg(musb->controller, "TUSB NOR not ready\n"); 855 } 856 857 /* work around issue 13 (2nd half) */ 858 tusb_set_clock_source(musb, 1); 859 860 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE); 861 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); 862 if (reg & ~TUSB_PRCM_WNORCS) { 863 musb->is_active = 1; 864 schedule_delayed_work(&musb->irq_work, 0); 865 } 866 dev_dbg(musb->controller, "wake %sactive %02x\n", 867 musb->is_active ? "" : "in", reg); 868 869 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 870 } 871 872 if (int_src & TUSB_INT_SRC_USB_IP_CONN) 873 del_timer(&musb->dev_timer); 874 875 /* OTG state change reports (annoyingly) not issued by Mentor core */ 876 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG 877 | TUSB_INT_SRC_OTG_TIMEOUT 878 | TUSB_INT_SRC_ID_STATUS_CHNG)) 879 idle_timeout = tusb_otg_ints(musb, int_src, tbase); 880 881 /* 882 * Just clear the DMA interrupt if it comes as the completion for both 883 * TX and RX is handled by the DMA callback in tusb6010_omap 884 */ 885 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) { 886 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 887 888 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src); 889 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src); 890 } 891 892 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */ 893 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) { 894 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC); 895 896 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src); 897 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1); 898 musb->int_tx = (musb_src & 0xffff); 899 } else { 900 musb->int_rx = 0; 901 musb->int_tx = 0; 902 } 903 904 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff)) 905 musb_interrupt(musb); 906 907 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */ 908 musb_writel(tbase, TUSB_INT_SRC_CLEAR, 909 int_src & ~TUSB_INT_MASK_RESERVED_BITS); 910 911 tusb_musb_try_idle(musb, idle_timeout); 912 913 musb_writel(tbase, TUSB_INT_MASK, int_mask); 914 spin_unlock_irqrestore(&musb->lock, flags); 915 916 return IRQ_HANDLED; 917 } 918 919 static int dma_off; 920 921 /* 922 * Enables TUSB6010. Caller must take care of locking. 923 * REVISIT: 924 * - Check what is unnecessary in MGC_HdrcStart() 925 */ 926 static void tusb_musb_enable(struct musb *musb) 927 { 928 void __iomem *tbase = musb->ctrl_base; 929 930 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF. 931 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */ 932 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF); 933 934 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */ 935 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0); 936 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 937 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 938 939 /* Clear all subsystem interrups */ 940 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff); 941 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff); 942 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff); 943 944 /* Acknowledge pending interrupt(s) */ 945 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS); 946 947 /* Only 0 clock cycles for minimum interrupt de-assertion time and 948 * interrupt polarity active low seems to work reliably here */ 949 musb_writel(tbase, TUSB_INT_CTRL_CONF, 950 TUSB_INT_CTRL_CONF_INT_RELCYC(0)); 951 952 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW); 953 954 /* maybe force into the Default-A OTG state machine */ 955 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT) 956 & TUSB_DEV_OTG_STAT_ID_STATUS)) 957 musb_writel(tbase, TUSB_INT_SRC_SET, 958 TUSB_INT_SRC_ID_STATUS_CHNG); 959 960 if (is_dma_capable() && dma_off) 961 printk(KERN_WARNING "%s %s: dma not reactivated\n", 962 __FILE__, __func__); 963 else 964 dma_off = 1; 965 } 966 967 /* 968 * Disables TUSB6010. Caller must take care of locking. 969 */ 970 static void tusb_musb_disable(struct musb *musb) 971 { 972 void __iomem *tbase = musb->ctrl_base; 973 974 /* FIXME stop DMA, IRQs, timers, ... */ 975 976 /* disable all IRQs */ 977 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 978 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff); 979 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 980 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 981 982 del_timer(&musb->dev_timer); 983 984 if (is_dma_capable() && !dma_off) { 985 printk(KERN_WARNING "%s %s: dma still active\n", 986 __FILE__, __func__); 987 dma_off = 1; 988 } 989 } 990 991 /* 992 * Sets up TUSB6010 CPU interface specific signals and registers 993 * Note: Settings optimized for OMAP24xx 994 */ 995 static void tusb_setup_cpu_interface(struct musb *musb) 996 { 997 void __iomem *tbase = musb->ctrl_base; 998 999 /* 1000 * Disable GPIO[5:0] pullups (used as output DMA requests) 1001 * Don't disable GPIO[7:6] as they are needed for wake-up. 1002 */ 1003 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F); 1004 1005 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */ 1006 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF); 1007 1008 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */ 1009 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f)); 1010 1011 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request 1012 * de-assertion time 2 system clocks p 62 */ 1013 musb_writel(tbase, TUSB_DMA_REQ_CONF, 1014 TUSB_DMA_REQ_CONF_BURST_SIZE(2) | 1015 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | 1016 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 1017 1018 /* Set 0 wait count for synchronous burst access */ 1019 musb_writel(tbase, TUSB_WAIT_COUNT, 1); 1020 } 1021 1022 static int tusb_musb_start(struct musb *musb) 1023 { 1024 void __iomem *tbase = musb->ctrl_base; 1025 int ret = 0; 1026 unsigned long flags; 1027 u32 reg; 1028 1029 if (musb->board_set_power) 1030 ret = musb->board_set_power(1); 1031 if (ret != 0) { 1032 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n"); 1033 return ret; 1034 } 1035 1036 spin_lock_irqsave(&musb->lock, flags); 1037 1038 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) != 1039 TUSB_PROD_TEST_RESET_VAL) { 1040 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n"); 1041 goto err; 1042 } 1043 1044 musb->tusb_revision = tusb_get_revision(musb); 1045 tusb_print_revision(musb); 1046 if (musb->tusb_revision < 2) { 1047 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n", 1048 musb->tusb_revision); 1049 goto err; 1050 } 1051 1052 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when 1053 * NOR FLASH interface is used */ 1054 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8); 1055 1056 /* Select PHY free running 60MHz as a system clock */ 1057 tusb_set_clock_source(musb, 1); 1058 1059 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for 1060 * power saving, enable VBus detect and session end comparators, 1061 * enable IDpullup, enable VBus charging */ 1062 musb_writel(tbase, TUSB_PRCM_MNGMT, 1063 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) | 1064 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN | 1065 TUSB_PRCM_MNGMT_OTG_SESS_END_EN | 1066 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN | 1067 TUSB_PRCM_MNGMT_OTG_ID_PULLUP); 1068 tusb_setup_cpu_interface(musb); 1069 1070 /* simplify: always sense/pullup ID pins, as if in OTG mode */ 1071 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 1072 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1073 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg); 1074 1075 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 1076 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1077 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg); 1078 1079 spin_unlock_irqrestore(&musb->lock, flags); 1080 1081 return 0; 1082 1083 err: 1084 spin_unlock_irqrestore(&musb->lock, flags); 1085 1086 if (musb->board_set_power) 1087 musb->board_set_power(0); 1088 1089 return -ENODEV; 1090 } 1091 1092 static int tusb_musb_init(struct musb *musb) 1093 { 1094 struct platform_device *pdev; 1095 struct resource *mem; 1096 void __iomem *sync = NULL; 1097 int ret; 1098 1099 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 1100 if (IS_ERR_OR_NULL(musb->xceiv)) 1101 return -EPROBE_DEFER; 1102 1103 pdev = to_platform_device(musb->controller); 1104 1105 /* dma address for async dma */ 1106 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1107 if (!mem) { 1108 pr_debug("no async dma resource?\n"); 1109 ret = -ENODEV; 1110 goto done; 1111 } 1112 musb->async = mem->start; 1113 1114 /* dma address for sync dma */ 1115 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1116 if (!mem) { 1117 pr_debug("no sync dma resource?\n"); 1118 ret = -ENODEV; 1119 goto done; 1120 } 1121 musb->sync = mem->start; 1122 1123 sync = ioremap(mem->start, resource_size(mem)); 1124 if (!sync) { 1125 pr_debug("ioremap for sync failed\n"); 1126 ret = -ENOMEM; 1127 goto done; 1128 } 1129 musb->sync_va = sync; 1130 1131 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400, 1132 * FIFOs at 0x600, TUSB at 0x800 1133 */ 1134 musb->mregs += TUSB_BASE_OFFSET; 1135 1136 ret = tusb_musb_start(musb); 1137 if (ret) { 1138 printk(KERN_ERR "Could not start tusb6010 (%d)\n", 1139 ret); 1140 goto done; 1141 } 1142 musb->isr = tusb_musb_interrupt; 1143 1144 musb->xceiv->set_power = tusb_draw_power; 1145 the_musb = musb; 1146 1147 timer_setup(&musb->dev_timer, musb_do_idle, 0); 1148 1149 done: 1150 if (ret < 0) { 1151 if (sync) 1152 iounmap(sync); 1153 1154 usb_put_phy(musb->xceiv); 1155 } 1156 return ret; 1157 } 1158 1159 static int tusb_musb_exit(struct musb *musb) 1160 { 1161 del_timer_sync(&musb->dev_timer); 1162 the_musb = NULL; 1163 1164 if (musb->board_set_power) 1165 musb->board_set_power(0); 1166 1167 iounmap(musb->sync_va); 1168 1169 usb_put_phy(musb->xceiv); 1170 return 0; 1171 } 1172 1173 static const struct musb_platform_ops tusb_ops = { 1174 .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB | 1175 MUSB_G_NO_SKB_RESERVE, 1176 .init = tusb_musb_init, 1177 .exit = tusb_musb_exit, 1178 1179 .ep_offset = tusb_ep_offset, 1180 .ep_select = tusb_ep_select, 1181 .fifo_offset = tusb_fifo_offset, 1182 .readb = tusb_readb, 1183 .writeb = tusb_writeb, 1184 .read_fifo = tusb_read_fifo, 1185 .write_fifo = tusb_write_fifo, 1186 #ifdef CONFIG_USB_TUSB_OMAP_DMA 1187 .dma_init = tusb_dma_controller_create, 1188 .dma_exit = tusb_dma_controller_destroy, 1189 #endif 1190 .enable = tusb_musb_enable, 1191 .disable = tusb_musb_disable, 1192 1193 .set_mode = tusb_musb_set_mode, 1194 .try_idle = tusb_musb_try_idle, 1195 1196 .vbus_status = tusb_musb_vbus_status, 1197 .set_vbus = tusb_musb_set_vbus, 1198 }; 1199 1200 static const struct platform_device_info tusb_dev_info = { 1201 .name = "musb-hdrc", 1202 .id = PLATFORM_DEVID_AUTO, 1203 .dma_mask = DMA_BIT_MASK(32), 1204 }; 1205 1206 static int tusb_probe(struct platform_device *pdev) 1207 { 1208 struct resource musb_resources[3]; 1209 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); 1210 struct platform_device *musb; 1211 struct tusb6010_glue *glue; 1212 struct platform_device_info pinfo; 1213 int ret; 1214 1215 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 1216 if (!glue) 1217 return -ENOMEM; 1218 1219 glue->dev = &pdev->dev; 1220 1221 pdata->platform_ops = &tusb_ops; 1222 1223 usb_phy_generic_register(); 1224 platform_set_drvdata(pdev, glue); 1225 1226 memset(musb_resources, 0x00, sizeof(*musb_resources) * 1227 ARRAY_SIZE(musb_resources)); 1228 1229 musb_resources[0].name = pdev->resource[0].name; 1230 musb_resources[0].start = pdev->resource[0].start; 1231 musb_resources[0].end = pdev->resource[0].end; 1232 musb_resources[0].flags = pdev->resource[0].flags; 1233 1234 musb_resources[1].name = pdev->resource[1].name; 1235 musb_resources[1].start = pdev->resource[1].start; 1236 musb_resources[1].end = pdev->resource[1].end; 1237 musb_resources[1].flags = pdev->resource[1].flags; 1238 1239 musb_resources[2].name = pdev->resource[2].name; 1240 musb_resources[2].start = pdev->resource[2].start; 1241 musb_resources[2].end = pdev->resource[2].end; 1242 musb_resources[2].flags = pdev->resource[2].flags; 1243 1244 pinfo = tusb_dev_info; 1245 pinfo.parent = &pdev->dev; 1246 pinfo.res = musb_resources; 1247 pinfo.num_res = ARRAY_SIZE(musb_resources); 1248 pinfo.data = pdata; 1249 pinfo.size_data = sizeof(*pdata); 1250 1251 glue->musb = musb = platform_device_register_full(&pinfo); 1252 if (IS_ERR(musb)) { 1253 ret = PTR_ERR(musb); 1254 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret); 1255 return ret; 1256 } 1257 1258 return 0; 1259 } 1260 1261 static int tusb_remove(struct platform_device *pdev) 1262 { 1263 struct tusb6010_glue *glue = platform_get_drvdata(pdev); 1264 1265 platform_device_unregister(glue->musb); 1266 usb_phy_generic_unregister(glue->phy); 1267 1268 return 0; 1269 } 1270 1271 static struct platform_driver tusb_driver = { 1272 .probe = tusb_probe, 1273 .remove = tusb_remove, 1274 .driver = { 1275 .name = "musb-tusb", 1276 }, 1277 }; 1278 1279 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer"); 1280 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1281 MODULE_LICENSE("GPL v2"); 1282 module_platform_driver(tusb_driver); 1283