1 /* 2 * TUSB6010 USB 2.0 OTG Dual Role controller 3 * 4 * Copyright (C) 2006 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Notes: 12 * - Driver assumes that interface to external host (main CPU) is 13 * configured for NOR FLASH interface instead of VLYNQ serial 14 * interface. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/errno.h> 20 #include <linux/err.h> 21 #include <linux/prefetch.h> 22 #include <linux/usb.h> 23 #include <linux/irq.h> 24 #include <linux/io.h> 25 #include <linux/device.h> 26 #include <linux/platform_device.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/usb/usb_phy_generic.h> 29 30 #include "musb_core.h" 31 32 struct tusb6010_glue { 33 struct device *dev; 34 struct platform_device *musb; 35 struct platform_device *phy; 36 }; 37 38 static void tusb_musb_set_vbus(struct musb *musb, int is_on); 39 40 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) 41 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) 42 43 /* 44 * Checks the revision. We need to use the DMA register as 3.0 does not 45 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. 46 */ 47 static u8 tusb_get_revision(struct musb *musb) 48 { 49 void __iomem *tbase = musb->ctrl_base; 50 u32 die_id; 51 u8 rev; 52 53 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff; 54 if (TUSB_REV_MAJOR(rev) == 3) { 55 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, 56 TUSB_DIDR1_HI)); 57 if (die_id >= TUSB_DIDR1_HI_REV_31) 58 rev |= 1; 59 } 60 61 return rev; 62 } 63 64 static void tusb_print_revision(struct musb *musb) 65 { 66 void __iomem *tbase = musb->ctrl_base; 67 u8 rev; 68 69 rev = musb->tusb_revision; 70 71 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n", 72 "prcm", 73 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)), 74 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)), 75 "int", 76 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 77 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 78 "gpio", 79 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)), 80 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)), 81 "dma", 82 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 83 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 84 "dieid", 85 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)), 86 "rev", 87 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev)); 88 } 89 90 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \ 91 | TUSB_PHY_OTG_CTRL_TESTM0) 92 93 /* 94 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0. 95 * Disables power detection in PHY for the duration of idle. 96 */ 97 static void tusb_wbus_quirk(struct musb *musb, int enabled) 98 { 99 void __iomem *tbase = musb->ctrl_base; 100 static u32 phy_otg_ctrl, phy_otg_ena; 101 u32 tmp; 102 103 if (enabled) { 104 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 105 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 106 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT 107 | phy_otg_ena | WBUS_QUIRK_MASK; 108 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 109 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 110 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 111 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 112 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 113 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 114 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 115 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 116 & TUSB_PHY_OTG_CTRL_TESTM2) { 117 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl; 118 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 119 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 120 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 121 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 122 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 123 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 124 phy_otg_ctrl = 0; 125 phy_otg_ena = 0; 126 } 127 } 128 129 static u32 tusb_fifo_offset(u8 epnum) 130 { 131 return 0x200 + (epnum * 0x20); 132 } 133 134 static u32 tusb_ep_offset(u8 epnum, u16 offset) 135 { 136 return 0x10 + offset; 137 } 138 139 /* TUSB mapping: "flat" plus ep0 special cases */ 140 static void tusb_ep_select(void __iomem *mbase, u8 epnum) 141 { 142 musb_writeb(mbase, MUSB_INDEX, epnum); 143 } 144 145 /* 146 * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum. 147 */ 148 static u8 tusb_readb(const void __iomem *addr, unsigned offset) 149 { 150 u16 tmp; 151 u8 val; 152 153 tmp = __raw_readw(addr + (offset & ~1)); 154 if (offset & 1) 155 val = (tmp >> 8); 156 else 157 val = tmp & 0xff; 158 159 return val; 160 } 161 162 static void tusb_writeb(void __iomem *addr, unsigned offset, u8 data) 163 { 164 u16 tmp; 165 166 tmp = __raw_readw(addr + (offset & ~1)); 167 if (offset & 1) 168 tmp = (data << 8) | (tmp & 0xff); 169 else 170 tmp = (tmp & 0xff00) | data; 171 172 __raw_writew(tmp, addr + (offset & ~1)); 173 } 174 175 /* 176 * TUSB 6010 may use a parallel bus that doesn't support byte ops; 177 * so both loading and unloading FIFOs need explicit byte counts. 178 */ 179 180 static inline void 181 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len) 182 { 183 u32 val; 184 int i; 185 186 if (len > 4) { 187 for (i = 0; i < (len >> 2); i++) { 188 memcpy(&val, buf, 4); 189 musb_writel(fifo, 0, val); 190 buf += 4; 191 } 192 len %= 4; 193 } 194 if (len > 0) { 195 /* Write the rest 1 - 3 bytes to FIFO */ 196 memcpy(&val, buf, len); 197 musb_writel(fifo, 0, val); 198 } 199 } 200 201 static inline void tusb_fifo_read_unaligned(void __iomem *fifo, 202 void *buf, u16 len) 203 { 204 u32 val; 205 int i; 206 207 if (len > 4) { 208 for (i = 0; i < (len >> 2); i++) { 209 val = musb_readl(fifo, 0); 210 memcpy(buf, &val, 4); 211 buf += 4; 212 } 213 len %= 4; 214 } 215 if (len > 0) { 216 /* Read the rest 1 - 3 bytes from FIFO */ 217 val = musb_readl(fifo, 0); 218 memcpy(buf, &val, len); 219 } 220 } 221 222 static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) 223 { 224 struct musb *musb = hw_ep->musb; 225 void __iomem *ep_conf = hw_ep->conf; 226 void __iomem *fifo = hw_ep->fifo; 227 u8 epnum = hw_ep->epnum; 228 229 prefetch(buf); 230 231 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 232 'T', epnum, fifo, len, buf); 233 234 if (epnum) 235 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 236 TUSB_EP_CONFIG_XFR_SIZE(len)); 237 else 238 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX | 239 TUSB_EP0_CONFIG_XFR_SIZE(len)); 240 241 if (likely((0x01 & (unsigned long) buf) == 0)) { 242 243 /* Best case is 32bit-aligned destination address */ 244 if ((0x02 & (unsigned long) buf) == 0) { 245 if (len >= 4) { 246 iowrite32_rep(fifo, buf, len >> 2); 247 buf += (len & ~0x03); 248 len &= 0x03; 249 } 250 } else { 251 if (len >= 2) { 252 u32 val; 253 int i; 254 255 /* Cannot use writesw, fifo is 32-bit */ 256 for (i = 0; i < (len >> 2); i++) { 257 val = (u32)(*(u16 *)buf); 258 buf += 2; 259 val |= (*(u16 *)buf) << 16; 260 buf += 2; 261 musb_writel(fifo, 0, val); 262 } 263 len &= 0x03; 264 } 265 } 266 } 267 268 if (len > 0) 269 tusb_fifo_write_unaligned(fifo, buf, len); 270 } 271 272 static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) 273 { 274 struct musb *musb = hw_ep->musb; 275 void __iomem *ep_conf = hw_ep->conf; 276 void __iomem *fifo = hw_ep->fifo; 277 u8 epnum = hw_ep->epnum; 278 279 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 280 'R', epnum, fifo, len, buf); 281 282 if (epnum) 283 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 284 TUSB_EP_CONFIG_XFR_SIZE(len)); 285 else 286 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len)); 287 288 if (likely((0x01 & (unsigned long) buf) == 0)) { 289 290 /* Best case is 32bit-aligned destination address */ 291 if ((0x02 & (unsigned long) buf) == 0) { 292 if (len >= 4) { 293 ioread32_rep(fifo, buf, len >> 2); 294 buf += (len & ~0x03); 295 len &= 0x03; 296 } 297 } else { 298 if (len >= 2) { 299 u32 val; 300 int i; 301 302 /* Cannot use readsw, fifo is 32-bit */ 303 for (i = 0; i < (len >> 2); i++) { 304 val = musb_readl(fifo, 0); 305 *(u16 *)buf = (u16)(val & 0xffff); 306 buf += 2; 307 *(u16 *)buf = (u16)(val >> 16); 308 buf += 2; 309 } 310 len &= 0x03; 311 } 312 } 313 } 314 315 if (len > 0) 316 tusb_fifo_read_unaligned(fifo, buf, len); 317 } 318 319 static struct musb *the_musb; 320 321 /* This is used by gadget drivers, and OTG transceiver logic, allowing 322 * at most mA current to be drawn from VBUS during a Default-B session 323 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host 324 * mode), or low power Default-B sessions, something else supplies power. 325 * Caller must take care of locking. 326 */ 327 static int tusb_draw_power(struct usb_phy *x, unsigned mA) 328 { 329 struct musb *musb = the_musb; 330 void __iomem *tbase = musb->ctrl_base; 331 u32 reg; 332 333 /* tps65030 seems to consume max 100mA, with maybe 60mA available 334 * (measured on one board) for things other than tps and tusb. 335 * 336 * Boards sharing the CPU clock with CLKIN will need to prevent 337 * certain idle sleep states while the USB link is active. 338 * 339 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }. 340 * The actual current usage would be very board-specific. For now, 341 * it's simpler to just use an aggregate (also board-specific). 342 */ 343 if (x->otg->default_a || mA < (musb->min_power << 1)) 344 mA = 0; 345 346 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 347 if (mA) { 348 musb->is_bus_powered = 1; 349 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; 350 } else { 351 musb->is_bus_powered = 0; 352 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 353 } 354 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 355 356 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA); 357 return 0; 358 } 359 360 /* workaround for issue 13: change clock during chip idle 361 * (to be fixed in rev3 silicon) ... symptoms include disconnect 362 * or looping suspend/resume cycles 363 */ 364 static void tusb_set_clock_source(struct musb *musb, unsigned mode) 365 { 366 void __iomem *tbase = musb->ctrl_base; 367 u32 reg; 368 369 reg = musb_readl(tbase, TUSB_PRCM_CONF); 370 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); 371 372 /* 0 = refclk (clkin, XI) 373 * 1 = PHY 60 MHz (internal PLL) 374 * 2 = not supported 375 * 3 = what? 376 */ 377 if (mode > 0) 378 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); 379 380 musb_writel(tbase, TUSB_PRCM_CONF, reg); 381 382 /* FIXME tusb6010_platform_retime(mode == 0); */ 383 } 384 385 /* 386 * Idle TUSB6010 until next wake-up event; NOR access always wakes. 387 * Other code ensures that we idle unless we're connected _and_ the 388 * USB link is not suspended ... and tells us the relevant wakeup 389 * events. SW_EN for voltage is handled separately. 390 */ 391 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables) 392 { 393 void __iomem *tbase = musb->ctrl_base; 394 u32 reg; 395 396 if ((wakeup_enables & TUSB_PRCM_WBUS) 397 && (musb->tusb_revision == TUSB_REV_30)) 398 tusb_wbus_quirk(musb, 1); 399 400 tusb_set_clock_source(musb, 0); 401 402 wakeup_enables |= TUSB_PRCM_WNORCS; 403 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables); 404 405 /* REVISIT writeup of WID implies that if WID set and ID is grounded, 406 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared. 407 * Presumably that's mostly to save power, hence WID is immaterial ... 408 */ 409 410 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 411 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */ 412 if (is_host_active(musb)) { 413 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 414 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 415 } else { 416 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 417 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 418 } 419 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 420 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 421 422 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables); 423 } 424 425 /* 426 * Updates cable VBUS status. Caller must take care of locking. 427 */ 428 static int tusb_musb_vbus_status(struct musb *musb) 429 { 430 void __iomem *tbase = musb->ctrl_base; 431 u32 otg_stat, prcm_mngmt; 432 int ret = 0; 433 434 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 435 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT); 436 437 /* Temporarily enable VBUS detection if it was disabled for 438 * suspend mode. Unless it's enabled otg_stat and devctl will 439 * not show correct VBUS state. 440 */ 441 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) { 442 u32 tmp = prcm_mngmt; 443 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 444 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp); 445 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 446 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt); 447 } 448 449 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) 450 ret = 1; 451 452 return ret; 453 } 454 455 static struct timer_list musb_idle_timer; 456 457 static void musb_do_idle(unsigned long _musb) 458 { 459 struct musb *musb = (void *)_musb; 460 unsigned long flags; 461 462 spin_lock_irqsave(&musb->lock, flags); 463 464 switch (musb->xceiv->otg->state) { 465 case OTG_STATE_A_WAIT_BCON: 466 if ((musb->a_wait_bcon != 0) 467 && (musb->idle_timeout == 0 468 || time_after(jiffies, musb->idle_timeout))) { 469 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n", 470 usb_otg_state_string(musb->xceiv->otg->state)); 471 } 472 /* FALLTHROUGH */ 473 case OTG_STATE_A_IDLE: 474 tusb_musb_set_vbus(musb, 0); 475 default: 476 break; 477 } 478 479 if (!musb->is_active) { 480 u32 wakeups; 481 482 /* wait until hub_wq handles port change status */ 483 if (is_host_active(musb) && (musb->port1_status >> 16)) 484 goto done; 485 486 if (!musb->gadget_driver) { 487 wakeups = 0; 488 } else { 489 wakeups = TUSB_PRCM_WHOSTDISCON 490 | TUSB_PRCM_WBUS 491 | TUSB_PRCM_WVBUS; 492 wakeups |= TUSB_PRCM_WID; 493 } 494 tusb_allow_idle(musb, wakeups); 495 } 496 done: 497 spin_unlock_irqrestore(&musb->lock, flags); 498 } 499 500 /* 501 * Maybe put TUSB6010 into idle mode mode depending on USB link status, 502 * like "disconnected" or "suspended". We'll be woken out of it by 503 * connect, resume, or disconnect. 504 * 505 * Needs to be called as the last function everywhere where there is 506 * register access to TUSB6010 because of NOR flash wake-up. 507 * Caller should own controller spinlock. 508 * 509 * Delay because peripheral enables D+ pullup 3msec after SE0, and 510 * we don't want to treat that full speed J as a wakeup event. 511 * ... peripherals must draw only suspend current after 10 msec. 512 */ 513 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout) 514 { 515 unsigned long default_timeout = jiffies + msecs_to_jiffies(3); 516 static unsigned long last_timer; 517 518 if (timeout == 0) 519 timeout = default_timeout; 520 521 /* Never idle if active, or when VBUS timeout is not set as host */ 522 if (musb->is_active || ((musb->a_wait_bcon == 0) 523 && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) { 524 dev_dbg(musb->controller, "%s active, deleting timer\n", 525 usb_otg_state_string(musb->xceiv->otg->state)); 526 del_timer(&musb_idle_timer); 527 last_timer = jiffies; 528 return; 529 } 530 531 if (time_after(last_timer, timeout)) { 532 if (!timer_pending(&musb_idle_timer)) 533 last_timer = timeout; 534 else { 535 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n"); 536 return; 537 } 538 } 539 last_timer = timeout; 540 541 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n", 542 usb_otg_state_string(musb->xceiv->otg->state), 543 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 544 mod_timer(&musb_idle_timer, timeout); 545 } 546 547 /* ticks of 60 MHz clock */ 548 #define DEVCLOCK 60000000 549 #define OTG_TIMER_MS(msecs) ((msecs) \ 550 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \ 551 | TUSB_DEV_OTG_TIMER_ENABLE) \ 552 : 0) 553 554 static void tusb_musb_set_vbus(struct musb *musb, int is_on) 555 { 556 void __iomem *tbase = musb->ctrl_base; 557 u32 conf, prcm, timer; 558 u8 devctl; 559 struct usb_otg *otg = musb->xceiv->otg; 560 561 /* HDRC controls CPEN, but beware current surges during device 562 * connect. They can trigger transient overcurrent conditions 563 * that must be ignored. 564 */ 565 566 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT); 567 conf = musb_readl(tbase, TUSB_DEV_CONF); 568 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 569 570 if (is_on) { 571 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); 572 otg->default_a = 1; 573 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 574 devctl |= MUSB_DEVCTL_SESSION; 575 576 conf |= TUSB_DEV_CONF_USB_HOST_MODE; 577 MUSB_HST_MODE(musb); 578 } else { 579 u32 otg_stat; 580 581 timer = 0; 582 583 /* If ID pin is grounded, we want to be a_idle */ 584 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 585 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { 586 switch (musb->xceiv->otg->state) { 587 case OTG_STATE_A_WAIT_VRISE: 588 case OTG_STATE_A_WAIT_BCON: 589 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; 590 break; 591 case OTG_STATE_A_WAIT_VFALL: 592 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 593 break; 594 default: 595 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 596 } 597 musb->is_active = 0; 598 otg->default_a = 1; 599 MUSB_HST_MODE(musb); 600 } else { 601 musb->is_active = 0; 602 otg->default_a = 0; 603 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 604 MUSB_DEV_MODE(musb); 605 } 606 607 devctl &= ~MUSB_DEVCTL_SESSION; 608 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE; 609 } 610 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 611 612 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm); 613 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer); 614 musb_writel(tbase, TUSB_DEV_CONF, conf); 615 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 616 617 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 618 usb_otg_state_string(musb->xceiv->otg->state), 619 musb_readb(musb->mregs, MUSB_DEVCTL), 620 musb_readl(tbase, TUSB_DEV_OTG_STAT), 621 conf, prcm); 622 } 623 624 /* 625 * Sets the mode to OTG, peripheral or host by changing the ID detection. 626 * Caller must take care of locking. 627 * 628 * Note that if a mini-A cable is plugged in the ID line will stay down as 629 * the weak ID pull-up is not able to pull the ID up. 630 */ 631 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode) 632 { 633 void __iomem *tbase = musb->ctrl_base; 634 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf; 635 636 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 637 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 638 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 639 dev_conf = musb_readl(tbase, TUSB_DEV_CONF); 640 641 switch (musb_mode) { 642 643 case MUSB_HOST: /* Disable PHY ID detect, ground ID */ 644 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 645 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 646 dev_conf |= TUSB_DEV_CONF_ID_SEL; 647 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID; 648 break; 649 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */ 650 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 651 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 652 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 653 break; 654 case MUSB_OTG: /* Use PHY ID detection */ 655 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 656 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 657 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 658 break; 659 660 default: 661 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode); 662 return -EINVAL; 663 } 664 665 musb_writel(tbase, TUSB_PHY_OTG_CTRL, 666 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl); 667 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, 668 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena); 669 musb_writel(tbase, TUSB_DEV_CONF, dev_conf); 670 671 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 672 if ((musb_mode == MUSB_PERIPHERAL) && 673 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) 674 INFO("Cannot be peripheral with mini-A cable " 675 "otg_stat: %08x\n", otg_stat); 676 677 return 0; 678 } 679 680 static inline unsigned long 681 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) 682 { 683 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 684 unsigned long idle_timeout = 0; 685 struct usb_otg *otg = musb->xceiv->otg; 686 687 /* ID pin */ 688 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) { 689 int default_a; 690 691 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 692 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B'); 693 otg->default_a = default_a; 694 tusb_musb_set_vbus(musb, default_a); 695 696 /* Don't allow idling immediately */ 697 if (default_a) 698 idle_timeout = jiffies + (HZ * 3); 699 } 700 701 /* VBUS state change */ 702 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { 703 704 /* B-dev state machine: no vbus ~= disconnect */ 705 if (!otg->default_a) { 706 /* ? musb_root_disconnect(musb); */ 707 musb->port1_status &= 708 ~(USB_PORT_STAT_CONNECTION 709 | USB_PORT_STAT_ENABLE 710 | USB_PORT_STAT_LOW_SPEED 711 | USB_PORT_STAT_HIGH_SPEED 712 | USB_PORT_STAT_TEST 713 ); 714 715 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 716 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n"); 717 if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) { 718 /* INTR_DISCONNECT can hide... */ 719 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 720 musb->int_usb |= MUSB_INTR_DISCONNECT; 721 } 722 musb->is_active = 0; 723 } 724 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", 725 usb_otg_state_string(musb->xceiv->otg->state), otg_stat); 726 idle_timeout = jiffies + (1 * HZ); 727 schedule_work(&musb->irq_work); 728 729 } else /* A-dev state machine */ { 730 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", 731 usb_otg_state_string(musb->xceiv->otg->state), otg_stat); 732 733 switch (musb->xceiv->otg->state) { 734 case OTG_STATE_A_IDLE: 735 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n"); 736 musb_platform_set_vbus(musb, 1); 737 738 /* CONNECT can wake if a_wait_bcon is set */ 739 if (musb->a_wait_bcon != 0) 740 musb->is_active = 0; 741 else 742 musb->is_active = 1; 743 744 /* 745 * OPT FS A TD.4.6 needs few seconds for 746 * A_WAIT_VRISE 747 */ 748 idle_timeout = jiffies + (2 * HZ); 749 750 break; 751 case OTG_STATE_A_WAIT_VRISE: 752 /* ignore; A-session-valid < VBUS_VALID/2, 753 * we monitor this with the timer 754 */ 755 break; 756 case OTG_STATE_A_WAIT_VFALL: 757 /* REVISIT this irq triggers during short 758 * spikes caused by enumeration ... 759 */ 760 if (musb->vbuserr_retry) { 761 musb->vbuserr_retry--; 762 tusb_musb_set_vbus(musb, 1); 763 } else { 764 musb->vbuserr_retry 765 = VBUSERR_RETRY_COUNT; 766 tusb_musb_set_vbus(musb, 0); 767 } 768 break; 769 default: 770 break; 771 } 772 } 773 } 774 775 /* OTG timer expiration */ 776 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 777 u8 devctl; 778 779 dev_dbg(musb->controller, "%s timer, %03x\n", 780 usb_otg_state_string(musb->xceiv->otg->state), otg_stat); 781 782 switch (musb->xceiv->otg->state) { 783 case OTG_STATE_A_WAIT_VRISE: 784 /* VBUS has probably been valid for a while now, 785 * but may well have bounced out of range a bit 786 */ 787 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 788 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 789 if ((devctl & MUSB_DEVCTL_VBUS) 790 != MUSB_DEVCTL_VBUS) { 791 dev_dbg(musb->controller, "devctl %02x\n", devctl); 792 break; 793 } 794 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; 795 musb->is_active = 0; 796 idle_timeout = jiffies 797 + msecs_to_jiffies(musb->a_wait_bcon); 798 } else { 799 /* REVISIT report overcurrent to hub? */ 800 ERR("vbus too slow, devctl %02x\n", devctl); 801 tusb_musb_set_vbus(musb, 0); 802 } 803 break; 804 case OTG_STATE_A_WAIT_BCON: 805 if (musb->a_wait_bcon != 0) 806 idle_timeout = jiffies 807 + msecs_to_jiffies(musb->a_wait_bcon); 808 break; 809 case OTG_STATE_A_SUSPEND: 810 break; 811 case OTG_STATE_B_WAIT_ACON: 812 break; 813 default: 814 break; 815 } 816 } 817 schedule_work(&musb->irq_work); 818 819 return idle_timeout; 820 } 821 822 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci) 823 { 824 struct musb *musb = __hci; 825 void __iomem *tbase = musb->ctrl_base; 826 unsigned long flags, idle_timeout = 0; 827 u32 int_mask, int_src; 828 829 spin_lock_irqsave(&musb->lock, flags); 830 831 /* Mask all interrupts to allow using both edge and level GPIO irq */ 832 int_mask = musb_readl(tbase, TUSB_INT_MASK); 833 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 834 835 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 836 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src); 837 838 musb->int_usb = (u8) int_src; 839 840 /* Acknowledge wake-up source interrupts */ 841 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) { 842 u32 reg; 843 u32 i; 844 845 if (musb->tusb_revision == TUSB_REV_30) 846 tusb_wbus_quirk(musb, 0); 847 848 /* there are issues re-locking the PLL on wakeup ... */ 849 850 /* work around issue 8 */ 851 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) { 852 musb_writel(tbase, TUSB_SCRATCH_PAD, 0); 853 musb_writel(tbase, TUSB_SCRATCH_PAD, i); 854 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 855 if (reg == i) 856 break; 857 dev_dbg(musb->controller, "TUSB NOR not ready\n"); 858 } 859 860 /* work around issue 13 (2nd half) */ 861 tusb_set_clock_source(musb, 1); 862 863 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE); 864 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); 865 if (reg & ~TUSB_PRCM_WNORCS) { 866 musb->is_active = 1; 867 schedule_work(&musb->irq_work); 868 } 869 dev_dbg(musb->controller, "wake %sactive %02x\n", 870 musb->is_active ? "" : "in", reg); 871 872 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 873 } 874 875 if (int_src & TUSB_INT_SRC_USB_IP_CONN) 876 del_timer(&musb_idle_timer); 877 878 /* OTG state change reports (annoyingly) not issued by Mentor core */ 879 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG 880 | TUSB_INT_SRC_OTG_TIMEOUT 881 | TUSB_INT_SRC_ID_STATUS_CHNG)) 882 idle_timeout = tusb_otg_ints(musb, int_src, tbase); 883 884 /* TX dma callback must be handled here, RX dma callback is 885 * handled in tusb_omap_dma_cb. 886 */ 887 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) { 888 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 889 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK); 890 891 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src); 892 real_dma_src = ~real_dma_src & dma_src; 893 if (tusb_dma_omap(musb) && real_dma_src) { 894 int tx_source = (real_dma_src & 0xffff); 895 int i; 896 897 for (i = 1; i <= 15; i++) { 898 if (tx_source & (1 << i)) { 899 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx"); 900 musb_dma_completion(musb, i, 1); 901 } 902 } 903 } 904 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src); 905 } 906 907 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */ 908 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) { 909 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC); 910 911 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src); 912 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1); 913 musb->int_tx = (musb_src & 0xffff); 914 } else { 915 musb->int_rx = 0; 916 musb->int_tx = 0; 917 } 918 919 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff)) 920 musb_interrupt(musb); 921 922 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */ 923 musb_writel(tbase, TUSB_INT_SRC_CLEAR, 924 int_src & ~TUSB_INT_MASK_RESERVED_BITS); 925 926 tusb_musb_try_idle(musb, idle_timeout); 927 928 musb_writel(tbase, TUSB_INT_MASK, int_mask); 929 spin_unlock_irqrestore(&musb->lock, flags); 930 931 return IRQ_HANDLED; 932 } 933 934 static int dma_off; 935 936 /* 937 * Enables TUSB6010. Caller must take care of locking. 938 * REVISIT: 939 * - Check what is unnecessary in MGC_HdrcStart() 940 */ 941 static void tusb_musb_enable(struct musb *musb) 942 { 943 void __iomem *tbase = musb->ctrl_base; 944 945 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF. 946 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */ 947 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF); 948 949 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */ 950 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0); 951 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 952 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 953 954 /* Clear all subsystem interrups */ 955 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff); 956 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff); 957 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff); 958 959 /* Acknowledge pending interrupt(s) */ 960 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS); 961 962 /* Only 0 clock cycles for minimum interrupt de-assertion time and 963 * interrupt polarity active low seems to work reliably here */ 964 musb_writel(tbase, TUSB_INT_CTRL_CONF, 965 TUSB_INT_CTRL_CONF_INT_RELCYC(0)); 966 967 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW); 968 969 /* maybe force into the Default-A OTG state machine */ 970 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT) 971 & TUSB_DEV_OTG_STAT_ID_STATUS)) 972 musb_writel(tbase, TUSB_INT_SRC_SET, 973 TUSB_INT_SRC_ID_STATUS_CHNG); 974 975 if (is_dma_capable() && dma_off) 976 printk(KERN_WARNING "%s %s: dma not reactivated\n", 977 __FILE__, __func__); 978 else 979 dma_off = 1; 980 } 981 982 /* 983 * Disables TUSB6010. Caller must take care of locking. 984 */ 985 static void tusb_musb_disable(struct musb *musb) 986 { 987 void __iomem *tbase = musb->ctrl_base; 988 989 /* FIXME stop DMA, IRQs, timers, ... */ 990 991 /* disable all IRQs */ 992 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 993 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff); 994 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 995 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 996 997 del_timer(&musb_idle_timer); 998 999 if (is_dma_capable() && !dma_off) { 1000 printk(KERN_WARNING "%s %s: dma still active\n", 1001 __FILE__, __func__); 1002 dma_off = 1; 1003 } 1004 } 1005 1006 /* 1007 * Sets up TUSB6010 CPU interface specific signals and registers 1008 * Note: Settings optimized for OMAP24xx 1009 */ 1010 static void tusb_setup_cpu_interface(struct musb *musb) 1011 { 1012 void __iomem *tbase = musb->ctrl_base; 1013 1014 /* 1015 * Disable GPIO[5:0] pullups (used as output DMA requests) 1016 * Don't disable GPIO[7:6] as they are needed for wake-up. 1017 */ 1018 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F); 1019 1020 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */ 1021 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF); 1022 1023 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */ 1024 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f)); 1025 1026 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request 1027 * de-assertion time 2 system clocks p 62 */ 1028 musb_writel(tbase, TUSB_DMA_REQ_CONF, 1029 TUSB_DMA_REQ_CONF_BURST_SIZE(2) | 1030 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | 1031 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 1032 1033 /* Set 0 wait count for synchronous burst access */ 1034 musb_writel(tbase, TUSB_WAIT_COUNT, 1); 1035 } 1036 1037 static int tusb_musb_start(struct musb *musb) 1038 { 1039 void __iomem *tbase = musb->ctrl_base; 1040 int ret = 0; 1041 unsigned long flags; 1042 u32 reg; 1043 1044 if (musb->board_set_power) 1045 ret = musb->board_set_power(1); 1046 if (ret != 0) { 1047 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n"); 1048 return ret; 1049 } 1050 1051 spin_lock_irqsave(&musb->lock, flags); 1052 1053 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) != 1054 TUSB_PROD_TEST_RESET_VAL) { 1055 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n"); 1056 goto err; 1057 } 1058 1059 musb->tusb_revision = tusb_get_revision(musb); 1060 tusb_print_revision(musb); 1061 if (musb->tusb_revision < 2) { 1062 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n", 1063 musb->tusb_revision); 1064 goto err; 1065 } 1066 1067 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when 1068 * NOR FLASH interface is used */ 1069 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8); 1070 1071 /* Select PHY free running 60MHz as a system clock */ 1072 tusb_set_clock_source(musb, 1); 1073 1074 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for 1075 * power saving, enable VBus detect and session end comparators, 1076 * enable IDpullup, enable VBus charging */ 1077 musb_writel(tbase, TUSB_PRCM_MNGMT, 1078 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) | 1079 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN | 1080 TUSB_PRCM_MNGMT_OTG_SESS_END_EN | 1081 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN | 1082 TUSB_PRCM_MNGMT_OTG_ID_PULLUP); 1083 tusb_setup_cpu_interface(musb); 1084 1085 /* simplify: always sense/pullup ID pins, as if in OTG mode */ 1086 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 1087 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1088 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg); 1089 1090 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 1091 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1092 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg); 1093 1094 spin_unlock_irqrestore(&musb->lock, flags); 1095 1096 return 0; 1097 1098 err: 1099 spin_unlock_irqrestore(&musb->lock, flags); 1100 1101 if (musb->board_set_power) 1102 musb->board_set_power(0); 1103 1104 return -ENODEV; 1105 } 1106 1107 static int tusb_musb_init(struct musb *musb) 1108 { 1109 struct platform_device *pdev; 1110 struct resource *mem; 1111 void __iomem *sync = NULL; 1112 int ret; 1113 1114 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 1115 if (IS_ERR_OR_NULL(musb->xceiv)) 1116 return -EPROBE_DEFER; 1117 1118 pdev = to_platform_device(musb->controller); 1119 1120 /* dma address for async dma */ 1121 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1122 musb->async = mem->start; 1123 1124 /* dma address for sync dma */ 1125 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1126 if (!mem) { 1127 pr_debug("no sync dma resource?\n"); 1128 ret = -ENODEV; 1129 goto done; 1130 } 1131 musb->sync = mem->start; 1132 1133 sync = ioremap(mem->start, resource_size(mem)); 1134 if (!sync) { 1135 pr_debug("ioremap for sync failed\n"); 1136 ret = -ENOMEM; 1137 goto done; 1138 } 1139 musb->sync_va = sync; 1140 1141 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400, 1142 * FIFOs at 0x600, TUSB at 0x800 1143 */ 1144 musb->mregs += TUSB_BASE_OFFSET; 1145 1146 ret = tusb_musb_start(musb); 1147 if (ret) { 1148 printk(KERN_ERR "Could not start tusb6010 (%d)\n", 1149 ret); 1150 goto done; 1151 } 1152 musb->isr = tusb_musb_interrupt; 1153 1154 musb->xceiv->set_power = tusb_draw_power; 1155 the_musb = musb; 1156 1157 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); 1158 1159 done: 1160 if (ret < 0) { 1161 if (sync) 1162 iounmap(sync); 1163 1164 usb_put_phy(musb->xceiv); 1165 } 1166 return ret; 1167 } 1168 1169 static int tusb_musb_exit(struct musb *musb) 1170 { 1171 del_timer_sync(&musb_idle_timer); 1172 the_musb = NULL; 1173 1174 if (musb->board_set_power) 1175 musb->board_set_power(0); 1176 1177 iounmap(musb->sync_va); 1178 1179 usb_put_phy(musb->xceiv); 1180 return 0; 1181 } 1182 1183 static const struct musb_platform_ops tusb_ops = { 1184 .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB, 1185 .init = tusb_musb_init, 1186 .exit = tusb_musb_exit, 1187 1188 .ep_offset = tusb_ep_offset, 1189 .ep_select = tusb_ep_select, 1190 .fifo_offset = tusb_fifo_offset, 1191 .readb = tusb_readb, 1192 .writeb = tusb_writeb, 1193 .read_fifo = tusb_read_fifo, 1194 .write_fifo = tusb_write_fifo, 1195 #ifdef CONFIG_USB_TUSB_OMAP_DMA 1196 .dma_init = tusb_dma_controller_create, 1197 .dma_exit = tusb_dma_controller_destroy, 1198 #endif 1199 .enable = tusb_musb_enable, 1200 .disable = tusb_musb_disable, 1201 1202 .set_mode = tusb_musb_set_mode, 1203 .try_idle = tusb_musb_try_idle, 1204 1205 .vbus_status = tusb_musb_vbus_status, 1206 .set_vbus = tusb_musb_set_vbus, 1207 }; 1208 1209 static const struct platform_device_info tusb_dev_info = { 1210 .name = "musb-hdrc", 1211 .id = PLATFORM_DEVID_AUTO, 1212 .dma_mask = DMA_BIT_MASK(32), 1213 }; 1214 1215 static int tusb_probe(struct platform_device *pdev) 1216 { 1217 struct resource musb_resources[3]; 1218 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); 1219 struct platform_device *musb; 1220 struct tusb6010_glue *glue; 1221 struct platform_device_info pinfo; 1222 int ret; 1223 1224 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 1225 if (!glue) 1226 return -ENOMEM; 1227 1228 glue->dev = &pdev->dev; 1229 1230 pdata->platform_ops = &tusb_ops; 1231 1232 usb_phy_generic_register(); 1233 platform_set_drvdata(pdev, glue); 1234 1235 memset(musb_resources, 0x00, sizeof(*musb_resources) * 1236 ARRAY_SIZE(musb_resources)); 1237 1238 musb_resources[0].name = pdev->resource[0].name; 1239 musb_resources[0].start = pdev->resource[0].start; 1240 musb_resources[0].end = pdev->resource[0].end; 1241 musb_resources[0].flags = pdev->resource[0].flags; 1242 1243 musb_resources[1].name = pdev->resource[1].name; 1244 musb_resources[1].start = pdev->resource[1].start; 1245 musb_resources[1].end = pdev->resource[1].end; 1246 musb_resources[1].flags = pdev->resource[1].flags; 1247 1248 musb_resources[2].name = pdev->resource[2].name; 1249 musb_resources[2].start = pdev->resource[2].start; 1250 musb_resources[2].end = pdev->resource[2].end; 1251 musb_resources[2].flags = pdev->resource[2].flags; 1252 1253 pinfo = tusb_dev_info; 1254 pinfo.parent = &pdev->dev; 1255 pinfo.res = musb_resources; 1256 pinfo.num_res = ARRAY_SIZE(musb_resources); 1257 pinfo.data = pdata; 1258 pinfo.size_data = sizeof(*pdata); 1259 1260 glue->musb = musb = platform_device_register_full(&pinfo); 1261 if (IS_ERR(musb)) { 1262 ret = PTR_ERR(musb); 1263 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret); 1264 return ret; 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int tusb_remove(struct platform_device *pdev) 1271 { 1272 struct tusb6010_glue *glue = platform_get_drvdata(pdev); 1273 1274 platform_device_unregister(glue->musb); 1275 usb_phy_generic_unregister(glue->phy); 1276 1277 return 0; 1278 } 1279 1280 static struct platform_driver tusb_driver = { 1281 .probe = tusb_probe, 1282 .remove = tusb_remove, 1283 .driver = { 1284 .name = "musb-tusb", 1285 }, 1286 }; 1287 1288 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer"); 1289 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1290 MODULE_LICENSE("GPL v2"); 1291 module_platform_driver(tusb_driver); 1292