1 /* 2 * TUSB6010 USB 2.0 OTG Dual Role controller 3 * 4 * Copyright (C) 2006 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Notes: 12 * - Driver assumes that interface to external host (main CPU) is 13 * configured for NOR FLASH interface instead of VLYNQ serial 14 * interface. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/errno.h> 20 #include <linux/err.h> 21 #include <linux/init.h> 22 #include <linux/prefetch.h> 23 #include <linux/usb.h> 24 #include <linux/irq.h> 25 #include <linux/io.h> 26 #include <linux/platform_device.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/usb/usb_phy_gen_xceiv.h> 29 30 #include "musb_core.h" 31 32 struct tusb6010_glue { 33 struct device *dev; 34 struct platform_device *musb; 35 }; 36 37 static void tusb_musb_set_vbus(struct musb *musb, int is_on); 38 39 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) 40 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) 41 42 /* 43 * Checks the revision. We need to use the DMA register as 3.0 does not 44 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. 45 */ 46 u8 tusb_get_revision(struct musb *musb) 47 { 48 void __iomem *tbase = musb->ctrl_base; 49 u32 die_id; 50 u8 rev; 51 52 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff; 53 if (TUSB_REV_MAJOR(rev) == 3) { 54 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, 55 TUSB_DIDR1_HI)); 56 if (die_id >= TUSB_DIDR1_HI_REV_31) 57 rev |= 1; 58 } 59 60 return rev; 61 } 62 EXPORT_SYMBOL_GPL(tusb_get_revision); 63 64 static int tusb_print_revision(struct musb *musb) 65 { 66 void __iomem *tbase = musb->ctrl_base; 67 u8 rev; 68 69 rev = tusb_get_revision(musb); 70 71 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n", 72 "prcm", 73 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)), 74 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)), 75 "int", 76 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 77 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 78 "gpio", 79 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)), 80 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)), 81 "dma", 82 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 83 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 84 "dieid", 85 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)), 86 "rev", 87 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev)); 88 89 return tusb_get_revision(musb); 90 } 91 92 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \ 93 | TUSB_PHY_OTG_CTRL_TESTM0) 94 95 /* 96 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0. 97 * Disables power detection in PHY for the duration of idle. 98 */ 99 static void tusb_wbus_quirk(struct musb *musb, int enabled) 100 { 101 void __iomem *tbase = musb->ctrl_base; 102 static u32 phy_otg_ctrl, phy_otg_ena; 103 u32 tmp; 104 105 if (enabled) { 106 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 107 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 108 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT 109 | phy_otg_ena | WBUS_QUIRK_MASK; 110 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 111 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 112 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 113 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 114 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 115 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 116 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 117 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 118 & TUSB_PHY_OTG_CTRL_TESTM2) { 119 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl; 120 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 121 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 122 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 123 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 124 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 125 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 126 phy_otg_ctrl = 0; 127 phy_otg_ena = 0; 128 } 129 } 130 131 /* 132 * TUSB 6010 may use a parallel bus that doesn't support byte ops; 133 * so both loading and unloading FIFOs need explicit byte counts. 134 */ 135 136 static inline void 137 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len) 138 { 139 u32 val; 140 int i; 141 142 if (len > 4) { 143 for (i = 0; i < (len >> 2); i++) { 144 memcpy(&val, buf, 4); 145 musb_writel(fifo, 0, val); 146 buf += 4; 147 } 148 len %= 4; 149 } 150 if (len > 0) { 151 /* Write the rest 1 - 3 bytes to FIFO */ 152 memcpy(&val, buf, len); 153 musb_writel(fifo, 0, val); 154 } 155 } 156 157 static inline void tusb_fifo_read_unaligned(void __iomem *fifo, 158 void *buf, u16 len) 159 { 160 u32 val; 161 int i; 162 163 if (len > 4) { 164 for (i = 0; i < (len >> 2); i++) { 165 val = musb_readl(fifo, 0); 166 memcpy(buf, &val, 4); 167 buf += 4; 168 } 169 len %= 4; 170 } 171 if (len > 0) { 172 /* Read the rest 1 - 3 bytes from FIFO */ 173 val = musb_readl(fifo, 0); 174 memcpy(buf, &val, len); 175 } 176 } 177 178 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) 179 { 180 struct musb *musb = hw_ep->musb; 181 void __iomem *ep_conf = hw_ep->conf; 182 void __iomem *fifo = hw_ep->fifo; 183 u8 epnum = hw_ep->epnum; 184 185 prefetch(buf); 186 187 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 188 'T', epnum, fifo, len, buf); 189 190 if (epnum) 191 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 192 TUSB_EP_CONFIG_XFR_SIZE(len)); 193 else 194 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX | 195 TUSB_EP0_CONFIG_XFR_SIZE(len)); 196 197 if (likely((0x01 & (unsigned long) buf) == 0)) { 198 199 /* Best case is 32bit-aligned destination address */ 200 if ((0x02 & (unsigned long) buf) == 0) { 201 if (len >= 4) { 202 iowrite32_rep(fifo, buf, len >> 2); 203 buf += (len & ~0x03); 204 len &= 0x03; 205 } 206 } else { 207 if (len >= 2) { 208 u32 val; 209 int i; 210 211 /* Cannot use writesw, fifo is 32-bit */ 212 for (i = 0; i < (len >> 2); i++) { 213 val = (u32)(*(u16 *)buf); 214 buf += 2; 215 val |= (*(u16 *)buf) << 16; 216 buf += 2; 217 musb_writel(fifo, 0, val); 218 } 219 len &= 0x03; 220 } 221 } 222 } 223 224 if (len > 0) 225 tusb_fifo_write_unaligned(fifo, buf, len); 226 } 227 228 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) 229 { 230 struct musb *musb = hw_ep->musb; 231 void __iomem *ep_conf = hw_ep->conf; 232 void __iomem *fifo = hw_ep->fifo; 233 u8 epnum = hw_ep->epnum; 234 235 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 236 'R', epnum, fifo, len, buf); 237 238 if (epnum) 239 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 240 TUSB_EP_CONFIG_XFR_SIZE(len)); 241 else 242 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len)); 243 244 if (likely((0x01 & (unsigned long) buf) == 0)) { 245 246 /* Best case is 32bit-aligned destination address */ 247 if ((0x02 & (unsigned long) buf) == 0) { 248 if (len >= 4) { 249 ioread32_rep(fifo, buf, len >> 2); 250 buf += (len & ~0x03); 251 len &= 0x03; 252 } 253 } else { 254 if (len >= 2) { 255 u32 val; 256 int i; 257 258 /* Cannot use readsw, fifo is 32-bit */ 259 for (i = 0; i < (len >> 2); i++) { 260 val = musb_readl(fifo, 0); 261 *(u16 *)buf = (u16)(val & 0xffff); 262 buf += 2; 263 *(u16 *)buf = (u16)(val >> 16); 264 buf += 2; 265 } 266 len &= 0x03; 267 } 268 } 269 } 270 271 if (len > 0) 272 tusb_fifo_read_unaligned(fifo, buf, len); 273 } 274 275 static struct musb *the_musb; 276 277 /* This is used by gadget drivers, and OTG transceiver logic, allowing 278 * at most mA current to be drawn from VBUS during a Default-B session 279 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host 280 * mode), or low power Default-B sessions, something else supplies power. 281 * Caller must take care of locking. 282 */ 283 static int tusb_draw_power(struct usb_phy *x, unsigned mA) 284 { 285 struct musb *musb = the_musb; 286 void __iomem *tbase = musb->ctrl_base; 287 u32 reg; 288 289 /* tps65030 seems to consume max 100mA, with maybe 60mA available 290 * (measured on one board) for things other than tps and tusb. 291 * 292 * Boards sharing the CPU clock with CLKIN will need to prevent 293 * certain idle sleep states while the USB link is active. 294 * 295 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }. 296 * The actual current usage would be very board-specific. For now, 297 * it's simpler to just use an aggregate (also board-specific). 298 */ 299 if (x->otg->default_a || mA < (musb->min_power << 1)) 300 mA = 0; 301 302 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 303 if (mA) { 304 musb->is_bus_powered = 1; 305 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; 306 } else { 307 musb->is_bus_powered = 0; 308 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 309 } 310 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 311 312 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA); 313 return 0; 314 } 315 316 /* workaround for issue 13: change clock during chip idle 317 * (to be fixed in rev3 silicon) ... symptoms include disconnect 318 * or looping suspend/resume cycles 319 */ 320 static void tusb_set_clock_source(struct musb *musb, unsigned mode) 321 { 322 void __iomem *tbase = musb->ctrl_base; 323 u32 reg; 324 325 reg = musb_readl(tbase, TUSB_PRCM_CONF); 326 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); 327 328 /* 0 = refclk (clkin, XI) 329 * 1 = PHY 60 MHz (internal PLL) 330 * 2 = not supported 331 * 3 = what? 332 */ 333 if (mode > 0) 334 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); 335 336 musb_writel(tbase, TUSB_PRCM_CONF, reg); 337 338 /* FIXME tusb6010_platform_retime(mode == 0); */ 339 } 340 341 /* 342 * Idle TUSB6010 until next wake-up event; NOR access always wakes. 343 * Other code ensures that we idle unless we're connected _and_ the 344 * USB link is not suspended ... and tells us the relevant wakeup 345 * events. SW_EN for voltage is handled separately. 346 */ 347 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables) 348 { 349 void __iomem *tbase = musb->ctrl_base; 350 u32 reg; 351 352 if ((wakeup_enables & TUSB_PRCM_WBUS) 353 && (tusb_get_revision(musb) == TUSB_REV_30)) 354 tusb_wbus_quirk(musb, 1); 355 356 tusb_set_clock_source(musb, 0); 357 358 wakeup_enables |= TUSB_PRCM_WNORCS; 359 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables); 360 361 /* REVISIT writeup of WID implies that if WID set and ID is grounded, 362 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared. 363 * Presumably that's mostly to save power, hence WID is immaterial ... 364 */ 365 366 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 367 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */ 368 if (is_host_active(musb)) { 369 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 370 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 371 } else { 372 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 373 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 374 } 375 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 376 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 377 378 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables); 379 } 380 381 /* 382 * Updates cable VBUS status. Caller must take care of locking. 383 */ 384 static int tusb_musb_vbus_status(struct musb *musb) 385 { 386 void __iomem *tbase = musb->ctrl_base; 387 u32 otg_stat, prcm_mngmt; 388 int ret = 0; 389 390 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 391 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT); 392 393 /* Temporarily enable VBUS detection if it was disabled for 394 * suspend mode. Unless it's enabled otg_stat and devctl will 395 * not show correct VBUS state. 396 */ 397 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) { 398 u32 tmp = prcm_mngmt; 399 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 400 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp); 401 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 402 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt); 403 } 404 405 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) 406 ret = 1; 407 408 return ret; 409 } 410 411 static struct timer_list musb_idle_timer; 412 413 static void musb_do_idle(unsigned long _musb) 414 { 415 struct musb *musb = (void *)_musb; 416 unsigned long flags; 417 418 spin_lock_irqsave(&musb->lock, flags); 419 420 switch (musb->xceiv->state) { 421 case OTG_STATE_A_WAIT_BCON: 422 if ((musb->a_wait_bcon != 0) 423 && (musb->idle_timeout == 0 424 || time_after(jiffies, musb->idle_timeout))) { 425 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n", 426 usb_otg_state_string(musb->xceiv->state)); 427 } 428 /* FALLTHROUGH */ 429 case OTG_STATE_A_IDLE: 430 tusb_musb_set_vbus(musb, 0); 431 default: 432 break; 433 } 434 435 if (!musb->is_active) { 436 u32 wakeups; 437 438 /* wait until khubd handles port change status */ 439 if (is_host_active(musb) && (musb->port1_status >> 16)) 440 goto done; 441 442 if (!musb->gadget_driver) { 443 wakeups = 0; 444 } else { 445 wakeups = TUSB_PRCM_WHOSTDISCON 446 | TUSB_PRCM_WBUS 447 | TUSB_PRCM_WVBUS; 448 wakeups |= TUSB_PRCM_WID; 449 } 450 tusb_allow_idle(musb, wakeups); 451 } 452 done: 453 spin_unlock_irqrestore(&musb->lock, flags); 454 } 455 456 /* 457 * Maybe put TUSB6010 into idle mode mode depending on USB link status, 458 * like "disconnected" or "suspended". We'll be woken out of it by 459 * connect, resume, or disconnect. 460 * 461 * Needs to be called as the last function everywhere where there is 462 * register access to TUSB6010 because of NOR flash wake-up. 463 * Caller should own controller spinlock. 464 * 465 * Delay because peripheral enables D+ pullup 3msec after SE0, and 466 * we don't want to treat that full speed J as a wakeup event. 467 * ... peripherals must draw only suspend current after 10 msec. 468 */ 469 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout) 470 { 471 unsigned long default_timeout = jiffies + msecs_to_jiffies(3); 472 static unsigned long last_timer; 473 474 if (timeout == 0) 475 timeout = default_timeout; 476 477 /* Never idle if active, or when VBUS timeout is not set as host */ 478 if (musb->is_active || ((musb->a_wait_bcon == 0) 479 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) { 480 dev_dbg(musb->controller, "%s active, deleting timer\n", 481 usb_otg_state_string(musb->xceiv->state)); 482 del_timer(&musb_idle_timer); 483 last_timer = jiffies; 484 return; 485 } 486 487 if (time_after(last_timer, timeout)) { 488 if (!timer_pending(&musb_idle_timer)) 489 last_timer = timeout; 490 else { 491 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n"); 492 return; 493 } 494 } 495 last_timer = timeout; 496 497 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n", 498 usb_otg_state_string(musb->xceiv->state), 499 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 500 mod_timer(&musb_idle_timer, timeout); 501 } 502 503 /* ticks of 60 MHz clock */ 504 #define DEVCLOCK 60000000 505 #define OTG_TIMER_MS(msecs) ((msecs) \ 506 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \ 507 | TUSB_DEV_OTG_TIMER_ENABLE) \ 508 : 0) 509 510 static void tusb_musb_set_vbus(struct musb *musb, int is_on) 511 { 512 void __iomem *tbase = musb->ctrl_base; 513 u32 conf, prcm, timer; 514 u8 devctl; 515 struct usb_otg *otg = musb->xceiv->otg; 516 517 /* HDRC controls CPEN, but beware current surges during device 518 * connect. They can trigger transient overcurrent conditions 519 * that must be ignored. 520 */ 521 522 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT); 523 conf = musb_readl(tbase, TUSB_DEV_CONF); 524 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 525 526 if (is_on) { 527 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); 528 otg->default_a = 1; 529 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 530 devctl |= MUSB_DEVCTL_SESSION; 531 532 conf |= TUSB_DEV_CONF_USB_HOST_MODE; 533 MUSB_HST_MODE(musb); 534 } else { 535 u32 otg_stat; 536 537 timer = 0; 538 539 /* If ID pin is grounded, we want to be a_idle */ 540 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 541 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { 542 switch (musb->xceiv->state) { 543 case OTG_STATE_A_WAIT_VRISE: 544 case OTG_STATE_A_WAIT_BCON: 545 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 546 break; 547 case OTG_STATE_A_WAIT_VFALL: 548 musb->xceiv->state = OTG_STATE_A_IDLE; 549 break; 550 default: 551 musb->xceiv->state = OTG_STATE_A_IDLE; 552 } 553 musb->is_active = 0; 554 otg->default_a = 1; 555 MUSB_HST_MODE(musb); 556 } else { 557 musb->is_active = 0; 558 otg->default_a = 0; 559 musb->xceiv->state = OTG_STATE_B_IDLE; 560 MUSB_DEV_MODE(musb); 561 } 562 563 devctl &= ~MUSB_DEVCTL_SESSION; 564 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE; 565 } 566 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 567 568 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm); 569 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer); 570 musb_writel(tbase, TUSB_DEV_CONF, conf); 571 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 572 573 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 574 usb_otg_state_string(musb->xceiv->state), 575 musb_readb(musb->mregs, MUSB_DEVCTL), 576 musb_readl(tbase, TUSB_DEV_OTG_STAT), 577 conf, prcm); 578 } 579 580 /* 581 * Sets the mode to OTG, peripheral or host by changing the ID detection. 582 * Caller must take care of locking. 583 * 584 * Note that if a mini-A cable is plugged in the ID line will stay down as 585 * the weak ID pull-up is not able to pull the ID up. 586 */ 587 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode) 588 { 589 void __iomem *tbase = musb->ctrl_base; 590 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf; 591 592 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 593 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 594 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 595 dev_conf = musb_readl(tbase, TUSB_DEV_CONF); 596 597 switch (musb_mode) { 598 599 case MUSB_HOST: /* Disable PHY ID detect, ground ID */ 600 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 601 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 602 dev_conf |= TUSB_DEV_CONF_ID_SEL; 603 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID; 604 break; 605 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */ 606 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 607 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 608 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 609 break; 610 case MUSB_OTG: /* Use PHY ID detection */ 611 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 612 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 613 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 614 break; 615 616 default: 617 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode); 618 return -EINVAL; 619 } 620 621 musb_writel(tbase, TUSB_PHY_OTG_CTRL, 622 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl); 623 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, 624 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena); 625 musb_writel(tbase, TUSB_DEV_CONF, dev_conf); 626 627 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 628 if ((musb_mode == MUSB_PERIPHERAL) && 629 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) 630 INFO("Cannot be peripheral with mini-A cable " 631 "otg_stat: %08x\n", otg_stat); 632 633 return 0; 634 } 635 636 static inline unsigned long 637 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) 638 { 639 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 640 unsigned long idle_timeout = 0; 641 struct usb_otg *otg = musb->xceiv->otg; 642 643 /* ID pin */ 644 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) { 645 int default_a; 646 647 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 648 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B'); 649 otg->default_a = default_a; 650 tusb_musb_set_vbus(musb, default_a); 651 652 /* Don't allow idling immediately */ 653 if (default_a) 654 idle_timeout = jiffies + (HZ * 3); 655 } 656 657 /* VBUS state change */ 658 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { 659 660 /* B-dev state machine: no vbus ~= disconnect */ 661 if (!otg->default_a) { 662 /* ? musb_root_disconnect(musb); */ 663 musb->port1_status &= 664 ~(USB_PORT_STAT_CONNECTION 665 | USB_PORT_STAT_ENABLE 666 | USB_PORT_STAT_LOW_SPEED 667 | USB_PORT_STAT_HIGH_SPEED 668 | USB_PORT_STAT_TEST 669 ); 670 671 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 672 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n"); 673 if (musb->xceiv->state != OTG_STATE_B_IDLE) { 674 /* INTR_DISCONNECT can hide... */ 675 musb->xceiv->state = OTG_STATE_B_IDLE; 676 musb->int_usb |= MUSB_INTR_DISCONNECT; 677 } 678 musb->is_active = 0; 679 } 680 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", 681 usb_otg_state_string(musb->xceiv->state), otg_stat); 682 idle_timeout = jiffies + (1 * HZ); 683 schedule_work(&musb->irq_work); 684 685 } else /* A-dev state machine */ { 686 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", 687 usb_otg_state_string(musb->xceiv->state), otg_stat); 688 689 switch (musb->xceiv->state) { 690 case OTG_STATE_A_IDLE: 691 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n"); 692 musb_platform_set_vbus(musb, 1); 693 694 /* CONNECT can wake if a_wait_bcon is set */ 695 if (musb->a_wait_bcon != 0) 696 musb->is_active = 0; 697 else 698 musb->is_active = 1; 699 700 /* 701 * OPT FS A TD.4.6 needs few seconds for 702 * A_WAIT_VRISE 703 */ 704 idle_timeout = jiffies + (2 * HZ); 705 706 break; 707 case OTG_STATE_A_WAIT_VRISE: 708 /* ignore; A-session-valid < VBUS_VALID/2, 709 * we monitor this with the timer 710 */ 711 break; 712 case OTG_STATE_A_WAIT_VFALL: 713 /* REVISIT this irq triggers during short 714 * spikes caused by enumeration ... 715 */ 716 if (musb->vbuserr_retry) { 717 musb->vbuserr_retry--; 718 tusb_musb_set_vbus(musb, 1); 719 } else { 720 musb->vbuserr_retry 721 = VBUSERR_RETRY_COUNT; 722 tusb_musb_set_vbus(musb, 0); 723 } 724 break; 725 default: 726 break; 727 } 728 } 729 } 730 731 /* OTG timer expiration */ 732 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 733 u8 devctl; 734 735 dev_dbg(musb->controller, "%s timer, %03x\n", 736 usb_otg_state_string(musb->xceiv->state), otg_stat); 737 738 switch (musb->xceiv->state) { 739 case OTG_STATE_A_WAIT_VRISE: 740 /* VBUS has probably been valid for a while now, 741 * but may well have bounced out of range a bit 742 */ 743 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 744 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 745 if ((devctl & MUSB_DEVCTL_VBUS) 746 != MUSB_DEVCTL_VBUS) { 747 dev_dbg(musb->controller, "devctl %02x\n", devctl); 748 break; 749 } 750 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 751 musb->is_active = 0; 752 idle_timeout = jiffies 753 + msecs_to_jiffies(musb->a_wait_bcon); 754 } else { 755 /* REVISIT report overcurrent to hub? */ 756 ERR("vbus too slow, devctl %02x\n", devctl); 757 tusb_musb_set_vbus(musb, 0); 758 } 759 break; 760 case OTG_STATE_A_WAIT_BCON: 761 if (musb->a_wait_bcon != 0) 762 idle_timeout = jiffies 763 + msecs_to_jiffies(musb->a_wait_bcon); 764 break; 765 case OTG_STATE_A_SUSPEND: 766 break; 767 case OTG_STATE_B_WAIT_ACON: 768 break; 769 default: 770 break; 771 } 772 } 773 schedule_work(&musb->irq_work); 774 775 return idle_timeout; 776 } 777 778 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci) 779 { 780 struct musb *musb = __hci; 781 void __iomem *tbase = musb->ctrl_base; 782 unsigned long flags, idle_timeout = 0; 783 u32 int_mask, int_src; 784 785 spin_lock_irqsave(&musb->lock, flags); 786 787 /* Mask all interrupts to allow using both edge and level GPIO irq */ 788 int_mask = musb_readl(tbase, TUSB_INT_MASK); 789 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 790 791 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 792 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src); 793 794 musb->int_usb = (u8) int_src; 795 796 /* Acknowledge wake-up source interrupts */ 797 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) { 798 u32 reg; 799 u32 i; 800 801 if (tusb_get_revision(musb) == TUSB_REV_30) 802 tusb_wbus_quirk(musb, 0); 803 804 /* there are issues re-locking the PLL on wakeup ... */ 805 806 /* work around issue 8 */ 807 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) { 808 musb_writel(tbase, TUSB_SCRATCH_PAD, 0); 809 musb_writel(tbase, TUSB_SCRATCH_PAD, i); 810 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 811 if (reg == i) 812 break; 813 dev_dbg(musb->controller, "TUSB NOR not ready\n"); 814 } 815 816 /* work around issue 13 (2nd half) */ 817 tusb_set_clock_source(musb, 1); 818 819 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE); 820 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); 821 if (reg & ~TUSB_PRCM_WNORCS) { 822 musb->is_active = 1; 823 schedule_work(&musb->irq_work); 824 } 825 dev_dbg(musb->controller, "wake %sactive %02x\n", 826 musb->is_active ? "" : "in", reg); 827 828 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 829 } 830 831 if (int_src & TUSB_INT_SRC_USB_IP_CONN) 832 del_timer(&musb_idle_timer); 833 834 /* OTG state change reports (annoyingly) not issued by Mentor core */ 835 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG 836 | TUSB_INT_SRC_OTG_TIMEOUT 837 | TUSB_INT_SRC_ID_STATUS_CHNG)) 838 idle_timeout = tusb_otg_ints(musb, int_src, tbase); 839 840 /* TX dma callback must be handled here, RX dma callback is 841 * handled in tusb_omap_dma_cb. 842 */ 843 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) { 844 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 845 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK); 846 847 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src); 848 real_dma_src = ~real_dma_src & dma_src; 849 if (tusb_dma_omap() && real_dma_src) { 850 int tx_source = (real_dma_src & 0xffff); 851 int i; 852 853 for (i = 1; i <= 15; i++) { 854 if (tx_source & (1 << i)) { 855 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx"); 856 musb_dma_completion(musb, i, 1); 857 } 858 } 859 } 860 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src); 861 } 862 863 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */ 864 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) { 865 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC); 866 867 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src); 868 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1); 869 musb->int_tx = (musb_src & 0xffff); 870 } else { 871 musb->int_rx = 0; 872 musb->int_tx = 0; 873 } 874 875 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff)) 876 musb_interrupt(musb); 877 878 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */ 879 musb_writel(tbase, TUSB_INT_SRC_CLEAR, 880 int_src & ~TUSB_INT_MASK_RESERVED_BITS); 881 882 tusb_musb_try_idle(musb, idle_timeout); 883 884 musb_writel(tbase, TUSB_INT_MASK, int_mask); 885 spin_unlock_irqrestore(&musb->lock, flags); 886 887 return IRQ_HANDLED; 888 } 889 890 static int dma_off; 891 892 /* 893 * Enables TUSB6010. Caller must take care of locking. 894 * REVISIT: 895 * - Check what is unnecessary in MGC_HdrcStart() 896 */ 897 static void tusb_musb_enable(struct musb *musb) 898 { 899 void __iomem *tbase = musb->ctrl_base; 900 901 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF. 902 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */ 903 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF); 904 905 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */ 906 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0); 907 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 908 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 909 910 /* Clear all subsystem interrups */ 911 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff); 912 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff); 913 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff); 914 915 /* Acknowledge pending interrupt(s) */ 916 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS); 917 918 /* Only 0 clock cycles for minimum interrupt de-assertion time and 919 * interrupt polarity active low seems to work reliably here */ 920 musb_writel(tbase, TUSB_INT_CTRL_CONF, 921 TUSB_INT_CTRL_CONF_INT_RELCYC(0)); 922 923 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW); 924 925 /* maybe force into the Default-A OTG state machine */ 926 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT) 927 & TUSB_DEV_OTG_STAT_ID_STATUS)) 928 musb_writel(tbase, TUSB_INT_SRC_SET, 929 TUSB_INT_SRC_ID_STATUS_CHNG); 930 931 if (is_dma_capable() && dma_off) 932 printk(KERN_WARNING "%s %s: dma not reactivated\n", 933 __FILE__, __func__); 934 else 935 dma_off = 1; 936 } 937 938 /* 939 * Disables TUSB6010. Caller must take care of locking. 940 */ 941 static void tusb_musb_disable(struct musb *musb) 942 { 943 void __iomem *tbase = musb->ctrl_base; 944 945 /* FIXME stop DMA, IRQs, timers, ... */ 946 947 /* disable all IRQs */ 948 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 949 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff); 950 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 951 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 952 953 del_timer(&musb_idle_timer); 954 955 if (is_dma_capable() && !dma_off) { 956 printk(KERN_WARNING "%s %s: dma still active\n", 957 __FILE__, __func__); 958 dma_off = 1; 959 } 960 } 961 962 /* 963 * Sets up TUSB6010 CPU interface specific signals and registers 964 * Note: Settings optimized for OMAP24xx 965 */ 966 static void tusb_setup_cpu_interface(struct musb *musb) 967 { 968 void __iomem *tbase = musb->ctrl_base; 969 970 /* 971 * Disable GPIO[5:0] pullups (used as output DMA requests) 972 * Don't disable GPIO[7:6] as they are needed for wake-up. 973 */ 974 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F); 975 976 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */ 977 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF); 978 979 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */ 980 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f)); 981 982 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request 983 * de-assertion time 2 system clocks p 62 */ 984 musb_writel(tbase, TUSB_DMA_REQ_CONF, 985 TUSB_DMA_REQ_CONF_BURST_SIZE(2) | 986 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | 987 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 988 989 /* Set 0 wait count for synchronous burst access */ 990 musb_writel(tbase, TUSB_WAIT_COUNT, 1); 991 } 992 993 static int tusb_musb_start(struct musb *musb) 994 { 995 void __iomem *tbase = musb->ctrl_base; 996 int ret = 0; 997 unsigned long flags; 998 u32 reg; 999 1000 if (musb->board_set_power) 1001 ret = musb->board_set_power(1); 1002 if (ret != 0) { 1003 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n"); 1004 return ret; 1005 } 1006 1007 spin_lock_irqsave(&musb->lock, flags); 1008 1009 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) != 1010 TUSB_PROD_TEST_RESET_VAL) { 1011 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n"); 1012 goto err; 1013 } 1014 1015 ret = tusb_print_revision(musb); 1016 if (ret < 2) { 1017 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n", 1018 ret); 1019 goto err; 1020 } 1021 1022 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when 1023 * NOR FLASH interface is used */ 1024 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8); 1025 1026 /* Select PHY free running 60MHz as a system clock */ 1027 tusb_set_clock_source(musb, 1); 1028 1029 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for 1030 * power saving, enable VBus detect and session end comparators, 1031 * enable IDpullup, enable VBus charging */ 1032 musb_writel(tbase, TUSB_PRCM_MNGMT, 1033 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) | 1034 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN | 1035 TUSB_PRCM_MNGMT_OTG_SESS_END_EN | 1036 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN | 1037 TUSB_PRCM_MNGMT_OTG_ID_PULLUP); 1038 tusb_setup_cpu_interface(musb); 1039 1040 /* simplify: always sense/pullup ID pins, as if in OTG mode */ 1041 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 1042 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1043 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg); 1044 1045 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 1046 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1047 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg); 1048 1049 spin_unlock_irqrestore(&musb->lock, flags); 1050 1051 return 0; 1052 1053 err: 1054 spin_unlock_irqrestore(&musb->lock, flags); 1055 1056 if (musb->board_set_power) 1057 musb->board_set_power(0); 1058 1059 return -ENODEV; 1060 } 1061 1062 static int tusb_musb_init(struct musb *musb) 1063 { 1064 struct platform_device *pdev; 1065 struct resource *mem; 1066 void __iomem *sync = NULL; 1067 int ret; 1068 1069 usb_nop_xceiv_register(); 1070 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 1071 if (IS_ERR_OR_NULL(musb->xceiv)) 1072 return -EPROBE_DEFER; 1073 1074 pdev = to_platform_device(musb->controller); 1075 1076 /* dma address for async dma */ 1077 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1078 musb->async = mem->start; 1079 1080 /* dma address for sync dma */ 1081 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1082 if (!mem) { 1083 pr_debug("no sync dma resource?\n"); 1084 ret = -ENODEV; 1085 goto done; 1086 } 1087 musb->sync = mem->start; 1088 1089 sync = ioremap(mem->start, resource_size(mem)); 1090 if (!sync) { 1091 pr_debug("ioremap for sync failed\n"); 1092 ret = -ENOMEM; 1093 goto done; 1094 } 1095 musb->sync_va = sync; 1096 1097 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400, 1098 * FIFOs at 0x600, TUSB at 0x800 1099 */ 1100 musb->mregs += TUSB_BASE_OFFSET; 1101 1102 ret = tusb_musb_start(musb); 1103 if (ret) { 1104 printk(KERN_ERR "Could not start tusb6010 (%d)\n", 1105 ret); 1106 goto done; 1107 } 1108 musb->isr = tusb_musb_interrupt; 1109 1110 musb->xceiv->set_power = tusb_draw_power; 1111 the_musb = musb; 1112 1113 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); 1114 1115 done: 1116 if (ret < 0) { 1117 if (sync) 1118 iounmap(sync); 1119 1120 usb_put_phy(musb->xceiv); 1121 usb_nop_xceiv_unregister(); 1122 } 1123 return ret; 1124 } 1125 1126 static int tusb_musb_exit(struct musb *musb) 1127 { 1128 del_timer_sync(&musb_idle_timer); 1129 the_musb = NULL; 1130 1131 if (musb->board_set_power) 1132 musb->board_set_power(0); 1133 1134 iounmap(musb->sync_va); 1135 1136 usb_put_phy(musb->xceiv); 1137 usb_nop_xceiv_unregister(); 1138 return 0; 1139 } 1140 1141 static const struct musb_platform_ops tusb_ops = { 1142 .init = tusb_musb_init, 1143 .exit = tusb_musb_exit, 1144 1145 .enable = tusb_musb_enable, 1146 .disable = tusb_musb_disable, 1147 1148 .set_mode = tusb_musb_set_mode, 1149 .try_idle = tusb_musb_try_idle, 1150 1151 .vbus_status = tusb_musb_vbus_status, 1152 .set_vbus = tusb_musb_set_vbus, 1153 }; 1154 1155 static u64 tusb_dmamask = DMA_BIT_MASK(32); 1156 1157 static int tusb_probe(struct platform_device *pdev) 1158 { 1159 struct resource musb_resources[3]; 1160 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); 1161 struct platform_device *musb; 1162 struct tusb6010_glue *glue; 1163 1164 int ret = -ENOMEM; 1165 1166 glue = kzalloc(sizeof(*glue), GFP_KERNEL); 1167 if (!glue) { 1168 dev_err(&pdev->dev, "failed to allocate glue context\n"); 1169 goto err0; 1170 } 1171 1172 musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO); 1173 if (!musb) { 1174 dev_err(&pdev->dev, "failed to allocate musb device\n"); 1175 goto err1; 1176 } 1177 1178 musb->dev.parent = &pdev->dev; 1179 musb->dev.dma_mask = &tusb_dmamask; 1180 musb->dev.coherent_dma_mask = tusb_dmamask; 1181 1182 glue->dev = &pdev->dev; 1183 glue->musb = musb; 1184 1185 pdata->platform_ops = &tusb_ops; 1186 1187 platform_set_drvdata(pdev, glue); 1188 1189 memset(musb_resources, 0x00, sizeof(*musb_resources) * 1190 ARRAY_SIZE(musb_resources)); 1191 1192 musb_resources[0].name = pdev->resource[0].name; 1193 musb_resources[0].start = pdev->resource[0].start; 1194 musb_resources[0].end = pdev->resource[0].end; 1195 musb_resources[0].flags = pdev->resource[0].flags; 1196 1197 musb_resources[1].name = pdev->resource[1].name; 1198 musb_resources[1].start = pdev->resource[1].start; 1199 musb_resources[1].end = pdev->resource[1].end; 1200 musb_resources[1].flags = pdev->resource[1].flags; 1201 1202 musb_resources[2].name = pdev->resource[2].name; 1203 musb_resources[2].start = pdev->resource[2].start; 1204 musb_resources[2].end = pdev->resource[2].end; 1205 musb_resources[2].flags = pdev->resource[2].flags; 1206 1207 ret = platform_device_add_resources(musb, musb_resources, 1208 ARRAY_SIZE(musb_resources)); 1209 if (ret) { 1210 dev_err(&pdev->dev, "failed to add resources\n"); 1211 goto err3; 1212 } 1213 1214 ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); 1215 if (ret) { 1216 dev_err(&pdev->dev, "failed to add platform_data\n"); 1217 goto err3; 1218 } 1219 1220 ret = platform_device_add(musb); 1221 if (ret) { 1222 dev_err(&pdev->dev, "failed to register musb device\n"); 1223 goto err3; 1224 } 1225 1226 return 0; 1227 1228 err3: 1229 platform_device_put(musb); 1230 1231 err1: 1232 kfree(glue); 1233 1234 err0: 1235 return ret; 1236 } 1237 1238 static int tusb_remove(struct platform_device *pdev) 1239 { 1240 struct tusb6010_glue *glue = platform_get_drvdata(pdev); 1241 1242 platform_device_unregister(glue->musb); 1243 kfree(glue); 1244 1245 return 0; 1246 } 1247 1248 static struct platform_driver tusb_driver = { 1249 .probe = tusb_probe, 1250 .remove = tusb_remove, 1251 .driver = { 1252 .name = "musb-tusb", 1253 }, 1254 }; 1255 1256 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer"); 1257 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1258 MODULE_LICENSE("GPL v2"); 1259 module_platform_driver(tusb_driver); 1260