1 /* 2 * TUSB6010 USB 2.0 OTG Dual Role controller 3 * 4 * Copyright (C) 2006 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Notes: 12 * - Driver assumes that interface to external host (main CPU) is 13 * configured for NOR FLASH interface instead of VLYNQ serial 14 * interface. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/errno.h> 20 #include <linux/init.h> 21 #include <linux/usb.h> 22 #include <linux/irq.h> 23 #include <linux/platform_device.h> 24 #include <linux/dma-mapping.h> 25 26 #include "musb_core.h" 27 28 struct tusb6010_glue { 29 struct device *dev; 30 struct platform_device *musb; 31 }; 32 33 static void tusb_musb_set_vbus(struct musb *musb, int is_on); 34 35 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) 36 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) 37 38 /* 39 * Checks the revision. We need to use the DMA register as 3.0 does not 40 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. 41 */ 42 u8 tusb_get_revision(struct musb *musb) 43 { 44 void __iomem *tbase = musb->ctrl_base; 45 u32 die_id; 46 u8 rev; 47 48 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff; 49 if (TUSB_REV_MAJOR(rev) == 3) { 50 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, 51 TUSB_DIDR1_HI)); 52 if (die_id >= TUSB_DIDR1_HI_REV_31) 53 rev |= 1; 54 } 55 56 return rev; 57 } 58 59 static int tusb_print_revision(struct musb *musb) 60 { 61 void __iomem *tbase = musb->ctrl_base; 62 u8 rev; 63 64 rev = tusb_get_revision(musb); 65 66 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n", 67 "prcm", 68 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)), 69 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)), 70 "int", 71 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 72 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 73 "gpio", 74 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)), 75 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)), 76 "dma", 77 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 78 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 79 "dieid", 80 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)), 81 "rev", 82 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev)); 83 84 return tusb_get_revision(musb); 85 } 86 87 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \ 88 | TUSB_PHY_OTG_CTRL_TESTM0) 89 90 /* 91 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0. 92 * Disables power detection in PHY for the duration of idle. 93 */ 94 static void tusb_wbus_quirk(struct musb *musb, int enabled) 95 { 96 void __iomem *tbase = musb->ctrl_base; 97 static u32 phy_otg_ctrl, phy_otg_ena; 98 u32 tmp; 99 100 if (enabled) { 101 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 102 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 103 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT 104 | phy_otg_ena | WBUS_QUIRK_MASK; 105 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 109 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 110 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 113 & TUSB_PHY_OTG_CTRL_TESTM2) { 114 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl; 115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 118 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 119 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 121 phy_otg_ctrl = 0; 122 phy_otg_ena = 0; 123 } 124 } 125 126 /* 127 * TUSB 6010 may use a parallel bus that doesn't support byte ops; 128 * so both loading and unloading FIFOs need explicit byte counts. 129 */ 130 131 static inline void 132 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len) 133 { 134 u32 val; 135 int i; 136 137 if (len > 4) { 138 for (i = 0; i < (len >> 2); i++) { 139 memcpy(&val, buf, 4); 140 musb_writel(fifo, 0, val); 141 buf += 4; 142 } 143 len %= 4; 144 } 145 if (len > 0) { 146 /* Write the rest 1 - 3 bytes to FIFO */ 147 memcpy(&val, buf, len); 148 musb_writel(fifo, 0, val); 149 } 150 } 151 152 static inline void tusb_fifo_read_unaligned(void __iomem *fifo, 153 void __iomem *buf, u16 len) 154 { 155 u32 val; 156 int i; 157 158 if (len > 4) { 159 for (i = 0; i < (len >> 2); i++) { 160 val = musb_readl(fifo, 0); 161 memcpy(buf, &val, 4); 162 buf += 4; 163 } 164 len %= 4; 165 } 166 if (len > 0) { 167 /* Read the rest 1 - 3 bytes from FIFO */ 168 val = musb_readl(fifo, 0); 169 memcpy(buf, &val, len); 170 } 171 } 172 173 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) 174 { 175 void __iomem *ep_conf = hw_ep->conf; 176 void __iomem *fifo = hw_ep->fifo; 177 u8 epnum = hw_ep->epnum; 178 179 prefetch(buf); 180 181 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 182 'T', epnum, fifo, len, buf); 183 184 if (epnum) 185 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 186 TUSB_EP_CONFIG_XFR_SIZE(len)); 187 else 188 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX | 189 TUSB_EP0_CONFIG_XFR_SIZE(len)); 190 191 if (likely((0x01 & (unsigned long) buf) == 0)) { 192 193 /* Best case is 32bit-aligned destination address */ 194 if ((0x02 & (unsigned long) buf) == 0) { 195 if (len >= 4) { 196 writesl(fifo, buf, len >> 2); 197 buf += (len & ~0x03); 198 len &= 0x03; 199 } 200 } else { 201 if (len >= 2) { 202 u32 val; 203 int i; 204 205 /* Cannot use writesw, fifo is 32-bit */ 206 for (i = 0; i < (len >> 2); i++) { 207 val = (u32)(*(u16 *)buf); 208 buf += 2; 209 val |= (*(u16 *)buf) << 16; 210 buf += 2; 211 musb_writel(fifo, 0, val); 212 } 213 len &= 0x03; 214 } 215 } 216 } 217 218 if (len > 0) 219 tusb_fifo_write_unaligned(fifo, buf, len); 220 } 221 222 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) 223 { 224 void __iomem *ep_conf = hw_ep->conf; 225 void __iomem *fifo = hw_ep->fifo; 226 u8 epnum = hw_ep->epnum; 227 228 DBG(4, "%cX ep%d fifo %p count %d buf %p\n", 229 'R', epnum, fifo, len, buf); 230 231 if (epnum) 232 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 233 TUSB_EP_CONFIG_XFR_SIZE(len)); 234 else 235 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len)); 236 237 if (likely((0x01 & (unsigned long) buf) == 0)) { 238 239 /* Best case is 32bit-aligned destination address */ 240 if ((0x02 & (unsigned long) buf) == 0) { 241 if (len >= 4) { 242 readsl(fifo, buf, len >> 2); 243 buf += (len & ~0x03); 244 len &= 0x03; 245 } 246 } else { 247 if (len >= 2) { 248 u32 val; 249 int i; 250 251 /* Cannot use readsw, fifo is 32-bit */ 252 for (i = 0; i < (len >> 2); i++) { 253 val = musb_readl(fifo, 0); 254 *(u16 *)buf = (u16)(val & 0xffff); 255 buf += 2; 256 *(u16 *)buf = (u16)(val >> 16); 257 buf += 2; 258 } 259 len &= 0x03; 260 } 261 } 262 } 263 264 if (len > 0) 265 tusb_fifo_read_unaligned(fifo, buf, len); 266 } 267 268 static struct musb *the_musb; 269 270 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 271 272 /* This is used by gadget drivers, and OTG transceiver logic, allowing 273 * at most mA current to be drawn from VBUS during a Default-B session 274 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host 275 * mode), or low power Default-B sessions, something else supplies power. 276 * Caller must take care of locking. 277 */ 278 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA) 279 { 280 struct musb *musb = the_musb; 281 void __iomem *tbase = musb->ctrl_base; 282 u32 reg; 283 284 /* tps65030 seems to consume max 100mA, with maybe 60mA available 285 * (measured on one board) for things other than tps and tusb. 286 * 287 * Boards sharing the CPU clock with CLKIN will need to prevent 288 * certain idle sleep states while the USB link is active. 289 * 290 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }. 291 * The actual current usage would be very board-specific. For now, 292 * it's simpler to just use an aggregate (also board-specific). 293 */ 294 if (x->default_a || mA < (musb->min_power << 1)) 295 mA = 0; 296 297 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 298 if (mA) { 299 musb->is_bus_powered = 1; 300 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; 301 } else { 302 musb->is_bus_powered = 0; 303 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 304 } 305 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 306 307 DBG(2, "draw max %d mA VBUS\n", mA); 308 return 0; 309 } 310 311 #else 312 #define tusb_draw_power NULL 313 #endif 314 315 /* workaround for issue 13: change clock during chip idle 316 * (to be fixed in rev3 silicon) ... symptoms include disconnect 317 * or looping suspend/resume cycles 318 */ 319 static void tusb_set_clock_source(struct musb *musb, unsigned mode) 320 { 321 void __iomem *tbase = musb->ctrl_base; 322 u32 reg; 323 324 reg = musb_readl(tbase, TUSB_PRCM_CONF); 325 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); 326 327 /* 0 = refclk (clkin, XI) 328 * 1 = PHY 60 MHz (internal PLL) 329 * 2 = not supported 330 * 3 = what? 331 */ 332 if (mode > 0) 333 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); 334 335 musb_writel(tbase, TUSB_PRCM_CONF, reg); 336 337 /* FIXME tusb6010_platform_retime(mode == 0); */ 338 } 339 340 /* 341 * Idle TUSB6010 until next wake-up event; NOR access always wakes. 342 * Other code ensures that we idle unless we're connected _and_ the 343 * USB link is not suspended ... and tells us the relevant wakeup 344 * events. SW_EN for voltage is handled separately. 345 */ 346 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables) 347 { 348 void __iomem *tbase = musb->ctrl_base; 349 u32 reg; 350 351 if ((wakeup_enables & TUSB_PRCM_WBUS) 352 && (tusb_get_revision(musb) == TUSB_REV_30)) 353 tusb_wbus_quirk(musb, 1); 354 355 tusb_set_clock_source(musb, 0); 356 357 wakeup_enables |= TUSB_PRCM_WNORCS; 358 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables); 359 360 /* REVISIT writeup of WID implies that if WID set and ID is grounded, 361 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared. 362 * Presumably that's mostly to save power, hence WID is immaterial ... 363 */ 364 365 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 366 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */ 367 if (is_host_active(musb)) { 368 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 369 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 370 } else { 371 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 372 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 373 } 374 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 375 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 376 377 DBG(6, "idle, wake on %02x\n", wakeup_enables); 378 } 379 380 /* 381 * Updates cable VBUS status. Caller must take care of locking. 382 */ 383 static int tusb_musb_vbus_status(struct musb *musb) 384 { 385 void __iomem *tbase = musb->ctrl_base; 386 u32 otg_stat, prcm_mngmt; 387 int ret = 0; 388 389 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 390 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT); 391 392 /* Temporarily enable VBUS detection if it was disabled for 393 * suspend mode. Unless it's enabled otg_stat and devctl will 394 * not show correct VBUS state. 395 */ 396 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) { 397 u32 tmp = prcm_mngmt; 398 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 399 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp); 400 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 401 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt); 402 } 403 404 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) 405 ret = 1; 406 407 return ret; 408 } 409 410 static struct timer_list musb_idle_timer; 411 412 static void musb_do_idle(unsigned long _musb) 413 { 414 struct musb *musb = (void *)_musb; 415 unsigned long flags; 416 417 spin_lock_irqsave(&musb->lock, flags); 418 419 switch (musb->xceiv->state) { 420 case OTG_STATE_A_WAIT_BCON: 421 if ((musb->a_wait_bcon != 0) 422 && (musb->idle_timeout == 0 423 || time_after(jiffies, musb->idle_timeout))) { 424 DBG(4, "Nothing connected %s, turning off VBUS\n", 425 otg_state_string(musb)); 426 } 427 /* FALLTHROUGH */ 428 case OTG_STATE_A_IDLE: 429 tusb_musb_set_vbus(musb, 0); 430 default: 431 break; 432 } 433 434 if (!musb->is_active) { 435 u32 wakeups; 436 437 /* wait until khubd handles port change status */ 438 if (is_host_active(musb) && (musb->port1_status >> 16)) 439 goto done; 440 441 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 442 if (is_peripheral_enabled(musb) && !musb->gadget_driver) 443 wakeups = 0; 444 else { 445 wakeups = TUSB_PRCM_WHOSTDISCON 446 | TUSB_PRCM_WBUS 447 | TUSB_PRCM_WVBUS; 448 if (is_otg_enabled(musb)) 449 wakeups |= TUSB_PRCM_WID; 450 } 451 #else 452 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS; 453 #endif 454 tusb_allow_idle(musb, wakeups); 455 } 456 done: 457 spin_unlock_irqrestore(&musb->lock, flags); 458 } 459 460 /* 461 * Maybe put TUSB6010 into idle mode mode depending on USB link status, 462 * like "disconnected" or "suspended". We'll be woken out of it by 463 * connect, resume, or disconnect. 464 * 465 * Needs to be called as the last function everywhere where there is 466 * register access to TUSB6010 because of NOR flash wake-up. 467 * Caller should own controller spinlock. 468 * 469 * Delay because peripheral enables D+ pullup 3msec after SE0, and 470 * we don't want to treat that full speed J as a wakeup event. 471 * ... peripherals must draw only suspend current after 10 msec. 472 */ 473 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout) 474 { 475 unsigned long default_timeout = jiffies + msecs_to_jiffies(3); 476 static unsigned long last_timer; 477 478 if (timeout == 0) 479 timeout = default_timeout; 480 481 /* Never idle if active, or when VBUS timeout is not set as host */ 482 if (musb->is_active || ((musb->a_wait_bcon == 0) 483 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) { 484 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 485 del_timer(&musb_idle_timer); 486 last_timer = jiffies; 487 return; 488 } 489 490 if (time_after(last_timer, timeout)) { 491 if (!timer_pending(&musb_idle_timer)) 492 last_timer = timeout; 493 else { 494 DBG(4, "Longer idle timer already pending, ignoring\n"); 495 return; 496 } 497 } 498 last_timer = timeout; 499 500 DBG(4, "%s inactive, for idle timer for %lu ms\n", 501 otg_state_string(musb), 502 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 503 mod_timer(&musb_idle_timer, timeout); 504 } 505 506 /* ticks of 60 MHz clock */ 507 #define DEVCLOCK 60000000 508 #define OTG_TIMER_MS(msecs) ((msecs) \ 509 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \ 510 | TUSB_DEV_OTG_TIMER_ENABLE) \ 511 : 0) 512 513 static void tusb_musb_set_vbus(struct musb *musb, int is_on) 514 { 515 void __iomem *tbase = musb->ctrl_base; 516 u32 conf, prcm, timer; 517 u8 devctl; 518 519 /* HDRC controls CPEN, but beware current surges during device 520 * connect. They can trigger transient overcurrent conditions 521 * that must be ignored. 522 */ 523 524 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT); 525 conf = musb_readl(tbase, TUSB_DEV_CONF); 526 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 527 528 if (is_on) { 529 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); 530 musb->xceiv->default_a = 1; 531 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 532 devctl |= MUSB_DEVCTL_SESSION; 533 534 conf |= TUSB_DEV_CONF_USB_HOST_MODE; 535 MUSB_HST_MODE(musb); 536 } else { 537 u32 otg_stat; 538 539 timer = 0; 540 541 /* If ID pin is grounded, we want to be a_idle */ 542 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 543 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { 544 switch (musb->xceiv->state) { 545 case OTG_STATE_A_WAIT_VRISE: 546 case OTG_STATE_A_WAIT_BCON: 547 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 548 break; 549 case OTG_STATE_A_WAIT_VFALL: 550 musb->xceiv->state = OTG_STATE_A_IDLE; 551 break; 552 default: 553 musb->xceiv->state = OTG_STATE_A_IDLE; 554 } 555 musb->is_active = 0; 556 musb->xceiv->default_a = 1; 557 MUSB_HST_MODE(musb); 558 } else { 559 musb->is_active = 0; 560 musb->xceiv->default_a = 0; 561 musb->xceiv->state = OTG_STATE_B_IDLE; 562 MUSB_DEV_MODE(musb); 563 } 564 565 devctl &= ~MUSB_DEVCTL_SESSION; 566 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE; 567 } 568 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 569 570 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm); 571 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer); 572 musb_writel(tbase, TUSB_DEV_CONF, conf); 573 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 574 575 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 576 otg_state_string(musb), 577 musb_readb(musb->mregs, MUSB_DEVCTL), 578 musb_readl(tbase, TUSB_DEV_OTG_STAT), 579 conf, prcm); 580 } 581 582 /* 583 * Sets the mode to OTG, peripheral or host by changing the ID detection. 584 * Caller must take care of locking. 585 * 586 * Note that if a mini-A cable is plugged in the ID line will stay down as 587 * the weak ID pull-up is not able to pull the ID up. 588 * 589 * REVISIT: It would be possible to add support for changing between host 590 * and peripheral modes in non-OTG configurations by reconfiguring hardware 591 * and then setting musb->board_mode. For now, only support OTG mode. 592 */ 593 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode) 594 { 595 void __iomem *tbase = musb->ctrl_base; 596 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf; 597 598 if (musb->board_mode != MUSB_OTG) { 599 ERR("Changing mode currently only supported in OTG mode\n"); 600 return -EINVAL; 601 } 602 603 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 604 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 605 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 606 dev_conf = musb_readl(tbase, TUSB_DEV_CONF); 607 608 switch (musb_mode) { 609 610 #ifdef CONFIG_USB_MUSB_HDRC_HCD 611 case MUSB_HOST: /* Disable PHY ID detect, ground ID */ 612 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 613 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 614 dev_conf |= TUSB_DEV_CONF_ID_SEL; 615 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID; 616 break; 617 #endif 618 619 #ifdef CONFIG_USB_GADGET_MUSB_HDRC 620 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */ 621 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 622 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 623 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 624 break; 625 #endif 626 627 #ifdef CONFIG_USB_MUSB_OTG 628 case MUSB_OTG: /* Use PHY ID detection */ 629 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 630 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 631 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 632 break; 633 #endif 634 635 default: 636 DBG(2, "Trying to set mode %i\n", musb_mode); 637 return -EINVAL; 638 } 639 640 musb_writel(tbase, TUSB_PHY_OTG_CTRL, 641 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl); 642 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, 643 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena); 644 musb_writel(tbase, TUSB_DEV_CONF, dev_conf); 645 646 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 647 if ((musb_mode == MUSB_PERIPHERAL) && 648 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) 649 INFO("Cannot be peripheral with mini-A cable " 650 "otg_stat: %08x\n", otg_stat); 651 652 return 0; 653 } 654 655 static inline unsigned long 656 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) 657 { 658 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 659 unsigned long idle_timeout = 0; 660 661 /* ID pin */ 662 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) { 663 int default_a; 664 665 if (is_otg_enabled(musb)) 666 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 667 else 668 default_a = is_host_enabled(musb); 669 DBG(2, "Default-%c\n", default_a ? 'A' : 'B'); 670 musb->xceiv->default_a = default_a; 671 tusb_musb_set_vbus(musb, default_a); 672 673 /* Don't allow idling immediately */ 674 if (default_a) 675 idle_timeout = jiffies + (HZ * 3); 676 } 677 678 /* VBUS state change */ 679 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { 680 681 /* B-dev state machine: no vbus ~= disconnect */ 682 if ((is_otg_enabled(musb) && !musb->xceiv->default_a) 683 || !is_host_enabled(musb)) { 684 #ifdef CONFIG_USB_MUSB_HDRC_HCD 685 /* ? musb_root_disconnect(musb); */ 686 musb->port1_status &= 687 ~(USB_PORT_STAT_CONNECTION 688 | USB_PORT_STAT_ENABLE 689 | USB_PORT_STAT_LOW_SPEED 690 | USB_PORT_STAT_HIGH_SPEED 691 | USB_PORT_STAT_TEST 692 ); 693 #endif 694 695 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 696 DBG(1, "Forcing disconnect (no interrupt)\n"); 697 if (musb->xceiv->state != OTG_STATE_B_IDLE) { 698 /* INTR_DISCONNECT can hide... */ 699 musb->xceiv->state = OTG_STATE_B_IDLE; 700 musb->int_usb |= MUSB_INTR_DISCONNECT; 701 } 702 musb->is_active = 0; 703 } 704 DBG(2, "vbus change, %s, otg %03x\n", 705 otg_state_string(musb), otg_stat); 706 idle_timeout = jiffies + (1 * HZ); 707 schedule_work(&musb->irq_work); 708 709 } else /* A-dev state machine */ { 710 DBG(2, "vbus change, %s, otg %03x\n", 711 otg_state_string(musb), otg_stat); 712 713 switch (musb->xceiv->state) { 714 case OTG_STATE_A_IDLE: 715 DBG(2, "Got SRP, turning on VBUS\n"); 716 musb_platform_set_vbus(musb, 1); 717 718 /* CONNECT can wake if a_wait_bcon is set */ 719 if (musb->a_wait_bcon != 0) 720 musb->is_active = 0; 721 else 722 musb->is_active = 1; 723 724 /* 725 * OPT FS A TD.4.6 needs few seconds for 726 * A_WAIT_VRISE 727 */ 728 idle_timeout = jiffies + (2 * HZ); 729 730 break; 731 case OTG_STATE_A_WAIT_VRISE: 732 /* ignore; A-session-valid < VBUS_VALID/2, 733 * we monitor this with the timer 734 */ 735 break; 736 case OTG_STATE_A_WAIT_VFALL: 737 /* REVISIT this irq triggers during short 738 * spikes caused by enumeration ... 739 */ 740 if (musb->vbuserr_retry) { 741 musb->vbuserr_retry--; 742 tusb_musb_set_vbus(musb, 1); 743 } else { 744 musb->vbuserr_retry 745 = VBUSERR_RETRY_COUNT; 746 tusb_musb_set_vbus(musb, 0); 747 } 748 break; 749 default: 750 break; 751 } 752 } 753 } 754 755 /* OTG timer expiration */ 756 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 757 u8 devctl; 758 759 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat); 760 761 switch (musb->xceiv->state) { 762 case OTG_STATE_A_WAIT_VRISE: 763 /* VBUS has probably been valid for a while now, 764 * but may well have bounced out of range a bit 765 */ 766 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 767 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 768 if ((devctl & MUSB_DEVCTL_VBUS) 769 != MUSB_DEVCTL_VBUS) { 770 DBG(2, "devctl %02x\n", devctl); 771 break; 772 } 773 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 774 musb->is_active = 0; 775 idle_timeout = jiffies 776 + msecs_to_jiffies(musb->a_wait_bcon); 777 } else { 778 /* REVISIT report overcurrent to hub? */ 779 ERR("vbus too slow, devctl %02x\n", devctl); 780 tusb_musb_set_vbus(musb, 0); 781 } 782 break; 783 case OTG_STATE_A_WAIT_BCON: 784 if (musb->a_wait_bcon != 0) 785 idle_timeout = jiffies 786 + msecs_to_jiffies(musb->a_wait_bcon); 787 break; 788 case OTG_STATE_A_SUSPEND: 789 break; 790 case OTG_STATE_B_WAIT_ACON: 791 break; 792 default: 793 break; 794 } 795 } 796 schedule_work(&musb->irq_work); 797 798 return idle_timeout; 799 } 800 801 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci) 802 { 803 struct musb *musb = __hci; 804 void __iomem *tbase = musb->ctrl_base; 805 unsigned long flags, idle_timeout = 0; 806 u32 int_mask, int_src; 807 808 spin_lock_irqsave(&musb->lock, flags); 809 810 /* Mask all interrupts to allow using both edge and level GPIO irq */ 811 int_mask = musb_readl(tbase, TUSB_INT_MASK); 812 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 813 814 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 815 DBG(3, "TUSB IRQ %08x\n", int_src); 816 817 musb->int_usb = (u8) int_src; 818 819 /* Acknowledge wake-up source interrupts */ 820 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) { 821 u32 reg; 822 u32 i; 823 824 if (tusb_get_revision(musb) == TUSB_REV_30) 825 tusb_wbus_quirk(musb, 0); 826 827 /* there are issues re-locking the PLL on wakeup ... */ 828 829 /* work around issue 8 */ 830 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) { 831 musb_writel(tbase, TUSB_SCRATCH_PAD, 0); 832 musb_writel(tbase, TUSB_SCRATCH_PAD, i); 833 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 834 if (reg == i) 835 break; 836 DBG(6, "TUSB NOR not ready\n"); 837 } 838 839 /* work around issue 13 (2nd half) */ 840 tusb_set_clock_source(musb, 1); 841 842 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE); 843 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); 844 if (reg & ~TUSB_PRCM_WNORCS) { 845 musb->is_active = 1; 846 schedule_work(&musb->irq_work); 847 } 848 DBG(3, "wake %sactive %02x\n", 849 musb->is_active ? "" : "in", reg); 850 851 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 852 } 853 854 if (int_src & TUSB_INT_SRC_USB_IP_CONN) 855 del_timer(&musb_idle_timer); 856 857 /* OTG state change reports (annoyingly) not issued by Mentor core */ 858 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG 859 | TUSB_INT_SRC_OTG_TIMEOUT 860 | TUSB_INT_SRC_ID_STATUS_CHNG)) 861 idle_timeout = tusb_otg_ints(musb, int_src, tbase); 862 863 /* TX dma callback must be handled here, RX dma callback is 864 * handled in tusb_omap_dma_cb. 865 */ 866 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) { 867 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 868 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK); 869 870 DBG(3, "DMA IRQ %08x\n", dma_src); 871 real_dma_src = ~real_dma_src & dma_src; 872 if (tusb_dma_omap() && real_dma_src) { 873 int tx_source = (real_dma_src & 0xffff); 874 int i; 875 876 for (i = 1; i <= 15; i++) { 877 if (tx_source & (1 << i)) { 878 DBG(3, "completing ep%i %s\n", i, "tx"); 879 musb_dma_completion(musb, i, 1); 880 } 881 } 882 } 883 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src); 884 } 885 886 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */ 887 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) { 888 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC); 889 890 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src); 891 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1); 892 musb->int_tx = (musb_src & 0xffff); 893 } else { 894 musb->int_rx = 0; 895 musb->int_tx = 0; 896 } 897 898 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff)) 899 musb_interrupt(musb); 900 901 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */ 902 musb_writel(tbase, TUSB_INT_SRC_CLEAR, 903 int_src & ~TUSB_INT_MASK_RESERVED_BITS); 904 905 tusb_musb_try_idle(musb, idle_timeout); 906 907 musb_writel(tbase, TUSB_INT_MASK, int_mask); 908 spin_unlock_irqrestore(&musb->lock, flags); 909 910 return IRQ_HANDLED; 911 } 912 913 static int dma_off; 914 915 /* 916 * Enables TUSB6010. Caller must take care of locking. 917 * REVISIT: 918 * - Check what is unnecessary in MGC_HdrcStart() 919 */ 920 static void tusb_musb_enable(struct musb *musb) 921 { 922 void __iomem *tbase = musb->ctrl_base; 923 924 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF. 925 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */ 926 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF); 927 928 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */ 929 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0); 930 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 931 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 932 933 /* Clear all subsystem interrups */ 934 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff); 935 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff); 936 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff); 937 938 /* Acknowledge pending interrupt(s) */ 939 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS); 940 941 /* Only 0 clock cycles for minimum interrupt de-assertion time and 942 * interrupt polarity active low seems to work reliably here */ 943 musb_writel(tbase, TUSB_INT_CTRL_CONF, 944 TUSB_INT_CTRL_CONF_INT_RELCYC(0)); 945 946 set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW); 947 948 /* maybe force into the Default-A OTG state machine */ 949 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT) 950 & TUSB_DEV_OTG_STAT_ID_STATUS)) 951 musb_writel(tbase, TUSB_INT_SRC_SET, 952 TUSB_INT_SRC_ID_STATUS_CHNG); 953 954 if (is_dma_capable() && dma_off) 955 printk(KERN_WARNING "%s %s: dma not reactivated\n", 956 __FILE__, __func__); 957 else 958 dma_off = 1; 959 } 960 961 /* 962 * Disables TUSB6010. Caller must take care of locking. 963 */ 964 static void tusb_musb_disable(struct musb *musb) 965 { 966 void __iomem *tbase = musb->ctrl_base; 967 968 /* FIXME stop DMA, IRQs, timers, ... */ 969 970 /* disable all IRQs */ 971 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 972 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff); 973 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 974 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 975 976 del_timer(&musb_idle_timer); 977 978 if (is_dma_capable() && !dma_off) { 979 printk(KERN_WARNING "%s %s: dma still active\n", 980 __FILE__, __func__); 981 dma_off = 1; 982 } 983 } 984 985 /* 986 * Sets up TUSB6010 CPU interface specific signals and registers 987 * Note: Settings optimized for OMAP24xx 988 */ 989 static void tusb_setup_cpu_interface(struct musb *musb) 990 { 991 void __iomem *tbase = musb->ctrl_base; 992 993 /* 994 * Disable GPIO[5:0] pullups (used as output DMA requests) 995 * Don't disable GPIO[7:6] as they are needed for wake-up. 996 */ 997 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F); 998 999 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */ 1000 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF); 1001 1002 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */ 1003 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f)); 1004 1005 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request 1006 * de-assertion time 2 system clocks p 62 */ 1007 musb_writel(tbase, TUSB_DMA_REQ_CONF, 1008 TUSB_DMA_REQ_CONF_BURST_SIZE(2) | 1009 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | 1010 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 1011 1012 /* Set 0 wait count for synchronous burst access */ 1013 musb_writel(tbase, TUSB_WAIT_COUNT, 1); 1014 } 1015 1016 static int tusb_musb_start(struct musb *musb) 1017 { 1018 void __iomem *tbase = musb->ctrl_base; 1019 int ret = 0; 1020 unsigned long flags; 1021 u32 reg; 1022 1023 if (musb->board_set_power) 1024 ret = musb->board_set_power(1); 1025 if (ret != 0) { 1026 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n"); 1027 return ret; 1028 } 1029 1030 spin_lock_irqsave(&musb->lock, flags); 1031 1032 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) != 1033 TUSB_PROD_TEST_RESET_VAL) { 1034 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n"); 1035 goto err; 1036 } 1037 1038 ret = tusb_print_revision(musb); 1039 if (ret < 2) { 1040 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n", 1041 ret); 1042 goto err; 1043 } 1044 1045 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when 1046 * NOR FLASH interface is used */ 1047 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8); 1048 1049 /* Select PHY free running 60MHz as a system clock */ 1050 tusb_set_clock_source(musb, 1); 1051 1052 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for 1053 * power saving, enable VBus detect and session end comparators, 1054 * enable IDpullup, enable VBus charging */ 1055 musb_writel(tbase, TUSB_PRCM_MNGMT, 1056 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) | 1057 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN | 1058 TUSB_PRCM_MNGMT_OTG_SESS_END_EN | 1059 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN | 1060 TUSB_PRCM_MNGMT_OTG_ID_PULLUP); 1061 tusb_setup_cpu_interface(musb); 1062 1063 /* simplify: always sense/pullup ID pins, as if in OTG mode */ 1064 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 1065 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1066 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg); 1067 1068 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 1069 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1070 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg); 1071 1072 spin_unlock_irqrestore(&musb->lock, flags); 1073 1074 return 0; 1075 1076 err: 1077 spin_unlock_irqrestore(&musb->lock, flags); 1078 1079 if (musb->board_set_power) 1080 musb->board_set_power(0); 1081 1082 return -ENODEV; 1083 } 1084 1085 static int tusb_musb_init(struct musb *musb) 1086 { 1087 struct platform_device *pdev; 1088 struct resource *mem; 1089 void __iomem *sync = NULL; 1090 int ret; 1091 1092 usb_nop_xceiv_register(); 1093 musb->xceiv = otg_get_transceiver(); 1094 if (!musb->xceiv) 1095 return -ENODEV; 1096 1097 pdev = to_platform_device(musb->controller); 1098 1099 /* dma address for async dma */ 1100 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1101 musb->async = mem->start; 1102 1103 /* dma address for sync dma */ 1104 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1105 if (!mem) { 1106 pr_debug("no sync dma resource?\n"); 1107 ret = -ENODEV; 1108 goto done; 1109 } 1110 musb->sync = mem->start; 1111 1112 sync = ioremap(mem->start, resource_size(mem)); 1113 if (!sync) { 1114 pr_debug("ioremap for sync failed\n"); 1115 ret = -ENOMEM; 1116 goto done; 1117 } 1118 musb->sync_va = sync; 1119 1120 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400, 1121 * FIFOs at 0x600, TUSB at 0x800 1122 */ 1123 musb->mregs += TUSB_BASE_OFFSET; 1124 1125 ret = tusb_musb_start(musb); 1126 if (ret) { 1127 printk(KERN_ERR "Could not start tusb6010 (%d)\n", 1128 ret); 1129 goto done; 1130 } 1131 musb->isr = tusb_musb_interrupt; 1132 1133 if (is_peripheral_enabled(musb)) { 1134 musb->xceiv->set_power = tusb_draw_power; 1135 the_musb = musb; 1136 } 1137 1138 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); 1139 1140 done: 1141 if (ret < 0) { 1142 if (sync) 1143 iounmap(sync); 1144 1145 otg_put_transceiver(musb->xceiv); 1146 usb_nop_xceiv_unregister(); 1147 } 1148 return ret; 1149 } 1150 1151 static int tusb_musb_exit(struct musb *musb) 1152 { 1153 del_timer_sync(&musb_idle_timer); 1154 the_musb = NULL; 1155 1156 if (musb->board_set_power) 1157 musb->board_set_power(0); 1158 1159 iounmap(musb->sync_va); 1160 1161 otg_put_transceiver(musb->xceiv); 1162 usb_nop_xceiv_unregister(); 1163 return 0; 1164 } 1165 1166 static const struct musb_platform_ops tusb_ops = { 1167 .init = tusb_musb_init, 1168 .exit = tusb_musb_exit, 1169 1170 .enable = tusb_musb_enable, 1171 .disable = tusb_musb_disable, 1172 1173 .set_mode = tusb_musb_set_mode, 1174 .try_idle = tusb_musb_try_idle, 1175 1176 .vbus_status = tusb_musb_vbus_status, 1177 .set_vbus = tusb_musb_set_vbus, 1178 }; 1179 1180 static u64 tusb_dmamask = DMA_BIT_MASK(32); 1181 1182 static int __init tusb_probe(struct platform_device *pdev) 1183 { 1184 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; 1185 struct platform_device *musb; 1186 struct tusb6010_glue *glue; 1187 1188 int ret = -ENOMEM; 1189 1190 glue = kzalloc(sizeof(*glue), GFP_KERNEL); 1191 if (!glue) { 1192 dev_err(&pdev->dev, "failed to allocate glue context\n"); 1193 goto err0; 1194 } 1195 1196 musb = platform_device_alloc("musb-hdrc", -1); 1197 if (!musb) { 1198 dev_err(&pdev->dev, "failed to allocate musb device\n"); 1199 goto err1; 1200 } 1201 1202 musb->dev.parent = &pdev->dev; 1203 musb->dev.dma_mask = &tusb_dmamask; 1204 musb->dev.coherent_dma_mask = tusb_dmamask; 1205 1206 glue->dev = &pdev->dev; 1207 glue->musb = musb; 1208 1209 pdata->platform_ops = &tusb_ops; 1210 1211 platform_set_drvdata(pdev, glue); 1212 1213 ret = platform_device_add_resources(musb, pdev->resource, 1214 pdev->num_resources); 1215 if (ret) { 1216 dev_err(&pdev->dev, "failed to add resources\n"); 1217 goto err2; 1218 } 1219 1220 ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); 1221 if (ret) { 1222 dev_err(&pdev->dev, "failed to add platform_data\n"); 1223 goto err2; 1224 } 1225 1226 ret = platform_device_add(musb); 1227 if (ret) { 1228 dev_err(&pdev->dev, "failed to register musb device\n"); 1229 goto err1; 1230 } 1231 1232 return 0; 1233 1234 err2: 1235 platform_device_put(musb); 1236 1237 err1: 1238 kfree(glue); 1239 1240 err0: 1241 return ret; 1242 } 1243 1244 static int __exit tusb_remove(struct platform_device *pdev) 1245 { 1246 struct tusb6010_glue *glue = platform_get_drvdata(pdev); 1247 1248 platform_device_del(glue->musb); 1249 platform_device_put(glue->musb); 1250 kfree(glue); 1251 1252 return 0; 1253 } 1254 1255 static struct platform_driver tusb_driver = { 1256 .remove = __exit_p(tusb_remove), 1257 .driver = { 1258 .name = "musb-tusb", 1259 }, 1260 }; 1261 1262 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer"); 1263 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1264 MODULE_LICENSE("GPL v2"); 1265 1266 static int __init tusb_init(void) 1267 { 1268 return platform_driver_probe(&tusb_driver, tusb_probe); 1269 } 1270 subsys_initcall(tusb_init); 1271 1272 static void __exit tusb_exit(void) 1273 { 1274 platform_driver_unregister(&tusb_driver); 1275 } 1276 module_exit(tusb_exit); 1277