1 /* 2 * TUSB6010 USB 2.0 OTG Dual Role controller 3 * 4 * Copyright (C) 2006 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Notes: 12 * - Driver assumes that interface to external host (main CPU) is 13 * configured for NOR FLASH interface instead of VLYNQ serial 14 * interface. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/errno.h> 20 #include <linux/err.h> 21 #include <linux/init.h> 22 #include <linux/prefetch.h> 23 #include <linux/usb.h> 24 #include <linux/irq.h> 25 #include <linux/platform_device.h> 26 #include <linux/dma-mapping.h> 27 28 #include "musb_core.h" 29 30 struct tusb6010_glue { 31 struct device *dev; 32 struct platform_device *musb; 33 }; 34 35 static void tusb_musb_set_vbus(struct musb *musb, int is_on); 36 37 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) 38 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) 39 40 /* 41 * Checks the revision. We need to use the DMA register as 3.0 does not 42 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. 43 */ 44 u8 tusb_get_revision(struct musb *musb) 45 { 46 void __iomem *tbase = musb->ctrl_base; 47 u32 die_id; 48 u8 rev; 49 50 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff; 51 if (TUSB_REV_MAJOR(rev) == 3) { 52 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, 53 TUSB_DIDR1_HI)); 54 if (die_id >= TUSB_DIDR1_HI_REV_31) 55 rev |= 1; 56 } 57 58 return rev; 59 } 60 EXPORT_SYMBOL_GPL(tusb_get_revision); 61 62 static int tusb_print_revision(struct musb *musb) 63 { 64 void __iomem *tbase = musb->ctrl_base; 65 u8 rev; 66 67 rev = tusb_get_revision(musb); 68 69 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n", 70 "prcm", 71 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)), 72 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)), 73 "int", 74 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 75 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 76 "gpio", 77 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)), 78 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)), 79 "dma", 80 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 81 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 82 "dieid", 83 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)), 84 "rev", 85 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev)); 86 87 return tusb_get_revision(musb); 88 } 89 90 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \ 91 | TUSB_PHY_OTG_CTRL_TESTM0) 92 93 /* 94 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0. 95 * Disables power detection in PHY for the duration of idle. 96 */ 97 static void tusb_wbus_quirk(struct musb *musb, int enabled) 98 { 99 void __iomem *tbase = musb->ctrl_base; 100 static u32 phy_otg_ctrl, phy_otg_ena; 101 u32 tmp; 102 103 if (enabled) { 104 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 105 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 106 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT 107 | phy_otg_ena | WBUS_QUIRK_MASK; 108 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 109 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 110 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 111 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 112 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 113 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 114 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 115 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 116 & TUSB_PHY_OTG_CTRL_TESTM2) { 117 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl; 118 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 119 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 120 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 121 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 122 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 123 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 124 phy_otg_ctrl = 0; 125 phy_otg_ena = 0; 126 } 127 } 128 129 /* 130 * TUSB 6010 may use a parallel bus that doesn't support byte ops; 131 * so both loading and unloading FIFOs need explicit byte counts. 132 */ 133 134 static inline void 135 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len) 136 { 137 u32 val; 138 int i; 139 140 if (len > 4) { 141 for (i = 0; i < (len >> 2); i++) { 142 memcpy(&val, buf, 4); 143 musb_writel(fifo, 0, val); 144 buf += 4; 145 } 146 len %= 4; 147 } 148 if (len > 0) { 149 /* Write the rest 1 - 3 bytes to FIFO */ 150 memcpy(&val, buf, len); 151 musb_writel(fifo, 0, val); 152 } 153 } 154 155 static inline void tusb_fifo_read_unaligned(void __iomem *fifo, 156 void __iomem *buf, u16 len) 157 { 158 u32 val; 159 int i; 160 161 if (len > 4) { 162 for (i = 0; i < (len >> 2); i++) { 163 val = musb_readl(fifo, 0); 164 memcpy(buf, &val, 4); 165 buf += 4; 166 } 167 len %= 4; 168 } 169 if (len > 0) { 170 /* Read the rest 1 - 3 bytes from FIFO */ 171 val = musb_readl(fifo, 0); 172 memcpy(buf, &val, len); 173 } 174 } 175 176 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) 177 { 178 struct musb *musb = hw_ep->musb; 179 void __iomem *ep_conf = hw_ep->conf; 180 void __iomem *fifo = hw_ep->fifo; 181 u8 epnum = hw_ep->epnum; 182 183 prefetch(buf); 184 185 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 186 'T', epnum, fifo, len, buf); 187 188 if (epnum) 189 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 190 TUSB_EP_CONFIG_XFR_SIZE(len)); 191 else 192 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX | 193 TUSB_EP0_CONFIG_XFR_SIZE(len)); 194 195 if (likely((0x01 & (unsigned long) buf) == 0)) { 196 197 /* Best case is 32bit-aligned destination address */ 198 if ((0x02 & (unsigned long) buf) == 0) { 199 if (len >= 4) { 200 writesl(fifo, buf, len >> 2); 201 buf += (len & ~0x03); 202 len &= 0x03; 203 } 204 } else { 205 if (len >= 2) { 206 u32 val; 207 int i; 208 209 /* Cannot use writesw, fifo is 32-bit */ 210 for (i = 0; i < (len >> 2); i++) { 211 val = (u32)(*(u16 *)buf); 212 buf += 2; 213 val |= (*(u16 *)buf) << 16; 214 buf += 2; 215 musb_writel(fifo, 0, val); 216 } 217 len &= 0x03; 218 } 219 } 220 } 221 222 if (len > 0) 223 tusb_fifo_write_unaligned(fifo, buf, len); 224 } 225 226 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) 227 { 228 struct musb *musb = hw_ep->musb; 229 void __iomem *ep_conf = hw_ep->conf; 230 void __iomem *fifo = hw_ep->fifo; 231 u8 epnum = hw_ep->epnum; 232 233 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 234 'R', epnum, fifo, len, buf); 235 236 if (epnum) 237 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 238 TUSB_EP_CONFIG_XFR_SIZE(len)); 239 else 240 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len)); 241 242 if (likely((0x01 & (unsigned long) buf) == 0)) { 243 244 /* Best case is 32bit-aligned destination address */ 245 if ((0x02 & (unsigned long) buf) == 0) { 246 if (len >= 4) { 247 readsl(fifo, buf, len >> 2); 248 buf += (len & ~0x03); 249 len &= 0x03; 250 } 251 } else { 252 if (len >= 2) { 253 u32 val; 254 int i; 255 256 /* Cannot use readsw, fifo is 32-bit */ 257 for (i = 0; i < (len >> 2); i++) { 258 val = musb_readl(fifo, 0); 259 *(u16 *)buf = (u16)(val & 0xffff); 260 buf += 2; 261 *(u16 *)buf = (u16)(val >> 16); 262 buf += 2; 263 } 264 len &= 0x03; 265 } 266 } 267 } 268 269 if (len > 0) 270 tusb_fifo_read_unaligned(fifo, buf, len); 271 } 272 273 static struct musb *the_musb; 274 275 /* This is used by gadget drivers, and OTG transceiver logic, allowing 276 * at most mA current to be drawn from VBUS during a Default-B session 277 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host 278 * mode), or low power Default-B sessions, something else supplies power. 279 * Caller must take care of locking. 280 */ 281 static int tusb_draw_power(struct usb_phy *x, unsigned mA) 282 { 283 struct musb *musb = the_musb; 284 void __iomem *tbase = musb->ctrl_base; 285 u32 reg; 286 287 /* tps65030 seems to consume max 100mA, with maybe 60mA available 288 * (measured on one board) for things other than tps and tusb. 289 * 290 * Boards sharing the CPU clock with CLKIN will need to prevent 291 * certain idle sleep states while the USB link is active. 292 * 293 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }. 294 * The actual current usage would be very board-specific. For now, 295 * it's simpler to just use an aggregate (also board-specific). 296 */ 297 if (x->otg->default_a || mA < (musb->min_power << 1)) 298 mA = 0; 299 300 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 301 if (mA) { 302 musb->is_bus_powered = 1; 303 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; 304 } else { 305 musb->is_bus_powered = 0; 306 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 307 } 308 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 309 310 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA); 311 return 0; 312 } 313 314 /* workaround for issue 13: change clock during chip idle 315 * (to be fixed in rev3 silicon) ... symptoms include disconnect 316 * or looping suspend/resume cycles 317 */ 318 static void tusb_set_clock_source(struct musb *musb, unsigned mode) 319 { 320 void __iomem *tbase = musb->ctrl_base; 321 u32 reg; 322 323 reg = musb_readl(tbase, TUSB_PRCM_CONF); 324 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); 325 326 /* 0 = refclk (clkin, XI) 327 * 1 = PHY 60 MHz (internal PLL) 328 * 2 = not supported 329 * 3 = what? 330 */ 331 if (mode > 0) 332 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); 333 334 musb_writel(tbase, TUSB_PRCM_CONF, reg); 335 336 /* FIXME tusb6010_platform_retime(mode == 0); */ 337 } 338 339 /* 340 * Idle TUSB6010 until next wake-up event; NOR access always wakes. 341 * Other code ensures that we idle unless we're connected _and_ the 342 * USB link is not suspended ... and tells us the relevant wakeup 343 * events. SW_EN for voltage is handled separately. 344 */ 345 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables) 346 { 347 void __iomem *tbase = musb->ctrl_base; 348 u32 reg; 349 350 if ((wakeup_enables & TUSB_PRCM_WBUS) 351 && (tusb_get_revision(musb) == TUSB_REV_30)) 352 tusb_wbus_quirk(musb, 1); 353 354 tusb_set_clock_source(musb, 0); 355 356 wakeup_enables |= TUSB_PRCM_WNORCS; 357 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables); 358 359 /* REVISIT writeup of WID implies that if WID set and ID is grounded, 360 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared. 361 * Presumably that's mostly to save power, hence WID is immaterial ... 362 */ 363 364 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 365 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */ 366 if (is_host_active(musb)) { 367 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 368 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 369 } else { 370 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 371 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 372 } 373 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 374 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 375 376 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables); 377 } 378 379 /* 380 * Updates cable VBUS status. Caller must take care of locking. 381 */ 382 static int tusb_musb_vbus_status(struct musb *musb) 383 { 384 void __iomem *tbase = musb->ctrl_base; 385 u32 otg_stat, prcm_mngmt; 386 int ret = 0; 387 388 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 389 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT); 390 391 /* Temporarily enable VBUS detection if it was disabled for 392 * suspend mode. Unless it's enabled otg_stat and devctl will 393 * not show correct VBUS state. 394 */ 395 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) { 396 u32 tmp = prcm_mngmt; 397 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 398 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp); 399 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 400 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt); 401 } 402 403 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) 404 ret = 1; 405 406 return ret; 407 } 408 409 static struct timer_list musb_idle_timer; 410 411 static void musb_do_idle(unsigned long _musb) 412 { 413 struct musb *musb = (void *)_musb; 414 unsigned long flags; 415 416 spin_lock_irqsave(&musb->lock, flags); 417 418 switch (musb->xceiv->state) { 419 case OTG_STATE_A_WAIT_BCON: 420 if ((musb->a_wait_bcon != 0) 421 && (musb->idle_timeout == 0 422 || time_after(jiffies, musb->idle_timeout))) { 423 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n", 424 otg_state_string(musb->xceiv->state)); 425 } 426 /* FALLTHROUGH */ 427 case OTG_STATE_A_IDLE: 428 tusb_musb_set_vbus(musb, 0); 429 default: 430 break; 431 } 432 433 if (!musb->is_active) { 434 u32 wakeups; 435 436 /* wait until khubd handles port change status */ 437 if (is_host_active(musb) && (musb->port1_status >> 16)) 438 goto done; 439 440 if (is_peripheral_enabled(musb) && !musb->gadget_driver) { 441 wakeups = 0; 442 } else { 443 wakeups = TUSB_PRCM_WHOSTDISCON 444 | TUSB_PRCM_WBUS 445 | TUSB_PRCM_WVBUS; 446 if (is_otg_enabled(musb)) 447 wakeups |= TUSB_PRCM_WID; 448 } 449 tusb_allow_idle(musb, wakeups); 450 } 451 done: 452 spin_unlock_irqrestore(&musb->lock, flags); 453 } 454 455 /* 456 * Maybe put TUSB6010 into idle mode mode depending on USB link status, 457 * like "disconnected" or "suspended". We'll be woken out of it by 458 * connect, resume, or disconnect. 459 * 460 * Needs to be called as the last function everywhere where there is 461 * register access to TUSB6010 because of NOR flash wake-up. 462 * Caller should own controller spinlock. 463 * 464 * Delay because peripheral enables D+ pullup 3msec after SE0, and 465 * we don't want to treat that full speed J as a wakeup event. 466 * ... peripherals must draw only suspend current after 10 msec. 467 */ 468 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout) 469 { 470 unsigned long default_timeout = jiffies + msecs_to_jiffies(3); 471 static unsigned long last_timer; 472 473 if (timeout == 0) 474 timeout = default_timeout; 475 476 /* Never idle if active, or when VBUS timeout is not set as host */ 477 if (musb->is_active || ((musb->a_wait_bcon == 0) 478 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) { 479 dev_dbg(musb->controller, "%s active, deleting timer\n", 480 otg_state_string(musb->xceiv->state)); 481 del_timer(&musb_idle_timer); 482 last_timer = jiffies; 483 return; 484 } 485 486 if (time_after(last_timer, timeout)) { 487 if (!timer_pending(&musb_idle_timer)) 488 last_timer = timeout; 489 else { 490 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n"); 491 return; 492 } 493 } 494 last_timer = timeout; 495 496 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n", 497 otg_state_string(musb->xceiv->state), 498 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 499 mod_timer(&musb_idle_timer, timeout); 500 } 501 502 /* ticks of 60 MHz clock */ 503 #define DEVCLOCK 60000000 504 #define OTG_TIMER_MS(msecs) ((msecs) \ 505 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \ 506 | TUSB_DEV_OTG_TIMER_ENABLE) \ 507 : 0) 508 509 static void tusb_musb_set_vbus(struct musb *musb, int is_on) 510 { 511 void __iomem *tbase = musb->ctrl_base; 512 u32 conf, prcm, timer; 513 u8 devctl; 514 struct usb_otg *otg = musb->xceiv->otg; 515 516 /* HDRC controls CPEN, but beware current surges during device 517 * connect. They can trigger transient overcurrent conditions 518 * that must be ignored. 519 */ 520 521 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT); 522 conf = musb_readl(tbase, TUSB_DEV_CONF); 523 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 524 525 if (is_on) { 526 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); 527 otg->default_a = 1; 528 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 529 devctl |= MUSB_DEVCTL_SESSION; 530 531 conf |= TUSB_DEV_CONF_USB_HOST_MODE; 532 MUSB_HST_MODE(musb); 533 } else { 534 u32 otg_stat; 535 536 timer = 0; 537 538 /* If ID pin is grounded, we want to be a_idle */ 539 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 540 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { 541 switch (musb->xceiv->state) { 542 case OTG_STATE_A_WAIT_VRISE: 543 case OTG_STATE_A_WAIT_BCON: 544 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; 545 break; 546 case OTG_STATE_A_WAIT_VFALL: 547 musb->xceiv->state = OTG_STATE_A_IDLE; 548 break; 549 default: 550 musb->xceiv->state = OTG_STATE_A_IDLE; 551 } 552 musb->is_active = 0; 553 otg->default_a = 1; 554 MUSB_HST_MODE(musb); 555 } else { 556 musb->is_active = 0; 557 otg->default_a = 0; 558 musb->xceiv->state = OTG_STATE_B_IDLE; 559 MUSB_DEV_MODE(musb); 560 } 561 562 devctl &= ~MUSB_DEVCTL_SESSION; 563 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE; 564 } 565 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 566 567 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm); 568 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer); 569 musb_writel(tbase, TUSB_DEV_CONF, conf); 570 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 571 572 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 573 otg_state_string(musb->xceiv->state), 574 musb_readb(musb->mregs, MUSB_DEVCTL), 575 musb_readl(tbase, TUSB_DEV_OTG_STAT), 576 conf, prcm); 577 } 578 579 /* 580 * Sets the mode to OTG, peripheral or host by changing the ID detection. 581 * Caller must take care of locking. 582 * 583 * Note that if a mini-A cable is plugged in the ID line will stay down as 584 * the weak ID pull-up is not able to pull the ID up. 585 * 586 * REVISIT: It would be possible to add support for changing between host 587 * and peripheral modes in non-OTG configurations by reconfiguring hardware 588 * and then setting musb->board_mode. For now, only support OTG mode. 589 */ 590 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode) 591 { 592 void __iomem *tbase = musb->ctrl_base; 593 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf; 594 595 if (musb->board_mode != MUSB_OTG) { 596 ERR("Changing mode currently only supported in OTG mode\n"); 597 return -EINVAL; 598 } 599 600 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 601 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 602 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 603 dev_conf = musb_readl(tbase, TUSB_DEV_CONF); 604 605 switch (musb_mode) { 606 607 case MUSB_HOST: /* Disable PHY ID detect, ground ID */ 608 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 609 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 610 dev_conf |= TUSB_DEV_CONF_ID_SEL; 611 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID; 612 break; 613 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */ 614 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 615 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 616 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 617 break; 618 case MUSB_OTG: /* Use PHY ID detection */ 619 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 620 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 621 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 622 break; 623 624 default: 625 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode); 626 return -EINVAL; 627 } 628 629 musb_writel(tbase, TUSB_PHY_OTG_CTRL, 630 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl); 631 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, 632 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena); 633 musb_writel(tbase, TUSB_DEV_CONF, dev_conf); 634 635 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 636 if ((musb_mode == MUSB_PERIPHERAL) && 637 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) 638 INFO("Cannot be peripheral with mini-A cable " 639 "otg_stat: %08x\n", otg_stat); 640 641 return 0; 642 } 643 644 static inline unsigned long 645 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) 646 { 647 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 648 unsigned long idle_timeout = 0; 649 struct usb_otg *otg = musb->xceiv->otg; 650 651 /* ID pin */ 652 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) { 653 int default_a; 654 655 if (is_otg_enabled(musb)) 656 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 657 else 658 default_a = is_host_enabled(musb); 659 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B'); 660 otg->default_a = default_a; 661 tusb_musb_set_vbus(musb, default_a); 662 663 /* Don't allow idling immediately */ 664 if (default_a) 665 idle_timeout = jiffies + (HZ * 3); 666 } 667 668 /* VBUS state change */ 669 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { 670 671 /* B-dev state machine: no vbus ~= disconnect */ 672 if ((is_otg_enabled(musb) && !otg->default_a) 673 || !is_host_enabled(musb)) { 674 /* ? musb_root_disconnect(musb); */ 675 musb->port1_status &= 676 ~(USB_PORT_STAT_CONNECTION 677 | USB_PORT_STAT_ENABLE 678 | USB_PORT_STAT_LOW_SPEED 679 | USB_PORT_STAT_HIGH_SPEED 680 | USB_PORT_STAT_TEST 681 ); 682 683 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 684 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n"); 685 if (musb->xceiv->state != OTG_STATE_B_IDLE) { 686 /* INTR_DISCONNECT can hide... */ 687 musb->xceiv->state = OTG_STATE_B_IDLE; 688 musb->int_usb |= MUSB_INTR_DISCONNECT; 689 } 690 musb->is_active = 0; 691 } 692 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", 693 otg_state_string(musb->xceiv->state), otg_stat); 694 idle_timeout = jiffies + (1 * HZ); 695 schedule_work(&musb->irq_work); 696 697 } else /* A-dev state machine */ { 698 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", 699 otg_state_string(musb->xceiv->state), otg_stat); 700 701 switch (musb->xceiv->state) { 702 case OTG_STATE_A_IDLE: 703 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n"); 704 musb_platform_set_vbus(musb, 1); 705 706 /* CONNECT can wake if a_wait_bcon is set */ 707 if (musb->a_wait_bcon != 0) 708 musb->is_active = 0; 709 else 710 musb->is_active = 1; 711 712 /* 713 * OPT FS A TD.4.6 needs few seconds for 714 * A_WAIT_VRISE 715 */ 716 idle_timeout = jiffies + (2 * HZ); 717 718 break; 719 case OTG_STATE_A_WAIT_VRISE: 720 /* ignore; A-session-valid < VBUS_VALID/2, 721 * we monitor this with the timer 722 */ 723 break; 724 case OTG_STATE_A_WAIT_VFALL: 725 /* REVISIT this irq triggers during short 726 * spikes caused by enumeration ... 727 */ 728 if (musb->vbuserr_retry) { 729 musb->vbuserr_retry--; 730 tusb_musb_set_vbus(musb, 1); 731 } else { 732 musb->vbuserr_retry 733 = VBUSERR_RETRY_COUNT; 734 tusb_musb_set_vbus(musb, 0); 735 } 736 break; 737 default: 738 break; 739 } 740 } 741 } 742 743 /* OTG timer expiration */ 744 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 745 u8 devctl; 746 747 dev_dbg(musb->controller, "%s timer, %03x\n", 748 otg_state_string(musb->xceiv->state), otg_stat); 749 750 switch (musb->xceiv->state) { 751 case OTG_STATE_A_WAIT_VRISE: 752 /* VBUS has probably been valid for a while now, 753 * but may well have bounced out of range a bit 754 */ 755 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 756 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 757 if ((devctl & MUSB_DEVCTL_VBUS) 758 != MUSB_DEVCTL_VBUS) { 759 dev_dbg(musb->controller, "devctl %02x\n", devctl); 760 break; 761 } 762 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 763 musb->is_active = 0; 764 idle_timeout = jiffies 765 + msecs_to_jiffies(musb->a_wait_bcon); 766 } else { 767 /* REVISIT report overcurrent to hub? */ 768 ERR("vbus too slow, devctl %02x\n", devctl); 769 tusb_musb_set_vbus(musb, 0); 770 } 771 break; 772 case OTG_STATE_A_WAIT_BCON: 773 if (musb->a_wait_bcon != 0) 774 idle_timeout = jiffies 775 + msecs_to_jiffies(musb->a_wait_bcon); 776 break; 777 case OTG_STATE_A_SUSPEND: 778 break; 779 case OTG_STATE_B_WAIT_ACON: 780 break; 781 default: 782 break; 783 } 784 } 785 schedule_work(&musb->irq_work); 786 787 return idle_timeout; 788 } 789 790 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci) 791 { 792 struct musb *musb = __hci; 793 void __iomem *tbase = musb->ctrl_base; 794 unsigned long flags, idle_timeout = 0; 795 u32 int_mask, int_src; 796 797 spin_lock_irqsave(&musb->lock, flags); 798 799 /* Mask all interrupts to allow using both edge and level GPIO irq */ 800 int_mask = musb_readl(tbase, TUSB_INT_MASK); 801 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 802 803 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 804 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src); 805 806 musb->int_usb = (u8) int_src; 807 808 /* Acknowledge wake-up source interrupts */ 809 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) { 810 u32 reg; 811 u32 i; 812 813 if (tusb_get_revision(musb) == TUSB_REV_30) 814 tusb_wbus_quirk(musb, 0); 815 816 /* there are issues re-locking the PLL on wakeup ... */ 817 818 /* work around issue 8 */ 819 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) { 820 musb_writel(tbase, TUSB_SCRATCH_PAD, 0); 821 musb_writel(tbase, TUSB_SCRATCH_PAD, i); 822 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 823 if (reg == i) 824 break; 825 dev_dbg(musb->controller, "TUSB NOR not ready\n"); 826 } 827 828 /* work around issue 13 (2nd half) */ 829 tusb_set_clock_source(musb, 1); 830 831 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE); 832 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); 833 if (reg & ~TUSB_PRCM_WNORCS) { 834 musb->is_active = 1; 835 schedule_work(&musb->irq_work); 836 } 837 dev_dbg(musb->controller, "wake %sactive %02x\n", 838 musb->is_active ? "" : "in", reg); 839 840 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 841 } 842 843 if (int_src & TUSB_INT_SRC_USB_IP_CONN) 844 del_timer(&musb_idle_timer); 845 846 /* OTG state change reports (annoyingly) not issued by Mentor core */ 847 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG 848 | TUSB_INT_SRC_OTG_TIMEOUT 849 | TUSB_INT_SRC_ID_STATUS_CHNG)) 850 idle_timeout = tusb_otg_ints(musb, int_src, tbase); 851 852 /* TX dma callback must be handled here, RX dma callback is 853 * handled in tusb_omap_dma_cb. 854 */ 855 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) { 856 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 857 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK); 858 859 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src); 860 real_dma_src = ~real_dma_src & dma_src; 861 if (tusb_dma_omap() && real_dma_src) { 862 int tx_source = (real_dma_src & 0xffff); 863 int i; 864 865 for (i = 1; i <= 15; i++) { 866 if (tx_source & (1 << i)) { 867 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx"); 868 musb_dma_completion(musb, i, 1); 869 } 870 } 871 } 872 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src); 873 } 874 875 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */ 876 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) { 877 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC); 878 879 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src); 880 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1); 881 musb->int_tx = (musb_src & 0xffff); 882 } else { 883 musb->int_rx = 0; 884 musb->int_tx = 0; 885 } 886 887 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff)) 888 musb_interrupt(musb); 889 890 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */ 891 musb_writel(tbase, TUSB_INT_SRC_CLEAR, 892 int_src & ~TUSB_INT_MASK_RESERVED_BITS); 893 894 tusb_musb_try_idle(musb, idle_timeout); 895 896 musb_writel(tbase, TUSB_INT_MASK, int_mask); 897 spin_unlock_irqrestore(&musb->lock, flags); 898 899 return IRQ_HANDLED; 900 } 901 902 static int dma_off; 903 904 /* 905 * Enables TUSB6010. Caller must take care of locking. 906 * REVISIT: 907 * - Check what is unnecessary in MGC_HdrcStart() 908 */ 909 static void tusb_musb_enable(struct musb *musb) 910 { 911 void __iomem *tbase = musb->ctrl_base; 912 913 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF. 914 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */ 915 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF); 916 917 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */ 918 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0); 919 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 920 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 921 922 /* Clear all subsystem interrups */ 923 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff); 924 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff); 925 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff); 926 927 /* Acknowledge pending interrupt(s) */ 928 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS); 929 930 /* Only 0 clock cycles for minimum interrupt de-assertion time and 931 * interrupt polarity active low seems to work reliably here */ 932 musb_writel(tbase, TUSB_INT_CTRL_CONF, 933 TUSB_INT_CTRL_CONF_INT_RELCYC(0)); 934 935 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW); 936 937 /* maybe force into the Default-A OTG state machine */ 938 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT) 939 & TUSB_DEV_OTG_STAT_ID_STATUS)) 940 musb_writel(tbase, TUSB_INT_SRC_SET, 941 TUSB_INT_SRC_ID_STATUS_CHNG); 942 943 if (is_dma_capable() && dma_off) 944 printk(KERN_WARNING "%s %s: dma not reactivated\n", 945 __FILE__, __func__); 946 else 947 dma_off = 1; 948 } 949 950 /* 951 * Disables TUSB6010. Caller must take care of locking. 952 */ 953 static void tusb_musb_disable(struct musb *musb) 954 { 955 void __iomem *tbase = musb->ctrl_base; 956 957 /* FIXME stop DMA, IRQs, timers, ... */ 958 959 /* disable all IRQs */ 960 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 961 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff); 962 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 963 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 964 965 del_timer(&musb_idle_timer); 966 967 if (is_dma_capable() && !dma_off) { 968 printk(KERN_WARNING "%s %s: dma still active\n", 969 __FILE__, __func__); 970 dma_off = 1; 971 } 972 } 973 974 /* 975 * Sets up TUSB6010 CPU interface specific signals and registers 976 * Note: Settings optimized for OMAP24xx 977 */ 978 static void tusb_setup_cpu_interface(struct musb *musb) 979 { 980 void __iomem *tbase = musb->ctrl_base; 981 982 /* 983 * Disable GPIO[5:0] pullups (used as output DMA requests) 984 * Don't disable GPIO[7:6] as they are needed for wake-up. 985 */ 986 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F); 987 988 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */ 989 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF); 990 991 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */ 992 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f)); 993 994 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request 995 * de-assertion time 2 system clocks p 62 */ 996 musb_writel(tbase, TUSB_DMA_REQ_CONF, 997 TUSB_DMA_REQ_CONF_BURST_SIZE(2) | 998 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | 999 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 1000 1001 /* Set 0 wait count for synchronous burst access */ 1002 musb_writel(tbase, TUSB_WAIT_COUNT, 1); 1003 } 1004 1005 static int tusb_musb_start(struct musb *musb) 1006 { 1007 void __iomem *tbase = musb->ctrl_base; 1008 int ret = 0; 1009 unsigned long flags; 1010 u32 reg; 1011 1012 if (musb->board_set_power) 1013 ret = musb->board_set_power(1); 1014 if (ret != 0) { 1015 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n"); 1016 return ret; 1017 } 1018 1019 spin_lock_irqsave(&musb->lock, flags); 1020 1021 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) != 1022 TUSB_PROD_TEST_RESET_VAL) { 1023 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n"); 1024 goto err; 1025 } 1026 1027 ret = tusb_print_revision(musb); 1028 if (ret < 2) { 1029 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n", 1030 ret); 1031 goto err; 1032 } 1033 1034 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when 1035 * NOR FLASH interface is used */ 1036 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8); 1037 1038 /* Select PHY free running 60MHz as a system clock */ 1039 tusb_set_clock_source(musb, 1); 1040 1041 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for 1042 * power saving, enable VBus detect and session end comparators, 1043 * enable IDpullup, enable VBus charging */ 1044 musb_writel(tbase, TUSB_PRCM_MNGMT, 1045 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) | 1046 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN | 1047 TUSB_PRCM_MNGMT_OTG_SESS_END_EN | 1048 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN | 1049 TUSB_PRCM_MNGMT_OTG_ID_PULLUP); 1050 tusb_setup_cpu_interface(musb); 1051 1052 /* simplify: always sense/pullup ID pins, as if in OTG mode */ 1053 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 1054 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1055 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg); 1056 1057 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 1058 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1059 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg); 1060 1061 spin_unlock_irqrestore(&musb->lock, flags); 1062 1063 return 0; 1064 1065 err: 1066 spin_unlock_irqrestore(&musb->lock, flags); 1067 1068 if (musb->board_set_power) 1069 musb->board_set_power(0); 1070 1071 return -ENODEV; 1072 } 1073 1074 static int tusb_musb_init(struct musb *musb) 1075 { 1076 struct platform_device *pdev; 1077 struct resource *mem; 1078 void __iomem *sync = NULL; 1079 int ret; 1080 1081 usb_nop_xceiv_register(); 1082 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 1083 if (IS_ERR_OR_NULL(musb->xceiv)) 1084 return -ENODEV; 1085 1086 pdev = to_platform_device(musb->controller); 1087 1088 /* dma address for async dma */ 1089 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1090 musb->async = mem->start; 1091 1092 /* dma address for sync dma */ 1093 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1094 if (!mem) { 1095 pr_debug("no sync dma resource?\n"); 1096 ret = -ENODEV; 1097 goto done; 1098 } 1099 musb->sync = mem->start; 1100 1101 sync = ioremap(mem->start, resource_size(mem)); 1102 if (!sync) { 1103 pr_debug("ioremap for sync failed\n"); 1104 ret = -ENOMEM; 1105 goto done; 1106 } 1107 musb->sync_va = sync; 1108 1109 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400, 1110 * FIFOs at 0x600, TUSB at 0x800 1111 */ 1112 musb->mregs += TUSB_BASE_OFFSET; 1113 1114 ret = tusb_musb_start(musb); 1115 if (ret) { 1116 printk(KERN_ERR "Could not start tusb6010 (%d)\n", 1117 ret); 1118 goto done; 1119 } 1120 musb->isr = tusb_musb_interrupt; 1121 1122 if (is_peripheral_enabled(musb)) { 1123 musb->xceiv->set_power = tusb_draw_power; 1124 the_musb = musb; 1125 } 1126 1127 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); 1128 1129 done: 1130 if (ret < 0) { 1131 if (sync) 1132 iounmap(sync); 1133 1134 usb_put_phy(musb->xceiv); 1135 usb_nop_xceiv_unregister(); 1136 } 1137 return ret; 1138 } 1139 1140 static int tusb_musb_exit(struct musb *musb) 1141 { 1142 del_timer_sync(&musb_idle_timer); 1143 the_musb = NULL; 1144 1145 if (musb->board_set_power) 1146 musb->board_set_power(0); 1147 1148 iounmap(musb->sync_va); 1149 1150 usb_put_phy(musb->xceiv); 1151 usb_nop_xceiv_unregister(); 1152 return 0; 1153 } 1154 1155 static const struct musb_platform_ops tusb_ops = { 1156 .init = tusb_musb_init, 1157 .exit = tusb_musb_exit, 1158 1159 .enable = tusb_musb_enable, 1160 .disable = tusb_musb_disable, 1161 1162 .set_mode = tusb_musb_set_mode, 1163 .try_idle = tusb_musb_try_idle, 1164 1165 .vbus_status = tusb_musb_vbus_status, 1166 .set_vbus = tusb_musb_set_vbus, 1167 }; 1168 1169 static u64 tusb_dmamask = DMA_BIT_MASK(32); 1170 1171 static int __devinit tusb_probe(struct platform_device *pdev) 1172 { 1173 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; 1174 struct platform_device *musb; 1175 struct tusb6010_glue *glue; 1176 1177 int ret = -ENOMEM; 1178 1179 glue = kzalloc(sizeof(*glue), GFP_KERNEL); 1180 if (!glue) { 1181 dev_err(&pdev->dev, "failed to allocate glue context\n"); 1182 goto err0; 1183 } 1184 1185 musb = platform_device_alloc("musb-hdrc", -1); 1186 if (!musb) { 1187 dev_err(&pdev->dev, "failed to allocate musb device\n"); 1188 goto err1; 1189 } 1190 1191 musb->dev.parent = &pdev->dev; 1192 musb->dev.dma_mask = &tusb_dmamask; 1193 musb->dev.coherent_dma_mask = tusb_dmamask; 1194 1195 glue->dev = &pdev->dev; 1196 glue->musb = musb; 1197 1198 pdata->platform_ops = &tusb_ops; 1199 1200 platform_set_drvdata(pdev, glue); 1201 1202 ret = platform_device_add_resources(musb, pdev->resource, 1203 pdev->num_resources); 1204 if (ret) { 1205 dev_err(&pdev->dev, "failed to add resources\n"); 1206 goto err2; 1207 } 1208 1209 ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); 1210 if (ret) { 1211 dev_err(&pdev->dev, "failed to add platform_data\n"); 1212 goto err2; 1213 } 1214 1215 ret = platform_device_add(musb); 1216 if (ret) { 1217 dev_err(&pdev->dev, "failed to register musb device\n"); 1218 goto err1; 1219 } 1220 1221 return 0; 1222 1223 err2: 1224 platform_device_put(musb); 1225 1226 err1: 1227 kfree(glue); 1228 1229 err0: 1230 return ret; 1231 } 1232 1233 static int __devexit tusb_remove(struct platform_device *pdev) 1234 { 1235 struct tusb6010_glue *glue = platform_get_drvdata(pdev); 1236 1237 platform_device_del(glue->musb); 1238 platform_device_put(glue->musb); 1239 kfree(glue); 1240 1241 return 0; 1242 } 1243 1244 static struct platform_driver tusb_driver = { 1245 .probe = tusb_probe, 1246 .remove = __devexit_p(tusb_remove), 1247 .driver = { 1248 .name = "musb-tusb", 1249 }, 1250 }; 1251 1252 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer"); 1253 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1254 MODULE_LICENSE("GPL v2"); 1255 1256 static int __init tusb_init(void) 1257 { 1258 return platform_driver_register(&tusb_driver); 1259 } 1260 module_init(tusb_init); 1261 1262 static void __exit tusb_exit(void) 1263 { 1264 platform_driver_unregister(&tusb_driver); 1265 } 1266 module_exit(tusb_exit); 1267