1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TUSB6010 USB 2.0 OTG Dual Role controller 4 * 5 * Copyright (C) 2006 Nokia Corporation 6 * Tony Lindgren <tony@atomide.com> 7 * 8 * Notes: 9 * - Driver assumes that interface to external host (main CPU) is 10 * configured for NOR FLASH interface instead of VLYNQ serial 11 * interface. 12 */ 13 14 #include <linux/gpio/consumer.h> 15 #include <linux/delay.h> 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/errno.h> 19 #include <linux/err.h> 20 #include <linux/prefetch.h> 21 #include <linux/usb.h> 22 #include <linux/irq.h> 23 #include <linux/io.h> 24 #include <linux/device.h> 25 #include <linux/platform_device.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/usb/usb_phy_generic.h> 28 29 #include "musb_core.h" 30 31 struct tusb6010_glue { 32 struct device *dev; 33 struct platform_device *musb; 34 struct platform_device *phy; 35 struct gpio_desc *enable; 36 struct gpio_desc *intpin; 37 }; 38 39 static void tusb_musb_set_vbus(struct musb *musb, int is_on); 40 41 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) 42 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) 43 44 /* 45 * Checks the revision. We need to use the DMA register as 3.0 does not 46 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. 47 */ 48 static u8 tusb_get_revision(struct musb *musb) 49 { 50 void __iomem *tbase = musb->ctrl_base; 51 u32 die_id; 52 u8 rev; 53 54 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff; 55 if (TUSB_REV_MAJOR(rev) == 3) { 56 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, 57 TUSB_DIDR1_HI)); 58 if (die_id >= TUSB_DIDR1_HI_REV_31) 59 rev |= 1; 60 } 61 62 return rev; 63 } 64 65 static void tusb_print_revision(struct musb *musb) 66 { 67 void __iomem *tbase = musb->ctrl_base; 68 u8 rev; 69 70 rev = musb->tusb_revision; 71 72 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n", 73 "prcm", 74 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)), 75 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)), 76 "int", 77 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 78 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), 79 "gpio", 80 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)), 81 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)), 82 "dma", 83 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 84 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), 85 "dieid", 86 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)), 87 "rev", 88 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev)); 89 } 90 91 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \ 92 | TUSB_PHY_OTG_CTRL_TESTM0) 93 94 /* 95 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0. 96 * Disables power detection in PHY for the duration of idle. 97 */ 98 static void tusb_wbus_quirk(struct musb *musb, int enabled) 99 { 100 void __iomem *tbase = musb->ctrl_base; 101 static u32 phy_otg_ctrl, phy_otg_ena; 102 u32 tmp; 103 104 if (enabled) { 105 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 106 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 107 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT 108 | phy_otg_ena | WBUS_QUIRK_MASK; 109 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 110 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; 111 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; 112 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 113 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", 114 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 115 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 116 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) 117 & TUSB_PHY_OTG_CTRL_TESTM2) { 118 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl; 119 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); 120 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; 121 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); 122 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", 123 musb_readl(tbase, TUSB_PHY_OTG_CTRL), 124 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); 125 phy_otg_ctrl = 0; 126 phy_otg_ena = 0; 127 } 128 } 129 130 static u32 tusb_fifo_offset(u8 epnum) 131 { 132 return 0x200 + (epnum * 0x20); 133 } 134 135 static u32 tusb_ep_offset(u8 epnum, u16 offset) 136 { 137 return 0x10 + offset; 138 } 139 140 /* TUSB mapping: "flat" plus ep0 special cases */ 141 static void tusb_ep_select(void __iomem *mbase, u8 epnum) 142 { 143 musb_writeb(mbase, MUSB_INDEX, epnum); 144 } 145 146 /* 147 * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum. 148 */ 149 static u8 tusb_readb(void __iomem *addr, u32 offset) 150 { 151 u16 tmp; 152 u8 val; 153 154 tmp = __raw_readw(addr + (offset & ~1)); 155 if (offset & 1) 156 val = (tmp >> 8); 157 else 158 val = tmp & 0xff; 159 160 return val; 161 } 162 163 static void tusb_writeb(void __iomem *addr, u32 offset, u8 data) 164 { 165 u16 tmp; 166 167 tmp = __raw_readw(addr + (offset & ~1)); 168 if (offset & 1) 169 tmp = (data << 8) | (tmp & 0xff); 170 else 171 tmp = (tmp & 0xff00) | data; 172 173 __raw_writew(tmp, addr + (offset & ~1)); 174 } 175 176 /* 177 * TUSB 6010 may use a parallel bus that doesn't support byte ops; 178 * so both loading and unloading FIFOs need explicit byte counts. 179 */ 180 181 static inline void 182 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len) 183 { 184 u32 val; 185 int i; 186 187 if (len > 4) { 188 for (i = 0; i < (len >> 2); i++) { 189 memcpy(&val, buf, 4); 190 musb_writel(fifo, 0, val); 191 buf += 4; 192 } 193 len %= 4; 194 } 195 if (len > 0) { 196 /* Write the rest 1 - 3 bytes to FIFO */ 197 val = 0; 198 memcpy(&val, buf, len); 199 musb_writel(fifo, 0, val); 200 } 201 } 202 203 static inline void tusb_fifo_read_unaligned(void __iomem *fifo, 204 void *buf, u16 len) 205 { 206 u32 val; 207 int i; 208 209 if (len > 4) { 210 for (i = 0; i < (len >> 2); i++) { 211 val = musb_readl(fifo, 0); 212 memcpy(buf, &val, 4); 213 buf += 4; 214 } 215 len %= 4; 216 } 217 if (len > 0) { 218 /* Read the rest 1 - 3 bytes from FIFO */ 219 val = musb_readl(fifo, 0); 220 memcpy(buf, &val, len); 221 } 222 } 223 224 static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) 225 { 226 struct musb *musb = hw_ep->musb; 227 void __iomem *ep_conf = hw_ep->conf; 228 void __iomem *fifo = hw_ep->fifo; 229 u8 epnum = hw_ep->epnum; 230 231 prefetch(buf); 232 233 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 234 'T', epnum, fifo, len, buf); 235 236 if (epnum) 237 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 238 TUSB_EP_CONFIG_XFR_SIZE(len)); 239 else 240 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX | 241 TUSB_EP0_CONFIG_XFR_SIZE(len)); 242 243 if (likely((0x01 & (unsigned long) buf) == 0)) { 244 245 /* Best case is 32bit-aligned destination address */ 246 if ((0x02 & (unsigned long) buf) == 0) { 247 if (len >= 4) { 248 iowrite32_rep(fifo, buf, len >> 2); 249 buf += (len & ~0x03); 250 len &= 0x03; 251 } 252 } else { 253 if (len >= 2) { 254 u32 val; 255 int i; 256 257 /* Cannot use writesw, fifo is 32-bit */ 258 for (i = 0; i < (len >> 2); i++) { 259 val = (u32)(*(u16 *)buf); 260 buf += 2; 261 val |= (*(u16 *)buf) << 16; 262 buf += 2; 263 musb_writel(fifo, 0, val); 264 } 265 len &= 0x03; 266 } 267 } 268 } 269 270 if (len > 0) 271 tusb_fifo_write_unaligned(fifo, buf, len); 272 } 273 274 static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) 275 { 276 struct musb *musb = hw_ep->musb; 277 void __iomem *ep_conf = hw_ep->conf; 278 void __iomem *fifo = hw_ep->fifo; 279 u8 epnum = hw_ep->epnum; 280 281 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", 282 'R', epnum, fifo, len, buf); 283 284 if (epnum) 285 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 286 TUSB_EP_CONFIG_XFR_SIZE(len)); 287 else 288 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len)); 289 290 if (likely((0x01 & (unsigned long) buf) == 0)) { 291 292 /* Best case is 32bit-aligned destination address */ 293 if ((0x02 & (unsigned long) buf) == 0) { 294 if (len >= 4) { 295 ioread32_rep(fifo, buf, len >> 2); 296 buf += (len & ~0x03); 297 len &= 0x03; 298 } 299 } else { 300 if (len >= 2) { 301 u32 val; 302 int i; 303 304 /* Cannot use readsw, fifo is 32-bit */ 305 for (i = 0; i < (len >> 2); i++) { 306 val = musb_readl(fifo, 0); 307 *(u16 *)buf = (u16)(val & 0xffff); 308 buf += 2; 309 *(u16 *)buf = (u16)(val >> 16); 310 buf += 2; 311 } 312 len &= 0x03; 313 } 314 } 315 } 316 317 if (len > 0) 318 tusb_fifo_read_unaligned(fifo, buf, len); 319 } 320 321 static struct musb *the_musb; 322 323 /* This is used by gadget drivers, and OTG transceiver logic, allowing 324 * at most mA current to be drawn from VBUS during a Default-B session 325 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host 326 * mode), or low power Default-B sessions, something else supplies power. 327 * Caller must take care of locking. 328 */ 329 static int tusb_draw_power(struct usb_phy *x, unsigned mA) 330 { 331 struct musb *musb = the_musb; 332 void __iomem *tbase = musb->ctrl_base; 333 u32 reg; 334 335 /* tps65030 seems to consume max 100mA, with maybe 60mA available 336 * (measured on one board) for things other than tps and tusb. 337 * 338 * Boards sharing the CPU clock with CLKIN will need to prevent 339 * certain idle sleep states while the USB link is active. 340 * 341 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }. 342 * The actual current usage would be very board-specific. For now, 343 * it's simpler to just use an aggregate (also board-specific). 344 */ 345 if (x->otg->default_a || mA < (musb->min_power << 1)) 346 mA = 0; 347 348 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 349 if (mA) { 350 musb->is_bus_powered = 1; 351 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; 352 } else { 353 musb->is_bus_powered = 0; 354 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 355 } 356 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 357 358 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA); 359 return 0; 360 } 361 362 /* workaround for issue 13: change clock during chip idle 363 * (to be fixed in rev3 silicon) ... symptoms include disconnect 364 * or looping suspend/resume cycles 365 */ 366 static void tusb_set_clock_source(struct musb *musb, unsigned mode) 367 { 368 void __iomem *tbase = musb->ctrl_base; 369 u32 reg; 370 371 reg = musb_readl(tbase, TUSB_PRCM_CONF); 372 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); 373 374 /* 0 = refclk (clkin, XI) 375 * 1 = PHY 60 MHz (internal PLL) 376 * 2 = not supported 377 * 3 = what? 378 */ 379 if (mode > 0) 380 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); 381 382 musb_writel(tbase, TUSB_PRCM_CONF, reg); 383 384 /* FIXME tusb6010_platform_retime(mode == 0); */ 385 } 386 387 /* 388 * Idle TUSB6010 until next wake-up event; NOR access always wakes. 389 * Other code ensures that we idle unless we're connected _and_ the 390 * USB link is not suspended ... and tells us the relevant wakeup 391 * events. SW_EN for voltage is handled separately. 392 */ 393 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables) 394 { 395 void __iomem *tbase = musb->ctrl_base; 396 u32 reg; 397 398 if ((wakeup_enables & TUSB_PRCM_WBUS) 399 && (musb->tusb_revision == TUSB_REV_30)) 400 tusb_wbus_quirk(musb, 1); 401 402 tusb_set_clock_source(musb, 0); 403 404 wakeup_enables |= TUSB_PRCM_WNORCS; 405 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables); 406 407 /* REVISIT writeup of WID implies that if WID set and ID is grounded, 408 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared. 409 * Presumably that's mostly to save power, hence WID is immaterial ... 410 */ 411 412 reg = musb_readl(tbase, TUSB_PRCM_MNGMT); 413 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */ 414 if (is_host_active(musb)) { 415 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 416 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 417 } else { 418 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; 419 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 420 } 421 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; 422 musb_writel(tbase, TUSB_PRCM_MNGMT, reg); 423 424 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables); 425 } 426 427 /* 428 * Updates cable VBUS status. Caller must take care of locking. 429 */ 430 static int tusb_musb_vbus_status(struct musb *musb) 431 { 432 void __iomem *tbase = musb->ctrl_base; 433 u32 otg_stat, prcm_mngmt; 434 int ret = 0; 435 436 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 437 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT); 438 439 /* Temporarily enable VBUS detection if it was disabled for 440 * suspend mode. Unless it's enabled otg_stat and devctl will 441 * not show correct VBUS state. 442 */ 443 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) { 444 u32 tmp = prcm_mngmt; 445 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; 446 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp); 447 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 448 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt); 449 } 450 451 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) 452 ret = 1; 453 454 return ret; 455 } 456 457 static void musb_do_idle(struct timer_list *t) 458 { 459 struct musb *musb = from_timer(musb, t, dev_timer); 460 unsigned long flags; 461 462 spin_lock_irqsave(&musb->lock, flags); 463 464 switch (musb->xceiv->otg->state) { 465 case OTG_STATE_A_WAIT_BCON: 466 if ((musb->a_wait_bcon != 0) 467 && (musb->idle_timeout == 0 468 || time_after(jiffies, musb->idle_timeout))) { 469 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n", 470 usb_otg_state_string(musb->xceiv->otg->state)); 471 } 472 fallthrough; 473 case OTG_STATE_A_IDLE: 474 tusb_musb_set_vbus(musb, 0); 475 break; 476 default: 477 break; 478 } 479 480 if (!musb->is_active) { 481 u32 wakeups; 482 483 /* wait until hub_wq handles port change status */ 484 if (is_host_active(musb) && (musb->port1_status >> 16)) 485 goto done; 486 487 if (!musb->gadget_driver) { 488 wakeups = 0; 489 } else { 490 wakeups = TUSB_PRCM_WHOSTDISCON 491 | TUSB_PRCM_WBUS 492 | TUSB_PRCM_WVBUS; 493 wakeups |= TUSB_PRCM_WID; 494 } 495 tusb_allow_idle(musb, wakeups); 496 } 497 done: 498 spin_unlock_irqrestore(&musb->lock, flags); 499 } 500 501 /* 502 * Maybe put TUSB6010 into idle mode depending on USB link status, 503 * like "disconnected" or "suspended". We'll be woken out of it by 504 * connect, resume, or disconnect. 505 * 506 * Needs to be called as the last function everywhere where there is 507 * register access to TUSB6010 because of NOR flash wake-up. 508 * Caller should own controller spinlock. 509 * 510 * Delay because peripheral enables D+ pullup 3msec after SE0, and 511 * we don't want to treat that full speed J as a wakeup event. 512 * ... peripherals must draw only suspend current after 10 msec. 513 */ 514 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout) 515 { 516 unsigned long default_timeout = jiffies + msecs_to_jiffies(3); 517 static unsigned long last_timer; 518 519 if (timeout == 0) 520 timeout = default_timeout; 521 522 /* Never idle if active, or when VBUS timeout is not set as host */ 523 if (musb->is_active || ((musb->a_wait_bcon == 0) 524 && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) { 525 dev_dbg(musb->controller, "%s active, deleting timer\n", 526 usb_otg_state_string(musb->xceiv->otg->state)); 527 del_timer(&musb->dev_timer); 528 last_timer = jiffies; 529 return; 530 } 531 532 if (time_after(last_timer, timeout)) { 533 if (!timer_pending(&musb->dev_timer)) 534 last_timer = timeout; 535 else { 536 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n"); 537 return; 538 } 539 } 540 last_timer = timeout; 541 542 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n", 543 usb_otg_state_string(musb->xceiv->otg->state), 544 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 545 mod_timer(&musb->dev_timer, timeout); 546 } 547 548 /* ticks of 60 MHz clock */ 549 #define DEVCLOCK 60000000 550 #define OTG_TIMER_MS(msecs) ((msecs) \ 551 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \ 552 | TUSB_DEV_OTG_TIMER_ENABLE) \ 553 : 0) 554 555 static void tusb_musb_set_vbus(struct musb *musb, int is_on) 556 { 557 void __iomem *tbase = musb->ctrl_base; 558 u32 conf, prcm, timer; 559 u8 devctl; 560 struct usb_otg *otg = musb->xceiv->otg; 561 562 /* HDRC controls CPEN, but beware current surges during device 563 * connect. They can trigger transient overcurrent conditions 564 * that must be ignored. 565 */ 566 567 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT); 568 conf = musb_readl(tbase, TUSB_DEV_CONF); 569 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 570 571 if (is_on) { 572 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); 573 otg->default_a = 1; 574 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 575 devctl |= MUSB_DEVCTL_SESSION; 576 577 conf |= TUSB_DEV_CONF_USB_HOST_MODE; 578 MUSB_HST_MODE(musb); 579 } else { 580 u32 otg_stat; 581 582 timer = 0; 583 584 /* If ID pin is grounded, we want to be a_idle */ 585 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 586 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { 587 switch (musb->xceiv->otg->state) { 588 case OTG_STATE_A_WAIT_VRISE: 589 case OTG_STATE_A_WAIT_BCON: 590 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; 591 break; 592 case OTG_STATE_A_WAIT_VFALL: 593 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 594 break; 595 default: 596 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 597 } 598 musb->is_active = 0; 599 otg->default_a = 1; 600 MUSB_HST_MODE(musb); 601 } else { 602 musb->is_active = 0; 603 otg->default_a = 0; 604 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 605 MUSB_DEV_MODE(musb); 606 } 607 608 devctl &= ~MUSB_DEVCTL_SESSION; 609 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE; 610 } 611 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); 612 613 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm); 614 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer); 615 musb_writel(tbase, TUSB_DEV_CONF, conf); 616 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 617 618 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", 619 usb_otg_state_string(musb->xceiv->otg->state), 620 musb_readb(musb->mregs, MUSB_DEVCTL), 621 musb_readl(tbase, TUSB_DEV_OTG_STAT), 622 conf, prcm); 623 } 624 625 /* 626 * Sets the mode to OTG, peripheral or host by changing the ID detection. 627 * Caller must take care of locking. 628 * 629 * Note that if a mini-A cable is plugged in the ID line will stay down as 630 * the weak ID pull-up is not able to pull the ID up. 631 */ 632 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode) 633 { 634 void __iomem *tbase = musb->ctrl_base; 635 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf; 636 637 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 638 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 639 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 640 dev_conf = musb_readl(tbase, TUSB_DEV_CONF); 641 642 switch (musb_mode) { 643 644 case MUSB_HOST: /* Disable PHY ID detect, ground ID */ 645 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 646 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 647 dev_conf |= TUSB_DEV_CONF_ID_SEL; 648 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID; 649 break; 650 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */ 651 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 652 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 653 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 654 break; 655 case MUSB_OTG: /* Use PHY ID detection */ 656 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 657 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 658 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); 659 break; 660 661 default: 662 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode); 663 return -EINVAL; 664 } 665 666 musb_writel(tbase, TUSB_PHY_OTG_CTRL, 667 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl); 668 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, 669 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena); 670 musb_writel(tbase, TUSB_DEV_CONF, dev_conf); 671 672 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 673 if ((musb_mode == MUSB_PERIPHERAL) && 674 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) 675 INFO("Cannot be peripheral with mini-A cable " 676 "otg_stat: %08x\n", otg_stat); 677 678 return 0; 679 } 680 681 static inline unsigned long 682 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) 683 { 684 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); 685 unsigned long idle_timeout = 0; 686 struct usb_otg *otg = musb->xceiv->otg; 687 688 /* ID pin */ 689 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) { 690 int default_a; 691 692 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); 693 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B'); 694 otg->default_a = default_a; 695 tusb_musb_set_vbus(musb, default_a); 696 697 /* Don't allow idling immediately */ 698 if (default_a) 699 idle_timeout = jiffies + (HZ * 3); 700 } 701 702 /* VBUS state change */ 703 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { 704 705 /* B-dev state machine: no vbus ~= disconnect */ 706 if (!otg->default_a) { 707 /* ? musb_root_disconnect(musb); */ 708 musb->port1_status &= 709 ~(USB_PORT_STAT_CONNECTION 710 | USB_PORT_STAT_ENABLE 711 | USB_PORT_STAT_LOW_SPEED 712 | USB_PORT_STAT_HIGH_SPEED 713 | USB_PORT_STAT_TEST 714 ); 715 716 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { 717 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n"); 718 if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) { 719 /* INTR_DISCONNECT can hide... */ 720 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 721 musb->int_usb |= MUSB_INTR_DISCONNECT; 722 } 723 musb->is_active = 0; 724 } 725 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", 726 usb_otg_state_string(musb->xceiv->otg->state), otg_stat); 727 idle_timeout = jiffies + (1 * HZ); 728 schedule_delayed_work(&musb->irq_work, 0); 729 730 } else /* A-dev state machine */ { 731 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", 732 usb_otg_state_string(musb->xceiv->otg->state), otg_stat); 733 734 switch (musb->xceiv->otg->state) { 735 case OTG_STATE_A_IDLE: 736 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n"); 737 musb_platform_set_vbus(musb, 1); 738 739 /* CONNECT can wake if a_wait_bcon is set */ 740 if (musb->a_wait_bcon != 0) 741 musb->is_active = 0; 742 else 743 musb->is_active = 1; 744 745 /* 746 * OPT FS A TD.4.6 needs few seconds for 747 * A_WAIT_VRISE 748 */ 749 idle_timeout = jiffies + (2 * HZ); 750 751 break; 752 case OTG_STATE_A_WAIT_VRISE: 753 /* ignore; A-session-valid < VBUS_VALID/2, 754 * we monitor this with the timer 755 */ 756 break; 757 case OTG_STATE_A_WAIT_VFALL: 758 /* REVISIT this irq triggers during short 759 * spikes caused by enumeration ... 760 */ 761 if (musb->vbuserr_retry) { 762 musb->vbuserr_retry--; 763 tusb_musb_set_vbus(musb, 1); 764 } else { 765 musb->vbuserr_retry 766 = VBUSERR_RETRY_COUNT; 767 tusb_musb_set_vbus(musb, 0); 768 } 769 break; 770 default: 771 break; 772 } 773 } 774 } 775 776 /* OTG timer expiration */ 777 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { 778 u8 devctl; 779 780 dev_dbg(musb->controller, "%s timer, %03x\n", 781 usb_otg_state_string(musb->xceiv->otg->state), otg_stat); 782 783 switch (musb->xceiv->otg->state) { 784 case OTG_STATE_A_WAIT_VRISE: 785 /* VBUS has probably been valid for a while now, 786 * but may well have bounced out of range a bit 787 */ 788 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 789 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { 790 if ((devctl & MUSB_DEVCTL_VBUS) 791 != MUSB_DEVCTL_VBUS) { 792 dev_dbg(musb->controller, "devctl %02x\n", devctl); 793 break; 794 } 795 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; 796 musb->is_active = 0; 797 idle_timeout = jiffies 798 + msecs_to_jiffies(musb->a_wait_bcon); 799 } else { 800 /* REVISIT report overcurrent to hub? */ 801 ERR("vbus too slow, devctl %02x\n", devctl); 802 tusb_musb_set_vbus(musb, 0); 803 } 804 break; 805 case OTG_STATE_A_WAIT_BCON: 806 if (musb->a_wait_bcon != 0) 807 idle_timeout = jiffies 808 + msecs_to_jiffies(musb->a_wait_bcon); 809 break; 810 case OTG_STATE_A_SUSPEND: 811 break; 812 case OTG_STATE_B_WAIT_ACON: 813 break; 814 default: 815 break; 816 } 817 } 818 schedule_delayed_work(&musb->irq_work, 0); 819 820 return idle_timeout; 821 } 822 823 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci) 824 { 825 struct musb *musb = __hci; 826 void __iomem *tbase = musb->ctrl_base; 827 unsigned long flags, idle_timeout = 0; 828 u32 int_mask, int_src; 829 830 spin_lock_irqsave(&musb->lock, flags); 831 832 /* Mask all interrupts to allow using both edge and level GPIO irq */ 833 int_mask = musb_readl(tbase, TUSB_INT_MASK); 834 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 835 836 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; 837 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src); 838 839 musb->int_usb = (u8) int_src; 840 841 /* Acknowledge wake-up source interrupts */ 842 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) { 843 u32 reg; 844 u32 i; 845 846 if (musb->tusb_revision == TUSB_REV_30) 847 tusb_wbus_quirk(musb, 0); 848 849 /* there are issues re-locking the PLL on wakeup ... */ 850 851 /* work around issue 8 */ 852 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) { 853 musb_writel(tbase, TUSB_SCRATCH_PAD, 0); 854 musb_writel(tbase, TUSB_SCRATCH_PAD, i); 855 reg = musb_readl(tbase, TUSB_SCRATCH_PAD); 856 if (reg == i) 857 break; 858 dev_dbg(musb->controller, "TUSB NOR not ready\n"); 859 } 860 861 /* work around issue 13 (2nd half) */ 862 tusb_set_clock_source(musb, 1); 863 864 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE); 865 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); 866 if (reg & ~TUSB_PRCM_WNORCS) { 867 musb->is_active = 1; 868 schedule_delayed_work(&musb->irq_work, 0); 869 } 870 dev_dbg(musb->controller, "wake %sactive %02x\n", 871 musb->is_active ? "" : "in", reg); 872 873 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ 874 } 875 876 if (int_src & TUSB_INT_SRC_USB_IP_CONN) 877 del_timer(&musb->dev_timer); 878 879 /* OTG state change reports (annoyingly) not issued by Mentor core */ 880 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG 881 | TUSB_INT_SRC_OTG_TIMEOUT 882 | TUSB_INT_SRC_ID_STATUS_CHNG)) 883 idle_timeout = tusb_otg_ints(musb, int_src, tbase); 884 885 /* 886 * Just clear the DMA interrupt if it comes as the completion for both 887 * TX and RX is handled by the DMA callback in tusb6010_omap 888 */ 889 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) { 890 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); 891 892 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src); 893 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src); 894 } 895 896 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */ 897 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) { 898 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC); 899 900 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src); 901 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1); 902 musb->int_tx = (musb_src & 0xffff); 903 } else { 904 musb->int_rx = 0; 905 musb->int_tx = 0; 906 } 907 908 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff)) 909 musb_interrupt(musb); 910 911 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */ 912 musb_writel(tbase, TUSB_INT_SRC_CLEAR, 913 int_src & ~TUSB_INT_MASK_RESERVED_BITS); 914 915 tusb_musb_try_idle(musb, idle_timeout); 916 917 musb_writel(tbase, TUSB_INT_MASK, int_mask); 918 spin_unlock_irqrestore(&musb->lock, flags); 919 920 return IRQ_HANDLED; 921 } 922 923 static int dma_off; 924 925 /* 926 * Enables TUSB6010. Caller must take care of locking. 927 * REVISIT: 928 * - Check what is unnecessary in MGC_HdrcStart() 929 */ 930 static void tusb_musb_enable(struct musb *musb) 931 { 932 void __iomem *tbase = musb->ctrl_base; 933 934 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF. 935 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */ 936 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF); 937 938 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */ 939 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0); 940 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 941 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 942 943 /* Clear all subsystem interrups */ 944 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff); 945 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff); 946 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff); 947 948 /* Acknowledge pending interrupt(s) */ 949 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS); 950 951 /* Only 0 clock cycles for minimum interrupt de-assertion time and 952 * interrupt polarity active low seems to work reliably here */ 953 musb_writel(tbase, TUSB_INT_CTRL_CONF, 954 TUSB_INT_CTRL_CONF_INT_RELCYC(0)); 955 956 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW); 957 958 /* maybe force into the Default-A OTG state machine */ 959 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT) 960 & TUSB_DEV_OTG_STAT_ID_STATUS)) 961 musb_writel(tbase, TUSB_INT_SRC_SET, 962 TUSB_INT_SRC_ID_STATUS_CHNG); 963 964 if (is_dma_capable() && dma_off) 965 printk(KERN_WARNING "%s %s: dma not reactivated\n", 966 __FILE__, __func__); 967 else 968 dma_off = 1; 969 } 970 971 /* 972 * Disables TUSB6010. Caller must take care of locking. 973 */ 974 static void tusb_musb_disable(struct musb *musb) 975 { 976 void __iomem *tbase = musb->ctrl_base; 977 978 /* FIXME stop DMA, IRQs, timers, ... */ 979 980 /* disable all IRQs */ 981 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); 982 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff); 983 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); 984 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); 985 986 del_timer(&musb->dev_timer); 987 988 if (is_dma_capable() && !dma_off) { 989 printk(KERN_WARNING "%s %s: dma still active\n", 990 __FILE__, __func__); 991 dma_off = 1; 992 } 993 } 994 995 /* 996 * Sets up TUSB6010 CPU interface specific signals and registers 997 * Note: Settings optimized for OMAP24xx 998 */ 999 static void tusb_setup_cpu_interface(struct musb *musb) 1000 { 1001 void __iomem *tbase = musb->ctrl_base; 1002 1003 /* 1004 * Disable GPIO[5:0] pullups (used as output DMA requests) 1005 * Don't disable GPIO[7:6] as they are needed for wake-up. 1006 */ 1007 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F); 1008 1009 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */ 1010 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF); 1011 1012 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */ 1013 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f)); 1014 1015 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request 1016 * de-assertion time 2 system clocks p 62 */ 1017 musb_writel(tbase, TUSB_DMA_REQ_CONF, 1018 TUSB_DMA_REQ_CONF_BURST_SIZE(2) | 1019 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | 1020 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 1021 1022 /* Set 0 wait count for synchronous burst access */ 1023 musb_writel(tbase, TUSB_WAIT_COUNT, 1); 1024 } 1025 1026 static int tusb_musb_start(struct musb *musb) 1027 { 1028 struct tusb6010_glue *glue = dev_get_drvdata(musb->controller->parent); 1029 void __iomem *tbase = musb->ctrl_base; 1030 unsigned long flags; 1031 u32 reg; 1032 int i; 1033 1034 /* 1035 * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and 1036 * 1.5 V voltage regulators of PM companion chip. Companion chip will then 1037 * provide then PGOOD signal to TUSB6010 which will release it from reset. 1038 */ 1039 gpiod_set_value(glue->enable, 1); 1040 msleep(1); 1041 1042 /* Wait for 100ms until TUSB6010 pulls INT pin down */ 1043 i = 100; 1044 while (i && gpiod_get_value(glue->intpin)) { 1045 msleep(1); 1046 i--; 1047 } 1048 if (!i) { 1049 pr_err("tusb: Powerup respones failed\n"); 1050 return -ENODEV; 1051 } 1052 1053 spin_lock_irqsave(&musb->lock, flags); 1054 1055 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) != 1056 TUSB_PROD_TEST_RESET_VAL) { 1057 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n"); 1058 goto err; 1059 } 1060 1061 musb->tusb_revision = tusb_get_revision(musb); 1062 tusb_print_revision(musb); 1063 if (musb->tusb_revision < 2) { 1064 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n", 1065 musb->tusb_revision); 1066 goto err; 1067 } 1068 1069 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when 1070 * NOR FLASH interface is used */ 1071 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8); 1072 1073 /* Select PHY free running 60MHz as a system clock */ 1074 tusb_set_clock_source(musb, 1); 1075 1076 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for 1077 * power saving, enable VBus detect and session end comparators, 1078 * enable IDpullup, enable VBus charging */ 1079 musb_writel(tbase, TUSB_PRCM_MNGMT, 1080 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) | 1081 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN | 1082 TUSB_PRCM_MNGMT_OTG_SESS_END_EN | 1083 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN | 1084 TUSB_PRCM_MNGMT_OTG_ID_PULLUP); 1085 tusb_setup_cpu_interface(musb); 1086 1087 /* simplify: always sense/pullup ID pins, as if in OTG mode */ 1088 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); 1089 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1090 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg); 1091 1092 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL); 1093 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; 1094 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg); 1095 1096 spin_unlock_irqrestore(&musb->lock, flags); 1097 1098 return 0; 1099 1100 err: 1101 spin_unlock_irqrestore(&musb->lock, flags); 1102 1103 gpiod_set_value(glue->enable, 0); 1104 msleep(10); 1105 1106 return -ENODEV; 1107 } 1108 1109 static int tusb_musb_init(struct musb *musb) 1110 { 1111 struct platform_device *pdev; 1112 struct resource *mem; 1113 void __iomem *sync = NULL; 1114 int ret; 1115 1116 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); 1117 if (IS_ERR_OR_NULL(musb->xceiv)) 1118 return -EPROBE_DEFER; 1119 1120 pdev = to_platform_device(musb->controller); 1121 1122 /* dma address for async dma */ 1123 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1124 if (!mem) { 1125 pr_debug("no async dma resource?\n"); 1126 ret = -ENODEV; 1127 goto done; 1128 } 1129 musb->async = mem->start; 1130 1131 /* dma address for sync dma */ 1132 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1133 if (!mem) { 1134 pr_debug("no sync dma resource?\n"); 1135 ret = -ENODEV; 1136 goto done; 1137 } 1138 musb->sync = mem->start; 1139 1140 sync = ioremap(mem->start, resource_size(mem)); 1141 if (!sync) { 1142 pr_debug("ioremap for sync failed\n"); 1143 ret = -ENOMEM; 1144 goto done; 1145 } 1146 musb->sync_va = sync; 1147 1148 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400, 1149 * FIFOs at 0x600, TUSB at 0x800 1150 */ 1151 musb->mregs += TUSB_BASE_OFFSET; 1152 1153 ret = tusb_musb_start(musb); 1154 if (ret) { 1155 printk(KERN_ERR "Could not start tusb6010 (%d)\n", 1156 ret); 1157 goto done; 1158 } 1159 musb->isr = tusb_musb_interrupt; 1160 1161 musb->xceiv->set_power = tusb_draw_power; 1162 the_musb = musb; 1163 1164 timer_setup(&musb->dev_timer, musb_do_idle, 0); 1165 1166 done: 1167 if (ret < 0) { 1168 if (sync) 1169 iounmap(sync); 1170 1171 usb_put_phy(musb->xceiv); 1172 } 1173 return ret; 1174 } 1175 1176 static int tusb_musb_exit(struct musb *musb) 1177 { 1178 struct tusb6010_glue *glue = dev_get_drvdata(musb->controller->parent); 1179 1180 del_timer_sync(&musb->dev_timer); 1181 the_musb = NULL; 1182 1183 gpiod_set_value(glue->enable, 0); 1184 msleep(10); 1185 1186 iounmap(musb->sync_va); 1187 1188 usb_put_phy(musb->xceiv); 1189 return 0; 1190 } 1191 1192 static const struct musb_platform_ops tusb_ops = { 1193 .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB | 1194 MUSB_G_NO_SKB_RESERVE, 1195 .init = tusb_musb_init, 1196 .exit = tusb_musb_exit, 1197 1198 .ep_offset = tusb_ep_offset, 1199 .ep_select = tusb_ep_select, 1200 .fifo_offset = tusb_fifo_offset, 1201 .readb = tusb_readb, 1202 .writeb = tusb_writeb, 1203 .read_fifo = tusb_read_fifo, 1204 .write_fifo = tusb_write_fifo, 1205 #ifdef CONFIG_USB_TUSB_OMAP_DMA 1206 .dma_init = tusb_dma_controller_create, 1207 .dma_exit = tusb_dma_controller_destroy, 1208 #endif 1209 .enable = tusb_musb_enable, 1210 .disable = tusb_musb_disable, 1211 1212 .set_mode = tusb_musb_set_mode, 1213 .try_idle = tusb_musb_try_idle, 1214 1215 .vbus_status = tusb_musb_vbus_status, 1216 .set_vbus = tusb_musb_set_vbus, 1217 }; 1218 1219 static const struct platform_device_info tusb_dev_info = { 1220 .name = "musb-hdrc", 1221 .id = PLATFORM_DEVID_AUTO, 1222 .dma_mask = DMA_BIT_MASK(32), 1223 }; 1224 1225 static int tusb_probe(struct platform_device *pdev) 1226 { 1227 struct resource musb_resources[3]; 1228 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); 1229 struct platform_device *musb; 1230 struct tusb6010_glue *glue; 1231 struct platform_device_info pinfo; 1232 int ret; 1233 1234 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 1235 if (!glue) 1236 return -ENOMEM; 1237 1238 glue->dev = &pdev->dev; 1239 1240 glue->enable = devm_gpiod_get(glue->dev, "enable", GPIOD_OUT_LOW); 1241 if (IS_ERR(glue->enable)) 1242 return dev_err_probe(glue->dev, PTR_ERR(glue->enable), 1243 "could not obtain power on/off GPIO\n"); 1244 glue->intpin = devm_gpiod_get(glue->dev, "int", GPIOD_IN); 1245 if (IS_ERR(glue->intpin)) 1246 return dev_err_probe(glue->dev, PTR_ERR(glue->intpin), 1247 "could not obtain INT GPIO\n"); 1248 1249 pdata->platform_ops = &tusb_ops; 1250 1251 usb_phy_generic_register(); 1252 platform_set_drvdata(pdev, glue); 1253 1254 memset(musb_resources, 0x00, sizeof(*musb_resources) * 1255 ARRAY_SIZE(musb_resources)); 1256 1257 musb_resources[0].name = pdev->resource[0].name; 1258 musb_resources[0].start = pdev->resource[0].start; 1259 musb_resources[0].end = pdev->resource[0].end; 1260 musb_resources[0].flags = pdev->resource[0].flags; 1261 1262 musb_resources[1].name = pdev->resource[1].name; 1263 musb_resources[1].start = pdev->resource[1].start; 1264 musb_resources[1].end = pdev->resource[1].end; 1265 musb_resources[1].flags = pdev->resource[1].flags; 1266 1267 musb_resources[2] = DEFINE_RES_IRQ_NAMED(gpiod_to_irq(glue->intpin), "mc"); 1268 1269 pinfo = tusb_dev_info; 1270 pinfo.parent = &pdev->dev; 1271 pinfo.res = musb_resources; 1272 pinfo.num_res = ARRAY_SIZE(musb_resources); 1273 pinfo.data = pdata; 1274 pinfo.size_data = sizeof(*pdata); 1275 1276 glue->musb = musb = platform_device_register_full(&pinfo); 1277 if (IS_ERR(musb)) { 1278 ret = PTR_ERR(musb); 1279 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret); 1280 return ret; 1281 } 1282 1283 return 0; 1284 } 1285 1286 static void tusb_remove(struct platform_device *pdev) 1287 { 1288 struct tusb6010_glue *glue = platform_get_drvdata(pdev); 1289 1290 platform_device_unregister(glue->musb); 1291 usb_phy_generic_unregister(glue->phy); 1292 } 1293 1294 static struct platform_driver tusb_driver = { 1295 .probe = tusb_probe, 1296 .remove_new = tusb_remove, 1297 .driver = { 1298 .name = "musb-tusb", 1299 }, 1300 }; 1301 1302 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer"); 1303 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 1304 MODULE_LICENSE("GPL v2"); 1305 module_platform_driver(tusb_driver); 1306