1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Allwinner sun4i MUSB Glue Layer 4 * 5 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> 6 * 7 * Based on code from 8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/err.h> 13 #include <linux/extcon.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/phy/phy-sun4i-usb.h> 19 #include <linux/platform_device.h> 20 #include <linux/reset.h> 21 #include <linux/soc/sunxi/sunxi_sram.h> 22 #include <linux/usb/musb.h> 23 #include <linux/usb/of.h> 24 #include <linux/usb/usb_phy_generic.h> 25 #include <linux/workqueue.h> 26 #include "musb_core.h" 27 28 /* 29 * Register offsets, note sunxi musb has a different layout then most 30 * musb implementations, we translate the layout in musb_readb & friends. 31 */ 32 #define SUNXI_MUSB_POWER 0x0040 33 #define SUNXI_MUSB_DEVCTL 0x0041 34 #define SUNXI_MUSB_INDEX 0x0042 35 #define SUNXI_MUSB_VEND0 0x0043 36 #define SUNXI_MUSB_INTRTX 0x0044 37 #define SUNXI_MUSB_INTRRX 0x0046 38 #define SUNXI_MUSB_INTRTXE 0x0048 39 #define SUNXI_MUSB_INTRRXE 0x004a 40 #define SUNXI_MUSB_INTRUSB 0x004c 41 #define SUNXI_MUSB_INTRUSBE 0x0050 42 #define SUNXI_MUSB_FRAME 0x0054 43 #define SUNXI_MUSB_TXFIFOSZ 0x0090 44 #define SUNXI_MUSB_TXFIFOADD 0x0092 45 #define SUNXI_MUSB_RXFIFOSZ 0x0094 46 #define SUNXI_MUSB_RXFIFOADD 0x0096 47 #define SUNXI_MUSB_FADDR 0x0098 48 #define SUNXI_MUSB_TXFUNCADDR 0x0098 49 #define SUNXI_MUSB_TXHUBADDR 0x009a 50 #define SUNXI_MUSB_TXHUBPORT 0x009b 51 #define SUNXI_MUSB_RXFUNCADDR 0x009c 52 #define SUNXI_MUSB_RXHUBADDR 0x009e 53 #define SUNXI_MUSB_RXHUBPORT 0x009f 54 #define SUNXI_MUSB_CONFIGDATA 0x00c0 55 56 /* VEND0 bits */ 57 #define SUNXI_MUSB_VEND0_PIO_MODE 0 58 59 /* flags */ 60 #define SUNXI_MUSB_FL_ENABLED 0 61 #define SUNXI_MUSB_FL_HOSTMODE 1 62 #define SUNXI_MUSB_FL_HOSTMODE_PEND 2 63 #define SUNXI_MUSB_FL_VBUS_ON 3 64 #define SUNXI_MUSB_FL_PHY_ON 4 65 #define SUNXI_MUSB_FL_HAS_SRAM 5 66 #define SUNXI_MUSB_FL_HAS_RESET 6 67 #define SUNXI_MUSB_FL_NO_CONFIGDATA 7 68 #define SUNXI_MUSB_FL_PHY_MODE_PEND 8 69 70 /* Our read/write methods need access and do not get passed in a musb ref :| */ 71 static struct musb *sunxi_musb; 72 73 struct sunxi_glue { 74 struct device *dev; 75 struct musb *musb; 76 struct platform_device *musb_pdev; 77 struct clk *clk; 78 struct reset_control *rst; 79 struct phy *phy; 80 struct platform_device *usb_phy; 81 struct usb_phy *xceiv; 82 enum phy_mode phy_mode; 83 unsigned long flags; 84 struct work_struct work; 85 struct extcon_dev *extcon; 86 struct notifier_block host_nb; 87 }; 88 89 /* phy_power_on / off may sleep, so we use a workqueue */ 90 static void sunxi_musb_work(struct work_struct *work) 91 { 92 struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work); 93 bool vbus_on, phy_on; 94 95 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) 96 return; 97 98 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) { 99 struct musb *musb = glue->musb; 100 unsigned long flags; 101 u8 devctl; 102 103 spin_lock_irqsave(&musb->lock, flags); 104 105 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL); 106 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) { 107 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 108 musb->xceiv->otg->default_a = 1; 109 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 110 MUSB_HST_MODE(musb); 111 devctl |= MUSB_DEVCTL_SESSION; 112 } else { 113 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 114 musb->xceiv->otg->default_a = 0; 115 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 116 MUSB_DEV_MODE(musb); 117 devctl &= ~MUSB_DEVCTL_SESSION; 118 } 119 writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL); 120 121 spin_unlock_irqrestore(&musb->lock, flags); 122 } 123 124 vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 125 phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 126 127 if (phy_on != vbus_on) { 128 if (vbus_on) { 129 phy_power_on(glue->phy); 130 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 131 } else { 132 phy_power_off(glue->phy); 133 clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 134 } 135 } 136 137 if (test_and_clear_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags)) 138 phy_set_mode(glue->phy, glue->phy_mode); 139 } 140 141 static void sunxi_musb_set_vbus(struct musb *musb, int is_on) 142 { 143 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 144 145 if (is_on) { 146 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 147 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 148 } else { 149 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 150 } 151 152 schedule_work(&glue->work); 153 } 154 155 static void sunxi_musb_pre_root_reset_end(struct musb *musb) 156 { 157 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 158 159 sun4i_usb_phy_set_squelch_detect(glue->phy, false); 160 } 161 162 static void sunxi_musb_post_root_reset_end(struct musb *musb) 163 { 164 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 165 166 sun4i_usb_phy_set_squelch_detect(glue->phy, true); 167 } 168 169 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci) 170 { 171 struct musb *musb = __hci; 172 unsigned long flags; 173 174 spin_lock_irqsave(&musb->lock, flags); 175 176 musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB); 177 if (musb->int_usb) 178 writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB); 179 180 if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) { 181 /* ep0 FADDR must be 0 when (re)entering peripheral mode */ 182 musb_ep_select(musb->mregs, 0); 183 musb_writeb(musb->mregs, MUSB_FADDR, 0); 184 } 185 186 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX); 187 if (musb->int_tx) 188 writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX); 189 190 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX); 191 if (musb->int_rx) 192 writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX); 193 194 musb_interrupt(musb); 195 196 spin_unlock_irqrestore(&musb->lock, flags); 197 198 return IRQ_HANDLED; 199 } 200 201 static int sunxi_musb_host_notifier(struct notifier_block *nb, 202 unsigned long event, void *ptr) 203 { 204 struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb); 205 206 if (event) 207 set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); 208 else 209 clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); 210 211 set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags); 212 schedule_work(&glue->work); 213 214 return NOTIFY_DONE; 215 } 216 217 static int sunxi_musb_init(struct musb *musb) 218 { 219 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 220 int ret; 221 222 sunxi_musb = musb; 223 musb->phy = glue->phy; 224 musb->xceiv = glue->xceiv; 225 226 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) { 227 ret = sunxi_sram_claim(musb->controller->parent); 228 if (ret) 229 return ret; 230 } 231 232 ret = clk_prepare_enable(glue->clk); 233 if (ret) 234 goto error_sram_release; 235 236 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { 237 ret = reset_control_deassert(glue->rst); 238 if (ret) 239 goto error_clk_disable; 240 } 241 242 writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0); 243 244 /* Register notifier before calling phy_init() */ 245 ret = devm_extcon_register_notifier(glue->dev, glue->extcon, 246 EXTCON_USB_HOST, &glue->host_nb); 247 if (ret) 248 goto error_reset_assert; 249 250 ret = phy_init(glue->phy); 251 if (ret) 252 goto error_reset_assert; 253 254 musb->isr = sunxi_musb_interrupt; 255 256 /* Stop the musb-core from doing runtime pm (not supported on sunxi) */ 257 pm_runtime_get(musb->controller); 258 259 return 0; 260 261 error_reset_assert: 262 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) 263 reset_control_assert(glue->rst); 264 error_clk_disable: 265 clk_disable_unprepare(glue->clk); 266 error_sram_release: 267 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) 268 sunxi_sram_release(musb->controller->parent); 269 return ret; 270 } 271 272 static int sunxi_musb_exit(struct musb *musb) 273 { 274 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 275 276 pm_runtime_put(musb->controller); 277 278 cancel_work_sync(&glue->work); 279 if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags)) 280 phy_power_off(glue->phy); 281 282 phy_exit(glue->phy); 283 284 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) 285 reset_control_assert(glue->rst); 286 287 clk_disable_unprepare(glue->clk); 288 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) 289 sunxi_sram_release(musb->controller->parent); 290 291 devm_usb_put_phy(glue->dev, glue->xceiv); 292 293 return 0; 294 } 295 296 static void sunxi_musb_enable(struct musb *musb) 297 { 298 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 299 300 glue->musb = musb; 301 302 /* musb_core does not call us in a balanced manner */ 303 if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) 304 return; 305 306 schedule_work(&glue->work); 307 } 308 309 static void sunxi_musb_disable(struct musb *musb) 310 { 311 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 312 313 clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags); 314 } 315 316 static struct dma_controller * 317 sunxi_musb_dma_controller_create(struct musb *musb, void __iomem *base) 318 { 319 return NULL; 320 } 321 322 static void sunxi_musb_dma_controller_destroy(struct dma_controller *c) 323 { 324 } 325 326 static int sunxi_musb_set_mode(struct musb *musb, u8 mode) 327 { 328 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 329 enum phy_mode new_mode; 330 331 switch (mode) { 332 case MUSB_HOST: 333 new_mode = PHY_MODE_USB_HOST; 334 break; 335 case MUSB_PERIPHERAL: 336 new_mode = PHY_MODE_USB_DEVICE; 337 break; 338 case MUSB_OTG: 339 new_mode = PHY_MODE_USB_OTG; 340 break; 341 default: 342 dev_err(musb->controller->parent, 343 "Error requested mode not supported by this kernel\n"); 344 return -EINVAL; 345 } 346 347 if (glue->phy_mode == new_mode) 348 return 0; 349 350 if (musb->port_mode != MUSB_PORT_MODE_DUAL_ROLE) { 351 dev_err(musb->controller->parent, 352 "Error changing modes is only supported in dual role mode\n"); 353 return -EINVAL; 354 } 355 356 if (musb->port1_status & USB_PORT_STAT_ENABLE) 357 musb_root_disconnect(musb); 358 359 /* 360 * phy_set_mode may sleep, and we're called with a spinlock held, 361 * so let sunxi_musb_work deal with it. 362 */ 363 glue->phy_mode = new_mode; 364 set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags); 365 schedule_work(&glue->work); 366 367 return 0; 368 } 369 370 static int sunxi_musb_recover(struct musb *musb) 371 { 372 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 373 374 /* 375 * Schedule a phy_set_mode with the current glue->phy_mode value, 376 * this will force end the current session. 377 */ 378 set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags); 379 schedule_work(&glue->work); 380 381 return 0; 382 } 383 384 /* 385 * sunxi musb register layout 386 * 0x00 - 0x17 fifo regs, 1 long per fifo 387 * 0x40 - 0x57 generic control regs (power - frame) 388 * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed) 389 * 0x90 - 0x97 fifo control regs (indexed) 390 * 0x98 - 0x9f multipoint / busctl regs (indexed) 391 * 0xc0 configdata reg 392 */ 393 394 static u32 sunxi_musb_fifo_offset(u8 epnum) 395 { 396 return (epnum * 4); 397 } 398 399 static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset) 400 { 401 WARN_ONCE(offset != 0, 402 "sunxi_musb_ep_offset called with non 0 offset\n"); 403 404 return 0x80; /* indexed, so ignore epnum */ 405 } 406 407 static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset) 408 { 409 return SUNXI_MUSB_TXFUNCADDR + offset; 410 } 411 412 static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset) 413 { 414 struct sunxi_glue *glue; 415 416 if (addr == sunxi_musb->mregs) { 417 /* generic control or fifo control reg access */ 418 switch (offset) { 419 case MUSB_FADDR: 420 return readb(addr + SUNXI_MUSB_FADDR); 421 case MUSB_POWER: 422 return readb(addr + SUNXI_MUSB_POWER); 423 case MUSB_INTRUSB: 424 return readb(addr + SUNXI_MUSB_INTRUSB); 425 case MUSB_INTRUSBE: 426 return readb(addr + SUNXI_MUSB_INTRUSBE); 427 case MUSB_INDEX: 428 return readb(addr + SUNXI_MUSB_INDEX); 429 case MUSB_TESTMODE: 430 return 0; /* No testmode on sunxi */ 431 case MUSB_DEVCTL: 432 return readb(addr + SUNXI_MUSB_DEVCTL); 433 case MUSB_TXFIFOSZ: 434 return readb(addr + SUNXI_MUSB_TXFIFOSZ); 435 case MUSB_RXFIFOSZ: 436 return readb(addr + SUNXI_MUSB_RXFIFOSZ); 437 case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */ 438 glue = dev_get_drvdata(sunxi_musb->controller->parent); 439 /* A33 saves a reg, and we get to hardcode this */ 440 if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, 441 &glue->flags)) 442 return 0xde; 443 444 return readb(addr + SUNXI_MUSB_CONFIGDATA); 445 /* Offset for these is fixed by sunxi_musb_busctl_offset() */ 446 case SUNXI_MUSB_TXFUNCADDR: 447 case SUNXI_MUSB_TXHUBADDR: 448 case SUNXI_MUSB_TXHUBPORT: 449 case SUNXI_MUSB_RXFUNCADDR: 450 case SUNXI_MUSB_RXHUBADDR: 451 case SUNXI_MUSB_RXHUBPORT: 452 /* multipoint / busctl reg access */ 453 return readb(addr + offset); 454 default: 455 dev_err(sunxi_musb->controller->parent, 456 "Error unknown readb offset %u\n", offset); 457 return 0; 458 } 459 } else if (addr == (sunxi_musb->mregs + 0x80)) { 460 /* ep control reg access */ 461 /* sunxi has a 2 byte hole before the txtype register */ 462 if (offset >= MUSB_TXTYPE) 463 offset += 2; 464 return readb(addr + offset); 465 } 466 467 dev_err(sunxi_musb->controller->parent, 468 "Error unknown readb at 0x%x bytes offset\n", 469 (int)(addr - sunxi_musb->mregs)); 470 return 0; 471 } 472 473 static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data) 474 { 475 if (addr == sunxi_musb->mregs) { 476 /* generic control or fifo control reg access */ 477 switch (offset) { 478 case MUSB_FADDR: 479 return writeb(data, addr + SUNXI_MUSB_FADDR); 480 case MUSB_POWER: 481 return writeb(data, addr + SUNXI_MUSB_POWER); 482 case MUSB_INTRUSB: 483 return writeb(data, addr + SUNXI_MUSB_INTRUSB); 484 case MUSB_INTRUSBE: 485 return writeb(data, addr + SUNXI_MUSB_INTRUSBE); 486 case MUSB_INDEX: 487 return writeb(data, addr + SUNXI_MUSB_INDEX); 488 case MUSB_TESTMODE: 489 if (data) 490 dev_warn(sunxi_musb->controller->parent, 491 "sunxi-musb does not have testmode\n"); 492 return; 493 case MUSB_DEVCTL: 494 return writeb(data, addr + SUNXI_MUSB_DEVCTL); 495 case MUSB_TXFIFOSZ: 496 return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ); 497 case MUSB_RXFIFOSZ: 498 return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ); 499 /* Offset for these is fixed by sunxi_musb_busctl_offset() */ 500 case SUNXI_MUSB_TXFUNCADDR: 501 case SUNXI_MUSB_TXHUBADDR: 502 case SUNXI_MUSB_TXHUBPORT: 503 case SUNXI_MUSB_RXFUNCADDR: 504 case SUNXI_MUSB_RXHUBADDR: 505 case SUNXI_MUSB_RXHUBPORT: 506 /* multipoint / busctl reg access */ 507 return writeb(data, addr + offset); 508 default: 509 dev_err(sunxi_musb->controller->parent, 510 "Error unknown writeb offset %u\n", offset); 511 return; 512 } 513 } else if (addr == (sunxi_musb->mregs + 0x80)) { 514 /* ep control reg access */ 515 if (offset >= MUSB_TXTYPE) 516 offset += 2; 517 return writeb(data, addr + offset); 518 } 519 520 dev_err(sunxi_musb->controller->parent, 521 "Error unknown writeb at 0x%x bytes offset\n", 522 (int)(addr - sunxi_musb->mregs)); 523 } 524 525 static u16 sunxi_musb_readw(const void __iomem *addr, unsigned offset) 526 { 527 if (addr == sunxi_musb->mregs) { 528 /* generic control or fifo control reg access */ 529 switch (offset) { 530 case MUSB_INTRTX: 531 return readw(addr + SUNXI_MUSB_INTRTX); 532 case MUSB_INTRRX: 533 return readw(addr + SUNXI_MUSB_INTRRX); 534 case MUSB_INTRTXE: 535 return readw(addr + SUNXI_MUSB_INTRTXE); 536 case MUSB_INTRRXE: 537 return readw(addr + SUNXI_MUSB_INTRRXE); 538 case MUSB_FRAME: 539 return readw(addr + SUNXI_MUSB_FRAME); 540 case MUSB_TXFIFOADD: 541 return readw(addr + SUNXI_MUSB_TXFIFOADD); 542 case MUSB_RXFIFOADD: 543 return readw(addr + SUNXI_MUSB_RXFIFOADD); 544 case MUSB_HWVERS: 545 return 0; /* sunxi musb version is not known */ 546 default: 547 dev_err(sunxi_musb->controller->parent, 548 "Error unknown readw offset %u\n", offset); 549 return 0; 550 } 551 } else if (addr == (sunxi_musb->mregs + 0x80)) { 552 /* ep control reg access */ 553 return readw(addr + offset); 554 } 555 556 dev_err(sunxi_musb->controller->parent, 557 "Error unknown readw at 0x%x bytes offset\n", 558 (int)(addr - sunxi_musb->mregs)); 559 return 0; 560 } 561 562 static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data) 563 { 564 if (addr == sunxi_musb->mregs) { 565 /* generic control or fifo control reg access */ 566 switch (offset) { 567 case MUSB_INTRTX: 568 return writew(data, addr + SUNXI_MUSB_INTRTX); 569 case MUSB_INTRRX: 570 return writew(data, addr + SUNXI_MUSB_INTRRX); 571 case MUSB_INTRTXE: 572 return writew(data, addr + SUNXI_MUSB_INTRTXE); 573 case MUSB_INTRRXE: 574 return writew(data, addr + SUNXI_MUSB_INTRRXE); 575 case MUSB_FRAME: 576 return writew(data, addr + SUNXI_MUSB_FRAME); 577 case MUSB_TXFIFOADD: 578 return writew(data, addr + SUNXI_MUSB_TXFIFOADD); 579 case MUSB_RXFIFOADD: 580 return writew(data, addr + SUNXI_MUSB_RXFIFOADD); 581 default: 582 dev_err(sunxi_musb->controller->parent, 583 "Error unknown writew offset %u\n", offset); 584 return; 585 } 586 } else if (addr == (sunxi_musb->mregs + 0x80)) { 587 /* ep control reg access */ 588 return writew(data, addr + offset); 589 } 590 591 dev_err(sunxi_musb->controller->parent, 592 "Error unknown writew at 0x%x bytes offset\n", 593 (int)(addr - sunxi_musb->mregs)); 594 } 595 596 static const struct musb_platform_ops sunxi_musb_ops = { 597 .quirks = MUSB_INDEXED_EP, 598 .init = sunxi_musb_init, 599 .exit = sunxi_musb_exit, 600 .enable = sunxi_musb_enable, 601 .disable = sunxi_musb_disable, 602 .fifo_offset = sunxi_musb_fifo_offset, 603 .ep_offset = sunxi_musb_ep_offset, 604 .busctl_offset = sunxi_musb_busctl_offset, 605 .readb = sunxi_musb_readb, 606 .writeb = sunxi_musb_writeb, 607 .readw = sunxi_musb_readw, 608 .writew = sunxi_musb_writew, 609 .dma_init = sunxi_musb_dma_controller_create, 610 .dma_exit = sunxi_musb_dma_controller_destroy, 611 .set_mode = sunxi_musb_set_mode, 612 .recover = sunxi_musb_recover, 613 .set_vbus = sunxi_musb_set_vbus, 614 .pre_root_reset_end = sunxi_musb_pre_root_reset_end, 615 .post_root_reset_end = sunxi_musb_post_root_reset_end, 616 }; 617 618 /* Allwinner OTG supports up to 5 endpoints */ 619 #define SUNXI_MUSB_MAX_EP_NUM 6 620 #define SUNXI_MUSB_RAM_BITS 11 621 622 static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = { 623 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), 624 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), 625 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), 626 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), 627 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), 628 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), 629 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), 630 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), 631 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512), 632 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512), 633 }; 634 635 /* H3/V3s OTG supports only 4 endpoints */ 636 #define SUNXI_MUSB_MAX_EP_NUM_H3 5 637 638 static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = { 639 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), 640 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), 641 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), 642 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), 643 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), 644 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), 645 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), 646 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), 647 }; 648 649 static const struct musb_hdrc_config sunxi_musb_hdrc_config = { 650 .fifo_cfg = sunxi_musb_mode_cfg, 651 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg), 652 .multipoint = true, 653 .dyn_fifo = true, 654 .soft_con = true, 655 .num_eps = SUNXI_MUSB_MAX_EP_NUM, 656 .ram_bits = SUNXI_MUSB_RAM_BITS, 657 .dma = 0, 658 }; 659 660 static struct musb_hdrc_config sunxi_musb_hdrc_config_h3 = { 661 .fifo_cfg = sunxi_musb_mode_cfg_h3, 662 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3), 663 .multipoint = true, 664 .dyn_fifo = true, 665 .soft_con = true, 666 .num_eps = SUNXI_MUSB_MAX_EP_NUM_H3, 667 .ram_bits = SUNXI_MUSB_RAM_BITS, 668 .dma = 0, 669 }; 670 671 672 static int sunxi_musb_probe(struct platform_device *pdev) 673 { 674 struct musb_hdrc_platform_data pdata; 675 struct platform_device_info pinfo; 676 struct sunxi_glue *glue; 677 struct device_node *np = pdev->dev.of_node; 678 int ret; 679 680 if (!np) { 681 dev_err(&pdev->dev, "Error no device tree node found\n"); 682 return -EINVAL; 683 } 684 685 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 686 if (!glue) 687 return -ENOMEM; 688 689 memset(&pdata, 0, sizeof(pdata)); 690 switch (usb_get_dr_mode(&pdev->dev)) { 691 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST 692 case USB_DR_MODE_HOST: 693 pdata.mode = MUSB_PORT_MODE_HOST; 694 glue->phy_mode = PHY_MODE_USB_HOST; 695 break; 696 #endif 697 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_GADGET 698 case USB_DR_MODE_PERIPHERAL: 699 pdata.mode = MUSB_PORT_MODE_GADGET; 700 glue->phy_mode = PHY_MODE_USB_DEVICE; 701 break; 702 #endif 703 #ifdef CONFIG_USB_MUSB_DUAL_ROLE 704 case USB_DR_MODE_OTG: 705 pdata.mode = MUSB_PORT_MODE_DUAL_ROLE; 706 glue->phy_mode = PHY_MODE_USB_OTG; 707 break; 708 #endif 709 default: 710 dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n"); 711 return -EINVAL; 712 } 713 pdata.platform_ops = &sunxi_musb_ops; 714 if (!of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) 715 pdata.config = &sunxi_musb_hdrc_config; 716 else 717 pdata.config = &sunxi_musb_hdrc_config_h3; 718 719 glue->dev = &pdev->dev; 720 INIT_WORK(&glue->work, sunxi_musb_work); 721 glue->host_nb.notifier_call = sunxi_musb_host_notifier; 722 723 if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb")) 724 set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags); 725 726 if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb")) 727 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags); 728 729 if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") || 730 of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) { 731 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags); 732 set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags); 733 } 734 735 glue->clk = devm_clk_get(&pdev->dev, NULL); 736 if (IS_ERR(glue->clk)) { 737 dev_err(&pdev->dev, "Error getting clock: %ld\n", 738 PTR_ERR(glue->clk)); 739 return PTR_ERR(glue->clk); 740 } 741 742 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { 743 glue->rst = devm_reset_control_get(&pdev->dev, NULL); 744 if (IS_ERR(glue->rst)) { 745 if (PTR_ERR(glue->rst) == -EPROBE_DEFER) 746 return -EPROBE_DEFER; 747 dev_err(&pdev->dev, "Error getting reset %ld\n", 748 PTR_ERR(glue->rst)); 749 return PTR_ERR(glue->rst); 750 } 751 } 752 753 glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0); 754 if (IS_ERR(glue->extcon)) { 755 if (PTR_ERR(glue->extcon) == -EPROBE_DEFER) 756 return -EPROBE_DEFER; 757 dev_err(&pdev->dev, "Invalid or missing extcon\n"); 758 return PTR_ERR(glue->extcon); 759 } 760 761 glue->phy = devm_phy_get(&pdev->dev, "usb"); 762 if (IS_ERR(glue->phy)) { 763 if (PTR_ERR(glue->phy) == -EPROBE_DEFER) 764 return -EPROBE_DEFER; 765 dev_err(&pdev->dev, "Error getting phy %ld\n", 766 PTR_ERR(glue->phy)); 767 return PTR_ERR(glue->phy); 768 } 769 770 glue->usb_phy = usb_phy_generic_register(); 771 if (IS_ERR(glue->usb_phy)) { 772 dev_err(&pdev->dev, "Error registering usb-phy %ld\n", 773 PTR_ERR(glue->usb_phy)); 774 return PTR_ERR(glue->usb_phy); 775 } 776 777 glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2); 778 if (IS_ERR(glue->xceiv)) { 779 ret = PTR_ERR(glue->xceiv); 780 dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret); 781 goto err_unregister_usb_phy; 782 } 783 784 platform_set_drvdata(pdev, glue); 785 786 memset(&pinfo, 0, sizeof(pinfo)); 787 pinfo.name = "musb-hdrc"; 788 pinfo.id = PLATFORM_DEVID_AUTO; 789 pinfo.parent = &pdev->dev; 790 pinfo.res = pdev->resource; 791 pinfo.num_res = pdev->num_resources; 792 pinfo.data = &pdata; 793 pinfo.size_data = sizeof(pdata); 794 795 glue->musb_pdev = platform_device_register_full(&pinfo); 796 if (IS_ERR(glue->musb_pdev)) { 797 ret = PTR_ERR(glue->musb_pdev); 798 dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret); 799 goto err_unregister_usb_phy; 800 } 801 802 return 0; 803 804 err_unregister_usb_phy: 805 usb_phy_generic_unregister(glue->usb_phy); 806 return ret; 807 } 808 809 static int sunxi_musb_remove(struct platform_device *pdev) 810 { 811 struct sunxi_glue *glue = platform_get_drvdata(pdev); 812 struct platform_device *usb_phy = glue->usb_phy; 813 814 platform_device_unregister(glue->musb_pdev); 815 usb_phy_generic_unregister(usb_phy); 816 817 return 0; 818 } 819 820 static const struct of_device_id sunxi_musb_match[] = { 821 { .compatible = "allwinner,sun4i-a10-musb", }, 822 { .compatible = "allwinner,sun6i-a31-musb", }, 823 { .compatible = "allwinner,sun8i-a33-musb", }, 824 { .compatible = "allwinner,sun8i-h3-musb", }, 825 {} 826 }; 827 MODULE_DEVICE_TABLE(of, sunxi_musb_match); 828 829 static struct platform_driver sunxi_musb_driver = { 830 .probe = sunxi_musb_probe, 831 .remove = sunxi_musb_remove, 832 .driver = { 833 .name = "musb-sunxi", 834 .of_match_table = sunxi_musb_match, 835 }, 836 }; 837 module_platform_driver(sunxi_musb_driver); 838 839 MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer"); 840 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); 841 MODULE_LICENSE("GPL v2"); 842