1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Allwinner sun4i MUSB Glue Layer 4 * 5 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> 6 * 7 * Based on code from 8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/err.h> 13 #include <linux/extcon.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/phy/phy-sun4i-usb.h> 19 #include <linux/platform_device.h> 20 #include <linux/reset.h> 21 #include <linux/soc/sunxi/sunxi_sram.h> 22 #include <linux/usb/musb.h> 23 #include <linux/usb/of.h> 24 #include <linux/usb/usb_phy_generic.h> 25 #include <linux/workqueue.h> 26 #include "musb_core.h" 27 28 /* 29 * Register offsets, note sunxi musb has a different layout then most 30 * musb implementations, we translate the layout in musb_readb & friends. 31 */ 32 #define SUNXI_MUSB_POWER 0x0040 33 #define SUNXI_MUSB_DEVCTL 0x0041 34 #define SUNXI_MUSB_INDEX 0x0042 35 #define SUNXI_MUSB_VEND0 0x0043 36 #define SUNXI_MUSB_INTRTX 0x0044 37 #define SUNXI_MUSB_INTRRX 0x0046 38 #define SUNXI_MUSB_INTRTXE 0x0048 39 #define SUNXI_MUSB_INTRRXE 0x004a 40 #define SUNXI_MUSB_INTRUSB 0x004c 41 #define SUNXI_MUSB_INTRUSBE 0x0050 42 #define SUNXI_MUSB_FRAME 0x0054 43 #define SUNXI_MUSB_TXFIFOSZ 0x0090 44 #define SUNXI_MUSB_TXFIFOADD 0x0092 45 #define SUNXI_MUSB_RXFIFOSZ 0x0094 46 #define SUNXI_MUSB_RXFIFOADD 0x0096 47 #define SUNXI_MUSB_FADDR 0x0098 48 #define SUNXI_MUSB_TXFUNCADDR 0x0098 49 #define SUNXI_MUSB_TXHUBADDR 0x009a 50 #define SUNXI_MUSB_TXHUBPORT 0x009b 51 #define SUNXI_MUSB_RXFUNCADDR 0x009c 52 #define SUNXI_MUSB_RXHUBADDR 0x009e 53 #define SUNXI_MUSB_RXHUBPORT 0x009f 54 #define SUNXI_MUSB_CONFIGDATA 0x00c0 55 56 /* VEND0 bits */ 57 #define SUNXI_MUSB_VEND0_PIO_MODE 0 58 59 /* flags */ 60 #define SUNXI_MUSB_FL_ENABLED 0 61 #define SUNXI_MUSB_FL_HOSTMODE 1 62 #define SUNXI_MUSB_FL_HOSTMODE_PEND 2 63 #define SUNXI_MUSB_FL_VBUS_ON 3 64 #define SUNXI_MUSB_FL_PHY_ON 4 65 #define SUNXI_MUSB_FL_HAS_SRAM 5 66 #define SUNXI_MUSB_FL_HAS_RESET 6 67 #define SUNXI_MUSB_FL_NO_CONFIGDATA 7 68 #define SUNXI_MUSB_FL_PHY_MODE_PEND 8 69 70 struct sunxi_musb_cfg { 71 const struct musb_hdrc_config *hdrc_config; 72 bool has_sram; 73 bool has_reset; 74 bool no_configdata; 75 }; 76 77 /* Our read/write methods need access and do not get passed in a musb ref :| */ 78 static struct musb *sunxi_musb; 79 80 struct sunxi_glue { 81 struct device *dev; 82 struct musb *musb; 83 struct platform_device *musb_pdev; 84 struct clk *clk; 85 struct reset_control *rst; 86 struct phy *phy; 87 struct platform_device *usb_phy; 88 struct usb_phy *xceiv; 89 enum phy_mode phy_mode; 90 unsigned long flags; 91 struct work_struct work; 92 struct extcon_dev *extcon; 93 struct notifier_block host_nb; 94 }; 95 96 /* phy_power_on / off may sleep, so we use a workqueue */ 97 static void sunxi_musb_work(struct work_struct *work) 98 { 99 struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work); 100 bool vbus_on, phy_on; 101 102 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) 103 return; 104 105 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) { 106 struct musb *musb = glue->musb; 107 unsigned long flags; 108 u8 devctl; 109 110 spin_lock_irqsave(&musb->lock, flags); 111 112 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL); 113 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) { 114 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 115 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 116 MUSB_HST_MODE(musb); 117 devctl |= MUSB_DEVCTL_SESSION; 118 } else { 119 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 120 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 121 MUSB_DEV_MODE(musb); 122 devctl &= ~MUSB_DEVCTL_SESSION; 123 } 124 writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL); 125 126 spin_unlock_irqrestore(&musb->lock, flags); 127 } 128 129 vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 130 phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 131 132 if (phy_on != vbus_on) { 133 if (vbus_on) { 134 phy_power_on(glue->phy); 135 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 136 } else { 137 phy_power_off(glue->phy); 138 clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 139 } 140 } 141 142 if (test_and_clear_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags)) 143 phy_set_mode(glue->phy, glue->phy_mode); 144 } 145 146 static void sunxi_musb_set_vbus(struct musb *musb, int is_on) 147 { 148 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 149 150 if (is_on) { 151 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 152 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 153 } else { 154 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 155 } 156 157 schedule_work(&glue->work); 158 } 159 160 static void sunxi_musb_pre_root_reset_end(struct musb *musb) 161 { 162 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 163 164 sun4i_usb_phy_set_squelch_detect(glue->phy, false); 165 } 166 167 static void sunxi_musb_post_root_reset_end(struct musb *musb) 168 { 169 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 170 171 sun4i_usb_phy_set_squelch_detect(glue->phy, true); 172 } 173 174 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci) 175 { 176 struct musb *musb = __hci; 177 unsigned long flags; 178 179 spin_lock_irqsave(&musb->lock, flags); 180 181 musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB); 182 if (musb->int_usb) 183 writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB); 184 185 if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) { 186 /* ep0 FADDR must be 0 when (re)entering peripheral mode */ 187 musb_ep_select(musb->mregs, 0); 188 musb_writeb(musb->mregs, MUSB_FADDR, 0); 189 } 190 191 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX); 192 if (musb->int_tx) 193 writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX); 194 195 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX); 196 if (musb->int_rx) 197 writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX); 198 199 musb_interrupt(musb); 200 201 spin_unlock_irqrestore(&musb->lock, flags); 202 203 return IRQ_HANDLED; 204 } 205 206 static int sunxi_musb_host_notifier(struct notifier_block *nb, 207 unsigned long event, void *ptr) 208 { 209 struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb); 210 211 if (event) 212 set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); 213 else 214 clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); 215 216 set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags); 217 schedule_work(&glue->work); 218 219 return NOTIFY_DONE; 220 } 221 222 static int sunxi_musb_init(struct musb *musb) 223 { 224 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 225 int ret; 226 227 sunxi_musb = musb; 228 musb->phy = glue->phy; 229 musb->xceiv = glue->xceiv; 230 231 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) { 232 ret = sunxi_sram_claim(musb->controller->parent); 233 if (ret) 234 return ret; 235 } 236 237 ret = clk_prepare_enable(glue->clk); 238 if (ret) 239 goto error_sram_release; 240 241 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { 242 ret = reset_control_deassert(glue->rst); 243 if (ret) 244 goto error_clk_disable; 245 } 246 247 writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0); 248 249 /* Register notifier before calling phy_init() */ 250 ret = devm_extcon_register_notifier(glue->dev, glue->extcon, 251 EXTCON_USB_HOST, &glue->host_nb); 252 if (ret) 253 goto error_reset_assert; 254 255 ret = phy_init(glue->phy); 256 if (ret) 257 goto error_reset_assert; 258 259 musb->isr = sunxi_musb_interrupt; 260 261 /* Stop the musb-core from doing runtime pm (not supported on sunxi) */ 262 pm_runtime_get(musb->controller); 263 264 return 0; 265 266 error_reset_assert: 267 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) 268 reset_control_assert(glue->rst); 269 error_clk_disable: 270 clk_disable_unprepare(glue->clk); 271 error_sram_release: 272 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) 273 sunxi_sram_release(musb->controller->parent); 274 return ret; 275 } 276 277 static int sunxi_musb_exit(struct musb *musb) 278 { 279 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 280 281 pm_runtime_put(musb->controller); 282 283 cancel_work_sync(&glue->work); 284 if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags)) 285 phy_power_off(glue->phy); 286 287 phy_exit(glue->phy); 288 289 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) 290 reset_control_assert(glue->rst); 291 292 clk_disable_unprepare(glue->clk); 293 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) 294 sunxi_sram_release(musb->controller->parent); 295 296 return 0; 297 } 298 299 static void sunxi_musb_enable(struct musb *musb) 300 { 301 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 302 303 glue->musb = musb; 304 305 /* musb_core does not call us in a balanced manner */ 306 if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) 307 return; 308 309 schedule_work(&glue->work); 310 } 311 312 static void sunxi_musb_disable(struct musb *musb) 313 { 314 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 315 316 clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags); 317 } 318 319 static struct dma_controller * 320 sunxi_musb_dma_controller_create(struct musb *musb, void __iomem *base) 321 { 322 return NULL; 323 } 324 325 static void sunxi_musb_dma_controller_destroy(struct dma_controller *c) 326 { 327 } 328 329 static int sunxi_musb_set_mode(struct musb *musb, u8 mode) 330 { 331 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 332 enum phy_mode new_mode; 333 334 switch (mode) { 335 case MUSB_HOST: 336 new_mode = PHY_MODE_USB_HOST; 337 break; 338 case MUSB_PERIPHERAL: 339 new_mode = PHY_MODE_USB_DEVICE; 340 break; 341 case MUSB_OTG: 342 new_mode = PHY_MODE_USB_OTG; 343 break; 344 default: 345 dev_err(musb->controller->parent, 346 "Error requested mode not supported by this kernel\n"); 347 return -EINVAL; 348 } 349 350 if (glue->phy_mode == new_mode) 351 return 0; 352 353 if (musb->port_mode != MUSB_OTG) { 354 dev_err(musb->controller->parent, 355 "Error changing modes is only supported in dual role mode\n"); 356 return -EINVAL; 357 } 358 359 if (musb->port1_status & USB_PORT_STAT_ENABLE) 360 musb_root_disconnect(musb); 361 362 /* 363 * phy_set_mode may sleep, and we're called with a spinlock held, 364 * so let sunxi_musb_work deal with it. 365 */ 366 glue->phy_mode = new_mode; 367 set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags); 368 schedule_work(&glue->work); 369 370 return 0; 371 } 372 373 static int sunxi_musb_recover(struct musb *musb) 374 { 375 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 376 377 /* 378 * Schedule a phy_set_mode with the current glue->phy_mode value, 379 * this will force end the current session. 380 */ 381 set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags); 382 schedule_work(&glue->work); 383 384 return 0; 385 } 386 387 /* 388 * sunxi musb register layout 389 * 0x00 - 0x17 fifo regs, 1 long per fifo 390 * 0x40 - 0x57 generic control regs (power - frame) 391 * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed) 392 * 0x90 - 0x97 fifo control regs (indexed) 393 * 0x98 - 0x9f multipoint / busctl regs (indexed) 394 * 0xc0 configdata reg 395 */ 396 397 static u32 sunxi_musb_fifo_offset(u8 epnum) 398 { 399 return (epnum * 4); 400 } 401 402 static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset) 403 { 404 WARN_ONCE(offset != 0, 405 "sunxi_musb_ep_offset called with non 0 offset\n"); 406 407 return 0x80; /* indexed, so ignore epnum */ 408 } 409 410 static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset) 411 { 412 return SUNXI_MUSB_TXFUNCADDR + offset; 413 } 414 415 static u8 sunxi_musb_readb(void __iomem *addr, u32 offset) 416 { 417 struct sunxi_glue *glue; 418 419 if (addr == sunxi_musb->mregs) { 420 /* generic control or fifo control reg access */ 421 switch (offset) { 422 case MUSB_FADDR: 423 return readb(addr + SUNXI_MUSB_FADDR); 424 case MUSB_POWER: 425 return readb(addr + SUNXI_MUSB_POWER); 426 case MUSB_INTRUSB: 427 return readb(addr + SUNXI_MUSB_INTRUSB); 428 case MUSB_INTRUSBE: 429 return readb(addr + SUNXI_MUSB_INTRUSBE); 430 case MUSB_INDEX: 431 return readb(addr + SUNXI_MUSB_INDEX); 432 case MUSB_TESTMODE: 433 return 0; /* No testmode on sunxi */ 434 case MUSB_DEVCTL: 435 return readb(addr + SUNXI_MUSB_DEVCTL); 436 case MUSB_TXFIFOSZ: 437 return readb(addr + SUNXI_MUSB_TXFIFOSZ); 438 case MUSB_RXFIFOSZ: 439 return readb(addr + SUNXI_MUSB_RXFIFOSZ); 440 case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */ 441 glue = dev_get_drvdata(sunxi_musb->controller->parent); 442 /* A33 saves a reg, and we get to hardcode this */ 443 if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, 444 &glue->flags)) 445 return 0xde; 446 447 return readb(addr + SUNXI_MUSB_CONFIGDATA); 448 case MUSB_ULPI_BUSCONTROL: 449 dev_warn(sunxi_musb->controller->parent, 450 "sunxi-musb does not have ULPI bus control register\n"); 451 return 0; 452 /* Offset for these is fixed by sunxi_musb_busctl_offset() */ 453 case SUNXI_MUSB_TXFUNCADDR: 454 case SUNXI_MUSB_TXHUBADDR: 455 case SUNXI_MUSB_TXHUBPORT: 456 case SUNXI_MUSB_RXFUNCADDR: 457 case SUNXI_MUSB_RXHUBADDR: 458 case SUNXI_MUSB_RXHUBPORT: 459 /* multipoint / busctl reg access */ 460 return readb(addr + offset); 461 default: 462 dev_err(sunxi_musb->controller->parent, 463 "Error unknown readb offset %u\n", offset); 464 return 0; 465 } 466 } else if (addr == (sunxi_musb->mregs + 0x80)) { 467 /* ep control reg access */ 468 /* sunxi has a 2 byte hole before the txtype register */ 469 if (offset >= MUSB_TXTYPE) 470 offset += 2; 471 return readb(addr + offset); 472 } 473 474 dev_err(sunxi_musb->controller->parent, 475 "Error unknown readb at 0x%x bytes offset\n", 476 (int)(addr - sunxi_musb->mregs)); 477 return 0; 478 } 479 480 static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data) 481 { 482 if (addr == sunxi_musb->mregs) { 483 /* generic control or fifo control reg access */ 484 switch (offset) { 485 case MUSB_FADDR: 486 return writeb(data, addr + SUNXI_MUSB_FADDR); 487 case MUSB_POWER: 488 return writeb(data, addr + SUNXI_MUSB_POWER); 489 case MUSB_INTRUSB: 490 return writeb(data, addr + SUNXI_MUSB_INTRUSB); 491 case MUSB_INTRUSBE: 492 return writeb(data, addr + SUNXI_MUSB_INTRUSBE); 493 case MUSB_INDEX: 494 return writeb(data, addr + SUNXI_MUSB_INDEX); 495 case MUSB_TESTMODE: 496 if (data) 497 dev_warn(sunxi_musb->controller->parent, 498 "sunxi-musb does not have testmode\n"); 499 return; 500 case MUSB_DEVCTL: 501 return writeb(data, addr + SUNXI_MUSB_DEVCTL); 502 case MUSB_TXFIFOSZ: 503 return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ); 504 case MUSB_RXFIFOSZ: 505 return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ); 506 case MUSB_ULPI_BUSCONTROL: 507 dev_warn(sunxi_musb->controller->parent, 508 "sunxi-musb does not have ULPI bus control register\n"); 509 return; 510 /* Offset for these is fixed by sunxi_musb_busctl_offset() */ 511 case SUNXI_MUSB_TXFUNCADDR: 512 case SUNXI_MUSB_TXHUBADDR: 513 case SUNXI_MUSB_TXHUBPORT: 514 case SUNXI_MUSB_RXFUNCADDR: 515 case SUNXI_MUSB_RXHUBADDR: 516 case SUNXI_MUSB_RXHUBPORT: 517 /* multipoint / busctl reg access */ 518 return writeb(data, addr + offset); 519 default: 520 dev_err(sunxi_musb->controller->parent, 521 "Error unknown writeb offset %u\n", offset); 522 return; 523 } 524 } else if (addr == (sunxi_musb->mregs + 0x80)) { 525 /* ep control reg access */ 526 if (offset >= MUSB_TXTYPE) 527 offset += 2; 528 return writeb(data, addr + offset); 529 } 530 531 dev_err(sunxi_musb->controller->parent, 532 "Error unknown writeb at 0x%x bytes offset\n", 533 (int)(addr - sunxi_musb->mregs)); 534 } 535 536 static u16 sunxi_musb_readw(void __iomem *addr, u32 offset) 537 { 538 if (addr == sunxi_musb->mregs) { 539 /* generic control or fifo control reg access */ 540 switch (offset) { 541 case MUSB_INTRTX: 542 return readw(addr + SUNXI_MUSB_INTRTX); 543 case MUSB_INTRRX: 544 return readw(addr + SUNXI_MUSB_INTRRX); 545 case MUSB_INTRTXE: 546 return readw(addr + SUNXI_MUSB_INTRTXE); 547 case MUSB_INTRRXE: 548 return readw(addr + SUNXI_MUSB_INTRRXE); 549 case MUSB_FRAME: 550 return readw(addr + SUNXI_MUSB_FRAME); 551 case MUSB_TXFIFOADD: 552 return readw(addr + SUNXI_MUSB_TXFIFOADD); 553 case MUSB_RXFIFOADD: 554 return readw(addr + SUNXI_MUSB_RXFIFOADD); 555 case MUSB_HWVERS: 556 return 0; /* sunxi musb version is not known */ 557 default: 558 dev_err(sunxi_musb->controller->parent, 559 "Error unknown readw offset %u\n", offset); 560 return 0; 561 } 562 } else if (addr == (sunxi_musb->mregs + 0x80)) { 563 /* ep control reg access */ 564 return readw(addr + offset); 565 } 566 567 dev_err(sunxi_musb->controller->parent, 568 "Error unknown readw at 0x%x bytes offset\n", 569 (int)(addr - sunxi_musb->mregs)); 570 return 0; 571 } 572 573 static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data) 574 { 575 if (addr == sunxi_musb->mregs) { 576 /* generic control or fifo control reg access */ 577 switch (offset) { 578 case MUSB_INTRTX: 579 return writew(data, addr + SUNXI_MUSB_INTRTX); 580 case MUSB_INTRRX: 581 return writew(data, addr + SUNXI_MUSB_INTRRX); 582 case MUSB_INTRTXE: 583 return writew(data, addr + SUNXI_MUSB_INTRTXE); 584 case MUSB_INTRRXE: 585 return writew(data, addr + SUNXI_MUSB_INTRRXE); 586 case MUSB_FRAME: 587 return writew(data, addr + SUNXI_MUSB_FRAME); 588 case MUSB_TXFIFOADD: 589 return writew(data, addr + SUNXI_MUSB_TXFIFOADD); 590 case MUSB_RXFIFOADD: 591 return writew(data, addr + SUNXI_MUSB_RXFIFOADD); 592 default: 593 dev_err(sunxi_musb->controller->parent, 594 "Error unknown writew offset %u\n", offset); 595 return; 596 } 597 } else if (addr == (sunxi_musb->mregs + 0x80)) { 598 /* ep control reg access */ 599 return writew(data, addr + offset); 600 } 601 602 dev_err(sunxi_musb->controller->parent, 603 "Error unknown writew at 0x%x bytes offset\n", 604 (int)(addr - sunxi_musb->mregs)); 605 } 606 607 static const struct musb_platform_ops sunxi_musb_ops = { 608 .quirks = MUSB_INDEXED_EP, 609 .init = sunxi_musb_init, 610 .exit = sunxi_musb_exit, 611 .enable = sunxi_musb_enable, 612 .disable = sunxi_musb_disable, 613 .fifo_offset = sunxi_musb_fifo_offset, 614 .ep_offset = sunxi_musb_ep_offset, 615 .busctl_offset = sunxi_musb_busctl_offset, 616 .readb = sunxi_musb_readb, 617 .writeb = sunxi_musb_writeb, 618 .readw = sunxi_musb_readw, 619 .writew = sunxi_musb_writew, 620 .dma_init = sunxi_musb_dma_controller_create, 621 .dma_exit = sunxi_musb_dma_controller_destroy, 622 .set_mode = sunxi_musb_set_mode, 623 .recover = sunxi_musb_recover, 624 .set_vbus = sunxi_musb_set_vbus, 625 .pre_root_reset_end = sunxi_musb_pre_root_reset_end, 626 .post_root_reset_end = sunxi_musb_post_root_reset_end, 627 }; 628 629 #define SUNXI_MUSB_RAM_BITS 11 630 631 /* Allwinner OTG supports up to 5 endpoints */ 632 static struct musb_fifo_cfg sunxi_musb_mode_cfg_5eps[] = { 633 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), 634 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), 635 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), 636 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), 637 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), 638 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), 639 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), 640 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), 641 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512), 642 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512), 643 }; 644 645 /* H3/V3s OTG supports only 4 endpoints */ 646 static struct musb_fifo_cfg sunxi_musb_mode_cfg_4eps[] = { 647 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), 648 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), 649 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), 650 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), 651 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), 652 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), 653 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), 654 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), 655 }; 656 657 static const struct musb_hdrc_config sunxi_musb_hdrc_config_5eps = { 658 .fifo_cfg = sunxi_musb_mode_cfg_5eps, 659 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_5eps), 660 .multipoint = true, 661 .dyn_fifo = true, 662 /* Two FIFOs per endpoint, plus ep_0. */ 663 .num_eps = (ARRAY_SIZE(sunxi_musb_mode_cfg_5eps) / 2) + 1, 664 .ram_bits = SUNXI_MUSB_RAM_BITS, 665 }; 666 667 static const struct musb_hdrc_config sunxi_musb_hdrc_config_4eps = { 668 .fifo_cfg = sunxi_musb_mode_cfg_4eps, 669 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_4eps), 670 .multipoint = true, 671 .dyn_fifo = true, 672 /* Two FIFOs per endpoint, plus ep_0. */ 673 .num_eps = (ARRAY_SIZE(sunxi_musb_mode_cfg_4eps) / 2) + 1, 674 .ram_bits = SUNXI_MUSB_RAM_BITS, 675 }; 676 677 static int sunxi_musb_probe(struct platform_device *pdev) 678 { 679 struct musb_hdrc_platform_data pdata; 680 struct platform_device_info pinfo; 681 struct sunxi_glue *glue; 682 struct device_node *np = pdev->dev.of_node; 683 const struct sunxi_musb_cfg *cfg; 684 int ret; 685 686 if (!np) { 687 dev_err(&pdev->dev, "Error no device tree node found\n"); 688 return -EINVAL; 689 } 690 691 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 692 if (!glue) 693 return -ENOMEM; 694 695 memset(&pdata, 0, sizeof(pdata)); 696 switch (usb_get_dr_mode(&pdev->dev)) { 697 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST 698 case USB_DR_MODE_HOST: 699 pdata.mode = MUSB_HOST; 700 glue->phy_mode = PHY_MODE_USB_HOST; 701 break; 702 #endif 703 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_GADGET 704 case USB_DR_MODE_PERIPHERAL: 705 pdata.mode = MUSB_PERIPHERAL; 706 glue->phy_mode = PHY_MODE_USB_DEVICE; 707 break; 708 #endif 709 #ifdef CONFIG_USB_MUSB_DUAL_ROLE 710 case USB_DR_MODE_OTG: 711 pdata.mode = MUSB_OTG; 712 glue->phy_mode = PHY_MODE_USB_OTG; 713 break; 714 #endif 715 default: 716 dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n"); 717 return -EINVAL; 718 } 719 pdata.platform_ops = &sunxi_musb_ops; 720 721 cfg = of_device_get_match_data(&pdev->dev); 722 if (!cfg) 723 return -EINVAL; 724 725 pdata.config = cfg->hdrc_config; 726 727 glue->dev = &pdev->dev; 728 INIT_WORK(&glue->work, sunxi_musb_work); 729 glue->host_nb.notifier_call = sunxi_musb_host_notifier; 730 731 if (cfg->has_sram) 732 set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags); 733 734 if (cfg->has_reset) 735 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags); 736 737 if (cfg->no_configdata) 738 set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags); 739 740 glue->clk = devm_clk_get(&pdev->dev, NULL); 741 if (IS_ERR(glue->clk)) { 742 dev_err(&pdev->dev, "Error getting clock: %ld\n", 743 PTR_ERR(glue->clk)); 744 return PTR_ERR(glue->clk); 745 } 746 747 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { 748 glue->rst = devm_reset_control_get(&pdev->dev, NULL); 749 if (IS_ERR(glue->rst)) 750 return dev_err_probe(&pdev->dev, PTR_ERR(glue->rst), 751 "Error getting reset\n"); 752 } 753 754 glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0); 755 if (IS_ERR(glue->extcon)) 756 return dev_err_probe(&pdev->dev, PTR_ERR(glue->extcon), 757 "Invalid or missing extcon\n"); 758 759 glue->phy = devm_phy_get(&pdev->dev, "usb"); 760 if (IS_ERR(glue->phy)) 761 return dev_err_probe(&pdev->dev, PTR_ERR(glue->phy), 762 "Error getting phy\n"); 763 764 glue->usb_phy = usb_phy_generic_register(); 765 if (IS_ERR(glue->usb_phy)) { 766 dev_err(&pdev->dev, "Error registering usb-phy %ld\n", 767 PTR_ERR(glue->usb_phy)); 768 return PTR_ERR(glue->usb_phy); 769 } 770 771 glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2); 772 if (IS_ERR(glue->xceiv)) { 773 ret = PTR_ERR(glue->xceiv); 774 dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret); 775 goto err_unregister_usb_phy; 776 } 777 778 platform_set_drvdata(pdev, glue); 779 780 memset(&pinfo, 0, sizeof(pinfo)); 781 pinfo.name = "musb-hdrc"; 782 pinfo.id = PLATFORM_DEVID_AUTO; 783 pinfo.parent = &pdev->dev; 784 pinfo.fwnode = of_fwnode_handle(pdev->dev.of_node); 785 pinfo.of_node_reused = true; 786 pinfo.res = pdev->resource; 787 pinfo.num_res = pdev->num_resources; 788 pinfo.data = &pdata; 789 pinfo.size_data = sizeof(pdata); 790 791 glue->musb_pdev = platform_device_register_full(&pinfo); 792 if (IS_ERR(glue->musb_pdev)) { 793 ret = PTR_ERR(glue->musb_pdev); 794 dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret); 795 goto err_unregister_usb_phy; 796 } 797 798 return 0; 799 800 err_unregister_usb_phy: 801 usb_phy_generic_unregister(glue->usb_phy); 802 return ret; 803 } 804 805 static void sunxi_musb_remove(struct platform_device *pdev) 806 { 807 struct sunxi_glue *glue = platform_get_drvdata(pdev); 808 struct platform_device *usb_phy = glue->usb_phy; 809 810 platform_device_unregister(glue->musb_pdev); 811 usb_phy_generic_unregister(usb_phy); 812 } 813 814 static const struct sunxi_musb_cfg sun4i_a10_musb_cfg = { 815 .hdrc_config = &sunxi_musb_hdrc_config_5eps, 816 .has_sram = true, 817 }; 818 819 static const struct sunxi_musb_cfg sun6i_a31_musb_cfg = { 820 .hdrc_config = &sunxi_musb_hdrc_config_5eps, 821 .has_reset = true, 822 }; 823 824 static const struct sunxi_musb_cfg sun8i_a33_musb_cfg = { 825 .hdrc_config = &sunxi_musb_hdrc_config_5eps, 826 .has_reset = true, 827 .no_configdata = true, 828 }; 829 830 static const struct sunxi_musb_cfg sun8i_h3_musb_cfg = { 831 .hdrc_config = &sunxi_musb_hdrc_config_4eps, 832 .has_reset = true, 833 .no_configdata = true, 834 }; 835 836 static const struct sunxi_musb_cfg suniv_f1c100s_musb_cfg = { 837 .hdrc_config = &sunxi_musb_hdrc_config_5eps, 838 .has_sram = true, 839 .has_reset = true, 840 .no_configdata = true, 841 }; 842 843 static const struct of_device_id sunxi_musb_match[] = { 844 { .compatible = "allwinner,sun4i-a10-musb", 845 .data = &sun4i_a10_musb_cfg, }, 846 { .compatible = "allwinner,sun6i-a31-musb", 847 .data = &sun6i_a31_musb_cfg, }, 848 { .compatible = "allwinner,sun8i-a33-musb", 849 .data = &sun8i_a33_musb_cfg, }, 850 { .compatible = "allwinner,sun8i-h3-musb", 851 .data = &sun8i_h3_musb_cfg, }, 852 { .compatible = "allwinner,suniv-f1c100s-musb", 853 .data = &suniv_f1c100s_musb_cfg, }, 854 {} 855 }; 856 MODULE_DEVICE_TABLE(of, sunxi_musb_match); 857 858 static struct platform_driver sunxi_musb_driver = { 859 .probe = sunxi_musb_probe, 860 .remove_new = sunxi_musb_remove, 861 .driver = { 862 .name = "musb-sunxi", 863 .of_match_table = sunxi_musb_match, 864 }, 865 }; 866 module_platform_driver(sunxi_musb_driver); 867 868 MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer"); 869 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); 870 MODULE_LICENSE("GPL v2"); 871