1 /* 2 * Allwinner sun4i MUSB Glue Layer 3 * 4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> 5 * 6 * Based on code from 7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/clk.h> 21 #include <linux/err.h> 22 #include <linux/extcon.h> 23 #include <linux/io.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/phy/phy-sun4i-usb.h> 28 #include <linux/platform_device.h> 29 #include <linux/reset.h> 30 #include <linux/soc/sunxi/sunxi_sram.h> 31 #include <linux/usb/musb.h> 32 #include <linux/usb/of.h> 33 #include <linux/usb/usb_phy_generic.h> 34 #include <linux/workqueue.h> 35 #include "musb_core.h" 36 37 /* 38 * Register offsets, note sunxi musb has a different layout then most 39 * musb implementations, we translate the layout in musb_readb & friends. 40 */ 41 #define SUNXI_MUSB_POWER 0x0040 42 #define SUNXI_MUSB_DEVCTL 0x0041 43 #define SUNXI_MUSB_INDEX 0x0042 44 #define SUNXI_MUSB_VEND0 0x0043 45 #define SUNXI_MUSB_INTRTX 0x0044 46 #define SUNXI_MUSB_INTRRX 0x0046 47 #define SUNXI_MUSB_INTRTXE 0x0048 48 #define SUNXI_MUSB_INTRRXE 0x004a 49 #define SUNXI_MUSB_INTRUSB 0x004c 50 #define SUNXI_MUSB_INTRUSBE 0x0050 51 #define SUNXI_MUSB_FRAME 0x0054 52 #define SUNXI_MUSB_TXFIFOSZ 0x0090 53 #define SUNXI_MUSB_TXFIFOADD 0x0092 54 #define SUNXI_MUSB_RXFIFOSZ 0x0094 55 #define SUNXI_MUSB_RXFIFOADD 0x0096 56 #define SUNXI_MUSB_FADDR 0x0098 57 #define SUNXI_MUSB_TXFUNCADDR 0x0098 58 #define SUNXI_MUSB_TXHUBADDR 0x009a 59 #define SUNXI_MUSB_TXHUBPORT 0x009b 60 #define SUNXI_MUSB_RXFUNCADDR 0x009c 61 #define SUNXI_MUSB_RXHUBADDR 0x009e 62 #define SUNXI_MUSB_RXHUBPORT 0x009f 63 #define SUNXI_MUSB_CONFIGDATA 0x00c0 64 65 /* VEND0 bits */ 66 #define SUNXI_MUSB_VEND0_PIO_MODE 0 67 68 /* flags */ 69 #define SUNXI_MUSB_FL_ENABLED 0 70 #define SUNXI_MUSB_FL_HOSTMODE 1 71 #define SUNXI_MUSB_FL_HOSTMODE_PEND 2 72 #define SUNXI_MUSB_FL_VBUS_ON 3 73 #define SUNXI_MUSB_FL_PHY_ON 4 74 #define SUNXI_MUSB_FL_HAS_SRAM 5 75 #define SUNXI_MUSB_FL_HAS_RESET 6 76 #define SUNXI_MUSB_FL_NO_CONFIGDATA 7 77 #define SUNXI_MUSB_FL_PHY_MODE_PEND 8 78 79 /* Our read/write methods need access and do not get passed in a musb ref :| */ 80 static struct musb *sunxi_musb; 81 82 struct sunxi_glue { 83 struct device *dev; 84 struct musb *musb; 85 struct platform_device *musb_pdev; 86 struct clk *clk; 87 struct reset_control *rst; 88 struct phy *phy; 89 struct platform_device *usb_phy; 90 struct usb_phy *xceiv; 91 enum phy_mode phy_mode; 92 unsigned long flags; 93 struct work_struct work; 94 struct extcon_dev *extcon; 95 struct notifier_block host_nb; 96 }; 97 98 /* phy_power_on / off may sleep, so we use a workqueue */ 99 static void sunxi_musb_work(struct work_struct *work) 100 { 101 struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work); 102 bool vbus_on, phy_on; 103 104 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) 105 return; 106 107 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) { 108 struct musb *musb = glue->musb; 109 unsigned long flags; 110 u8 devctl; 111 112 spin_lock_irqsave(&musb->lock, flags); 113 114 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL); 115 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) { 116 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 117 musb->xceiv->otg->default_a = 1; 118 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 119 MUSB_HST_MODE(musb); 120 devctl |= MUSB_DEVCTL_SESSION; 121 } else { 122 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 123 musb->xceiv->otg->default_a = 0; 124 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 125 MUSB_DEV_MODE(musb); 126 devctl &= ~MUSB_DEVCTL_SESSION; 127 } 128 writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL); 129 130 spin_unlock_irqrestore(&musb->lock, flags); 131 } 132 133 vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 134 phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 135 136 if (phy_on != vbus_on) { 137 if (vbus_on) { 138 phy_power_on(glue->phy); 139 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 140 } else { 141 phy_power_off(glue->phy); 142 clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 143 } 144 } 145 146 if (test_and_clear_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags)) 147 phy_set_mode(glue->phy, glue->phy_mode); 148 } 149 150 static void sunxi_musb_set_vbus(struct musb *musb, int is_on) 151 { 152 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 153 154 if (is_on) { 155 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 156 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 157 } else { 158 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 159 } 160 161 schedule_work(&glue->work); 162 } 163 164 static void sunxi_musb_pre_root_reset_end(struct musb *musb) 165 { 166 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 167 168 sun4i_usb_phy_set_squelch_detect(glue->phy, false); 169 } 170 171 static void sunxi_musb_post_root_reset_end(struct musb *musb) 172 { 173 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 174 175 sun4i_usb_phy_set_squelch_detect(glue->phy, true); 176 } 177 178 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci) 179 { 180 struct musb *musb = __hci; 181 unsigned long flags; 182 183 spin_lock_irqsave(&musb->lock, flags); 184 185 musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB); 186 if (musb->int_usb) 187 writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB); 188 189 /* 190 * sunxi musb often signals babble on low / full speed device 191 * disconnect, without ever raising MUSB_INTR_DISCONNECT, since 192 * normally babble never happens treat it as disconnect. 193 */ 194 if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) { 195 musb->int_usb &= ~MUSB_INTR_BABBLE; 196 musb->int_usb |= MUSB_INTR_DISCONNECT; 197 } 198 199 if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) { 200 /* ep0 FADDR must be 0 when (re)entering peripheral mode */ 201 musb_ep_select(musb->mregs, 0); 202 musb_writeb(musb->mregs, MUSB_FADDR, 0); 203 } 204 205 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX); 206 if (musb->int_tx) 207 writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX); 208 209 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX); 210 if (musb->int_rx) 211 writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX); 212 213 musb_interrupt(musb); 214 215 spin_unlock_irqrestore(&musb->lock, flags); 216 217 return IRQ_HANDLED; 218 } 219 220 static int sunxi_musb_host_notifier(struct notifier_block *nb, 221 unsigned long event, void *ptr) 222 { 223 struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb); 224 225 if (event) 226 set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); 227 else 228 clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); 229 230 set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags); 231 schedule_work(&glue->work); 232 233 return NOTIFY_DONE; 234 } 235 236 static int sunxi_musb_init(struct musb *musb) 237 { 238 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 239 int ret; 240 241 sunxi_musb = musb; 242 musb->phy = glue->phy; 243 musb->xceiv = glue->xceiv; 244 245 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) { 246 ret = sunxi_sram_claim(musb->controller->parent); 247 if (ret) 248 return ret; 249 } 250 251 ret = clk_prepare_enable(glue->clk); 252 if (ret) 253 goto error_sram_release; 254 255 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { 256 ret = reset_control_deassert(glue->rst); 257 if (ret) 258 goto error_clk_disable; 259 } 260 261 writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0); 262 263 /* Register notifier before calling phy_init() */ 264 ret = extcon_register_notifier(glue->extcon, EXTCON_USB_HOST, 265 &glue->host_nb); 266 if (ret) 267 goto error_reset_assert; 268 269 ret = phy_init(glue->phy); 270 if (ret) 271 goto error_unregister_notifier; 272 273 musb->isr = sunxi_musb_interrupt; 274 275 /* Stop the musb-core from doing runtime pm (not supported on sunxi) */ 276 pm_runtime_get(musb->controller); 277 278 return 0; 279 280 error_unregister_notifier: 281 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST, 282 &glue->host_nb); 283 error_reset_assert: 284 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) 285 reset_control_assert(glue->rst); 286 error_clk_disable: 287 clk_disable_unprepare(glue->clk); 288 error_sram_release: 289 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) 290 sunxi_sram_release(musb->controller->parent); 291 return ret; 292 } 293 294 static int sunxi_musb_exit(struct musb *musb) 295 { 296 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 297 298 pm_runtime_put(musb->controller); 299 300 cancel_work_sync(&glue->work); 301 if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags)) 302 phy_power_off(glue->phy); 303 304 phy_exit(glue->phy); 305 306 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST, 307 &glue->host_nb); 308 309 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) 310 reset_control_assert(glue->rst); 311 312 clk_disable_unprepare(glue->clk); 313 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) 314 sunxi_sram_release(musb->controller->parent); 315 316 return 0; 317 } 318 319 static void sunxi_musb_enable(struct musb *musb) 320 { 321 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 322 323 glue->musb = musb; 324 325 /* musb_core does not call us in a balanced manner */ 326 if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) 327 return; 328 329 schedule_work(&glue->work); 330 } 331 332 static void sunxi_musb_disable(struct musb *musb) 333 { 334 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 335 336 clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags); 337 } 338 339 static struct dma_controller * 340 sunxi_musb_dma_controller_create(struct musb *musb, void __iomem *base) 341 { 342 return NULL; 343 } 344 345 static void sunxi_musb_dma_controller_destroy(struct dma_controller *c) 346 { 347 } 348 349 static int sunxi_musb_set_mode(struct musb *musb, u8 mode) 350 { 351 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 352 enum phy_mode new_mode; 353 354 switch (mode) { 355 case MUSB_HOST: 356 new_mode = PHY_MODE_USB_HOST; 357 break; 358 case MUSB_PERIPHERAL: 359 new_mode = PHY_MODE_USB_DEVICE; 360 break; 361 case MUSB_OTG: 362 new_mode = PHY_MODE_USB_OTG; 363 break; 364 default: 365 dev_err(musb->controller->parent, 366 "Error requested mode not supported by this kernel\n"); 367 return -EINVAL; 368 } 369 370 if (glue->phy_mode == new_mode) 371 return 0; 372 373 if (musb->port_mode != MUSB_PORT_MODE_DUAL_ROLE) { 374 dev_err(musb->controller->parent, 375 "Error changing modes is only supported in dual role mode\n"); 376 return -EINVAL; 377 } 378 379 if (musb->port1_status & USB_PORT_STAT_ENABLE) 380 musb_root_disconnect(musb); 381 382 /* 383 * phy_set_mode may sleep, and we're called with a spinlock held, 384 * so let sunxi_musb_work deal with it. 385 */ 386 glue->phy_mode = new_mode; 387 set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags); 388 schedule_work(&glue->work); 389 390 return 0; 391 } 392 393 /* 394 * sunxi musb register layout 395 * 0x00 - 0x17 fifo regs, 1 long per fifo 396 * 0x40 - 0x57 generic control regs (power - frame) 397 * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed) 398 * 0x90 - 0x97 fifo control regs (indexed) 399 * 0x98 - 0x9f multipoint / busctl regs (indexed) 400 * 0xc0 configdata reg 401 */ 402 403 static u32 sunxi_musb_fifo_offset(u8 epnum) 404 { 405 return (epnum * 4); 406 } 407 408 static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset) 409 { 410 WARN_ONCE(offset != 0, 411 "sunxi_musb_ep_offset called with non 0 offset\n"); 412 413 return 0x80; /* indexed, so ignore epnum */ 414 } 415 416 static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset) 417 { 418 return SUNXI_MUSB_TXFUNCADDR + offset; 419 } 420 421 static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset) 422 { 423 struct sunxi_glue *glue; 424 425 if (addr == sunxi_musb->mregs) { 426 /* generic control or fifo control reg access */ 427 switch (offset) { 428 case MUSB_FADDR: 429 return readb(addr + SUNXI_MUSB_FADDR); 430 case MUSB_POWER: 431 return readb(addr + SUNXI_MUSB_POWER); 432 case MUSB_INTRUSB: 433 return readb(addr + SUNXI_MUSB_INTRUSB); 434 case MUSB_INTRUSBE: 435 return readb(addr + SUNXI_MUSB_INTRUSBE); 436 case MUSB_INDEX: 437 return readb(addr + SUNXI_MUSB_INDEX); 438 case MUSB_TESTMODE: 439 return 0; /* No testmode on sunxi */ 440 case MUSB_DEVCTL: 441 return readb(addr + SUNXI_MUSB_DEVCTL); 442 case MUSB_TXFIFOSZ: 443 return readb(addr + SUNXI_MUSB_TXFIFOSZ); 444 case MUSB_RXFIFOSZ: 445 return readb(addr + SUNXI_MUSB_RXFIFOSZ); 446 case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */ 447 glue = dev_get_drvdata(sunxi_musb->controller->parent); 448 /* A33 saves a reg, and we get to hardcode this */ 449 if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, 450 &glue->flags)) 451 return 0xde; 452 453 return readb(addr + SUNXI_MUSB_CONFIGDATA); 454 /* Offset for these is fixed by sunxi_musb_busctl_offset() */ 455 case SUNXI_MUSB_TXFUNCADDR: 456 case SUNXI_MUSB_TXHUBADDR: 457 case SUNXI_MUSB_TXHUBPORT: 458 case SUNXI_MUSB_RXFUNCADDR: 459 case SUNXI_MUSB_RXHUBADDR: 460 case SUNXI_MUSB_RXHUBPORT: 461 /* multipoint / busctl reg access */ 462 return readb(addr + offset); 463 default: 464 dev_err(sunxi_musb->controller->parent, 465 "Error unknown readb offset %u\n", offset); 466 return 0; 467 } 468 } else if (addr == (sunxi_musb->mregs + 0x80)) { 469 /* ep control reg access */ 470 /* sunxi has a 2 byte hole before the txtype register */ 471 if (offset >= MUSB_TXTYPE) 472 offset += 2; 473 return readb(addr + offset); 474 } 475 476 dev_err(sunxi_musb->controller->parent, 477 "Error unknown readb at 0x%x bytes offset\n", 478 (int)(addr - sunxi_musb->mregs)); 479 return 0; 480 } 481 482 static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data) 483 { 484 if (addr == sunxi_musb->mregs) { 485 /* generic control or fifo control reg access */ 486 switch (offset) { 487 case MUSB_FADDR: 488 return writeb(data, addr + SUNXI_MUSB_FADDR); 489 case MUSB_POWER: 490 return writeb(data, addr + SUNXI_MUSB_POWER); 491 case MUSB_INTRUSB: 492 return writeb(data, addr + SUNXI_MUSB_INTRUSB); 493 case MUSB_INTRUSBE: 494 return writeb(data, addr + SUNXI_MUSB_INTRUSBE); 495 case MUSB_INDEX: 496 return writeb(data, addr + SUNXI_MUSB_INDEX); 497 case MUSB_TESTMODE: 498 if (data) 499 dev_warn(sunxi_musb->controller->parent, 500 "sunxi-musb does not have testmode\n"); 501 return; 502 case MUSB_DEVCTL: 503 return writeb(data, addr + SUNXI_MUSB_DEVCTL); 504 case MUSB_TXFIFOSZ: 505 return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ); 506 case MUSB_RXFIFOSZ: 507 return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ); 508 /* Offset for these is fixed by sunxi_musb_busctl_offset() */ 509 case SUNXI_MUSB_TXFUNCADDR: 510 case SUNXI_MUSB_TXHUBADDR: 511 case SUNXI_MUSB_TXHUBPORT: 512 case SUNXI_MUSB_RXFUNCADDR: 513 case SUNXI_MUSB_RXHUBADDR: 514 case SUNXI_MUSB_RXHUBPORT: 515 /* multipoint / busctl reg access */ 516 return writeb(data, addr + offset); 517 default: 518 dev_err(sunxi_musb->controller->parent, 519 "Error unknown writeb offset %u\n", offset); 520 return; 521 } 522 } else if (addr == (sunxi_musb->mregs + 0x80)) { 523 /* ep control reg access */ 524 if (offset >= MUSB_TXTYPE) 525 offset += 2; 526 return writeb(data, addr + offset); 527 } 528 529 dev_err(sunxi_musb->controller->parent, 530 "Error unknown writeb at 0x%x bytes offset\n", 531 (int)(addr - sunxi_musb->mregs)); 532 } 533 534 static u16 sunxi_musb_readw(const void __iomem *addr, unsigned offset) 535 { 536 if (addr == sunxi_musb->mregs) { 537 /* generic control or fifo control reg access */ 538 switch (offset) { 539 case MUSB_INTRTX: 540 return readw(addr + SUNXI_MUSB_INTRTX); 541 case MUSB_INTRRX: 542 return readw(addr + SUNXI_MUSB_INTRRX); 543 case MUSB_INTRTXE: 544 return readw(addr + SUNXI_MUSB_INTRTXE); 545 case MUSB_INTRRXE: 546 return readw(addr + SUNXI_MUSB_INTRRXE); 547 case MUSB_FRAME: 548 return readw(addr + SUNXI_MUSB_FRAME); 549 case MUSB_TXFIFOADD: 550 return readw(addr + SUNXI_MUSB_TXFIFOADD); 551 case MUSB_RXFIFOADD: 552 return readw(addr + SUNXI_MUSB_RXFIFOADD); 553 case MUSB_HWVERS: 554 return 0; /* sunxi musb version is not known */ 555 default: 556 dev_err(sunxi_musb->controller->parent, 557 "Error unknown readw offset %u\n", offset); 558 return 0; 559 } 560 } else if (addr == (sunxi_musb->mregs + 0x80)) { 561 /* ep control reg access */ 562 return readw(addr + offset); 563 } 564 565 dev_err(sunxi_musb->controller->parent, 566 "Error unknown readw at 0x%x bytes offset\n", 567 (int)(addr - sunxi_musb->mregs)); 568 return 0; 569 } 570 571 static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data) 572 { 573 if (addr == sunxi_musb->mregs) { 574 /* generic control or fifo control reg access */ 575 switch (offset) { 576 case MUSB_INTRTX: 577 return writew(data, addr + SUNXI_MUSB_INTRTX); 578 case MUSB_INTRRX: 579 return writew(data, addr + SUNXI_MUSB_INTRRX); 580 case MUSB_INTRTXE: 581 return writew(data, addr + SUNXI_MUSB_INTRTXE); 582 case MUSB_INTRRXE: 583 return writew(data, addr + SUNXI_MUSB_INTRRXE); 584 case MUSB_FRAME: 585 return writew(data, addr + SUNXI_MUSB_FRAME); 586 case MUSB_TXFIFOADD: 587 return writew(data, addr + SUNXI_MUSB_TXFIFOADD); 588 case MUSB_RXFIFOADD: 589 return writew(data, addr + SUNXI_MUSB_RXFIFOADD); 590 default: 591 dev_err(sunxi_musb->controller->parent, 592 "Error unknown writew offset %u\n", offset); 593 return; 594 } 595 } else if (addr == (sunxi_musb->mregs + 0x80)) { 596 /* ep control reg access */ 597 return writew(data, addr + offset); 598 } 599 600 dev_err(sunxi_musb->controller->parent, 601 "Error unknown writew at 0x%x bytes offset\n", 602 (int)(addr - sunxi_musb->mregs)); 603 } 604 605 static const struct musb_platform_ops sunxi_musb_ops = { 606 .quirks = MUSB_INDEXED_EP, 607 .init = sunxi_musb_init, 608 .exit = sunxi_musb_exit, 609 .enable = sunxi_musb_enable, 610 .disable = sunxi_musb_disable, 611 .fifo_offset = sunxi_musb_fifo_offset, 612 .ep_offset = sunxi_musb_ep_offset, 613 .busctl_offset = sunxi_musb_busctl_offset, 614 .readb = sunxi_musb_readb, 615 .writeb = sunxi_musb_writeb, 616 .readw = sunxi_musb_readw, 617 .writew = sunxi_musb_writew, 618 .dma_init = sunxi_musb_dma_controller_create, 619 .dma_exit = sunxi_musb_dma_controller_destroy, 620 .set_mode = sunxi_musb_set_mode, 621 .set_vbus = sunxi_musb_set_vbus, 622 .pre_root_reset_end = sunxi_musb_pre_root_reset_end, 623 .post_root_reset_end = sunxi_musb_post_root_reset_end, 624 }; 625 626 /* Allwinner OTG supports up to 5 endpoints */ 627 #define SUNXI_MUSB_MAX_EP_NUM 6 628 #define SUNXI_MUSB_RAM_BITS 11 629 630 static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = { 631 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), 632 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), 633 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), 634 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), 635 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), 636 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), 637 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), 638 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), 639 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512), 640 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512), 641 }; 642 643 static struct musb_hdrc_config sunxi_musb_hdrc_config = { 644 .fifo_cfg = sunxi_musb_mode_cfg, 645 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg), 646 .multipoint = true, 647 .dyn_fifo = true, 648 .soft_con = true, 649 .num_eps = SUNXI_MUSB_MAX_EP_NUM, 650 .ram_bits = SUNXI_MUSB_RAM_BITS, 651 .dma = 0, 652 }; 653 654 static int sunxi_musb_probe(struct platform_device *pdev) 655 { 656 struct musb_hdrc_platform_data pdata; 657 struct platform_device_info pinfo; 658 struct sunxi_glue *glue; 659 struct device_node *np = pdev->dev.of_node; 660 int ret; 661 662 if (!np) { 663 dev_err(&pdev->dev, "Error no device tree node found\n"); 664 return -EINVAL; 665 } 666 667 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 668 if (!glue) 669 return -ENOMEM; 670 671 memset(&pdata, 0, sizeof(pdata)); 672 switch (usb_get_dr_mode(&pdev->dev)) { 673 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST 674 case USB_DR_MODE_HOST: 675 pdata.mode = MUSB_PORT_MODE_HOST; 676 glue->phy_mode = PHY_MODE_USB_HOST; 677 break; 678 #endif 679 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_GADGET 680 case USB_DR_MODE_PERIPHERAL: 681 pdata.mode = MUSB_PORT_MODE_GADGET; 682 glue->phy_mode = PHY_MODE_USB_DEVICE; 683 break; 684 #endif 685 #ifdef CONFIG_USB_MUSB_DUAL_ROLE 686 case USB_DR_MODE_OTG: 687 pdata.mode = MUSB_PORT_MODE_DUAL_ROLE; 688 glue->phy_mode = PHY_MODE_USB_OTG; 689 break; 690 #endif 691 default: 692 dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n"); 693 return -EINVAL; 694 } 695 pdata.platform_ops = &sunxi_musb_ops; 696 pdata.config = &sunxi_musb_hdrc_config; 697 698 glue->dev = &pdev->dev; 699 INIT_WORK(&glue->work, sunxi_musb_work); 700 glue->host_nb.notifier_call = sunxi_musb_host_notifier; 701 702 if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb")) 703 set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags); 704 705 if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb")) 706 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags); 707 708 if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb")) { 709 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags); 710 set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags); 711 } 712 713 glue->clk = devm_clk_get(&pdev->dev, NULL); 714 if (IS_ERR(glue->clk)) { 715 dev_err(&pdev->dev, "Error getting clock: %ld\n", 716 PTR_ERR(glue->clk)); 717 return PTR_ERR(glue->clk); 718 } 719 720 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { 721 glue->rst = devm_reset_control_get(&pdev->dev, NULL); 722 if (IS_ERR(glue->rst)) { 723 if (PTR_ERR(glue->rst) == -EPROBE_DEFER) 724 return -EPROBE_DEFER; 725 dev_err(&pdev->dev, "Error getting reset %ld\n", 726 PTR_ERR(glue->rst)); 727 return PTR_ERR(glue->rst); 728 } 729 } 730 731 glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0); 732 if (IS_ERR(glue->extcon)) { 733 if (PTR_ERR(glue->extcon) == -EPROBE_DEFER) 734 return -EPROBE_DEFER; 735 dev_err(&pdev->dev, "Invalid or missing extcon\n"); 736 return PTR_ERR(glue->extcon); 737 } 738 739 glue->phy = devm_phy_get(&pdev->dev, "usb"); 740 if (IS_ERR(glue->phy)) { 741 if (PTR_ERR(glue->phy) == -EPROBE_DEFER) 742 return -EPROBE_DEFER; 743 dev_err(&pdev->dev, "Error getting phy %ld\n", 744 PTR_ERR(glue->phy)); 745 return PTR_ERR(glue->phy); 746 } 747 748 glue->usb_phy = usb_phy_generic_register(); 749 if (IS_ERR(glue->usb_phy)) { 750 dev_err(&pdev->dev, "Error registering usb-phy %ld\n", 751 PTR_ERR(glue->usb_phy)); 752 return PTR_ERR(glue->usb_phy); 753 } 754 755 glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2); 756 if (IS_ERR(glue->xceiv)) { 757 ret = PTR_ERR(glue->xceiv); 758 dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret); 759 goto err_unregister_usb_phy; 760 } 761 762 platform_set_drvdata(pdev, glue); 763 764 memset(&pinfo, 0, sizeof(pinfo)); 765 pinfo.name = "musb-hdrc"; 766 pinfo.id = PLATFORM_DEVID_AUTO; 767 pinfo.parent = &pdev->dev; 768 pinfo.res = pdev->resource; 769 pinfo.num_res = pdev->num_resources; 770 pinfo.data = &pdata; 771 pinfo.size_data = sizeof(pdata); 772 773 glue->musb_pdev = platform_device_register_full(&pinfo); 774 if (IS_ERR(glue->musb_pdev)) { 775 ret = PTR_ERR(glue->musb_pdev); 776 dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret); 777 goto err_unregister_usb_phy; 778 } 779 780 return 0; 781 782 err_unregister_usb_phy: 783 usb_phy_generic_unregister(glue->usb_phy); 784 return ret; 785 } 786 787 static int sunxi_musb_remove(struct platform_device *pdev) 788 { 789 struct sunxi_glue *glue = platform_get_drvdata(pdev); 790 struct platform_device *usb_phy = glue->usb_phy; 791 792 platform_device_unregister(glue->musb_pdev); 793 usb_phy_generic_unregister(usb_phy); 794 795 return 0; 796 } 797 798 static const struct of_device_id sunxi_musb_match[] = { 799 { .compatible = "allwinner,sun4i-a10-musb", }, 800 { .compatible = "allwinner,sun6i-a31-musb", }, 801 { .compatible = "allwinner,sun8i-a33-musb", }, 802 {} 803 }; 804 MODULE_DEVICE_TABLE(of, sunxi_musb_match); 805 806 static struct platform_driver sunxi_musb_driver = { 807 .probe = sunxi_musb_probe, 808 .remove = sunxi_musb_remove, 809 .driver = { 810 .name = "musb-sunxi", 811 .of_match_table = sunxi_musb_match, 812 }, 813 }; 814 module_platform_driver(sunxi_musb_driver); 815 816 MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer"); 817 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); 818 MODULE_LICENSE("GPL v2"); 819