1 /* 2 * Allwinner sun4i MUSB Glue Layer 3 * 4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> 5 * 6 * Based on code from 7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/clk.h> 21 #include <linux/err.h> 22 #include <linux/extcon.h> 23 #include <linux/io.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/phy/phy-sun4i-usb.h> 28 #include <linux/platform_device.h> 29 #include <linux/reset.h> 30 #include <linux/soc/sunxi/sunxi_sram.h> 31 #include <linux/usb/musb.h> 32 #include <linux/usb/of.h> 33 #include <linux/usb/usb_phy_generic.h> 34 #include <linux/workqueue.h> 35 #include "musb_core.h" 36 37 /* 38 * Register offsets, note sunxi musb has a different layout then most 39 * musb implementations, we translate the layout in musb_readb & friends. 40 */ 41 #define SUNXI_MUSB_POWER 0x0040 42 #define SUNXI_MUSB_DEVCTL 0x0041 43 #define SUNXI_MUSB_INDEX 0x0042 44 #define SUNXI_MUSB_VEND0 0x0043 45 #define SUNXI_MUSB_INTRTX 0x0044 46 #define SUNXI_MUSB_INTRRX 0x0046 47 #define SUNXI_MUSB_INTRTXE 0x0048 48 #define SUNXI_MUSB_INTRRXE 0x004a 49 #define SUNXI_MUSB_INTRUSB 0x004c 50 #define SUNXI_MUSB_INTRUSBE 0x0050 51 #define SUNXI_MUSB_FRAME 0x0054 52 #define SUNXI_MUSB_TXFIFOSZ 0x0090 53 #define SUNXI_MUSB_TXFIFOADD 0x0092 54 #define SUNXI_MUSB_RXFIFOSZ 0x0094 55 #define SUNXI_MUSB_RXFIFOADD 0x0096 56 #define SUNXI_MUSB_FADDR 0x0098 57 #define SUNXI_MUSB_TXFUNCADDR 0x0098 58 #define SUNXI_MUSB_TXHUBADDR 0x009a 59 #define SUNXI_MUSB_TXHUBPORT 0x009b 60 #define SUNXI_MUSB_RXFUNCADDR 0x009c 61 #define SUNXI_MUSB_RXHUBADDR 0x009e 62 #define SUNXI_MUSB_RXHUBPORT 0x009f 63 #define SUNXI_MUSB_CONFIGDATA 0x00c0 64 65 /* VEND0 bits */ 66 #define SUNXI_MUSB_VEND0_PIO_MODE 0 67 68 /* flags */ 69 #define SUNXI_MUSB_FL_ENABLED 0 70 #define SUNXI_MUSB_FL_HOSTMODE 1 71 #define SUNXI_MUSB_FL_HOSTMODE_PEND 2 72 #define SUNXI_MUSB_FL_VBUS_ON 3 73 #define SUNXI_MUSB_FL_PHY_ON 4 74 #define SUNXI_MUSB_FL_HAS_SRAM 5 75 #define SUNXI_MUSB_FL_HAS_RESET 6 76 #define SUNXI_MUSB_FL_NO_CONFIGDATA 7 77 78 /* Our read/write methods need access and do not get passed in a musb ref :| */ 79 static struct musb *sunxi_musb; 80 81 struct sunxi_glue { 82 struct device *dev; 83 struct platform_device *musb; 84 struct clk *clk; 85 struct reset_control *rst; 86 struct phy *phy; 87 struct platform_device *usb_phy; 88 struct usb_phy *xceiv; 89 unsigned long flags; 90 struct work_struct work; 91 struct extcon_dev *extcon; 92 struct notifier_block host_nb; 93 }; 94 95 /* phy_power_on / off may sleep, so we use a workqueue */ 96 static void sunxi_musb_work(struct work_struct *work) 97 { 98 struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work); 99 bool vbus_on, phy_on; 100 101 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) 102 return; 103 104 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) { 105 struct musb *musb = platform_get_drvdata(glue->musb); 106 unsigned long flags; 107 u8 devctl; 108 109 spin_lock_irqsave(&musb->lock, flags); 110 111 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL); 112 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) { 113 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 114 musb->xceiv->otg->default_a = 1; 115 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 116 MUSB_HST_MODE(musb); 117 devctl |= MUSB_DEVCTL_SESSION; 118 } else { 119 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 120 musb->xceiv->otg->default_a = 0; 121 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 122 MUSB_DEV_MODE(musb); 123 devctl &= ~MUSB_DEVCTL_SESSION; 124 } 125 writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL); 126 127 spin_unlock_irqrestore(&musb->lock, flags); 128 } 129 130 vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 131 phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 132 133 if (phy_on != vbus_on) { 134 if (vbus_on) { 135 phy_power_on(glue->phy); 136 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 137 } else { 138 phy_power_off(glue->phy); 139 clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 140 } 141 } 142 } 143 144 static void sunxi_musb_set_vbus(struct musb *musb, int is_on) 145 { 146 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 147 148 if (is_on) 149 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 150 else 151 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 152 153 schedule_work(&glue->work); 154 } 155 156 static void sunxi_musb_pre_root_reset_end(struct musb *musb) 157 { 158 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 159 160 sun4i_usb_phy_set_squelch_detect(glue->phy, false); 161 } 162 163 static void sunxi_musb_post_root_reset_end(struct musb *musb) 164 { 165 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 166 167 sun4i_usb_phy_set_squelch_detect(glue->phy, true); 168 } 169 170 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci) 171 { 172 struct musb *musb = __hci; 173 unsigned long flags; 174 175 spin_lock_irqsave(&musb->lock, flags); 176 177 musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB); 178 if (musb->int_usb) 179 writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB); 180 181 /* 182 * sunxi musb often signals babble on low / full speed device 183 * disconnect, without ever raising MUSB_INTR_DISCONNECT, since 184 * normally babble never happens treat it as disconnect. 185 */ 186 if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) { 187 musb->int_usb &= ~MUSB_INTR_BABBLE; 188 musb->int_usb |= MUSB_INTR_DISCONNECT; 189 } 190 191 if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) { 192 /* ep0 FADDR must be 0 when (re)entering peripheral mode */ 193 musb_ep_select(musb->mregs, 0); 194 musb_writeb(musb->mregs, MUSB_FADDR, 0); 195 } 196 197 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX); 198 if (musb->int_tx) 199 writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX); 200 201 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX); 202 if (musb->int_rx) 203 writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX); 204 205 musb_interrupt(musb); 206 207 spin_unlock_irqrestore(&musb->lock, flags); 208 209 return IRQ_HANDLED; 210 } 211 212 static int sunxi_musb_host_notifier(struct notifier_block *nb, 213 unsigned long event, void *ptr) 214 { 215 struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb); 216 217 if (event) 218 set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); 219 else 220 clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); 221 222 set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags); 223 schedule_work(&glue->work); 224 225 return NOTIFY_DONE; 226 } 227 228 static int sunxi_musb_init(struct musb *musb) 229 { 230 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 231 int ret; 232 233 sunxi_musb = musb; 234 musb->phy = glue->phy; 235 musb->xceiv = glue->xceiv; 236 237 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) { 238 ret = sunxi_sram_claim(musb->controller->parent); 239 if (ret) 240 return ret; 241 } 242 243 ret = clk_prepare_enable(glue->clk); 244 if (ret) 245 goto error_sram_release; 246 247 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { 248 ret = reset_control_deassert(glue->rst); 249 if (ret) 250 goto error_clk_disable; 251 } 252 253 writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0); 254 255 /* Register notifier before calling phy_init() */ 256 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE) { 257 ret = extcon_register_notifier(glue->extcon, EXTCON_USB_HOST, 258 &glue->host_nb); 259 if (ret) 260 goto error_reset_assert; 261 } 262 263 ret = phy_init(glue->phy); 264 if (ret) 265 goto error_unregister_notifier; 266 267 if (musb->port_mode == MUSB_PORT_MODE_HOST) { 268 ret = phy_power_on(glue->phy); 269 if (ret) 270 goto error_phy_exit; 271 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 272 /* Stop musb work from turning vbus off again */ 273 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 274 } 275 276 musb->isr = sunxi_musb_interrupt; 277 278 /* Stop the musb-core from doing runtime pm (not supported on sunxi) */ 279 pm_runtime_get(musb->controller); 280 281 return 0; 282 283 error_phy_exit: 284 phy_exit(glue->phy); 285 error_unregister_notifier: 286 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE) 287 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST, 288 &glue->host_nb); 289 error_reset_assert: 290 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) 291 reset_control_assert(glue->rst); 292 error_clk_disable: 293 clk_disable_unprepare(glue->clk); 294 error_sram_release: 295 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) 296 sunxi_sram_release(musb->controller->parent); 297 return ret; 298 } 299 300 static int sunxi_musb_exit(struct musb *musb) 301 { 302 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 303 304 pm_runtime_put(musb->controller); 305 306 cancel_work_sync(&glue->work); 307 if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags)) 308 phy_power_off(glue->phy); 309 310 phy_exit(glue->phy); 311 312 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE) 313 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST, 314 &glue->host_nb); 315 316 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) 317 reset_control_assert(glue->rst); 318 319 clk_disable_unprepare(glue->clk); 320 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) 321 sunxi_sram_release(musb->controller->parent); 322 323 return 0; 324 } 325 326 static void sunxi_musb_enable(struct musb *musb) 327 { 328 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 329 330 /* musb_core does not call us in a balanced manner */ 331 if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) 332 return; 333 334 schedule_work(&glue->work); 335 } 336 337 static void sunxi_musb_disable(struct musb *musb) 338 { 339 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 340 341 clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags); 342 } 343 344 struct dma_controller *sunxi_musb_dma_controller_create(struct musb *musb, 345 void __iomem *base) 346 { 347 return NULL; 348 } 349 350 void sunxi_musb_dma_controller_destroy(struct dma_controller *c) 351 { 352 } 353 354 /* 355 * sunxi musb register layout 356 * 0x00 - 0x17 fifo regs, 1 long per fifo 357 * 0x40 - 0x57 generic control regs (power - frame) 358 * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed) 359 * 0x90 - 0x97 fifo control regs (indexed) 360 * 0x98 - 0x9f multipoint / busctl regs (indexed) 361 * 0xc0 configdata reg 362 */ 363 364 static u32 sunxi_musb_fifo_offset(u8 epnum) 365 { 366 return (epnum * 4); 367 } 368 369 static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset) 370 { 371 WARN_ONCE(offset != 0, 372 "sunxi_musb_ep_offset called with non 0 offset\n"); 373 374 return 0x80; /* indexed, so ignore epnum */ 375 } 376 377 static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset) 378 { 379 return SUNXI_MUSB_TXFUNCADDR + offset; 380 } 381 382 static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset) 383 { 384 struct sunxi_glue *glue; 385 386 if (addr == sunxi_musb->mregs) { 387 /* generic control or fifo control reg access */ 388 switch (offset) { 389 case MUSB_FADDR: 390 return readb(addr + SUNXI_MUSB_FADDR); 391 case MUSB_POWER: 392 return readb(addr + SUNXI_MUSB_POWER); 393 case MUSB_INTRUSB: 394 return readb(addr + SUNXI_MUSB_INTRUSB); 395 case MUSB_INTRUSBE: 396 return readb(addr + SUNXI_MUSB_INTRUSBE); 397 case MUSB_INDEX: 398 return readb(addr + SUNXI_MUSB_INDEX); 399 case MUSB_TESTMODE: 400 return 0; /* No testmode on sunxi */ 401 case MUSB_DEVCTL: 402 return readb(addr + SUNXI_MUSB_DEVCTL); 403 case MUSB_TXFIFOSZ: 404 return readb(addr + SUNXI_MUSB_TXFIFOSZ); 405 case MUSB_RXFIFOSZ: 406 return readb(addr + SUNXI_MUSB_RXFIFOSZ); 407 case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */ 408 glue = dev_get_drvdata(sunxi_musb->controller->parent); 409 /* A33 saves a reg, and we get to hardcode this */ 410 if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, 411 &glue->flags)) 412 return 0xde; 413 414 return readb(addr + SUNXI_MUSB_CONFIGDATA); 415 /* Offset for these is fixed by sunxi_musb_busctl_offset() */ 416 case SUNXI_MUSB_TXFUNCADDR: 417 case SUNXI_MUSB_TXHUBADDR: 418 case SUNXI_MUSB_TXHUBPORT: 419 case SUNXI_MUSB_RXFUNCADDR: 420 case SUNXI_MUSB_RXHUBADDR: 421 case SUNXI_MUSB_RXHUBPORT: 422 /* multipoint / busctl reg access */ 423 return readb(addr + offset); 424 default: 425 dev_err(sunxi_musb->controller->parent, 426 "Error unknown readb offset %u\n", offset); 427 return 0; 428 } 429 } else if (addr == (sunxi_musb->mregs + 0x80)) { 430 /* ep control reg access */ 431 /* sunxi has a 2 byte hole before the txtype register */ 432 if (offset >= MUSB_TXTYPE) 433 offset += 2; 434 return readb(addr + offset); 435 } 436 437 dev_err(sunxi_musb->controller->parent, 438 "Error unknown readb at 0x%x bytes offset\n", 439 (int)(addr - sunxi_musb->mregs)); 440 return 0; 441 } 442 443 static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data) 444 { 445 if (addr == sunxi_musb->mregs) { 446 /* generic control or fifo control reg access */ 447 switch (offset) { 448 case MUSB_FADDR: 449 return writeb(data, addr + SUNXI_MUSB_FADDR); 450 case MUSB_POWER: 451 return writeb(data, addr + SUNXI_MUSB_POWER); 452 case MUSB_INTRUSB: 453 return writeb(data, addr + SUNXI_MUSB_INTRUSB); 454 case MUSB_INTRUSBE: 455 return writeb(data, addr + SUNXI_MUSB_INTRUSBE); 456 case MUSB_INDEX: 457 return writeb(data, addr + SUNXI_MUSB_INDEX); 458 case MUSB_TESTMODE: 459 if (data) 460 dev_warn(sunxi_musb->controller->parent, 461 "sunxi-musb does not have testmode\n"); 462 return; 463 case MUSB_DEVCTL: 464 return writeb(data, addr + SUNXI_MUSB_DEVCTL); 465 case MUSB_TXFIFOSZ: 466 return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ); 467 case MUSB_RXFIFOSZ: 468 return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ); 469 /* Offset for these is fixed by sunxi_musb_busctl_offset() */ 470 case SUNXI_MUSB_TXFUNCADDR: 471 case SUNXI_MUSB_TXHUBADDR: 472 case SUNXI_MUSB_TXHUBPORT: 473 case SUNXI_MUSB_RXFUNCADDR: 474 case SUNXI_MUSB_RXHUBADDR: 475 case SUNXI_MUSB_RXHUBPORT: 476 /* multipoint / busctl reg access */ 477 return writeb(data, addr + offset); 478 default: 479 dev_err(sunxi_musb->controller->parent, 480 "Error unknown writeb offset %u\n", offset); 481 return; 482 } 483 } else if (addr == (sunxi_musb->mregs + 0x80)) { 484 /* ep control reg access */ 485 if (offset >= MUSB_TXTYPE) 486 offset += 2; 487 return writeb(data, addr + offset); 488 } 489 490 dev_err(sunxi_musb->controller->parent, 491 "Error unknown writeb at 0x%x bytes offset\n", 492 (int)(addr - sunxi_musb->mregs)); 493 } 494 495 static u16 sunxi_musb_readw(const void __iomem *addr, unsigned offset) 496 { 497 if (addr == sunxi_musb->mregs) { 498 /* generic control or fifo control reg access */ 499 switch (offset) { 500 case MUSB_INTRTX: 501 return readw(addr + SUNXI_MUSB_INTRTX); 502 case MUSB_INTRRX: 503 return readw(addr + SUNXI_MUSB_INTRRX); 504 case MUSB_INTRTXE: 505 return readw(addr + SUNXI_MUSB_INTRTXE); 506 case MUSB_INTRRXE: 507 return readw(addr + SUNXI_MUSB_INTRRXE); 508 case MUSB_FRAME: 509 return readw(addr + SUNXI_MUSB_FRAME); 510 case MUSB_TXFIFOADD: 511 return readw(addr + SUNXI_MUSB_TXFIFOADD); 512 case MUSB_RXFIFOADD: 513 return readw(addr + SUNXI_MUSB_RXFIFOADD); 514 case MUSB_HWVERS: 515 return 0; /* sunxi musb version is not known */ 516 default: 517 dev_err(sunxi_musb->controller->parent, 518 "Error unknown readw offset %u\n", offset); 519 return 0; 520 } 521 } else if (addr == (sunxi_musb->mregs + 0x80)) { 522 /* ep control reg access */ 523 return readw(addr + offset); 524 } 525 526 dev_err(sunxi_musb->controller->parent, 527 "Error unknown readw at 0x%x bytes offset\n", 528 (int)(addr - sunxi_musb->mregs)); 529 return 0; 530 } 531 532 static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data) 533 { 534 if (addr == sunxi_musb->mregs) { 535 /* generic control or fifo control reg access */ 536 switch (offset) { 537 case MUSB_INTRTX: 538 return writew(data, addr + SUNXI_MUSB_INTRTX); 539 case MUSB_INTRRX: 540 return writew(data, addr + SUNXI_MUSB_INTRRX); 541 case MUSB_INTRTXE: 542 return writew(data, addr + SUNXI_MUSB_INTRTXE); 543 case MUSB_INTRRXE: 544 return writew(data, addr + SUNXI_MUSB_INTRRXE); 545 case MUSB_FRAME: 546 return writew(data, addr + SUNXI_MUSB_FRAME); 547 case MUSB_TXFIFOADD: 548 return writew(data, addr + SUNXI_MUSB_TXFIFOADD); 549 case MUSB_RXFIFOADD: 550 return writew(data, addr + SUNXI_MUSB_RXFIFOADD); 551 default: 552 dev_err(sunxi_musb->controller->parent, 553 "Error unknown writew offset %u\n", offset); 554 return; 555 } 556 } else if (addr == (sunxi_musb->mregs + 0x80)) { 557 /* ep control reg access */ 558 return writew(data, addr + offset); 559 } 560 561 dev_err(sunxi_musb->controller->parent, 562 "Error unknown writew at 0x%x bytes offset\n", 563 (int)(addr - sunxi_musb->mregs)); 564 } 565 566 static const struct musb_platform_ops sunxi_musb_ops = { 567 .quirks = MUSB_INDEXED_EP, 568 .init = sunxi_musb_init, 569 .exit = sunxi_musb_exit, 570 .enable = sunxi_musb_enable, 571 .disable = sunxi_musb_disable, 572 .fifo_offset = sunxi_musb_fifo_offset, 573 .ep_offset = sunxi_musb_ep_offset, 574 .busctl_offset = sunxi_musb_busctl_offset, 575 .readb = sunxi_musb_readb, 576 .writeb = sunxi_musb_writeb, 577 .readw = sunxi_musb_readw, 578 .writew = sunxi_musb_writew, 579 .dma_init = sunxi_musb_dma_controller_create, 580 .dma_exit = sunxi_musb_dma_controller_destroy, 581 .set_vbus = sunxi_musb_set_vbus, 582 .pre_root_reset_end = sunxi_musb_pre_root_reset_end, 583 .post_root_reset_end = sunxi_musb_post_root_reset_end, 584 }; 585 586 /* Allwinner OTG supports up to 5 endpoints */ 587 #define SUNXI_MUSB_MAX_EP_NUM 6 588 #define SUNXI_MUSB_RAM_BITS 11 589 590 static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = { 591 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), 592 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), 593 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), 594 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), 595 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), 596 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), 597 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), 598 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), 599 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512), 600 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512), 601 }; 602 603 static struct musb_hdrc_config sunxi_musb_hdrc_config = { 604 .fifo_cfg = sunxi_musb_mode_cfg, 605 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg), 606 .multipoint = true, 607 .dyn_fifo = true, 608 .soft_con = true, 609 .num_eps = SUNXI_MUSB_MAX_EP_NUM, 610 .ram_bits = SUNXI_MUSB_RAM_BITS, 611 .dma = 0, 612 }; 613 614 static int sunxi_musb_probe(struct platform_device *pdev) 615 { 616 struct musb_hdrc_platform_data pdata; 617 struct platform_device_info pinfo; 618 struct sunxi_glue *glue; 619 struct device_node *np = pdev->dev.of_node; 620 int ret; 621 622 if (!np) { 623 dev_err(&pdev->dev, "Error no device tree node found\n"); 624 return -EINVAL; 625 } 626 627 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 628 if (!glue) 629 return -ENOMEM; 630 631 memset(&pdata, 0, sizeof(pdata)); 632 switch (usb_get_dr_mode(&pdev->dev)) { 633 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST 634 case USB_DR_MODE_HOST: 635 pdata.mode = MUSB_PORT_MODE_HOST; 636 break; 637 #endif 638 #ifdef CONFIG_USB_MUSB_DUAL_ROLE 639 case USB_DR_MODE_OTG: 640 glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0); 641 if (IS_ERR(glue->extcon)) { 642 if (PTR_ERR(glue->extcon) == -EPROBE_DEFER) 643 return -EPROBE_DEFER; 644 dev_err(&pdev->dev, "Invalid or missing extcon\n"); 645 return PTR_ERR(glue->extcon); 646 } 647 pdata.mode = MUSB_PORT_MODE_DUAL_ROLE; 648 break; 649 #endif 650 default: 651 dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n"); 652 return -EINVAL; 653 } 654 pdata.platform_ops = &sunxi_musb_ops; 655 pdata.config = &sunxi_musb_hdrc_config; 656 657 glue->dev = &pdev->dev; 658 INIT_WORK(&glue->work, sunxi_musb_work); 659 glue->host_nb.notifier_call = sunxi_musb_host_notifier; 660 661 if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb")) 662 set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags); 663 664 if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb")) 665 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags); 666 667 if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb")) { 668 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags); 669 set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags); 670 } 671 672 glue->clk = devm_clk_get(&pdev->dev, NULL); 673 if (IS_ERR(glue->clk)) { 674 dev_err(&pdev->dev, "Error getting clock: %ld\n", 675 PTR_ERR(glue->clk)); 676 return PTR_ERR(glue->clk); 677 } 678 679 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { 680 glue->rst = devm_reset_control_get(&pdev->dev, NULL); 681 if (IS_ERR(glue->rst)) { 682 if (PTR_ERR(glue->rst) == -EPROBE_DEFER) 683 return -EPROBE_DEFER; 684 dev_err(&pdev->dev, "Error getting reset %ld\n", 685 PTR_ERR(glue->rst)); 686 return PTR_ERR(glue->rst); 687 } 688 } 689 690 glue->phy = devm_phy_get(&pdev->dev, "usb"); 691 if (IS_ERR(glue->phy)) { 692 if (PTR_ERR(glue->phy) == -EPROBE_DEFER) 693 return -EPROBE_DEFER; 694 dev_err(&pdev->dev, "Error getting phy %ld\n", 695 PTR_ERR(glue->phy)); 696 return PTR_ERR(glue->phy); 697 } 698 699 glue->usb_phy = usb_phy_generic_register(); 700 if (IS_ERR(glue->usb_phy)) { 701 dev_err(&pdev->dev, "Error registering usb-phy %ld\n", 702 PTR_ERR(glue->usb_phy)); 703 return PTR_ERR(glue->usb_phy); 704 } 705 706 glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2); 707 if (IS_ERR(glue->xceiv)) { 708 ret = PTR_ERR(glue->xceiv); 709 dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret); 710 goto err_unregister_usb_phy; 711 } 712 713 platform_set_drvdata(pdev, glue); 714 715 memset(&pinfo, 0, sizeof(pinfo)); 716 pinfo.name = "musb-hdrc"; 717 pinfo.id = PLATFORM_DEVID_AUTO; 718 pinfo.parent = &pdev->dev; 719 pinfo.res = pdev->resource; 720 pinfo.num_res = pdev->num_resources; 721 pinfo.data = &pdata; 722 pinfo.size_data = sizeof(pdata); 723 724 glue->musb = platform_device_register_full(&pinfo); 725 if (IS_ERR(glue->musb)) { 726 ret = PTR_ERR(glue->musb); 727 dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret); 728 goto err_unregister_usb_phy; 729 } 730 731 return 0; 732 733 err_unregister_usb_phy: 734 usb_phy_generic_unregister(glue->usb_phy); 735 return ret; 736 } 737 738 static int sunxi_musb_remove(struct platform_device *pdev) 739 { 740 struct sunxi_glue *glue = platform_get_drvdata(pdev); 741 struct platform_device *usb_phy = glue->usb_phy; 742 743 platform_device_unregister(glue->musb); /* Frees glue ! */ 744 usb_phy_generic_unregister(usb_phy); 745 746 return 0; 747 } 748 749 static const struct of_device_id sunxi_musb_match[] = { 750 { .compatible = "allwinner,sun4i-a10-musb", }, 751 { .compatible = "allwinner,sun6i-a31-musb", }, 752 { .compatible = "allwinner,sun8i-a33-musb", }, 753 {} 754 }; 755 756 static struct platform_driver sunxi_musb_driver = { 757 .probe = sunxi_musb_probe, 758 .remove = sunxi_musb_remove, 759 .driver = { 760 .name = "musb-sunxi", 761 .of_match_table = sunxi_musb_match, 762 }, 763 }; 764 module_platform_driver(sunxi_musb_driver); 765 766 MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer"); 767 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); 768 MODULE_LICENSE("GPL v2"); 769