1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Allwinner sun4i MUSB Glue Layer 4 * 5 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> 6 * 7 * Based on code from 8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/err.h> 13 #include <linux/extcon.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/phy/phy-sun4i-usb.h> 19 #include <linux/platform_device.h> 20 #include <linux/reset.h> 21 #include <linux/soc/sunxi/sunxi_sram.h> 22 #include <linux/usb/musb.h> 23 #include <linux/usb/of.h> 24 #include <linux/usb/usb_phy_generic.h> 25 #include <linux/workqueue.h> 26 #include "musb_core.h" 27 28 /* 29 * Register offsets, note sunxi musb has a different layout then most 30 * musb implementations, we translate the layout in musb_readb & friends. 31 */ 32 #define SUNXI_MUSB_POWER 0x0040 33 #define SUNXI_MUSB_DEVCTL 0x0041 34 #define SUNXI_MUSB_INDEX 0x0042 35 #define SUNXI_MUSB_VEND0 0x0043 36 #define SUNXI_MUSB_INTRTX 0x0044 37 #define SUNXI_MUSB_INTRRX 0x0046 38 #define SUNXI_MUSB_INTRTXE 0x0048 39 #define SUNXI_MUSB_INTRRXE 0x004a 40 #define SUNXI_MUSB_INTRUSB 0x004c 41 #define SUNXI_MUSB_INTRUSBE 0x0050 42 #define SUNXI_MUSB_FRAME 0x0054 43 #define SUNXI_MUSB_TXFIFOSZ 0x0090 44 #define SUNXI_MUSB_TXFIFOADD 0x0092 45 #define SUNXI_MUSB_RXFIFOSZ 0x0094 46 #define SUNXI_MUSB_RXFIFOADD 0x0096 47 #define SUNXI_MUSB_FADDR 0x0098 48 #define SUNXI_MUSB_TXFUNCADDR 0x0098 49 #define SUNXI_MUSB_TXHUBADDR 0x009a 50 #define SUNXI_MUSB_TXHUBPORT 0x009b 51 #define SUNXI_MUSB_RXFUNCADDR 0x009c 52 #define SUNXI_MUSB_RXHUBADDR 0x009e 53 #define SUNXI_MUSB_RXHUBPORT 0x009f 54 #define SUNXI_MUSB_CONFIGDATA 0x00c0 55 56 /* VEND0 bits */ 57 #define SUNXI_MUSB_VEND0_PIO_MODE 0 58 59 /* flags */ 60 #define SUNXI_MUSB_FL_ENABLED 0 61 #define SUNXI_MUSB_FL_HOSTMODE 1 62 #define SUNXI_MUSB_FL_HOSTMODE_PEND 2 63 #define SUNXI_MUSB_FL_VBUS_ON 3 64 #define SUNXI_MUSB_FL_PHY_ON 4 65 #define SUNXI_MUSB_FL_HAS_SRAM 5 66 #define SUNXI_MUSB_FL_HAS_RESET 6 67 #define SUNXI_MUSB_FL_NO_CONFIGDATA 7 68 #define SUNXI_MUSB_FL_PHY_MODE_PEND 8 69 70 struct sunxi_musb_cfg { 71 const struct musb_hdrc_config *hdrc_config; 72 bool has_sram; 73 bool has_reset; 74 bool no_configdata; 75 }; 76 77 /* Our read/write methods need access and do not get passed in a musb ref :| */ 78 static struct musb *sunxi_musb; 79 80 struct sunxi_glue { 81 struct device *dev; 82 struct musb *musb; 83 struct platform_device *musb_pdev; 84 struct clk *clk; 85 struct reset_control *rst; 86 struct phy *phy; 87 struct platform_device *usb_phy; 88 struct usb_phy *xceiv; 89 enum phy_mode phy_mode; 90 unsigned long flags; 91 struct work_struct work; 92 struct extcon_dev *extcon; 93 struct notifier_block host_nb; 94 }; 95 96 /* phy_power_on / off may sleep, so we use a workqueue */ 97 static void sunxi_musb_work(struct work_struct *work) 98 { 99 struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work); 100 bool vbus_on, phy_on; 101 102 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) 103 return; 104 105 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) { 106 struct musb *musb = glue->musb; 107 unsigned long flags; 108 u8 devctl; 109 110 spin_lock_irqsave(&musb->lock, flags); 111 112 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL); 113 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) { 114 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 115 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 116 MUSB_HST_MODE(musb); 117 devctl |= MUSB_DEVCTL_SESSION; 118 } else { 119 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 120 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 121 MUSB_DEV_MODE(musb); 122 devctl &= ~MUSB_DEVCTL_SESSION; 123 } 124 writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL); 125 126 spin_unlock_irqrestore(&musb->lock, flags); 127 } 128 129 vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 130 phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 131 132 if (phy_on != vbus_on) { 133 if (vbus_on) { 134 phy_power_on(glue->phy); 135 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 136 } else { 137 phy_power_off(glue->phy); 138 clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 139 } 140 } 141 142 if (test_and_clear_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags)) 143 phy_set_mode(glue->phy, glue->phy_mode); 144 } 145 146 static void sunxi_musb_set_vbus(struct musb *musb, int is_on) 147 { 148 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 149 150 if (is_on) { 151 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 152 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 153 } else { 154 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 155 } 156 157 schedule_work(&glue->work); 158 } 159 160 static void sunxi_musb_pre_root_reset_end(struct musb *musb) 161 { 162 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 163 164 sun4i_usb_phy_set_squelch_detect(glue->phy, false); 165 } 166 167 static void sunxi_musb_post_root_reset_end(struct musb *musb) 168 { 169 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 170 171 sun4i_usb_phy_set_squelch_detect(glue->phy, true); 172 } 173 174 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci) 175 { 176 struct musb *musb = __hci; 177 unsigned long flags; 178 179 spin_lock_irqsave(&musb->lock, flags); 180 181 musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB); 182 if (musb->int_usb) 183 writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB); 184 185 if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) { 186 /* ep0 FADDR must be 0 when (re)entering peripheral mode */ 187 musb_ep_select(musb->mregs, 0); 188 musb_writeb(musb->mregs, MUSB_FADDR, 0); 189 } 190 191 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX); 192 if (musb->int_tx) 193 writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX); 194 195 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX); 196 if (musb->int_rx) 197 writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX); 198 199 musb_interrupt(musb); 200 201 spin_unlock_irqrestore(&musb->lock, flags); 202 203 return IRQ_HANDLED; 204 } 205 206 static int sunxi_musb_host_notifier(struct notifier_block *nb, 207 unsigned long event, void *ptr) 208 { 209 struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb); 210 211 if (event) 212 set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); 213 else 214 clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); 215 216 set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags); 217 schedule_work(&glue->work); 218 219 return NOTIFY_DONE; 220 } 221 222 static int sunxi_musb_init(struct musb *musb) 223 { 224 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 225 int ret; 226 227 sunxi_musb = musb; 228 musb->phy = glue->phy; 229 musb->xceiv = glue->xceiv; 230 231 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) { 232 ret = sunxi_sram_claim(musb->controller->parent); 233 if (ret) 234 return ret; 235 } 236 237 ret = clk_prepare_enable(glue->clk); 238 if (ret) 239 goto error_sram_release; 240 241 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { 242 ret = reset_control_deassert(glue->rst); 243 if (ret) 244 goto error_clk_disable; 245 } 246 247 writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0); 248 249 /* Register notifier before calling phy_init() */ 250 ret = devm_extcon_register_notifier(glue->dev, glue->extcon, 251 EXTCON_USB_HOST, &glue->host_nb); 252 if (ret) 253 goto error_reset_assert; 254 255 ret = phy_init(glue->phy); 256 if (ret) 257 goto error_reset_assert; 258 259 musb->isr = sunxi_musb_interrupt; 260 261 /* Stop the musb-core from doing runtime pm (not supported on sunxi) */ 262 pm_runtime_get(musb->controller); 263 264 return 0; 265 266 error_reset_assert: 267 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) 268 reset_control_assert(glue->rst); 269 error_clk_disable: 270 clk_disable_unprepare(glue->clk); 271 error_sram_release: 272 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) 273 sunxi_sram_release(musb->controller->parent); 274 return ret; 275 } 276 277 static int sunxi_musb_exit(struct musb *musb) 278 { 279 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 280 281 pm_runtime_put(musb->controller); 282 283 cancel_work_sync(&glue->work); 284 if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags)) 285 phy_power_off(glue->phy); 286 287 phy_exit(glue->phy); 288 289 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) 290 reset_control_assert(glue->rst); 291 292 clk_disable_unprepare(glue->clk); 293 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) 294 sunxi_sram_release(musb->controller->parent); 295 296 devm_usb_put_phy(glue->dev, glue->xceiv); 297 298 return 0; 299 } 300 301 static void sunxi_musb_enable(struct musb *musb) 302 { 303 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 304 305 glue->musb = musb; 306 307 /* musb_core does not call us in a balanced manner */ 308 if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) 309 return; 310 311 schedule_work(&glue->work); 312 } 313 314 static void sunxi_musb_disable(struct musb *musb) 315 { 316 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 317 318 clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags); 319 } 320 321 static struct dma_controller * 322 sunxi_musb_dma_controller_create(struct musb *musb, void __iomem *base) 323 { 324 return NULL; 325 } 326 327 static void sunxi_musb_dma_controller_destroy(struct dma_controller *c) 328 { 329 } 330 331 static int sunxi_musb_set_mode(struct musb *musb, u8 mode) 332 { 333 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 334 enum phy_mode new_mode; 335 336 switch (mode) { 337 case MUSB_HOST: 338 new_mode = PHY_MODE_USB_HOST; 339 break; 340 case MUSB_PERIPHERAL: 341 new_mode = PHY_MODE_USB_DEVICE; 342 break; 343 case MUSB_OTG: 344 new_mode = PHY_MODE_USB_OTG; 345 break; 346 default: 347 dev_err(musb->controller->parent, 348 "Error requested mode not supported by this kernel\n"); 349 return -EINVAL; 350 } 351 352 if (glue->phy_mode == new_mode) 353 return 0; 354 355 if (musb->port_mode != MUSB_OTG) { 356 dev_err(musb->controller->parent, 357 "Error changing modes is only supported in dual role mode\n"); 358 return -EINVAL; 359 } 360 361 if (musb->port1_status & USB_PORT_STAT_ENABLE) 362 musb_root_disconnect(musb); 363 364 /* 365 * phy_set_mode may sleep, and we're called with a spinlock held, 366 * so let sunxi_musb_work deal with it. 367 */ 368 glue->phy_mode = new_mode; 369 set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags); 370 schedule_work(&glue->work); 371 372 return 0; 373 } 374 375 static int sunxi_musb_recover(struct musb *musb) 376 { 377 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 378 379 /* 380 * Schedule a phy_set_mode with the current glue->phy_mode value, 381 * this will force end the current session. 382 */ 383 set_bit(SUNXI_MUSB_FL_PHY_MODE_PEND, &glue->flags); 384 schedule_work(&glue->work); 385 386 return 0; 387 } 388 389 /* 390 * sunxi musb register layout 391 * 0x00 - 0x17 fifo regs, 1 long per fifo 392 * 0x40 - 0x57 generic control regs (power - frame) 393 * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed) 394 * 0x90 - 0x97 fifo control regs (indexed) 395 * 0x98 - 0x9f multipoint / busctl regs (indexed) 396 * 0xc0 configdata reg 397 */ 398 399 static u32 sunxi_musb_fifo_offset(u8 epnum) 400 { 401 return (epnum * 4); 402 } 403 404 static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset) 405 { 406 WARN_ONCE(offset != 0, 407 "sunxi_musb_ep_offset called with non 0 offset\n"); 408 409 return 0x80; /* indexed, so ignore epnum */ 410 } 411 412 static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset) 413 { 414 return SUNXI_MUSB_TXFUNCADDR + offset; 415 } 416 417 static u8 sunxi_musb_readb(void __iomem *addr, u32 offset) 418 { 419 struct sunxi_glue *glue; 420 421 if (addr == sunxi_musb->mregs) { 422 /* generic control or fifo control reg access */ 423 switch (offset) { 424 case MUSB_FADDR: 425 return readb(addr + SUNXI_MUSB_FADDR); 426 case MUSB_POWER: 427 return readb(addr + SUNXI_MUSB_POWER); 428 case MUSB_INTRUSB: 429 return readb(addr + SUNXI_MUSB_INTRUSB); 430 case MUSB_INTRUSBE: 431 return readb(addr + SUNXI_MUSB_INTRUSBE); 432 case MUSB_INDEX: 433 return readb(addr + SUNXI_MUSB_INDEX); 434 case MUSB_TESTMODE: 435 return 0; /* No testmode on sunxi */ 436 case MUSB_DEVCTL: 437 return readb(addr + SUNXI_MUSB_DEVCTL); 438 case MUSB_TXFIFOSZ: 439 return readb(addr + SUNXI_MUSB_TXFIFOSZ); 440 case MUSB_RXFIFOSZ: 441 return readb(addr + SUNXI_MUSB_RXFIFOSZ); 442 case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */ 443 glue = dev_get_drvdata(sunxi_musb->controller->parent); 444 /* A33 saves a reg, and we get to hardcode this */ 445 if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, 446 &glue->flags)) 447 return 0xde; 448 449 return readb(addr + SUNXI_MUSB_CONFIGDATA); 450 case MUSB_ULPI_BUSCONTROL: 451 dev_warn(sunxi_musb->controller->parent, 452 "sunxi-musb does not have ULPI bus control register\n"); 453 return 0; 454 /* Offset for these is fixed by sunxi_musb_busctl_offset() */ 455 case SUNXI_MUSB_TXFUNCADDR: 456 case SUNXI_MUSB_TXHUBADDR: 457 case SUNXI_MUSB_TXHUBPORT: 458 case SUNXI_MUSB_RXFUNCADDR: 459 case SUNXI_MUSB_RXHUBADDR: 460 case SUNXI_MUSB_RXHUBPORT: 461 /* multipoint / busctl reg access */ 462 return readb(addr + offset); 463 default: 464 dev_err(sunxi_musb->controller->parent, 465 "Error unknown readb offset %u\n", offset); 466 return 0; 467 } 468 } else if (addr == (sunxi_musb->mregs + 0x80)) { 469 /* ep control reg access */ 470 /* sunxi has a 2 byte hole before the txtype register */ 471 if (offset >= MUSB_TXTYPE) 472 offset += 2; 473 return readb(addr + offset); 474 } 475 476 dev_err(sunxi_musb->controller->parent, 477 "Error unknown readb at 0x%x bytes offset\n", 478 (int)(addr - sunxi_musb->mregs)); 479 return 0; 480 } 481 482 static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data) 483 { 484 if (addr == sunxi_musb->mregs) { 485 /* generic control or fifo control reg access */ 486 switch (offset) { 487 case MUSB_FADDR: 488 return writeb(data, addr + SUNXI_MUSB_FADDR); 489 case MUSB_POWER: 490 return writeb(data, addr + SUNXI_MUSB_POWER); 491 case MUSB_INTRUSB: 492 return writeb(data, addr + SUNXI_MUSB_INTRUSB); 493 case MUSB_INTRUSBE: 494 return writeb(data, addr + SUNXI_MUSB_INTRUSBE); 495 case MUSB_INDEX: 496 return writeb(data, addr + SUNXI_MUSB_INDEX); 497 case MUSB_TESTMODE: 498 if (data) 499 dev_warn(sunxi_musb->controller->parent, 500 "sunxi-musb does not have testmode\n"); 501 return; 502 case MUSB_DEVCTL: 503 return writeb(data, addr + SUNXI_MUSB_DEVCTL); 504 case MUSB_TXFIFOSZ: 505 return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ); 506 case MUSB_RXFIFOSZ: 507 return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ); 508 case MUSB_ULPI_BUSCONTROL: 509 dev_warn(sunxi_musb->controller->parent, 510 "sunxi-musb does not have ULPI bus control register\n"); 511 return; 512 /* Offset for these is fixed by sunxi_musb_busctl_offset() */ 513 case SUNXI_MUSB_TXFUNCADDR: 514 case SUNXI_MUSB_TXHUBADDR: 515 case SUNXI_MUSB_TXHUBPORT: 516 case SUNXI_MUSB_RXFUNCADDR: 517 case SUNXI_MUSB_RXHUBADDR: 518 case SUNXI_MUSB_RXHUBPORT: 519 /* multipoint / busctl reg access */ 520 return writeb(data, addr + offset); 521 default: 522 dev_err(sunxi_musb->controller->parent, 523 "Error unknown writeb offset %u\n", offset); 524 return; 525 } 526 } else if (addr == (sunxi_musb->mregs + 0x80)) { 527 /* ep control reg access */ 528 if (offset >= MUSB_TXTYPE) 529 offset += 2; 530 return writeb(data, addr + offset); 531 } 532 533 dev_err(sunxi_musb->controller->parent, 534 "Error unknown writeb at 0x%x bytes offset\n", 535 (int)(addr - sunxi_musb->mregs)); 536 } 537 538 static u16 sunxi_musb_readw(void __iomem *addr, u32 offset) 539 { 540 if (addr == sunxi_musb->mregs) { 541 /* generic control or fifo control reg access */ 542 switch (offset) { 543 case MUSB_INTRTX: 544 return readw(addr + SUNXI_MUSB_INTRTX); 545 case MUSB_INTRRX: 546 return readw(addr + SUNXI_MUSB_INTRRX); 547 case MUSB_INTRTXE: 548 return readw(addr + SUNXI_MUSB_INTRTXE); 549 case MUSB_INTRRXE: 550 return readw(addr + SUNXI_MUSB_INTRRXE); 551 case MUSB_FRAME: 552 return readw(addr + SUNXI_MUSB_FRAME); 553 case MUSB_TXFIFOADD: 554 return readw(addr + SUNXI_MUSB_TXFIFOADD); 555 case MUSB_RXFIFOADD: 556 return readw(addr + SUNXI_MUSB_RXFIFOADD); 557 case MUSB_HWVERS: 558 return 0; /* sunxi musb version is not known */ 559 default: 560 dev_err(sunxi_musb->controller->parent, 561 "Error unknown readw offset %u\n", offset); 562 return 0; 563 } 564 } else if (addr == (sunxi_musb->mregs + 0x80)) { 565 /* ep control reg access */ 566 return readw(addr + offset); 567 } 568 569 dev_err(sunxi_musb->controller->parent, 570 "Error unknown readw at 0x%x bytes offset\n", 571 (int)(addr - sunxi_musb->mregs)); 572 return 0; 573 } 574 575 static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data) 576 { 577 if (addr == sunxi_musb->mregs) { 578 /* generic control or fifo control reg access */ 579 switch (offset) { 580 case MUSB_INTRTX: 581 return writew(data, addr + SUNXI_MUSB_INTRTX); 582 case MUSB_INTRRX: 583 return writew(data, addr + SUNXI_MUSB_INTRRX); 584 case MUSB_INTRTXE: 585 return writew(data, addr + SUNXI_MUSB_INTRTXE); 586 case MUSB_INTRRXE: 587 return writew(data, addr + SUNXI_MUSB_INTRRXE); 588 case MUSB_FRAME: 589 return writew(data, addr + SUNXI_MUSB_FRAME); 590 case MUSB_TXFIFOADD: 591 return writew(data, addr + SUNXI_MUSB_TXFIFOADD); 592 case MUSB_RXFIFOADD: 593 return writew(data, addr + SUNXI_MUSB_RXFIFOADD); 594 default: 595 dev_err(sunxi_musb->controller->parent, 596 "Error unknown writew offset %u\n", offset); 597 return; 598 } 599 } else if (addr == (sunxi_musb->mregs + 0x80)) { 600 /* ep control reg access */ 601 return writew(data, addr + offset); 602 } 603 604 dev_err(sunxi_musb->controller->parent, 605 "Error unknown writew at 0x%x bytes offset\n", 606 (int)(addr - sunxi_musb->mregs)); 607 } 608 609 static const struct musb_platform_ops sunxi_musb_ops = { 610 .quirks = MUSB_INDEXED_EP, 611 .init = sunxi_musb_init, 612 .exit = sunxi_musb_exit, 613 .enable = sunxi_musb_enable, 614 .disable = sunxi_musb_disable, 615 .fifo_offset = sunxi_musb_fifo_offset, 616 .ep_offset = sunxi_musb_ep_offset, 617 .busctl_offset = sunxi_musb_busctl_offset, 618 .readb = sunxi_musb_readb, 619 .writeb = sunxi_musb_writeb, 620 .readw = sunxi_musb_readw, 621 .writew = sunxi_musb_writew, 622 .dma_init = sunxi_musb_dma_controller_create, 623 .dma_exit = sunxi_musb_dma_controller_destroy, 624 .set_mode = sunxi_musb_set_mode, 625 .recover = sunxi_musb_recover, 626 .set_vbus = sunxi_musb_set_vbus, 627 .pre_root_reset_end = sunxi_musb_pre_root_reset_end, 628 .post_root_reset_end = sunxi_musb_post_root_reset_end, 629 }; 630 631 #define SUNXI_MUSB_RAM_BITS 11 632 633 /* Allwinner OTG supports up to 5 endpoints */ 634 static struct musb_fifo_cfg sunxi_musb_mode_cfg_5eps[] = { 635 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), 636 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), 637 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), 638 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), 639 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), 640 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), 641 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), 642 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), 643 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512), 644 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512), 645 }; 646 647 /* H3/V3s OTG supports only 4 endpoints */ 648 static struct musb_fifo_cfg sunxi_musb_mode_cfg_4eps[] = { 649 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), 650 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), 651 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), 652 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), 653 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), 654 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), 655 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), 656 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), 657 }; 658 659 static const struct musb_hdrc_config sunxi_musb_hdrc_config_5eps = { 660 .fifo_cfg = sunxi_musb_mode_cfg_5eps, 661 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_5eps), 662 .multipoint = true, 663 .dyn_fifo = true, 664 /* Two FIFOs per endpoint, plus ep_0. */ 665 .num_eps = (ARRAY_SIZE(sunxi_musb_mode_cfg_5eps) / 2) + 1, 666 .ram_bits = SUNXI_MUSB_RAM_BITS, 667 }; 668 669 static const struct musb_hdrc_config sunxi_musb_hdrc_config_4eps = { 670 .fifo_cfg = sunxi_musb_mode_cfg_4eps, 671 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_4eps), 672 .multipoint = true, 673 .dyn_fifo = true, 674 /* Two FIFOs per endpoint, plus ep_0. */ 675 .num_eps = (ARRAY_SIZE(sunxi_musb_mode_cfg_4eps) / 2) + 1, 676 .ram_bits = SUNXI_MUSB_RAM_BITS, 677 }; 678 679 static int sunxi_musb_probe(struct platform_device *pdev) 680 { 681 struct musb_hdrc_platform_data pdata; 682 struct platform_device_info pinfo; 683 struct sunxi_glue *glue; 684 struct device_node *np = pdev->dev.of_node; 685 const struct sunxi_musb_cfg *cfg; 686 int ret; 687 688 if (!np) { 689 dev_err(&pdev->dev, "Error no device tree node found\n"); 690 return -EINVAL; 691 } 692 693 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 694 if (!glue) 695 return -ENOMEM; 696 697 memset(&pdata, 0, sizeof(pdata)); 698 switch (usb_get_dr_mode(&pdev->dev)) { 699 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST 700 case USB_DR_MODE_HOST: 701 pdata.mode = MUSB_HOST; 702 glue->phy_mode = PHY_MODE_USB_HOST; 703 break; 704 #endif 705 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_GADGET 706 case USB_DR_MODE_PERIPHERAL: 707 pdata.mode = MUSB_PERIPHERAL; 708 glue->phy_mode = PHY_MODE_USB_DEVICE; 709 break; 710 #endif 711 #ifdef CONFIG_USB_MUSB_DUAL_ROLE 712 case USB_DR_MODE_OTG: 713 pdata.mode = MUSB_OTG; 714 glue->phy_mode = PHY_MODE_USB_OTG; 715 break; 716 #endif 717 default: 718 dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n"); 719 return -EINVAL; 720 } 721 pdata.platform_ops = &sunxi_musb_ops; 722 723 cfg = of_device_get_match_data(&pdev->dev); 724 if (!cfg) 725 return -EINVAL; 726 727 pdata.config = cfg->hdrc_config; 728 729 glue->dev = &pdev->dev; 730 INIT_WORK(&glue->work, sunxi_musb_work); 731 glue->host_nb.notifier_call = sunxi_musb_host_notifier; 732 733 if (cfg->has_sram) 734 set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags); 735 736 if (cfg->has_reset) 737 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags); 738 739 if (cfg->no_configdata) 740 set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags); 741 742 glue->clk = devm_clk_get(&pdev->dev, NULL); 743 if (IS_ERR(glue->clk)) { 744 dev_err(&pdev->dev, "Error getting clock: %ld\n", 745 PTR_ERR(glue->clk)); 746 return PTR_ERR(glue->clk); 747 } 748 749 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { 750 glue->rst = devm_reset_control_get(&pdev->dev, NULL); 751 if (IS_ERR(glue->rst)) 752 return dev_err_probe(&pdev->dev, PTR_ERR(glue->rst), 753 "Error getting reset\n"); 754 } 755 756 glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0); 757 if (IS_ERR(glue->extcon)) 758 return dev_err_probe(&pdev->dev, PTR_ERR(glue->extcon), 759 "Invalid or missing extcon\n"); 760 761 glue->phy = devm_phy_get(&pdev->dev, "usb"); 762 if (IS_ERR(glue->phy)) 763 return dev_err_probe(&pdev->dev, PTR_ERR(glue->phy), 764 "Error getting phy\n"); 765 766 glue->usb_phy = usb_phy_generic_register(); 767 if (IS_ERR(glue->usb_phy)) { 768 dev_err(&pdev->dev, "Error registering usb-phy %ld\n", 769 PTR_ERR(glue->usb_phy)); 770 return PTR_ERR(glue->usb_phy); 771 } 772 773 glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2); 774 if (IS_ERR(glue->xceiv)) { 775 ret = PTR_ERR(glue->xceiv); 776 dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret); 777 goto err_unregister_usb_phy; 778 } 779 780 platform_set_drvdata(pdev, glue); 781 782 memset(&pinfo, 0, sizeof(pinfo)); 783 pinfo.name = "musb-hdrc"; 784 pinfo.id = PLATFORM_DEVID_AUTO; 785 pinfo.parent = &pdev->dev; 786 pinfo.fwnode = of_fwnode_handle(pdev->dev.of_node); 787 pinfo.of_node_reused = true; 788 pinfo.res = pdev->resource; 789 pinfo.num_res = pdev->num_resources; 790 pinfo.data = &pdata; 791 pinfo.size_data = sizeof(pdata); 792 793 glue->musb_pdev = platform_device_register_full(&pinfo); 794 if (IS_ERR(glue->musb_pdev)) { 795 ret = PTR_ERR(glue->musb_pdev); 796 dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret); 797 goto err_unregister_usb_phy; 798 } 799 800 return 0; 801 802 err_unregister_usb_phy: 803 usb_phy_generic_unregister(glue->usb_phy); 804 return ret; 805 } 806 807 static void sunxi_musb_remove(struct platform_device *pdev) 808 { 809 struct sunxi_glue *glue = platform_get_drvdata(pdev); 810 struct platform_device *usb_phy = glue->usb_phy; 811 812 platform_device_unregister(glue->musb_pdev); 813 usb_phy_generic_unregister(usb_phy); 814 } 815 816 static const struct sunxi_musb_cfg sun4i_a10_musb_cfg = { 817 .hdrc_config = &sunxi_musb_hdrc_config_5eps, 818 .has_sram = true, 819 }; 820 821 static const struct sunxi_musb_cfg sun6i_a31_musb_cfg = { 822 .hdrc_config = &sunxi_musb_hdrc_config_5eps, 823 .has_reset = true, 824 }; 825 826 static const struct sunxi_musb_cfg sun8i_a33_musb_cfg = { 827 .hdrc_config = &sunxi_musb_hdrc_config_5eps, 828 .has_reset = true, 829 .no_configdata = true, 830 }; 831 832 static const struct sunxi_musb_cfg sun8i_h3_musb_cfg = { 833 .hdrc_config = &sunxi_musb_hdrc_config_4eps, 834 .has_reset = true, 835 .no_configdata = true, 836 }; 837 838 static const struct sunxi_musb_cfg suniv_f1c100s_musb_cfg = { 839 .hdrc_config = &sunxi_musb_hdrc_config_5eps, 840 .has_sram = true, 841 .has_reset = true, 842 .no_configdata = true, 843 }; 844 845 static const struct of_device_id sunxi_musb_match[] = { 846 { .compatible = "allwinner,sun4i-a10-musb", 847 .data = &sun4i_a10_musb_cfg, }, 848 { .compatible = "allwinner,sun6i-a31-musb", 849 .data = &sun6i_a31_musb_cfg, }, 850 { .compatible = "allwinner,sun8i-a33-musb", 851 .data = &sun8i_a33_musb_cfg, }, 852 { .compatible = "allwinner,sun8i-h3-musb", 853 .data = &sun8i_h3_musb_cfg, }, 854 { .compatible = "allwinner,suniv-f1c100s-musb", 855 .data = &suniv_f1c100s_musb_cfg, }, 856 {} 857 }; 858 MODULE_DEVICE_TABLE(of, sunxi_musb_match); 859 860 static struct platform_driver sunxi_musb_driver = { 861 .probe = sunxi_musb_probe, 862 .remove_new = sunxi_musb_remove, 863 .driver = { 864 .name = "musb-sunxi", 865 .of_match_table = sunxi_musb_match, 866 }, 867 }; 868 module_platform_driver(sunxi_musb_driver); 869 870 MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer"); 871 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); 872 MODULE_LICENSE("GPL v2"); 873