1 /* 2 * Allwinner sun4i MUSB Glue Layer 3 * 4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> 5 * 6 * Based on code from 7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/clk.h> 21 #include <linux/err.h> 22 #include <linux/extcon.h> 23 #include <linux/io.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/phy/phy-sun4i-usb.h> 28 #include <linux/platform_device.h> 29 #include <linux/reset.h> 30 #include <linux/soc/sunxi/sunxi_sram.h> 31 #include <linux/usb/musb.h> 32 #include <linux/usb/of.h> 33 #include <linux/usb/usb_phy_generic.h> 34 #include <linux/workqueue.h> 35 #include "musb_core.h" 36 37 /* 38 * Register offsets, note sunxi musb has a different layout then most 39 * musb implementations, we translate the layout in musb_readb & friends. 40 */ 41 #define SUNXI_MUSB_POWER 0x0040 42 #define SUNXI_MUSB_DEVCTL 0x0041 43 #define SUNXI_MUSB_INDEX 0x0042 44 #define SUNXI_MUSB_VEND0 0x0043 45 #define SUNXI_MUSB_INTRTX 0x0044 46 #define SUNXI_MUSB_INTRRX 0x0046 47 #define SUNXI_MUSB_INTRTXE 0x0048 48 #define SUNXI_MUSB_INTRRXE 0x004a 49 #define SUNXI_MUSB_INTRUSB 0x004c 50 #define SUNXI_MUSB_INTRUSBE 0x0050 51 #define SUNXI_MUSB_FRAME 0x0054 52 #define SUNXI_MUSB_TXFIFOSZ 0x0090 53 #define SUNXI_MUSB_TXFIFOADD 0x0092 54 #define SUNXI_MUSB_RXFIFOSZ 0x0094 55 #define SUNXI_MUSB_RXFIFOADD 0x0096 56 #define SUNXI_MUSB_FADDR 0x0098 57 #define SUNXI_MUSB_TXFUNCADDR 0x0098 58 #define SUNXI_MUSB_TXHUBADDR 0x009a 59 #define SUNXI_MUSB_TXHUBPORT 0x009b 60 #define SUNXI_MUSB_RXFUNCADDR 0x009c 61 #define SUNXI_MUSB_RXHUBADDR 0x009e 62 #define SUNXI_MUSB_RXHUBPORT 0x009f 63 #define SUNXI_MUSB_CONFIGDATA 0x00c0 64 65 /* VEND0 bits */ 66 #define SUNXI_MUSB_VEND0_PIO_MODE 0 67 68 /* flags */ 69 #define SUNXI_MUSB_FL_ENABLED 0 70 #define SUNXI_MUSB_FL_HOSTMODE 1 71 #define SUNXI_MUSB_FL_HOSTMODE_PEND 2 72 #define SUNXI_MUSB_FL_VBUS_ON 3 73 #define SUNXI_MUSB_FL_PHY_ON 4 74 #define SUNXI_MUSB_FL_HAS_SRAM 5 75 #define SUNXI_MUSB_FL_HAS_RESET 6 76 #define SUNXI_MUSB_FL_NO_CONFIGDATA 7 77 78 /* Our read/write methods need access and do not get passed in a musb ref :| */ 79 static struct musb *sunxi_musb; 80 81 struct sunxi_glue { 82 struct device *dev; 83 struct musb *musb; 84 struct platform_device *musb_pdev; 85 struct clk *clk; 86 struct reset_control *rst; 87 struct phy *phy; 88 struct platform_device *usb_phy; 89 struct usb_phy *xceiv; 90 unsigned long flags; 91 struct work_struct work; 92 struct extcon_dev *extcon; 93 struct notifier_block host_nb; 94 }; 95 96 /* phy_power_on / off may sleep, so we use a workqueue */ 97 static void sunxi_musb_work(struct work_struct *work) 98 { 99 struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work); 100 bool vbus_on, phy_on; 101 102 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) 103 return; 104 105 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) { 106 struct musb *musb = glue->musb; 107 unsigned long flags; 108 u8 devctl; 109 110 spin_lock_irqsave(&musb->lock, flags); 111 112 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL); 113 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) { 114 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 115 musb->xceiv->otg->default_a = 1; 116 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 117 MUSB_HST_MODE(musb); 118 devctl |= MUSB_DEVCTL_SESSION; 119 } else { 120 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 121 musb->xceiv->otg->default_a = 0; 122 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 123 MUSB_DEV_MODE(musb); 124 devctl &= ~MUSB_DEVCTL_SESSION; 125 } 126 writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL); 127 128 spin_unlock_irqrestore(&musb->lock, flags); 129 } 130 131 vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 132 phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 133 134 if (phy_on != vbus_on) { 135 if (vbus_on) { 136 phy_power_on(glue->phy); 137 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 138 } else { 139 phy_power_off(glue->phy); 140 clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags); 141 } 142 } 143 } 144 145 static void sunxi_musb_set_vbus(struct musb *musb, int is_on) 146 { 147 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 148 149 if (is_on) { 150 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 151 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; 152 } else { 153 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags); 154 } 155 156 schedule_work(&glue->work); 157 } 158 159 static void sunxi_musb_pre_root_reset_end(struct musb *musb) 160 { 161 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 162 163 sun4i_usb_phy_set_squelch_detect(glue->phy, false); 164 } 165 166 static void sunxi_musb_post_root_reset_end(struct musb *musb) 167 { 168 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 169 170 sun4i_usb_phy_set_squelch_detect(glue->phy, true); 171 } 172 173 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci) 174 { 175 struct musb *musb = __hci; 176 unsigned long flags; 177 178 spin_lock_irqsave(&musb->lock, flags); 179 180 musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB); 181 if (musb->int_usb) 182 writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB); 183 184 /* 185 * sunxi musb often signals babble on low / full speed device 186 * disconnect, without ever raising MUSB_INTR_DISCONNECT, since 187 * normally babble never happens treat it as disconnect. 188 */ 189 if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) { 190 musb->int_usb &= ~MUSB_INTR_BABBLE; 191 musb->int_usb |= MUSB_INTR_DISCONNECT; 192 } 193 194 if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) { 195 /* ep0 FADDR must be 0 when (re)entering peripheral mode */ 196 musb_ep_select(musb->mregs, 0); 197 musb_writeb(musb->mregs, MUSB_FADDR, 0); 198 } 199 200 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX); 201 if (musb->int_tx) 202 writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX); 203 204 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX); 205 if (musb->int_rx) 206 writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX); 207 208 musb_interrupt(musb); 209 210 spin_unlock_irqrestore(&musb->lock, flags); 211 212 return IRQ_HANDLED; 213 } 214 215 static int sunxi_musb_host_notifier(struct notifier_block *nb, 216 unsigned long event, void *ptr) 217 { 218 struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb); 219 220 if (event) 221 set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); 222 else 223 clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags); 224 225 set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags); 226 schedule_work(&glue->work); 227 228 return NOTIFY_DONE; 229 } 230 231 static int sunxi_musb_init(struct musb *musb) 232 { 233 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 234 int ret; 235 236 sunxi_musb = musb; 237 musb->phy = glue->phy; 238 musb->xceiv = glue->xceiv; 239 240 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) { 241 ret = sunxi_sram_claim(musb->controller->parent); 242 if (ret) 243 return ret; 244 } 245 246 ret = clk_prepare_enable(glue->clk); 247 if (ret) 248 goto error_sram_release; 249 250 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { 251 ret = reset_control_deassert(glue->rst); 252 if (ret) 253 goto error_clk_disable; 254 } 255 256 writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0); 257 258 /* Register notifier before calling phy_init() */ 259 ret = extcon_register_notifier(glue->extcon, EXTCON_USB_HOST, 260 &glue->host_nb); 261 if (ret) 262 goto error_reset_assert; 263 264 ret = phy_init(glue->phy); 265 if (ret) 266 goto error_unregister_notifier; 267 268 musb->isr = sunxi_musb_interrupt; 269 270 /* Stop the musb-core from doing runtime pm (not supported on sunxi) */ 271 pm_runtime_get(musb->controller); 272 273 return 0; 274 275 error_unregister_notifier: 276 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST, 277 &glue->host_nb); 278 error_reset_assert: 279 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) 280 reset_control_assert(glue->rst); 281 error_clk_disable: 282 clk_disable_unprepare(glue->clk); 283 error_sram_release: 284 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) 285 sunxi_sram_release(musb->controller->parent); 286 return ret; 287 } 288 289 static int sunxi_musb_exit(struct musb *musb) 290 { 291 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 292 293 pm_runtime_put(musb->controller); 294 295 cancel_work_sync(&glue->work); 296 if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags)) 297 phy_power_off(glue->phy); 298 299 phy_exit(glue->phy); 300 301 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST, 302 &glue->host_nb); 303 304 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) 305 reset_control_assert(glue->rst); 306 307 clk_disable_unprepare(glue->clk); 308 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) 309 sunxi_sram_release(musb->controller->parent); 310 311 return 0; 312 } 313 314 static void sunxi_musb_enable(struct musb *musb) 315 { 316 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 317 318 glue->musb = musb; 319 320 /* musb_core does not call us in a balanced manner */ 321 if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags)) 322 return; 323 324 schedule_work(&glue->work); 325 } 326 327 static void sunxi_musb_disable(struct musb *musb) 328 { 329 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent); 330 331 clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags); 332 } 333 334 static struct dma_controller * 335 sunxi_musb_dma_controller_create(struct musb *musb, void __iomem *base) 336 { 337 return NULL; 338 } 339 340 static void sunxi_musb_dma_controller_destroy(struct dma_controller *c) 341 { 342 } 343 344 /* 345 * sunxi musb register layout 346 * 0x00 - 0x17 fifo regs, 1 long per fifo 347 * 0x40 - 0x57 generic control regs (power - frame) 348 * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed) 349 * 0x90 - 0x97 fifo control regs (indexed) 350 * 0x98 - 0x9f multipoint / busctl regs (indexed) 351 * 0xc0 configdata reg 352 */ 353 354 static u32 sunxi_musb_fifo_offset(u8 epnum) 355 { 356 return (epnum * 4); 357 } 358 359 static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset) 360 { 361 WARN_ONCE(offset != 0, 362 "sunxi_musb_ep_offset called with non 0 offset\n"); 363 364 return 0x80; /* indexed, so ignore epnum */ 365 } 366 367 static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset) 368 { 369 return SUNXI_MUSB_TXFUNCADDR + offset; 370 } 371 372 static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset) 373 { 374 struct sunxi_glue *glue; 375 376 if (addr == sunxi_musb->mregs) { 377 /* generic control or fifo control reg access */ 378 switch (offset) { 379 case MUSB_FADDR: 380 return readb(addr + SUNXI_MUSB_FADDR); 381 case MUSB_POWER: 382 return readb(addr + SUNXI_MUSB_POWER); 383 case MUSB_INTRUSB: 384 return readb(addr + SUNXI_MUSB_INTRUSB); 385 case MUSB_INTRUSBE: 386 return readb(addr + SUNXI_MUSB_INTRUSBE); 387 case MUSB_INDEX: 388 return readb(addr + SUNXI_MUSB_INDEX); 389 case MUSB_TESTMODE: 390 return 0; /* No testmode on sunxi */ 391 case MUSB_DEVCTL: 392 return readb(addr + SUNXI_MUSB_DEVCTL); 393 case MUSB_TXFIFOSZ: 394 return readb(addr + SUNXI_MUSB_TXFIFOSZ); 395 case MUSB_RXFIFOSZ: 396 return readb(addr + SUNXI_MUSB_RXFIFOSZ); 397 case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */ 398 glue = dev_get_drvdata(sunxi_musb->controller->parent); 399 /* A33 saves a reg, and we get to hardcode this */ 400 if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, 401 &glue->flags)) 402 return 0xde; 403 404 return readb(addr + SUNXI_MUSB_CONFIGDATA); 405 /* Offset for these is fixed by sunxi_musb_busctl_offset() */ 406 case SUNXI_MUSB_TXFUNCADDR: 407 case SUNXI_MUSB_TXHUBADDR: 408 case SUNXI_MUSB_TXHUBPORT: 409 case SUNXI_MUSB_RXFUNCADDR: 410 case SUNXI_MUSB_RXHUBADDR: 411 case SUNXI_MUSB_RXHUBPORT: 412 /* multipoint / busctl reg access */ 413 return readb(addr + offset); 414 default: 415 dev_err(sunxi_musb->controller->parent, 416 "Error unknown readb offset %u\n", offset); 417 return 0; 418 } 419 } else if (addr == (sunxi_musb->mregs + 0x80)) { 420 /* ep control reg access */ 421 /* sunxi has a 2 byte hole before the txtype register */ 422 if (offset >= MUSB_TXTYPE) 423 offset += 2; 424 return readb(addr + offset); 425 } 426 427 dev_err(sunxi_musb->controller->parent, 428 "Error unknown readb at 0x%x bytes offset\n", 429 (int)(addr - sunxi_musb->mregs)); 430 return 0; 431 } 432 433 static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data) 434 { 435 if (addr == sunxi_musb->mregs) { 436 /* generic control or fifo control reg access */ 437 switch (offset) { 438 case MUSB_FADDR: 439 return writeb(data, addr + SUNXI_MUSB_FADDR); 440 case MUSB_POWER: 441 return writeb(data, addr + SUNXI_MUSB_POWER); 442 case MUSB_INTRUSB: 443 return writeb(data, addr + SUNXI_MUSB_INTRUSB); 444 case MUSB_INTRUSBE: 445 return writeb(data, addr + SUNXI_MUSB_INTRUSBE); 446 case MUSB_INDEX: 447 return writeb(data, addr + SUNXI_MUSB_INDEX); 448 case MUSB_TESTMODE: 449 if (data) 450 dev_warn(sunxi_musb->controller->parent, 451 "sunxi-musb does not have testmode\n"); 452 return; 453 case MUSB_DEVCTL: 454 return writeb(data, addr + SUNXI_MUSB_DEVCTL); 455 case MUSB_TXFIFOSZ: 456 return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ); 457 case MUSB_RXFIFOSZ: 458 return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ); 459 /* Offset for these is fixed by sunxi_musb_busctl_offset() */ 460 case SUNXI_MUSB_TXFUNCADDR: 461 case SUNXI_MUSB_TXHUBADDR: 462 case SUNXI_MUSB_TXHUBPORT: 463 case SUNXI_MUSB_RXFUNCADDR: 464 case SUNXI_MUSB_RXHUBADDR: 465 case SUNXI_MUSB_RXHUBPORT: 466 /* multipoint / busctl reg access */ 467 return writeb(data, addr + offset); 468 default: 469 dev_err(sunxi_musb->controller->parent, 470 "Error unknown writeb offset %u\n", offset); 471 return; 472 } 473 } else if (addr == (sunxi_musb->mregs + 0x80)) { 474 /* ep control reg access */ 475 if (offset >= MUSB_TXTYPE) 476 offset += 2; 477 return writeb(data, addr + offset); 478 } 479 480 dev_err(sunxi_musb->controller->parent, 481 "Error unknown writeb at 0x%x bytes offset\n", 482 (int)(addr - sunxi_musb->mregs)); 483 } 484 485 static u16 sunxi_musb_readw(const void __iomem *addr, unsigned offset) 486 { 487 if (addr == sunxi_musb->mregs) { 488 /* generic control or fifo control reg access */ 489 switch (offset) { 490 case MUSB_INTRTX: 491 return readw(addr + SUNXI_MUSB_INTRTX); 492 case MUSB_INTRRX: 493 return readw(addr + SUNXI_MUSB_INTRRX); 494 case MUSB_INTRTXE: 495 return readw(addr + SUNXI_MUSB_INTRTXE); 496 case MUSB_INTRRXE: 497 return readw(addr + SUNXI_MUSB_INTRRXE); 498 case MUSB_FRAME: 499 return readw(addr + SUNXI_MUSB_FRAME); 500 case MUSB_TXFIFOADD: 501 return readw(addr + SUNXI_MUSB_TXFIFOADD); 502 case MUSB_RXFIFOADD: 503 return readw(addr + SUNXI_MUSB_RXFIFOADD); 504 case MUSB_HWVERS: 505 return 0; /* sunxi musb version is not known */ 506 default: 507 dev_err(sunxi_musb->controller->parent, 508 "Error unknown readw offset %u\n", offset); 509 return 0; 510 } 511 } else if (addr == (sunxi_musb->mregs + 0x80)) { 512 /* ep control reg access */ 513 return readw(addr + offset); 514 } 515 516 dev_err(sunxi_musb->controller->parent, 517 "Error unknown readw at 0x%x bytes offset\n", 518 (int)(addr - sunxi_musb->mregs)); 519 return 0; 520 } 521 522 static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data) 523 { 524 if (addr == sunxi_musb->mregs) { 525 /* generic control or fifo control reg access */ 526 switch (offset) { 527 case MUSB_INTRTX: 528 return writew(data, addr + SUNXI_MUSB_INTRTX); 529 case MUSB_INTRRX: 530 return writew(data, addr + SUNXI_MUSB_INTRRX); 531 case MUSB_INTRTXE: 532 return writew(data, addr + SUNXI_MUSB_INTRTXE); 533 case MUSB_INTRRXE: 534 return writew(data, addr + SUNXI_MUSB_INTRRXE); 535 case MUSB_FRAME: 536 return writew(data, addr + SUNXI_MUSB_FRAME); 537 case MUSB_TXFIFOADD: 538 return writew(data, addr + SUNXI_MUSB_TXFIFOADD); 539 case MUSB_RXFIFOADD: 540 return writew(data, addr + SUNXI_MUSB_RXFIFOADD); 541 default: 542 dev_err(sunxi_musb->controller->parent, 543 "Error unknown writew offset %u\n", offset); 544 return; 545 } 546 } else if (addr == (sunxi_musb->mregs + 0x80)) { 547 /* ep control reg access */ 548 return writew(data, addr + offset); 549 } 550 551 dev_err(sunxi_musb->controller->parent, 552 "Error unknown writew at 0x%x bytes offset\n", 553 (int)(addr - sunxi_musb->mregs)); 554 } 555 556 static const struct musb_platform_ops sunxi_musb_ops = { 557 .quirks = MUSB_INDEXED_EP, 558 .init = sunxi_musb_init, 559 .exit = sunxi_musb_exit, 560 .enable = sunxi_musb_enable, 561 .disable = sunxi_musb_disable, 562 .fifo_offset = sunxi_musb_fifo_offset, 563 .ep_offset = sunxi_musb_ep_offset, 564 .busctl_offset = sunxi_musb_busctl_offset, 565 .readb = sunxi_musb_readb, 566 .writeb = sunxi_musb_writeb, 567 .readw = sunxi_musb_readw, 568 .writew = sunxi_musb_writew, 569 .dma_init = sunxi_musb_dma_controller_create, 570 .dma_exit = sunxi_musb_dma_controller_destroy, 571 .set_vbus = sunxi_musb_set_vbus, 572 .pre_root_reset_end = sunxi_musb_pre_root_reset_end, 573 .post_root_reset_end = sunxi_musb_post_root_reset_end, 574 }; 575 576 /* Allwinner OTG supports up to 5 endpoints */ 577 #define SUNXI_MUSB_MAX_EP_NUM 6 578 #define SUNXI_MUSB_RAM_BITS 11 579 580 static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = { 581 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512), 582 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512), 583 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512), 584 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512), 585 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512), 586 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512), 587 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512), 588 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512), 589 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512), 590 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512), 591 }; 592 593 static struct musb_hdrc_config sunxi_musb_hdrc_config = { 594 .fifo_cfg = sunxi_musb_mode_cfg, 595 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg), 596 .multipoint = true, 597 .dyn_fifo = true, 598 .soft_con = true, 599 .num_eps = SUNXI_MUSB_MAX_EP_NUM, 600 .ram_bits = SUNXI_MUSB_RAM_BITS, 601 .dma = 0, 602 }; 603 604 static int sunxi_musb_probe(struct platform_device *pdev) 605 { 606 struct musb_hdrc_platform_data pdata; 607 struct platform_device_info pinfo; 608 struct sunxi_glue *glue; 609 struct device_node *np = pdev->dev.of_node; 610 int ret; 611 612 if (!np) { 613 dev_err(&pdev->dev, "Error no device tree node found\n"); 614 return -EINVAL; 615 } 616 617 memset(&pdata, 0, sizeof(pdata)); 618 switch (usb_get_dr_mode(&pdev->dev)) { 619 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST 620 case USB_DR_MODE_HOST: 621 pdata.mode = MUSB_PORT_MODE_HOST; 622 break; 623 #endif 624 #if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_GADGET 625 case USB_DR_MODE_PERIPHERAL: 626 pdata.mode = MUSB_PORT_MODE_GADGET; 627 break; 628 #endif 629 #ifdef CONFIG_USB_MUSB_DUAL_ROLE 630 case USB_DR_MODE_OTG: 631 pdata.mode = MUSB_PORT_MODE_DUAL_ROLE; 632 break; 633 #endif 634 default: 635 dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n"); 636 return -EINVAL; 637 } 638 pdata.platform_ops = &sunxi_musb_ops; 639 pdata.config = &sunxi_musb_hdrc_config; 640 641 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); 642 if (!glue) 643 return -ENOMEM; 644 645 glue->dev = &pdev->dev; 646 INIT_WORK(&glue->work, sunxi_musb_work); 647 glue->host_nb.notifier_call = sunxi_musb_host_notifier; 648 649 if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb")) 650 set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags); 651 652 if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb")) 653 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags); 654 655 if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb")) { 656 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags); 657 set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags); 658 } 659 660 glue->clk = devm_clk_get(&pdev->dev, NULL); 661 if (IS_ERR(glue->clk)) { 662 dev_err(&pdev->dev, "Error getting clock: %ld\n", 663 PTR_ERR(glue->clk)); 664 return PTR_ERR(glue->clk); 665 } 666 667 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) { 668 glue->rst = devm_reset_control_get(&pdev->dev, NULL); 669 if (IS_ERR(glue->rst)) { 670 if (PTR_ERR(glue->rst) == -EPROBE_DEFER) 671 return -EPROBE_DEFER; 672 dev_err(&pdev->dev, "Error getting reset %ld\n", 673 PTR_ERR(glue->rst)); 674 return PTR_ERR(glue->rst); 675 } 676 } 677 678 glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0); 679 if (IS_ERR(glue->extcon)) { 680 if (PTR_ERR(glue->extcon) == -EPROBE_DEFER) 681 return -EPROBE_DEFER; 682 dev_err(&pdev->dev, "Invalid or missing extcon\n"); 683 return PTR_ERR(glue->extcon); 684 } 685 686 glue->phy = devm_phy_get(&pdev->dev, "usb"); 687 if (IS_ERR(glue->phy)) { 688 if (PTR_ERR(glue->phy) == -EPROBE_DEFER) 689 return -EPROBE_DEFER; 690 dev_err(&pdev->dev, "Error getting phy %ld\n", 691 PTR_ERR(glue->phy)); 692 return PTR_ERR(glue->phy); 693 } 694 695 glue->usb_phy = usb_phy_generic_register(); 696 if (IS_ERR(glue->usb_phy)) { 697 dev_err(&pdev->dev, "Error registering usb-phy %ld\n", 698 PTR_ERR(glue->usb_phy)); 699 return PTR_ERR(glue->usb_phy); 700 } 701 702 glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2); 703 if (IS_ERR(glue->xceiv)) { 704 ret = PTR_ERR(glue->xceiv); 705 dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret); 706 goto err_unregister_usb_phy; 707 } 708 709 platform_set_drvdata(pdev, glue); 710 711 memset(&pinfo, 0, sizeof(pinfo)); 712 pinfo.name = "musb-hdrc"; 713 pinfo.id = PLATFORM_DEVID_AUTO; 714 pinfo.parent = &pdev->dev; 715 pinfo.res = pdev->resource; 716 pinfo.num_res = pdev->num_resources; 717 pinfo.data = &pdata; 718 pinfo.size_data = sizeof(pdata); 719 720 glue->musb_pdev = platform_device_register_full(&pinfo); 721 if (IS_ERR(glue->musb_pdev)) { 722 ret = PTR_ERR(glue->musb_pdev); 723 dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret); 724 goto err_unregister_usb_phy; 725 } 726 727 return 0; 728 729 err_unregister_usb_phy: 730 usb_phy_generic_unregister(glue->usb_phy); 731 return ret; 732 } 733 734 static int sunxi_musb_remove(struct platform_device *pdev) 735 { 736 struct sunxi_glue *glue = platform_get_drvdata(pdev); 737 struct platform_device *usb_phy = glue->usb_phy; 738 739 platform_device_unregister(glue->musb_pdev); 740 usb_phy_generic_unregister(usb_phy); 741 742 return 0; 743 } 744 745 static const struct of_device_id sunxi_musb_match[] = { 746 { .compatible = "allwinner,sun4i-a10-musb", }, 747 { .compatible = "allwinner,sun6i-a31-musb", }, 748 { .compatible = "allwinner,sun8i-a33-musb", }, 749 {} 750 }; 751 MODULE_DEVICE_TABLE(of, sunxi_musb_match); 752 753 static struct platform_driver sunxi_musb_driver = { 754 .probe = sunxi_musb_probe, 755 .remove = sunxi_musb_remove, 756 .driver = { 757 .name = "musb-sunxi", 758 .of_match_table = sunxi_musb_match, 759 }, 760 }; 761 module_platform_driver(sunxi_musb_driver); 762 763 MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer"); 764 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>"); 765 MODULE_LICENSE("GPL v2"); 766