1 /* 2 * Copyright (C) 2005-2007 by Texas Instruments 3 * Some code has been taken from tusb6010.c 4 * Copyrights for that are attributable to: 5 * Copyright (C) 2006 Nokia Corporation 6 * Tony Lindgren <tony@atomide.com> 7 * 8 * This file is part of the Inventra Controller Driver for Linux. 9 * 10 * The Inventra Controller Driver for Linux is free software; you 11 * can redistribute it and/or modify it under the terms of the GNU 12 * General Public License version 2 as published by the Free Software 13 * Foundation. 14 * 15 * The Inventra Controller Driver for Linux is distributed in 16 * the hope that it will be useful, but WITHOUT ANY WARRANTY; 17 * without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19 * License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with The Inventra Controller Driver for Linux ; if not, 23 * write to the Free Software Foundation, Inc., 59 Temple Place, 24 * Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27 #include <linux/module.h> 28 #include <linux/kernel.h> 29 #include <linux/sched.h> 30 #include <linux/slab.h> 31 #include <linux/init.h> 32 #include <linux/list.h> 33 #include <linux/clk.h> 34 #include <linux/io.h> 35 36 #include <asm/mach-types.h> 37 #include <mach/hardware.h> 38 #include <plat/mux.h> 39 40 #include "musb_core.h" 41 #include "omap2430.h" 42 43 #ifdef CONFIG_ARCH_OMAP3430 44 #define get_cpu_rev() 2 45 #endif 46 47 48 static struct timer_list musb_idle_timer; 49 50 static void musb_do_idle(unsigned long _musb) 51 { 52 struct musb *musb = (void *)_musb; 53 unsigned long flags; 54 #ifdef CONFIG_USB_MUSB_HDRC_HCD 55 u8 power; 56 #endif 57 u8 devctl; 58 59 spin_lock_irqsave(&musb->lock, flags); 60 61 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 62 63 switch (musb->xceiv->state) { 64 case OTG_STATE_A_WAIT_BCON: 65 devctl &= ~MUSB_DEVCTL_SESSION; 66 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 67 68 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 69 if (devctl & MUSB_DEVCTL_BDEVICE) { 70 musb->xceiv->state = OTG_STATE_B_IDLE; 71 MUSB_DEV_MODE(musb); 72 } else { 73 musb->xceiv->state = OTG_STATE_A_IDLE; 74 MUSB_HST_MODE(musb); 75 } 76 break; 77 #ifdef CONFIG_USB_MUSB_HDRC_HCD 78 case OTG_STATE_A_SUSPEND: 79 /* finish RESUME signaling? */ 80 if (musb->port1_status & MUSB_PORT_STAT_RESUME) { 81 power = musb_readb(musb->mregs, MUSB_POWER); 82 power &= ~MUSB_POWER_RESUME; 83 DBG(1, "root port resume stopped, power %02x\n", power); 84 musb_writeb(musb->mregs, MUSB_POWER, power); 85 musb->is_active = 1; 86 musb->port1_status &= ~(USB_PORT_STAT_SUSPEND 87 | MUSB_PORT_STAT_RESUME); 88 musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16; 89 usb_hcd_poll_rh_status(musb_to_hcd(musb)); 90 /* NOTE: it might really be A_WAIT_BCON ... */ 91 musb->xceiv->state = OTG_STATE_A_HOST; 92 } 93 break; 94 #endif 95 #ifdef CONFIG_USB_MUSB_HDRC_HCD 96 case OTG_STATE_A_HOST: 97 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 98 if (devctl & MUSB_DEVCTL_BDEVICE) 99 musb->xceiv->state = OTG_STATE_B_IDLE; 100 else 101 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 102 #endif 103 default: 104 break; 105 } 106 spin_unlock_irqrestore(&musb->lock, flags); 107 } 108 109 110 void musb_platform_try_idle(struct musb *musb, unsigned long timeout) 111 { 112 unsigned long default_timeout = jiffies + msecs_to_jiffies(3); 113 static unsigned long last_timer; 114 115 if (timeout == 0) 116 timeout = default_timeout; 117 118 /* Never idle if active, or when VBUS timeout is not set as host */ 119 if (musb->is_active || ((musb->a_wait_bcon == 0) 120 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) { 121 DBG(4, "%s active, deleting timer\n", otg_state_string(musb)); 122 del_timer(&musb_idle_timer); 123 last_timer = jiffies; 124 return; 125 } 126 127 if (time_after(last_timer, timeout)) { 128 if (!timer_pending(&musb_idle_timer)) 129 last_timer = timeout; 130 else { 131 DBG(4, "Longer idle timer already pending, ignoring\n"); 132 return; 133 } 134 } 135 last_timer = timeout; 136 137 DBG(4, "%s inactive, for idle timer for %lu ms\n", 138 otg_state_string(musb), 139 (unsigned long)jiffies_to_msecs(timeout - jiffies)); 140 mod_timer(&musb_idle_timer, timeout); 141 } 142 143 void musb_platform_enable(struct musb *musb) 144 { 145 } 146 void musb_platform_disable(struct musb *musb) 147 { 148 } 149 static void omap_vbus_power(struct musb *musb, int is_on, int sleeping) 150 { 151 } 152 153 static void omap_set_vbus(struct musb *musb, int is_on) 154 { 155 u8 devctl; 156 /* HDRC controls CPEN, but beware current surges during device 157 * connect. They can trigger transient overcurrent conditions 158 * that must be ignored. 159 */ 160 161 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 162 163 if (is_on) { 164 musb->is_active = 1; 165 musb->xceiv->default_a = 1; 166 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; 167 devctl |= MUSB_DEVCTL_SESSION; 168 169 MUSB_HST_MODE(musb); 170 } else { 171 musb->is_active = 0; 172 173 /* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and 174 * jumping right to B_IDLE... 175 */ 176 177 musb->xceiv->default_a = 0; 178 musb->xceiv->state = OTG_STATE_B_IDLE; 179 devctl &= ~MUSB_DEVCTL_SESSION; 180 181 MUSB_DEV_MODE(musb); 182 } 183 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 184 185 DBG(1, "VBUS %s, devctl %02x " 186 /* otg %3x conf %08x prcm %08x */ "\n", 187 otg_state_string(musb), 188 musb_readb(musb->mregs, MUSB_DEVCTL)); 189 } 190 191 static int musb_platform_resume(struct musb *musb); 192 193 int musb_platform_set_mode(struct musb *musb, u8 musb_mode) 194 { 195 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 196 197 devctl |= MUSB_DEVCTL_SESSION; 198 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); 199 200 return 0; 201 } 202 203 int __init musb_platform_init(struct musb *musb) 204 { 205 u32 l; 206 207 #if defined(CONFIG_ARCH_OMAP2430) 208 omap_cfg_reg(AE5_2430_USB0HS_STP); 209 #endif 210 211 /* We require some kind of external transceiver, hooked 212 * up through ULPI. TWL4030-family PMICs include one, 213 * which needs a driver, drivers aren't always needed. 214 */ 215 musb->xceiv = otg_get_transceiver(); 216 if (!musb->xceiv) { 217 pr_err("HS USB OTG: no transceiver configured\n"); 218 return -ENODEV; 219 } 220 221 musb_platform_resume(musb); 222 223 l = omap_readl(OTG_SYSCONFIG); 224 l &= ~ENABLEWAKEUP; /* disable wakeup */ 225 l &= ~NOSTDBY; /* remove possible nostdby */ 226 l |= SMARTSTDBY; /* enable smart standby */ 227 l &= ~AUTOIDLE; /* disable auto idle */ 228 l &= ~NOIDLE; /* remove possible noidle */ 229 l |= SMARTIDLE; /* enable smart idle */ 230 /* 231 * MUSB AUTOIDLE don't work in 3430. 232 * Workaround by Richard Woodruff/TI 233 */ 234 if (!cpu_is_omap3430()) 235 l |= AUTOIDLE; /* enable auto idle */ 236 omap_writel(l, OTG_SYSCONFIG); 237 238 l = omap_readl(OTG_INTERFSEL); 239 l |= ULPI_12PIN; 240 omap_writel(l, OTG_INTERFSEL); 241 242 pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, " 243 "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n", 244 omap_readl(OTG_REVISION), omap_readl(OTG_SYSCONFIG), 245 omap_readl(OTG_SYSSTATUS), omap_readl(OTG_INTERFSEL), 246 omap_readl(OTG_SIMENABLE)); 247 248 omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1); 249 250 if (is_host_enabled(musb)) 251 musb->board_set_vbus = omap_set_vbus; 252 253 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); 254 255 return 0; 256 } 257 258 int musb_platform_suspend(struct musb *musb) 259 { 260 u32 l; 261 262 if (!musb->clock) 263 return 0; 264 265 /* in any role */ 266 l = omap_readl(OTG_FORCESTDBY); 267 l |= ENABLEFORCE; /* enable MSTANDBY */ 268 omap_writel(l, OTG_FORCESTDBY); 269 270 l = omap_readl(OTG_SYSCONFIG); 271 l |= ENABLEWAKEUP; /* enable wakeup */ 272 omap_writel(l, OTG_SYSCONFIG); 273 274 otg_set_suspend(musb->xceiv, 1); 275 276 if (musb->set_clock) 277 musb->set_clock(musb->clock, 0); 278 else 279 clk_disable(musb->clock); 280 281 return 0; 282 } 283 284 static int musb_platform_resume(struct musb *musb) 285 { 286 u32 l; 287 288 if (!musb->clock) 289 return 0; 290 291 otg_set_suspend(musb->xceiv, 0); 292 293 if (musb->set_clock) 294 musb->set_clock(musb->clock, 1); 295 else 296 clk_enable(musb->clock); 297 298 l = omap_readl(OTG_SYSCONFIG); 299 l &= ~ENABLEWAKEUP; /* disable wakeup */ 300 omap_writel(l, OTG_SYSCONFIG); 301 302 l = omap_readl(OTG_FORCESTDBY); 303 l &= ~ENABLEFORCE; /* disable MSTANDBY */ 304 omap_writel(l, OTG_FORCESTDBY); 305 306 return 0; 307 } 308 309 310 int musb_platform_exit(struct musb *musb) 311 { 312 313 omap_vbus_power(musb, 0 /*off*/, 1); 314 315 musb_platform_suspend(musb); 316 317 clk_put(musb->clock); 318 musb->clock = NULL; 319 320 return 0; 321 } 322