1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MUSB OTG driver - support for Mentor's DMA controller 4 * 5 * Copyright 2005 Mentor Graphics Corporation 6 * Copyright (C) 2005-2007 by Texas Instruments 7 */ 8 #include <linux/device.h> 9 #include <linux/interrupt.h> 10 #include <linux/platform_device.h> 11 #include <linux/slab.h> 12 #include "musb_core.h" 13 #include "musbhsdma.h" 14 15 static void dma_channel_release(struct dma_channel *channel); 16 17 static void dma_controller_stop(struct musb_dma_controller *controller) 18 { 19 struct musb *musb = controller->private_data; 20 struct dma_channel *channel; 21 u8 bit; 22 23 if (controller->used_channels != 0) { 24 dev_err(musb->controller, 25 "Stopping DMA controller while channel active\n"); 26 27 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { 28 if (controller->used_channels & (1 << bit)) { 29 channel = &controller->channel[bit].channel; 30 dma_channel_release(channel); 31 32 if (!controller->used_channels) 33 break; 34 } 35 } 36 } 37 } 38 39 static struct dma_channel *dma_channel_allocate(struct dma_controller *c, 40 struct musb_hw_ep *hw_ep, u8 transmit) 41 { 42 struct musb_dma_controller *controller = container_of(c, 43 struct musb_dma_controller, controller); 44 struct musb_dma_channel *musb_channel = NULL; 45 struct dma_channel *channel = NULL; 46 u8 bit; 47 48 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { 49 if (!(controller->used_channels & (1 << bit))) { 50 controller->used_channels |= (1 << bit); 51 musb_channel = &(controller->channel[bit]); 52 musb_channel->controller = controller; 53 musb_channel->idx = bit; 54 musb_channel->epnum = hw_ep->epnum; 55 musb_channel->transmit = transmit; 56 channel = &(musb_channel->channel); 57 channel->private_data = musb_channel; 58 channel->status = MUSB_DMA_STATUS_FREE; 59 channel->max_len = 0x100000; 60 /* Tx => mode 1; Rx => mode 0 */ 61 channel->desired_mode = transmit; 62 channel->actual_len = 0; 63 break; 64 } 65 } 66 67 return channel; 68 } 69 70 static void dma_channel_release(struct dma_channel *channel) 71 { 72 struct musb_dma_channel *musb_channel = channel->private_data; 73 74 channel->actual_len = 0; 75 musb_channel->start_addr = 0; 76 musb_channel->len = 0; 77 78 musb_channel->controller->used_channels &= 79 ~(1 << musb_channel->idx); 80 81 channel->status = MUSB_DMA_STATUS_UNKNOWN; 82 } 83 84 static void configure_channel(struct dma_channel *channel, 85 u16 packet_sz, u8 mode, 86 dma_addr_t dma_addr, u32 len) 87 { 88 struct musb_dma_channel *musb_channel = channel->private_data; 89 struct musb_dma_controller *controller = musb_channel->controller; 90 struct musb *musb = controller->private_data; 91 void __iomem *mbase = controller->base; 92 u8 bchannel = musb_channel->idx; 93 u16 csr = 0; 94 95 musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d", 96 channel, packet_sz, &dma_addr, len, mode); 97 98 if (mode) { 99 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; 100 BUG_ON(len < packet_sz); 101 } 102 csr |= MUSB_HSDMA_BURSTMODE_INCR16 103 << MUSB_HSDMA_BURSTMODE_SHIFT; 104 105 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) 106 | (1 << MUSB_HSDMA_ENABLE_SHIFT) 107 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) 108 | (musb_channel->transmit 109 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) 110 : 0); 111 112 /* address/count */ 113 musb_write_hsdma_addr(mbase, bchannel, dma_addr); 114 musb_write_hsdma_count(mbase, bchannel, len); 115 116 /* control (this should start things) */ 117 musb_writew(mbase, 118 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), 119 csr); 120 } 121 122 static int dma_channel_program(struct dma_channel *channel, 123 u16 packet_sz, u8 mode, 124 dma_addr_t dma_addr, u32 len) 125 { 126 struct musb_dma_channel *musb_channel = channel->private_data; 127 struct musb_dma_controller *controller = musb_channel->controller; 128 struct musb *musb = controller->private_data; 129 130 musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d", 131 musb_channel->epnum, 132 musb_channel->transmit ? "Tx" : "Rx", 133 packet_sz, &dma_addr, len, mode); 134 135 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || 136 channel->status == MUSB_DMA_STATUS_BUSY); 137 138 /* Let targets check/tweak the arguments */ 139 if (musb->ops->adjust_channel_params) { 140 int ret = musb->ops->adjust_channel_params(channel, 141 packet_sz, &mode, &dma_addr, &len); 142 if (ret) 143 return ret; 144 } 145 146 /* 147 * The DMA engine in RTL1.8 and above cannot handle 148 * DMA addresses that are not aligned to a 4 byte boundary. 149 * It ends up masking the last two bits of the address 150 * programmed in DMA_ADDR. 151 * 152 * Fail such DMA transfers, so that the backup PIO mode 153 * can carry out the transfer 154 */ 155 if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4)) 156 return false; 157 158 channel->actual_len = 0; 159 musb_channel->start_addr = dma_addr; 160 musb_channel->len = len; 161 musb_channel->max_packet_sz = packet_sz; 162 channel->status = MUSB_DMA_STATUS_BUSY; 163 164 configure_channel(channel, packet_sz, mode, dma_addr, len); 165 166 return true; 167 } 168 169 static int dma_channel_abort(struct dma_channel *channel) 170 { 171 struct musb_dma_channel *musb_channel = channel->private_data; 172 void __iomem *mbase = musb_channel->controller->base; 173 struct musb *musb = musb_channel->controller->private_data; 174 175 u8 bchannel = musb_channel->idx; 176 int offset; 177 u16 csr; 178 179 if (channel->status == MUSB_DMA_STATUS_BUSY) { 180 if (musb_channel->transmit) { 181 offset = musb->io.ep_offset(musb_channel->epnum, 182 MUSB_TXCSR); 183 184 /* 185 * The programming guide says that we must clear 186 * the DMAENAB bit before the DMAMODE bit... 187 */ 188 csr = musb_readw(mbase, offset); 189 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 190 musb_writew(mbase, offset, csr); 191 csr &= ~MUSB_TXCSR_DMAMODE; 192 musb_writew(mbase, offset, csr); 193 } else { 194 offset = musb->io.ep_offset(musb_channel->epnum, 195 MUSB_RXCSR); 196 197 csr = musb_readw(mbase, offset); 198 csr &= ~(MUSB_RXCSR_AUTOCLEAR | 199 MUSB_RXCSR_DMAENAB | 200 MUSB_RXCSR_DMAMODE); 201 musb_writew(mbase, offset, csr); 202 } 203 204 musb_writew(mbase, 205 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), 206 0); 207 musb_write_hsdma_addr(mbase, bchannel, 0); 208 musb_write_hsdma_count(mbase, bchannel, 0); 209 channel->status = MUSB_DMA_STATUS_FREE; 210 } 211 212 return 0; 213 } 214 215 static irqreturn_t dma_controller_irq(int irq, void *private_data) 216 { 217 struct musb_dma_controller *controller = private_data; 218 struct musb *musb = controller->private_data; 219 struct musb_dma_channel *musb_channel; 220 struct dma_channel *channel; 221 222 void __iomem *mbase = controller->base; 223 224 irqreturn_t retval = IRQ_NONE; 225 226 unsigned long flags; 227 228 u8 bchannel; 229 u8 int_hsdma; 230 231 u32 addr, count; 232 u16 csr; 233 234 spin_lock_irqsave(&musb->lock, flags); 235 236 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); 237 238 #ifdef CONFIG_BLACKFIN 239 /* Clear DMA interrupt flags */ 240 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma); 241 #endif 242 243 if (!int_hsdma) { 244 musb_dbg(musb, "spurious DMA irq"); 245 246 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 247 musb_channel = (struct musb_dma_channel *) 248 &(controller->channel[bchannel]); 249 channel = &musb_channel->channel; 250 if (channel->status == MUSB_DMA_STATUS_BUSY) { 251 count = musb_read_hsdma_count(mbase, bchannel); 252 253 if (count == 0) 254 int_hsdma |= (1 << bchannel); 255 } 256 } 257 258 musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma); 259 260 if (!int_hsdma) 261 goto done; 262 } 263 264 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 265 if (int_hsdma & (1 << bchannel)) { 266 musb_channel = (struct musb_dma_channel *) 267 &(controller->channel[bchannel]); 268 channel = &musb_channel->channel; 269 270 csr = musb_readw(mbase, 271 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, 272 MUSB_HSDMA_CONTROL)); 273 274 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) { 275 musb_channel->channel.status = 276 MUSB_DMA_STATUS_BUS_ABORT; 277 } else { 278 u8 devctl; 279 280 addr = musb_read_hsdma_addr(mbase, 281 bchannel); 282 channel->actual_len = addr 283 - musb_channel->start_addr; 284 285 musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s", 286 channel, musb_channel->start_addr, 287 addr, channel->actual_len, 288 musb_channel->len, 289 (channel->actual_len 290 < musb_channel->len) ? 291 "=> reconfig 0" : "=> complete"); 292 293 devctl = musb_readb(mbase, MUSB_DEVCTL); 294 295 channel->status = MUSB_DMA_STATUS_FREE; 296 297 /* completed */ 298 if ((devctl & MUSB_DEVCTL_HM) 299 && (musb_channel->transmit) 300 && ((channel->desired_mode == 0) 301 || (channel->actual_len & 302 (musb_channel->max_packet_sz - 1))) 303 ) { 304 u8 epnum = musb_channel->epnum; 305 int offset = musb->io.ep_offset(epnum, 306 MUSB_TXCSR); 307 u16 txcsr; 308 309 /* 310 * The programming guide says that we 311 * must clear DMAENAB before DMAMODE. 312 */ 313 musb_ep_select(mbase, epnum); 314 txcsr = musb_readw(mbase, offset); 315 txcsr &= ~(MUSB_TXCSR_DMAENAB 316 | MUSB_TXCSR_AUTOSET); 317 musb_writew(mbase, offset, txcsr); 318 /* Send out the packet */ 319 txcsr &= ~MUSB_TXCSR_DMAMODE; 320 txcsr |= MUSB_TXCSR_TXPKTRDY; 321 musb_writew(mbase, offset, txcsr); 322 } 323 musb_dma_completion(musb, musb_channel->epnum, 324 musb_channel->transmit); 325 } 326 } 327 } 328 329 retval = IRQ_HANDLED; 330 done: 331 spin_unlock_irqrestore(&musb->lock, flags); 332 return retval; 333 } 334 335 void musbhs_dma_controller_destroy(struct dma_controller *c) 336 { 337 struct musb_dma_controller *controller = container_of(c, 338 struct musb_dma_controller, controller); 339 340 dma_controller_stop(controller); 341 342 if (controller->irq) 343 free_irq(controller->irq, c); 344 345 kfree(controller); 346 } 347 EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy); 348 349 struct dma_controller *musbhs_dma_controller_create(struct musb *musb, 350 void __iomem *base) 351 { 352 struct musb_dma_controller *controller; 353 struct device *dev = musb->controller; 354 struct platform_device *pdev = to_platform_device(dev); 355 int irq = platform_get_irq_byname(pdev, "dma"); 356 357 if (irq <= 0) { 358 dev_err(dev, "No DMA interrupt line!\n"); 359 return NULL; 360 } 361 362 controller = kzalloc(sizeof(*controller), GFP_KERNEL); 363 if (!controller) 364 return NULL; 365 366 controller->channel_count = MUSB_HSDMA_CHANNELS; 367 controller->private_data = musb; 368 controller->base = base; 369 370 controller->controller.channel_alloc = dma_channel_allocate; 371 controller->controller.channel_release = dma_channel_release; 372 controller->controller.channel_program = dma_channel_program; 373 controller->controller.channel_abort = dma_channel_abort; 374 375 if (request_irq(irq, dma_controller_irq, 0, 376 dev_name(musb->controller), &controller->controller)) { 377 dev_err(dev, "request_irq %d failed!\n", irq); 378 musb_dma_controller_destroy(&controller->controller); 379 380 return NULL; 381 } 382 383 controller->irq = irq; 384 385 return &controller->controller; 386 } 387 EXPORT_SYMBOL_GPL(musbhs_dma_controller_create); 388