1 /* 2 * MUSB OTG driver - support for Mentor's DMA controller 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2007 by Texas Instruments 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 19 * 02110-1301 USA 20 * 21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 #include <linux/device.h> 34 #include <linux/interrupt.h> 35 #include <linux/platform_device.h> 36 #include <linux/slab.h> 37 #include "musb_core.h" 38 #include "musbhsdma.h" 39 40 static int dma_controller_start(struct dma_controller *c) 41 { 42 /* nothing to do */ 43 return 0; 44 } 45 46 static void dma_channel_release(struct dma_channel *channel); 47 48 static int dma_controller_stop(struct dma_controller *c) 49 { 50 struct musb_dma_controller *controller = container_of(c, 51 struct musb_dma_controller, controller); 52 struct musb *musb = controller->private_data; 53 struct dma_channel *channel; 54 u8 bit; 55 56 if (controller->used_channels != 0) { 57 dev_err(musb->controller, 58 "Stopping DMA controller while channel active\n"); 59 60 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { 61 if (controller->used_channels & (1 << bit)) { 62 channel = &controller->channel[bit].channel; 63 dma_channel_release(channel); 64 65 if (!controller->used_channels) 66 break; 67 } 68 } 69 } 70 71 return 0; 72 } 73 74 static struct dma_channel *dma_channel_allocate(struct dma_controller *c, 75 struct musb_hw_ep *hw_ep, u8 transmit) 76 { 77 struct musb_dma_controller *controller = container_of(c, 78 struct musb_dma_controller, controller); 79 struct musb_dma_channel *musb_channel = NULL; 80 struct dma_channel *channel = NULL; 81 u8 bit; 82 83 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { 84 if (!(controller->used_channels & (1 << bit))) { 85 controller->used_channels |= (1 << bit); 86 musb_channel = &(controller->channel[bit]); 87 musb_channel->controller = controller; 88 musb_channel->idx = bit; 89 musb_channel->epnum = hw_ep->epnum; 90 musb_channel->transmit = transmit; 91 channel = &(musb_channel->channel); 92 channel->private_data = musb_channel; 93 channel->status = MUSB_DMA_STATUS_FREE; 94 channel->max_len = 0x100000; 95 /* Tx => mode 1; Rx => mode 0 */ 96 channel->desired_mode = transmit; 97 channel->actual_len = 0; 98 break; 99 } 100 } 101 102 return channel; 103 } 104 105 static void dma_channel_release(struct dma_channel *channel) 106 { 107 struct musb_dma_channel *musb_channel = channel->private_data; 108 109 channel->actual_len = 0; 110 musb_channel->start_addr = 0; 111 musb_channel->len = 0; 112 113 musb_channel->controller->used_channels &= 114 ~(1 << musb_channel->idx); 115 116 channel->status = MUSB_DMA_STATUS_UNKNOWN; 117 } 118 119 static void configure_channel(struct dma_channel *channel, 120 u16 packet_sz, u8 mode, 121 dma_addr_t dma_addr, u32 len) 122 { 123 struct musb_dma_channel *musb_channel = channel->private_data; 124 struct musb_dma_controller *controller = musb_channel->controller; 125 void __iomem *mbase = controller->base; 126 u8 bchannel = musb_channel->idx; 127 u16 csr = 0; 128 129 DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", 130 channel, packet_sz, dma_addr, len, mode); 131 132 if (mode) { 133 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; 134 BUG_ON(len < packet_sz); 135 } 136 csr |= MUSB_HSDMA_BURSTMODE_INCR16 137 << MUSB_HSDMA_BURSTMODE_SHIFT; 138 139 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) 140 | (1 << MUSB_HSDMA_ENABLE_SHIFT) 141 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) 142 | (musb_channel->transmit 143 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) 144 : 0); 145 146 /* address/count */ 147 musb_write_hsdma_addr(mbase, bchannel, dma_addr); 148 musb_write_hsdma_count(mbase, bchannel, len); 149 150 /* control (this should start things) */ 151 musb_writew(mbase, 152 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), 153 csr); 154 } 155 156 static int dma_channel_program(struct dma_channel *channel, 157 u16 packet_sz, u8 mode, 158 dma_addr_t dma_addr, u32 len) 159 { 160 struct musb_dma_channel *musb_channel = channel->private_data; 161 struct musb_dma_controller *controller = musb_channel->controller; 162 struct musb *musb = controller->private_data; 163 164 DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", 165 musb_channel->epnum, 166 musb_channel->transmit ? "Tx" : "Rx", 167 packet_sz, dma_addr, len, mode); 168 169 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || 170 channel->status == MUSB_DMA_STATUS_BUSY); 171 172 /* 173 * The DMA engine in RTL1.8 and above cannot handle 174 * DMA addresses that are not aligned to a 4 byte boundary. 175 * It ends up masking the last two bits of the address 176 * programmed in DMA_ADDR. 177 * 178 * Fail such DMA transfers, so that the backup PIO mode 179 * can carry out the transfer 180 */ 181 if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4)) 182 return false; 183 184 channel->actual_len = 0; 185 musb_channel->start_addr = dma_addr; 186 musb_channel->len = len; 187 musb_channel->max_packet_sz = packet_sz; 188 channel->status = MUSB_DMA_STATUS_BUSY; 189 190 configure_channel(channel, packet_sz, mode, dma_addr, len); 191 192 return true; 193 } 194 195 static int dma_channel_abort(struct dma_channel *channel) 196 { 197 struct musb_dma_channel *musb_channel = channel->private_data; 198 void __iomem *mbase = musb_channel->controller->base; 199 200 u8 bchannel = musb_channel->idx; 201 int offset; 202 u16 csr; 203 204 if (channel->status == MUSB_DMA_STATUS_BUSY) { 205 if (musb_channel->transmit) { 206 offset = MUSB_EP_OFFSET(musb_channel->epnum, 207 MUSB_TXCSR); 208 209 /* 210 * The programming guide says that we must clear 211 * the DMAENAB bit before the DMAMODE bit... 212 */ 213 csr = musb_readw(mbase, offset); 214 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 215 musb_writew(mbase, offset, csr); 216 csr &= ~MUSB_TXCSR_DMAMODE; 217 musb_writew(mbase, offset, csr); 218 } else { 219 offset = MUSB_EP_OFFSET(musb_channel->epnum, 220 MUSB_RXCSR); 221 222 csr = musb_readw(mbase, offset); 223 csr &= ~(MUSB_RXCSR_AUTOCLEAR | 224 MUSB_RXCSR_DMAENAB | 225 MUSB_RXCSR_DMAMODE); 226 musb_writew(mbase, offset, csr); 227 } 228 229 musb_writew(mbase, 230 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), 231 0); 232 musb_write_hsdma_addr(mbase, bchannel, 0); 233 musb_write_hsdma_count(mbase, bchannel, 0); 234 channel->status = MUSB_DMA_STATUS_FREE; 235 } 236 237 return 0; 238 } 239 240 static irqreturn_t dma_controller_irq(int irq, void *private_data) 241 { 242 struct musb_dma_controller *controller = private_data; 243 struct musb *musb = controller->private_data; 244 struct musb_dma_channel *musb_channel; 245 struct dma_channel *channel; 246 247 void __iomem *mbase = controller->base; 248 249 irqreturn_t retval = IRQ_NONE; 250 251 unsigned long flags; 252 253 u8 bchannel; 254 u8 int_hsdma; 255 256 u32 addr, count; 257 u16 csr; 258 259 spin_lock_irqsave(&musb->lock, flags); 260 261 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); 262 263 #ifdef CONFIG_BLACKFIN 264 /* Clear DMA interrupt flags */ 265 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma); 266 #endif 267 268 if (!int_hsdma) { 269 DBG(2, "spurious DMA irq\n"); 270 271 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 272 musb_channel = (struct musb_dma_channel *) 273 &(controller->channel[bchannel]); 274 channel = &musb_channel->channel; 275 if (channel->status == MUSB_DMA_STATUS_BUSY) { 276 count = musb_read_hsdma_count(mbase, bchannel); 277 278 if (count == 0) 279 int_hsdma |= (1 << bchannel); 280 } 281 } 282 283 DBG(2, "int_hsdma = 0x%x\n", int_hsdma); 284 285 if (!int_hsdma) 286 goto done; 287 } 288 289 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 290 if (int_hsdma & (1 << bchannel)) { 291 musb_channel = (struct musb_dma_channel *) 292 &(controller->channel[bchannel]); 293 channel = &musb_channel->channel; 294 295 csr = musb_readw(mbase, 296 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, 297 MUSB_HSDMA_CONTROL)); 298 299 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) { 300 musb_channel->channel.status = 301 MUSB_DMA_STATUS_BUS_ABORT; 302 } else { 303 u8 devctl; 304 305 addr = musb_read_hsdma_addr(mbase, 306 bchannel); 307 channel->actual_len = addr 308 - musb_channel->start_addr; 309 310 DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n", 311 channel, musb_channel->start_addr, 312 addr, channel->actual_len, 313 musb_channel->len, 314 (channel->actual_len 315 < musb_channel->len) ? 316 "=> reconfig 0" : "=> complete"); 317 318 devctl = musb_readb(mbase, MUSB_DEVCTL); 319 320 channel->status = MUSB_DMA_STATUS_FREE; 321 322 /* completed */ 323 if ((devctl & MUSB_DEVCTL_HM) 324 && (musb_channel->transmit) 325 && ((channel->desired_mode == 0) 326 || (channel->actual_len & 327 (musb_channel->max_packet_sz - 1))) 328 ) { 329 u8 epnum = musb_channel->epnum; 330 int offset = MUSB_EP_OFFSET(epnum, 331 MUSB_TXCSR); 332 u16 txcsr; 333 334 /* 335 * The programming guide says that we 336 * must clear DMAENAB before DMAMODE. 337 */ 338 musb_ep_select(mbase, epnum); 339 txcsr = musb_readw(mbase, offset); 340 txcsr &= ~(MUSB_TXCSR_DMAENAB 341 | MUSB_TXCSR_AUTOSET); 342 musb_writew(mbase, offset, txcsr); 343 /* Send out the packet */ 344 txcsr &= ~MUSB_TXCSR_DMAMODE; 345 txcsr |= MUSB_TXCSR_TXPKTRDY; 346 musb_writew(mbase, offset, txcsr); 347 } 348 musb_dma_completion(musb, musb_channel->epnum, 349 musb_channel->transmit); 350 } 351 } 352 } 353 354 retval = IRQ_HANDLED; 355 done: 356 spin_unlock_irqrestore(&musb->lock, flags); 357 return retval; 358 } 359 360 void dma_controller_destroy(struct dma_controller *c) 361 { 362 struct musb_dma_controller *controller = container_of(c, 363 struct musb_dma_controller, controller); 364 365 if (!controller) 366 return; 367 368 if (controller->irq) 369 free_irq(controller->irq, c); 370 371 kfree(controller); 372 } 373 374 struct dma_controller *__init 375 dma_controller_create(struct musb *musb, void __iomem *base) 376 { 377 struct musb_dma_controller *controller; 378 struct device *dev = musb->controller; 379 struct platform_device *pdev = to_platform_device(dev); 380 int irq = platform_get_irq_byname(pdev, "dma"); 381 382 if (irq == 0) { 383 dev_err(dev, "No DMA interrupt line!\n"); 384 return NULL; 385 } 386 387 controller = kzalloc(sizeof(*controller), GFP_KERNEL); 388 if (!controller) 389 return NULL; 390 391 controller->channel_count = MUSB_HSDMA_CHANNELS; 392 controller->private_data = musb; 393 controller->base = base; 394 395 controller->controller.start = dma_controller_start; 396 controller->controller.stop = dma_controller_stop; 397 controller->controller.channel_alloc = dma_channel_allocate; 398 controller->controller.channel_release = dma_channel_release; 399 controller->controller.channel_program = dma_channel_program; 400 controller->controller.channel_abort = dma_channel_abort; 401 402 if (request_irq(irq, dma_controller_irq, IRQF_DISABLED, 403 dev_name(musb->controller), &controller->controller)) { 404 dev_err(dev, "request_irq %d failed!\n", irq); 405 dma_controller_destroy(&controller->controller); 406 407 return NULL; 408 } 409 410 controller->irq = irq; 411 412 return &controller->controller; 413 } 414