1 /* 2 * MUSB OTG driver host support 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <linux/module.h> 37 #include <linux/kernel.h> 38 #include <linux/delay.h> 39 #include <linux/sched.h> 40 #include <linux/slab.h> 41 #include <linux/errno.h> 42 #include <linux/init.h> 43 #include <linux/list.h> 44 #include <linux/dma-mapping.h> 45 46 #include "musb_core.h" 47 #include "musb_host.h" 48 49 50 /* MUSB HOST status 22-mar-2006 51 * 52 * - There's still lots of partial code duplication for fault paths, so 53 * they aren't handled as consistently as they need to be. 54 * 55 * - PIO mostly behaved when last tested. 56 * + including ep0, with all usbtest cases 9, 10 57 * + usbtest 14 (ep0out) doesn't seem to run at all 58 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest 59 * configurations, but otherwise double buffering passes basic tests. 60 * + for 2.6.N, for N > ~10, needs API changes for hcd framework. 61 * 62 * - DMA (CPPI) ... partially behaves, not currently recommended 63 * + about 1/15 the speed of typical EHCI implementations (PCI) 64 * + RX, all too often reqpkt seems to misbehave after tx 65 * + TX, no known issues (other than evident silicon issue) 66 * 67 * - DMA (Mentor/OMAP) ...has at least toggle update problems 68 * 69 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet 70 * starvation ... nothing yet for TX, interrupt, or bulk. 71 * 72 * - Not tested with HNP, but some SRP paths seem to behave. 73 * 74 * NOTE 24-August-2006: 75 * 76 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an 77 * extra endpoint for periodic use enabling hub + keybd + mouse. That 78 * mostly works, except that with "usbnet" it's easy to trigger cases 79 * with "ping" where RX loses. (a) ping to davinci, even "ping -f", 80 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses 81 * although ARP RX wins. (That test was done with a full speed link.) 82 */ 83 84 85 /* 86 * NOTE on endpoint usage: 87 * 88 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN 89 * and OUT endpoints ... hardware is dedicated for those "async" queue(s). 90 * (Yes, bulk _could_ use more of the endpoints than that, and would even 91 * benefit from it.) 92 * 93 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. 94 * So far that scheduling is both dumb and optimistic: the endpoint will be 95 * "claimed" until its software queue is no longer refilled. No multiplexing 96 * of transfers between endpoints, or anything clever. 97 */ 98 99 100 static void musb_ep_program(struct musb *musb, u8 epnum, 101 struct urb *urb, int is_out, 102 u8 *buf, u32 offset, u32 len); 103 104 /* 105 * Clear TX fifo. Needed to avoid BABBLE errors. 106 */ 107 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) 108 { 109 struct musb *musb = ep->musb; 110 void __iomem *epio = ep->regs; 111 u16 csr; 112 u16 lastcsr = 0; 113 int retries = 1000; 114 115 csr = musb_readw(epio, MUSB_TXCSR); 116 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { 117 if (csr != lastcsr) 118 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr); 119 lastcsr = csr; 120 csr |= MUSB_TXCSR_FLUSHFIFO; 121 musb_writew(epio, MUSB_TXCSR, csr); 122 csr = musb_readw(epio, MUSB_TXCSR); 123 if (WARN(retries-- < 1, 124 "Could not flush host TX%d fifo: csr: %04x\n", 125 ep->epnum, csr)) 126 return; 127 mdelay(1); 128 } 129 } 130 131 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) 132 { 133 void __iomem *epio = ep->regs; 134 u16 csr; 135 int retries = 5; 136 137 /* scrub any data left in the fifo */ 138 do { 139 csr = musb_readw(epio, MUSB_TXCSR); 140 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) 141 break; 142 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO); 143 csr = musb_readw(epio, MUSB_TXCSR); 144 udelay(10); 145 } while (--retries); 146 147 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", 148 ep->epnum, csr); 149 150 /* and reset for the next transfer */ 151 musb_writew(epio, MUSB_TXCSR, 0); 152 } 153 154 /* 155 * Start transmit. Caller is responsible for locking shared resources. 156 * musb must be locked. 157 */ 158 static inline void musb_h_tx_start(struct musb_hw_ep *ep) 159 { 160 u16 txcsr; 161 162 /* NOTE: no locks here; caller should lock and select EP */ 163 if (ep->epnum) { 164 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 165 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; 166 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 167 } else { 168 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; 169 musb_writew(ep->regs, MUSB_CSR0, txcsr); 170 } 171 172 } 173 174 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep) 175 { 176 u16 txcsr; 177 178 /* NOTE: no locks here; caller should lock and select EP */ 179 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 180 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; 181 if (is_cppi_enabled()) 182 txcsr |= MUSB_TXCSR_DMAMODE; 183 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 184 } 185 186 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh) 187 { 188 if (is_in != 0 || ep->is_shared_fifo) 189 ep->in_qh = qh; 190 if (is_in == 0 || ep->is_shared_fifo) 191 ep->out_qh = qh; 192 } 193 194 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in) 195 { 196 return is_in ? ep->in_qh : ep->out_qh; 197 } 198 199 /* 200 * Start the URB at the front of an endpoint's queue 201 * end must be claimed from the caller. 202 * 203 * Context: controller locked, irqs blocked 204 */ 205 static void 206 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) 207 { 208 u16 frame; 209 u32 len; 210 void __iomem *mbase = musb->mregs; 211 struct urb *urb = next_urb(qh); 212 void *buf = urb->transfer_buffer; 213 u32 offset = 0; 214 struct musb_hw_ep *hw_ep = qh->hw_ep; 215 unsigned pipe = urb->pipe; 216 u8 address = usb_pipedevice(pipe); 217 int epnum = hw_ep->epnum; 218 219 /* initialize software qh state */ 220 qh->offset = 0; 221 qh->segsize = 0; 222 223 /* gather right source of data */ 224 switch (qh->type) { 225 case USB_ENDPOINT_XFER_CONTROL: 226 /* control transfers always start with SETUP */ 227 is_in = 0; 228 musb->ep0_stage = MUSB_EP0_START; 229 buf = urb->setup_packet; 230 len = 8; 231 break; 232 case USB_ENDPOINT_XFER_ISOC: 233 qh->iso_idx = 0; 234 qh->frame = 0; 235 offset = urb->iso_frame_desc[0].offset; 236 len = urb->iso_frame_desc[0].length; 237 break; 238 default: /* bulk, interrupt */ 239 /* actual_length may be nonzero on retry paths */ 240 buf = urb->transfer_buffer + urb->actual_length; 241 len = urb->transfer_buffer_length - urb->actual_length; 242 } 243 244 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", 245 qh, urb, address, qh->epnum, 246 is_in ? "in" : "out", 247 ({char *s; switch (qh->type) { 248 case USB_ENDPOINT_XFER_CONTROL: s = ""; break; 249 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break; 250 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break; 251 default: s = "-intr"; break; 252 }; s; }), 253 epnum, buf + offset, len); 254 255 /* Configure endpoint */ 256 musb_ep_set_qh(hw_ep, is_in, qh); 257 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len); 258 259 /* transmit may have more work: start it when it is time */ 260 if (is_in) 261 return; 262 263 /* determine if the time is right for a periodic transfer */ 264 switch (qh->type) { 265 case USB_ENDPOINT_XFER_ISOC: 266 case USB_ENDPOINT_XFER_INT: 267 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n"); 268 frame = musb_readw(mbase, MUSB_FRAME); 269 /* FIXME this doesn't implement that scheduling policy ... 270 * or handle framecounter wrapping 271 */ 272 if ((urb->transfer_flags & URB_ISO_ASAP) 273 || (frame >= urb->start_frame)) { 274 /* REVISIT the SOF irq handler shouldn't duplicate 275 * this code; and we don't init urb->start_frame... 276 */ 277 qh->frame = 0; 278 goto start; 279 } else { 280 qh->frame = urb->start_frame; 281 /* enable SOF interrupt so we can count down */ 282 dev_dbg(musb->controller, "SOF for %d\n", epnum); 283 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */ 284 musb_writeb(mbase, MUSB_INTRUSBE, 0xff); 285 #endif 286 } 287 break; 288 default: 289 start: 290 dev_dbg(musb->controller, "Start TX%d %s\n", epnum, 291 hw_ep->tx_channel ? "dma" : "pio"); 292 293 if (!hw_ep->tx_channel) 294 musb_h_tx_start(hw_ep); 295 else if (is_cppi_enabled() || tusb_dma_omap()) 296 musb_h_tx_dma_start(hw_ep); 297 } 298 } 299 300 /* Context: caller owns controller lock, IRQs are blocked */ 301 static void musb_giveback(struct musb *musb, struct urb *urb, int status) 302 __releases(musb->lock) 303 __acquires(musb->lock) 304 { 305 dev_dbg(musb->controller, 306 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", 307 urb, urb->complete, status, 308 usb_pipedevice(urb->pipe), 309 usb_pipeendpoint(urb->pipe), 310 usb_pipein(urb->pipe) ? "in" : "out", 311 urb->actual_length, urb->transfer_buffer_length 312 ); 313 314 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb); 315 spin_unlock(&musb->lock); 316 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status); 317 spin_lock(&musb->lock); 318 } 319 320 /* For bulk/interrupt endpoints only */ 321 static inline void musb_save_toggle(struct musb_qh *qh, int is_in, 322 struct urb *urb) 323 { 324 void __iomem *epio = qh->hw_ep->regs; 325 u16 csr; 326 327 /* 328 * FIXME: the current Mentor DMA code seems to have 329 * problems getting toggle correct. 330 */ 331 332 if (is_in) 333 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE; 334 else 335 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE; 336 337 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0); 338 } 339 340 /* 341 * Advance this hardware endpoint's queue, completing the specified URB and 342 * advancing to either the next URB queued to that qh, or else invalidating 343 * that qh and advancing to the next qh scheduled after the current one. 344 * 345 * Context: caller owns controller lock, IRQs are blocked 346 */ 347 static void musb_advance_schedule(struct musb *musb, struct urb *urb, 348 struct musb_hw_ep *hw_ep, int is_in) 349 { 350 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in); 351 struct musb_hw_ep *ep = qh->hw_ep; 352 int ready = qh->is_ready; 353 int status; 354 355 status = (urb->status == -EINPROGRESS) ? 0 : urb->status; 356 357 /* save toggle eagerly, for paranoia */ 358 switch (qh->type) { 359 case USB_ENDPOINT_XFER_BULK: 360 case USB_ENDPOINT_XFER_INT: 361 musb_save_toggle(qh, is_in, urb); 362 break; 363 case USB_ENDPOINT_XFER_ISOC: 364 if (status == 0 && urb->error_count) 365 status = -EXDEV; 366 break; 367 } 368 369 qh->is_ready = 0; 370 musb_giveback(musb, urb, status); 371 qh->is_ready = ready; 372 373 /* reclaim resources (and bandwidth) ASAP; deschedule it, and 374 * invalidate qh as soon as list_empty(&hep->urb_list) 375 */ 376 if (list_empty(&qh->hep->urb_list)) { 377 struct list_head *head; 378 struct dma_controller *dma = musb->dma_controller; 379 380 if (is_in) { 381 ep->rx_reinit = 1; 382 if (ep->rx_channel) { 383 dma->channel_release(ep->rx_channel); 384 ep->rx_channel = NULL; 385 } 386 } else { 387 ep->tx_reinit = 1; 388 if (ep->tx_channel) { 389 dma->channel_release(ep->tx_channel); 390 ep->tx_channel = NULL; 391 } 392 } 393 394 /* Clobber old pointers to this qh */ 395 musb_ep_set_qh(ep, is_in, NULL); 396 qh->hep->hcpriv = NULL; 397 398 switch (qh->type) { 399 400 case USB_ENDPOINT_XFER_CONTROL: 401 case USB_ENDPOINT_XFER_BULK: 402 /* fifo policy for these lists, except that NAKing 403 * should rotate a qh to the end (for fairness). 404 */ 405 if (qh->mux == 1) { 406 head = qh->ring.prev; 407 list_del(&qh->ring); 408 kfree(qh); 409 qh = first_qh(head); 410 break; 411 } 412 413 case USB_ENDPOINT_XFER_ISOC: 414 case USB_ENDPOINT_XFER_INT: 415 /* this is where periodic bandwidth should be 416 * de-allocated if it's tracked and allocated; 417 * and where we'd update the schedule tree... 418 */ 419 kfree(qh); 420 qh = NULL; 421 break; 422 } 423 } 424 425 if (qh != NULL && qh->is_ready) { 426 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n", 427 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); 428 musb_start_urb(musb, is_in, qh); 429 } 430 } 431 432 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) 433 { 434 /* we don't want fifo to fill itself again; 435 * ignore dma (various models), 436 * leave toggle alone (may not have been saved yet) 437 */ 438 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; 439 csr &= ~(MUSB_RXCSR_H_REQPKT 440 | MUSB_RXCSR_H_AUTOREQ 441 | MUSB_RXCSR_AUTOCLEAR); 442 443 /* write 2x to allow double buffering */ 444 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 445 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 446 447 /* flush writebuffer */ 448 return musb_readw(hw_ep->regs, MUSB_RXCSR); 449 } 450 451 /* 452 * PIO RX for a packet (or part of it). 453 */ 454 static bool 455 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) 456 { 457 u16 rx_count; 458 u8 *buf; 459 u16 csr; 460 bool done = false; 461 u32 length; 462 int do_flush = 0; 463 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 464 void __iomem *epio = hw_ep->regs; 465 struct musb_qh *qh = hw_ep->in_qh; 466 int pipe = urb->pipe; 467 void *buffer = urb->transfer_buffer; 468 469 /* musb_ep_select(mbase, epnum); */ 470 rx_count = musb_readw(epio, MUSB_RXCOUNT); 471 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, 472 urb->transfer_buffer, qh->offset, 473 urb->transfer_buffer_length); 474 475 /* unload FIFO */ 476 if (usb_pipeisoc(pipe)) { 477 int status = 0; 478 struct usb_iso_packet_descriptor *d; 479 480 if (iso_err) { 481 status = -EILSEQ; 482 urb->error_count++; 483 } 484 485 d = urb->iso_frame_desc + qh->iso_idx; 486 buf = buffer + d->offset; 487 length = d->length; 488 if (rx_count > length) { 489 if (status == 0) { 490 status = -EOVERFLOW; 491 urb->error_count++; 492 } 493 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); 494 do_flush = 1; 495 } else 496 length = rx_count; 497 urb->actual_length += length; 498 d->actual_length = length; 499 500 d->status = status; 501 502 /* see if we are done */ 503 done = (++qh->iso_idx >= urb->number_of_packets); 504 } else { 505 /* non-isoch */ 506 buf = buffer + qh->offset; 507 length = urb->transfer_buffer_length - qh->offset; 508 if (rx_count > length) { 509 if (urb->status == -EINPROGRESS) 510 urb->status = -EOVERFLOW; 511 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); 512 do_flush = 1; 513 } else 514 length = rx_count; 515 urb->actual_length += length; 516 qh->offset += length; 517 518 /* see if we are done */ 519 done = (urb->actual_length == urb->transfer_buffer_length) 520 || (rx_count < qh->maxpacket) 521 || (urb->status != -EINPROGRESS); 522 if (done 523 && (urb->status == -EINPROGRESS) 524 && (urb->transfer_flags & URB_SHORT_NOT_OK) 525 && (urb->actual_length 526 < urb->transfer_buffer_length)) 527 urb->status = -EREMOTEIO; 528 } 529 530 musb_read_fifo(hw_ep, length, buf); 531 532 csr = musb_readw(epio, MUSB_RXCSR); 533 csr |= MUSB_RXCSR_H_WZC_BITS; 534 if (unlikely(do_flush)) 535 musb_h_flush_rxfifo(hw_ep, csr); 536 else { 537 /* REVISIT this assumes AUTOCLEAR is never set */ 538 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); 539 if (!done) 540 csr |= MUSB_RXCSR_H_REQPKT; 541 musb_writew(epio, MUSB_RXCSR, csr); 542 } 543 544 return done; 545 } 546 547 /* we don't always need to reinit a given side of an endpoint... 548 * when we do, use tx/rx reinit routine and then construct a new CSR 549 * to address data toggle, NYET, and DMA or PIO. 550 * 551 * it's possible that driver bugs (especially for DMA) or aborting a 552 * transfer might have left the endpoint busier than it should be. 553 * the busy/not-empty tests are basically paranoia. 554 */ 555 static void 556 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) 557 { 558 u16 csr; 559 560 /* NOTE: we know the "rx" fifo reinit never triggers for ep0. 561 * That always uses tx_reinit since ep0 repurposes TX register 562 * offsets; the initial SETUP packet is also a kind of OUT. 563 */ 564 565 /* if programmed for Tx, put it in RX mode */ 566 if (ep->is_shared_fifo) { 567 csr = musb_readw(ep->regs, MUSB_TXCSR); 568 if (csr & MUSB_TXCSR_MODE) { 569 musb_h_tx_flush_fifo(ep); 570 csr = musb_readw(ep->regs, MUSB_TXCSR); 571 musb_writew(ep->regs, MUSB_TXCSR, 572 csr | MUSB_TXCSR_FRCDATATOG); 573 } 574 575 /* 576 * Clear the MODE bit (and everything else) to enable Rx. 577 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB. 578 */ 579 if (csr & MUSB_TXCSR_DMAMODE) 580 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE); 581 musb_writew(ep->regs, MUSB_TXCSR, 0); 582 583 /* scrub all previous state, clearing toggle */ 584 } else { 585 csr = musb_readw(ep->regs, MUSB_RXCSR); 586 if (csr & MUSB_RXCSR_RXPKTRDY) 587 WARNING("rx%d, packet/%d ready?\n", ep->epnum, 588 musb_readw(ep->regs, MUSB_RXCOUNT)); 589 590 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); 591 } 592 593 /* target addr and (for multipoint) hub addr/port */ 594 if (musb->is_multipoint) { 595 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg); 596 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg); 597 musb_write_rxhubport(ep->target_regs, qh->h_port_reg); 598 599 } else 600 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); 601 602 /* protocol/endpoint, interval/NAKlimit, i/o size */ 603 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); 604 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); 605 /* NOTE: bulk combining rewrites high bits of maxpacket */ 606 /* Set RXMAXP with the FIFO size of the endpoint 607 * to disable double buffer mode. 608 */ 609 if (musb->double_buffer_not_ok) 610 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx); 611 else 612 musb_writew(ep->regs, MUSB_RXMAXP, 613 qh->maxpacket | ((qh->hb_mult - 1) << 11)); 614 615 ep->rx_reinit = 0; 616 } 617 618 static bool musb_tx_dma_program(struct dma_controller *dma, 619 struct musb_hw_ep *hw_ep, struct musb_qh *qh, 620 struct urb *urb, u32 offset, u32 length) 621 { 622 struct dma_channel *channel = hw_ep->tx_channel; 623 void __iomem *epio = hw_ep->regs; 624 u16 pkt_size = qh->maxpacket; 625 u16 csr; 626 u8 mode; 627 628 #ifdef CONFIG_USB_INVENTRA_DMA 629 if (length > channel->max_len) 630 length = channel->max_len; 631 632 csr = musb_readw(epio, MUSB_TXCSR); 633 if (length > pkt_size) { 634 mode = 1; 635 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; 636 /* autoset shouldn't be set in high bandwidth */ 637 /* 638 * Enable Autoset according to table 639 * below 640 * bulk_split hb_mult Autoset_Enable 641 * 0 1 Yes(Normal) 642 * 0 >1 No(High BW ISO) 643 * 1 1 Yes(HS bulk) 644 * 1 >1 Yes(FS bulk) 645 */ 646 if (qh->hb_mult == 1 || (qh->hb_mult > 1 && 647 can_bulk_split(hw_ep->musb, qh->type))) 648 csr |= MUSB_TXCSR_AUTOSET; 649 } else { 650 mode = 0; 651 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); 652 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ 653 } 654 channel->desired_mode = mode; 655 musb_writew(epio, MUSB_TXCSR, csr); 656 #else 657 if (!is_cppi_enabled() && !tusb_dma_omap()) 658 return false; 659 660 channel->actual_len = 0; 661 662 /* 663 * TX uses "RNDIS" mode automatically but needs help 664 * to identify the zero-length-final-packet case. 665 */ 666 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; 667 #endif 668 669 qh->segsize = length; 670 671 /* 672 * Ensure the data reaches to main memory before starting 673 * DMA transfer 674 */ 675 wmb(); 676 677 if (!dma->channel_program(channel, pkt_size, mode, 678 urb->transfer_dma + offset, length)) { 679 dma->channel_release(channel); 680 hw_ep->tx_channel = NULL; 681 682 csr = musb_readw(epio, MUSB_TXCSR); 683 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 684 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); 685 return false; 686 } 687 return true; 688 } 689 690 /* 691 * Program an HDRC endpoint as per the given URB 692 * Context: irqs blocked, controller lock held 693 */ 694 static void musb_ep_program(struct musb *musb, u8 epnum, 695 struct urb *urb, int is_out, 696 u8 *buf, u32 offset, u32 len) 697 { 698 struct dma_controller *dma_controller; 699 struct dma_channel *dma_channel; 700 u8 dma_ok; 701 void __iomem *mbase = musb->mregs; 702 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 703 void __iomem *epio = hw_ep->regs; 704 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); 705 u16 packet_sz = qh->maxpacket; 706 u8 use_dma = 1; 707 u16 csr; 708 709 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s " 710 "h_addr%02x h_port%02x bytes %d\n", 711 is_out ? "-->" : "<--", 712 epnum, urb, urb->dev->speed, 713 qh->addr_reg, qh->epnum, is_out ? "out" : "in", 714 qh->h_addr_reg, qh->h_port_reg, 715 len); 716 717 musb_ep_select(mbase, epnum); 718 719 if (is_out && !len) { 720 use_dma = 0; 721 csr = musb_readw(epio, MUSB_TXCSR); 722 csr &= ~MUSB_TXCSR_DMAENAB; 723 musb_writew(epio, MUSB_TXCSR, csr); 724 hw_ep->tx_channel = NULL; 725 } 726 727 /* candidate for DMA? */ 728 dma_controller = musb->dma_controller; 729 if (use_dma && is_dma_capable() && epnum && dma_controller) { 730 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; 731 if (!dma_channel) { 732 dma_channel = dma_controller->channel_alloc( 733 dma_controller, hw_ep, is_out); 734 if (is_out) 735 hw_ep->tx_channel = dma_channel; 736 else 737 hw_ep->rx_channel = dma_channel; 738 } 739 } else 740 dma_channel = NULL; 741 742 /* make sure we clear DMAEnab, autoSet bits from previous run */ 743 744 /* OUT/transmit/EP0 or IN/receive? */ 745 if (is_out) { 746 u16 csr; 747 u16 int_txe; 748 u16 load_count; 749 750 csr = musb_readw(epio, MUSB_TXCSR); 751 752 /* disable interrupt in case we flush */ 753 int_txe = musb->intrtxe; 754 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); 755 756 /* general endpoint setup */ 757 if (epnum) { 758 /* flush all old state, set default */ 759 /* 760 * We could be flushing valid 761 * packets in double buffering 762 * case 763 */ 764 if (!hw_ep->tx_double_buffered) 765 musb_h_tx_flush_fifo(hw_ep); 766 767 /* 768 * We must not clear the DMAMODE bit before or in 769 * the same cycle with the DMAENAB bit, so we clear 770 * the latter first... 771 */ 772 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT 773 | MUSB_TXCSR_AUTOSET 774 | MUSB_TXCSR_DMAENAB 775 | MUSB_TXCSR_FRCDATATOG 776 | MUSB_TXCSR_H_RXSTALL 777 | MUSB_TXCSR_H_ERROR 778 | MUSB_TXCSR_TXPKTRDY 779 ); 780 csr |= MUSB_TXCSR_MODE; 781 782 if (!hw_ep->tx_double_buffered) { 783 if (usb_gettoggle(urb->dev, qh->epnum, 1)) 784 csr |= MUSB_TXCSR_H_WR_DATATOGGLE 785 | MUSB_TXCSR_H_DATATOGGLE; 786 else 787 csr |= MUSB_TXCSR_CLRDATATOG; 788 } 789 790 musb_writew(epio, MUSB_TXCSR, csr); 791 /* REVISIT may need to clear FLUSHFIFO ... */ 792 csr &= ~MUSB_TXCSR_DMAMODE; 793 musb_writew(epio, MUSB_TXCSR, csr); 794 csr = musb_readw(epio, MUSB_TXCSR); 795 } else { 796 /* endpoint 0: just flush */ 797 musb_h_ep0_flush_fifo(hw_ep); 798 } 799 800 /* target addr and (for multipoint) hub addr/port */ 801 if (musb->is_multipoint) { 802 musb_write_txfunaddr(mbase, epnum, qh->addr_reg); 803 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg); 804 musb_write_txhubport(mbase, epnum, qh->h_port_reg); 805 /* FIXME if !epnum, do the same for RX ... */ 806 } else 807 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); 808 809 /* protocol/endpoint/interval/NAKlimit */ 810 if (epnum) { 811 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); 812 if (musb->double_buffer_not_ok) { 813 musb_writew(epio, MUSB_TXMAXP, 814 hw_ep->max_packet_sz_tx); 815 } else if (can_bulk_split(musb, qh->type)) { 816 qh->hb_mult = hw_ep->max_packet_sz_tx 817 / packet_sz; 818 musb_writew(epio, MUSB_TXMAXP, packet_sz 819 | ((qh->hb_mult) - 1) << 11); 820 } else { 821 musb_writew(epio, MUSB_TXMAXP, 822 qh->maxpacket | 823 ((qh->hb_mult - 1) << 11)); 824 } 825 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); 826 } else { 827 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); 828 if (musb->is_multipoint) 829 musb_writeb(epio, MUSB_TYPE0, 830 qh->type_reg); 831 } 832 833 if (can_bulk_split(musb, qh->type)) 834 load_count = min((u32) hw_ep->max_packet_sz_tx, 835 len); 836 else 837 load_count = min((u32) packet_sz, len); 838 839 if (dma_channel && musb_tx_dma_program(dma_controller, 840 hw_ep, qh, urb, offset, len)) 841 load_count = 0; 842 843 if (load_count) { 844 /* PIO to load FIFO */ 845 qh->segsize = load_count; 846 if (!buf) { 847 sg_miter_start(&qh->sg_miter, urb->sg, 1, 848 SG_MITER_ATOMIC 849 | SG_MITER_FROM_SG); 850 if (!sg_miter_next(&qh->sg_miter)) { 851 dev_err(musb->controller, 852 "error: sg" 853 "list empty\n"); 854 sg_miter_stop(&qh->sg_miter); 855 goto finish; 856 } 857 buf = qh->sg_miter.addr + urb->sg->offset + 858 urb->actual_length; 859 load_count = min_t(u32, load_count, 860 qh->sg_miter.length); 861 musb_write_fifo(hw_ep, load_count, buf); 862 qh->sg_miter.consumed = load_count; 863 sg_miter_stop(&qh->sg_miter); 864 } else 865 musb_write_fifo(hw_ep, load_count, buf); 866 } 867 finish: 868 /* re-enable interrupt */ 869 musb_writew(mbase, MUSB_INTRTXE, int_txe); 870 871 /* IN/receive */ 872 } else { 873 u16 csr; 874 875 if (hw_ep->rx_reinit) { 876 musb_rx_reinit(musb, qh, hw_ep); 877 878 /* init new state: toggle and NYET, maybe DMA later */ 879 if (usb_gettoggle(urb->dev, qh->epnum, 0)) 880 csr = MUSB_RXCSR_H_WR_DATATOGGLE 881 | MUSB_RXCSR_H_DATATOGGLE; 882 else 883 csr = 0; 884 if (qh->type == USB_ENDPOINT_XFER_INT) 885 csr |= MUSB_RXCSR_DISNYET; 886 887 } else { 888 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 889 890 if (csr & (MUSB_RXCSR_RXPKTRDY 891 | MUSB_RXCSR_DMAENAB 892 | MUSB_RXCSR_H_REQPKT)) 893 ERR("broken !rx_reinit, ep%d csr %04x\n", 894 hw_ep->epnum, csr); 895 896 /* scrub any stale state, leaving toggle alone */ 897 csr &= MUSB_RXCSR_DISNYET; 898 } 899 900 /* kick things off */ 901 902 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { 903 /* Candidate for DMA */ 904 dma_channel->actual_len = 0L; 905 qh->segsize = len; 906 907 /* AUTOREQ is in a DMA register */ 908 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 909 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 910 911 /* 912 * Unless caller treats short RX transfers as 913 * errors, we dare not queue multiple transfers. 914 */ 915 dma_ok = dma_controller->channel_program(dma_channel, 916 packet_sz, !(urb->transfer_flags & 917 URB_SHORT_NOT_OK), 918 urb->transfer_dma + offset, 919 qh->segsize); 920 if (!dma_ok) { 921 dma_controller->channel_release(dma_channel); 922 hw_ep->rx_channel = dma_channel = NULL; 923 } else 924 csr |= MUSB_RXCSR_DMAENAB; 925 } 926 927 csr |= MUSB_RXCSR_H_REQPKT; 928 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr); 929 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 930 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 931 } 932 } 933 934 /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to 935 * the end; avoids starvation for other endpoints. 936 */ 937 static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep, 938 int is_in) 939 { 940 struct dma_channel *dma; 941 struct urb *urb; 942 void __iomem *mbase = musb->mregs; 943 void __iomem *epio = ep->regs; 944 struct musb_qh *cur_qh, *next_qh; 945 u16 rx_csr, tx_csr; 946 947 musb_ep_select(mbase, ep->epnum); 948 if (is_in) { 949 dma = is_dma_capable() ? ep->rx_channel : NULL; 950 951 /* clear nak timeout bit */ 952 rx_csr = musb_readw(epio, MUSB_RXCSR); 953 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 954 rx_csr &= ~MUSB_RXCSR_DATAERROR; 955 musb_writew(epio, MUSB_RXCSR, rx_csr); 956 957 cur_qh = first_qh(&musb->in_bulk); 958 } else { 959 dma = is_dma_capable() ? ep->tx_channel : NULL; 960 961 /* clear nak timeout bit */ 962 tx_csr = musb_readw(epio, MUSB_TXCSR); 963 tx_csr |= MUSB_TXCSR_H_WZC_BITS; 964 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT; 965 musb_writew(epio, MUSB_TXCSR, tx_csr); 966 967 cur_qh = first_qh(&musb->out_bulk); 968 } 969 if (cur_qh) { 970 urb = next_urb(cur_qh); 971 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 972 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 973 musb->dma_controller->channel_abort(dma); 974 urb->actual_length += dma->actual_len; 975 dma->actual_len = 0L; 976 } 977 musb_save_toggle(cur_qh, is_in, urb); 978 979 if (is_in) { 980 /* move cur_qh to end of queue */ 981 list_move_tail(&cur_qh->ring, &musb->in_bulk); 982 983 /* get the next qh from musb->in_bulk */ 984 next_qh = first_qh(&musb->in_bulk); 985 986 /* set rx_reinit and schedule the next qh */ 987 ep->rx_reinit = 1; 988 } else { 989 /* move cur_qh to end of queue */ 990 list_move_tail(&cur_qh->ring, &musb->out_bulk); 991 992 /* get the next qh from musb->out_bulk */ 993 next_qh = first_qh(&musb->out_bulk); 994 995 /* set tx_reinit and schedule the next qh */ 996 ep->tx_reinit = 1; 997 } 998 musb_start_urb(musb, is_in, next_qh); 999 } 1000 } 1001 1002 /* 1003 * Service the default endpoint (ep0) as host. 1004 * Return true until it's time to start the status stage. 1005 */ 1006 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) 1007 { 1008 bool more = false; 1009 u8 *fifo_dest = NULL; 1010 u16 fifo_count = 0; 1011 struct musb_hw_ep *hw_ep = musb->control_ep; 1012 struct musb_qh *qh = hw_ep->in_qh; 1013 struct usb_ctrlrequest *request; 1014 1015 switch (musb->ep0_stage) { 1016 case MUSB_EP0_IN: 1017 fifo_dest = urb->transfer_buffer + urb->actual_length; 1018 fifo_count = min_t(size_t, len, urb->transfer_buffer_length - 1019 urb->actual_length); 1020 if (fifo_count < len) 1021 urb->status = -EOVERFLOW; 1022 1023 musb_read_fifo(hw_ep, fifo_count, fifo_dest); 1024 1025 urb->actual_length += fifo_count; 1026 if (len < qh->maxpacket) { 1027 /* always terminate on short read; it's 1028 * rarely reported as an error. 1029 */ 1030 } else if (urb->actual_length < 1031 urb->transfer_buffer_length) 1032 more = true; 1033 break; 1034 case MUSB_EP0_START: 1035 request = (struct usb_ctrlrequest *) urb->setup_packet; 1036 1037 if (!request->wLength) { 1038 dev_dbg(musb->controller, "start no-DATA\n"); 1039 break; 1040 } else if (request->bRequestType & USB_DIR_IN) { 1041 dev_dbg(musb->controller, "start IN-DATA\n"); 1042 musb->ep0_stage = MUSB_EP0_IN; 1043 more = true; 1044 break; 1045 } else { 1046 dev_dbg(musb->controller, "start OUT-DATA\n"); 1047 musb->ep0_stage = MUSB_EP0_OUT; 1048 more = true; 1049 } 1050 /* FALLTHROUGH */ 1051 case MUSB_EP0_OUT: 1052 fifo_count = min_t(size_t, qh->maxpacket, 1053 urb->transfer_buffer_length - 1054 urb->actual_length); 1055 if (fifo_count) { 1056 fifo_dest = (u8 *) (urb->transfer_buffer 1057 + urb->actual_length); 1058 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n", 1059 fifo_count, 1060 (fifo_count == 1) ? "" : "s", 1061 fifo_dest); 1062 musb_write_fifo(hw_ep, fifo_count, fifo_dest); 1063 1064 urb->actual_length += fifo_count; 1065 more = true; 1066 } 1067 break; 1068 default: 1069 ERR("bogus ep0 stage %d\n", musb->ep0_stage); 1070 break; 1071 } 1072 1073 return more; 1074 } 1075 1076 /* 1077 * Handle default endpoint interrupt as host. Only called in IRQ time 1078 * from musb_interrupt(). 1079 * 1080 * called with controller irqlocked 1081 */ 1082 irqreturn_t musb_h_ep0_irq(struct musb *musb) 1083 { 1084 struct urb *urb; 1085 u16 csr, len; 1086 int status = 0; 1087 void __iomem *mbase = musb->mregs; 1088 struct musb_hw_ep *hw_ep = musb->control_ep; 1089 void __iomem *epio = hw_ep->regs; 1090 struct musb_qh *qh = hw_ep->in_qh; 1091 bool complete = false; 1092 irqreturn_t retval = IRQ_NONE; 1093 1094 /* ep0 only has one queue, "in" */ 1095 urb = next_urb(qh); 1096 1097 musb_ep_select(mbase, 0); 1098 csr = musb_readw(epio, MUSB_CSR0); 1099 len = (csr & MUSB_CSR0_RXPKTRDY) 1100 ? musb_readb(epio, MUSB_COUNT0) 1101 : 0; 1102 1103 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", 1104 csr, qh, len, urb, musb->ep0_stage); 1105 1106 /* if we just did status stage, we are done */ 1107 if (MUSB_EP0_STATUS == musb->ep0_stage) { 1108 retval = IRQ_HANDLED; 1109 complete = true; 1110 } 1111 1112 /* prepare status */ 1113 if (csr & MUSB_CSR0_H_RXSTALL) { 1114 dev_dbg(musb->controller, "STALLING ENDPOINT\n"); 1115 status = -EPIPE; 1116 1117 } else if (csr & MUSB_CSR0_H_ERROR) { 1118 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr); 1119 status = -EPROTO; 1120 1121 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { 1122 dev_dbg(musb->controller, "control NAK timeout\n"); 1123 1124 /* NOTE: this code path would be a good place to PAUSE a 1125 * control transfer, if another one is queued, so that 1126 * ep0 is more likely to stay busy. That's already done 1127 * for bulk RX transfers. 1128 * 1129 * if (qh->ring.next != &musb->control), then 1130 * we have a candidate... NAKing is *NOT* an error 1131 */ 1132 musb_writew(epio, MUSB_CSR0, 0); 1133 retval = IRQ_HANDLED; 1134 } 1135 1136 if (status) { 1137 dev_dbg(musb->controller, "aborting\n"); 1138 retval = IRQ_HANDLED; 1139 if (urb) 1140 urb->status = status; 1141 complete = true; 1142 1143 /* use the proper sequence to abort the transfer */ 1144 if (csr & MUSB_CSR0_H_REQPKT) { 1145 csr &= ~MUSB_CSR0_H_REQPKT; 1146 musb_writew(epio, MUSB_CSR0, csr); 1147 csr &= ~MUSB_CSR0_H_NAKTIMEOUT; 1148 musb_writew(epio, MUSB_CSR0, csr); 1149 } else { 1150 musb_h_ep0_flush_fifo(hw_ep); 1151 } 1152 1153 musb_writeb(epio, MUSB_NAKLIMIT0, 0); 1154 1155 /* clear it */ 1156 musb_writew(epio, MUSB_CSR0, 0); 1157 } 1158 1159 if (unlikely(!urb)) { 1160 /* stop endpoint since we have no place for its data, this 1161 * SHOULD NEVER HAPPEN! */ 1162 ERR("no URB for end 0\n"); 1163 1164 musb_h_ep0_flush_fifo(hw_ep); 1165 goto done; 1166 } 1167 1168 if (!complete) { 1169 /* call common logic and prepare response */ 1170 if (musb_h_ep0_continue(musb, len, urb)) { 1171 /* more packets required */ 1172 csr = (MUSB_EP0_IN == musb->ep0_stage) 1173 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; 1174 } else { 1175 /* data transfer complete; perform status phase */ 1176 if (usb_pipeout(urb->pipe) 1177 || !urb->transfer_buffer_length) 1178 csr = MUSB_CSR0_H_STATUSPKT 1179 | MUSB_CSR0_H_REQPKT; 1180 else 1181 csr = MUSB_CSR0_H_STATUSPKT 1182 | MUSB_CSR0_TXPKTRDY; 1183 1184 /* flag status stage */ 1185 musb->ep0_stage = MUSB_EP0_STATUS; 1186 1187 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr); 1188 1189 } 1190 musb_writew(epio, MUSB_CSR0, csr); 1191 retval = IRQ_HANDLED; 1192 } else 1193 musb->ep0_stage = MUSB_EP0_IDLE; 1194 1195 /* call completion handler if done */ 1196 if (complete) 1197 musb_advance_schedule(musb, urb, hw_ep, 1); 1198 done: 1199 return retval; 1200 } 1201 1202 1203 #ifdef CONFIG_USB_INVENTRA_DMA 1204 1205 /* Host side TX (OUT) using Mentor DMA works as follows: 1206 submit_urb -> 1207 - if queue was empty, Program Endpoint 1208 - ... which starts DMA to fifo in mode 1 or 0 1209 1210 DMA Isr (transfer complete) -> TxAvail() 1211 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens 1212 only in musb_cleanup_urb) 1213 - TxPktRdy has to be set in mode 0 or for 1214 short packets in mode 1. 1215 */ 1216 1217 #endif 1218 1219 /* Service a Tx-Available or dma completion irq for the endpoint */ 1220 void musb_host_tx(struct musb *musb, u8 epnum) 1221 { 1222 int pipe; 1223 bool done = false; 1224 u16 tx_csr; 1225 size_t length = 0; 1226 size_t offset = 0; 1227 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1228 void __iomem *epio = hw_ep->regs; 1229 struct musb_qh *qh = hw_ep->out_qh; 1230 struct urb *urb = next_urb(qh); 1231 u32 status = 0; 1232 void __iomem *mbase = musb->mregs; 1233 struct dma_channel *dma; 1234 bool transfer_pending = false; 1235 1236 musb_ep_select(mbase, epnum); 1237 tx_csr = musb_readw(epio, MUSB_TXCSR); 1238 1239 /* with CPPI, DMA sometimes triggers "extra" irqs */ 1240 if (!urb) { 1241 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1242 return; 1243 } 1244 1245 pipe = urb->pipe; 1246 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; 1247 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, 1248 dma ? ", dma" : ""); 1249 1250 /* check for errors */ 1251 if (tx_csr & MUSB_TXCSR_H_RXSTALL) { 1252 /* dma was disabled, fifo flushed */ 1253 dev_dbg(musb->controller, "TX end %d stall\n", epnum); 1254 1255 /* stall; record URB status */ 1256 status = -EPIPE; 1257 1258 } else if (tx_csr & MUSB_TXCSR_H_ERROR) { 1259 /* (NON-ISO) dma was disabled, fifo flushed */ 1260 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum); 1261 1262 status = -ETIMEDOUT; 1263 1264 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { 1265 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1 1266 && !list_is_singular(&musb->out_bulk)) { 1267 dev_dbg(musb->controller, 1268 "NAK timeout on TX%d ep\n", epnum); 1269 musb_bulk_nak_timeout(musb, hw_ep, 0); 1270 } else { 1271 dev_dbg(musb->controller, 1272 "TX end=%d device not responding\n", epnum); 1273 /* NOTE: this code path would be a good place to PAUSE a 1274 * transfer, if there's some other (nonperiodic) tx urb 1275 * that could use this fifo. (dma complicates it...) 1276 * That's already done for bulk RX transfers. 1277 * 1278 * if (bulk && qh->ring.next != &musb->out_bulk), then 1279 * we have a candidate... NAKing is *NOT* an error 1280 */ 1281 musb_ep_select(mbase, epnum); 1282 musb_writew(epio, MUSB_TXCSR, 1283 MUSB_TXCSR_H_WZC_BITS 1284 | MUSB_TXCSR_TXPKTRDY); 1285 } 1286 return; 1287 } 1288 1289 done: 1290 if (status) { 1291 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1292 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1293 (void) musb->dma_controller->channel_abort(dma); 1294 } 1295 1296 /* do the proper sequence to abort the transfer in the 1297 * usb core; the dma engine should already be stopped. 1298 */ 1299 musb_h_tx_flush_fifo(hw_ep); 1300 tx_csr &= ~(MUSB_TXCSR_AUTOSET 1301 | MUSB_TXCSR_DMAENAB 1302 | MUSB_TXCSR_H_ERROR 1303 | MUSB_TXCSR_H_RXSTALL 1304 | MUSB_TXCSR_H_NAKTIMEOUT 1305 ); 1306 1307 musb_ep_select(mbase, epnum); 1308 musb_writew(epio, MUSB_TXCSR, tx_csr); 1309 /* REVISIT may need to clear FLUSHFIFO ... */ 1310 musb_writew(epio, MUSB_TXCSR, tx_csr); 1311 musb_writeb(epio, MUSB_TXINTERVAL, 0); 1312 1313 done = true; 1314 } 1315 1316 /* second cppi case */ 1317 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1318 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1319 return; 1320 } 1321 1322 if (is_dma_capable() && dma && !status) { 1323 /* 1324 * DMA has completed. But if we're using DMA mode 1 (multi 1325 * packet DMA), we need a terminal TXPKTRDY interrupt before 1326 * we can consider this transfer completed, lest we trash 1327 * its last packet when writing the next URB's data. So we 1328 * switch back to mode 0 to get that interrupt; we'll come 1329 * back here once it happens. 1330 */ 1331 if (tx_csr & MUSB_TXCSR_DMAMODE) { 1332 /* 1333 * We shouldn't clear DMAMODE with DMAENAB set; so 1334 * clear them in a safe order. That should be OK 1335 * once TXPKTRDY has been set (and I've never seen 1336 * it being 0 at this moment -- DMA interrupt latency 1337 * is significant) but if it hasn't been then we have 1338 * no choice but to stop being polite and ignore the 1339 * programmer's guide... :-) 1340 * 1341 * Note that we must write TXCSR with TXPKTRDY cleared 1342 * in order not to re-trigger the packet send (this bit 1343 * can't be cleared by CPU), and there's another caveat: 1344 * TXPKTRDY may be set shortly and then cleared in the 1345 * double-buffered FIFO mode, so we do an extra TXCSR 1346 * read for debouncing... 1347 */ 1348 tx_csr &= musb_readw(epio, MUSB_TXCSR); 1349 if (tx_csr & MUSB_TXCSR_TXPKTRDY) { 1350 tx_csr &= ~(MUSB_TXCSR_DMAENAB | 1351 MUSB_TXCSR_TXPKTRDY); 1352 musb_writew(epio, MUSB_TXCSR, 1353 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1354 } 1355 tx_csr &= ~(MUSB_TXCSR_DMAMODE | 1356 MUSB_TXCSR_TXPKTRDY); 1357 musb_writew(epio, MUSB_TXCSR, 1358 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1359 1360 /* 1361 * There is no guarantee that we'll get an interrupt 1362 * after clearing DMAMODE as we might have done this 1363 * too late (after TXPKTRDY was cleared by controller). 1364 * Re-read TXCSR as we have spoiled its previous value. 1365 */ 1366 tx_csr = musb_readw(epio, MUSB_TXCSR); 1367 } 1368 1369 /* 1370 * We may get here from a DMA completion or TXPKTRDY interrupt. 1371 * In any case, we must check the FIFO status here and bail out 1372 * only if the FIFO still has data -- that should prevent the 1373 * "missed" TXPKTRDY interrupts and deal with double-buffered 1374 * FIFO mode too... 1375 */ 1376 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { 1377 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, " 1378 "CSR %04x\n", tx_csr); 1379 return; 1380 } 1381 } 1382 1383 if (!status || dma || usb_pipeisoc(pipe)) { 1384 if (dma) 1385 length = dma->actual_len; 1386 else 1387 length = qh->segsize; 1388 qh->offset += length; 1389 1390 if (usb_pipeisoc(pipe)) { 1391 struct usb_iso_packet_descriptor *d; 1392 1393 d = urb->iso_frame_desc + qh->iso_idx; 1394 d->actual_length = length; 1395 d->status = status; 1396 if (++qh->iso_idx >= urb->number_of_packets) { 1397 done = true; 1398 } else { 1399 d++; 1400 offset = d->offset; 1401 length = d->length; 1402 } 1403 } else if (dma && urb->transfer_buffer_length == qh->offset) { 1404 done = true; 1405 } else { 1406 /* see if we need to send more data, or ZLP */ 1407 if (qh->segsize < qh->maxpacket) 1408 done = true; 1409 else if (qh->offset == urb->transfer_buffer_length 1410 && !(urb->transfer_flags 1411 & URB_ZERO_PACKET)) 1412 done = true; 1413 if (!done) { 1414 offset = qh->offset; 1415 length = urb->transfer_buffer_length - offset; 1416 transfer_pending = true; 1417 } 1418 } 1419 } 1420 1421 /* urb->status != -EINPROGRESS means request has been faulted, 1422 * so we must abort this transfer after cleanup 1423 */ 1424 if (urb->status != -EINPROGRESS) { 1425 done = true; 1426 if (status == 0) 1427 status = urb->status; 1428 } 1429 1430 if (done) { 1431 /* set status */ 1432 urb->status = status; 1433 urb->actual_length = qh->offset; 1434 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); 1435 return; 1436 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) { 1437 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, 1438 offset, length)) { 1439 if (is_cppi_enabled() || tusb_dma_omap()) 1440 musb_h_tx_dma_start(hw_ep); 1441 return; 1442 } 1443 } else if (tx_csr & MUSB_TXCSR_DMAENAB) { 1444 dev_dbg(musb->controller, "not complete, but DMA enabled?\n"); 1445 return; 1446 } 1447 1448 /* 1449 * PIO: start next packet in this URB. 1450 * 1451 * REVISIT: some docs say that when hw_ep->tx_double_buffered, 1452 * (and presumably, FIFO is not half-full) we should write *two* 1453 * packets before updating TXCSR; other docs disagree... 1454 */ 1455 if (length > qh->maxpacket) 1456 length = qh->maxpacket; 1457 /* Unmap the buffer so that CPU can use it */ 1458 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb); 1459 1460 /* 1461 * We need to map sg if the transfer_buffer is 1462 * NULL. 1463 */ 1464 if (!urb->transfer_buffer) 1465 qh->use_sg = true; 1466 1467 if (qh->use_sg) { 1468 /* sg_miter_start is already done in musb_ep_program */ 1469 if (!sg_miter_next(&qh->sg_miter)) { 1470 dev_err(musb->controller, "error: sg list empty\n"); 1471 sg_miter_stop(&qh->sg_miter); 1472 status = -EINVAL; 1473 goto done; 1474 } 1475 urb->transfer_buffer = qh->sg_miter.addr; 1476 length = min_t(u32, length, qh->sg_miter.length); 1477 musb_write_fifo(hw_ep, length, urb->transfer_buffer); 1478 qh->sg_miter.consumed = length; 1479 sg_miter_stop(&qh->sg_miter); 1480 } else { 1481 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); 1482 } 1483 1484 qh->segsize = length; 1485 1486 if (qh->use_sg) { 1487 if (offset + length >= urb->transfer_buffer_length) 1488 qh->use_sg = false; 1489 } 1490 1491 musb_ep_select(mbase, epnum); 1492 musb_writew(epio, MUSB_TXCSR, 1493 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); 1494 } 1495 1496 1497 #ifdef CONFIG_USB_INVENTRA_DMA 1498 1499 /* Host side RX (IN) using Mentor DMA works as follows: 1500 submit_urb -> 1501 - if queue was empty, ProgramEndpoint 1502 - first IN token is sent out (by setting ReqPkt) 1503 LinuxIsr -> RxReady() 1504 /\ => first packet is received 1505 | - Set in mode 0 (DmaEnab, ~ReqPkt) 1506 | -> DMA Isr (transfer complete) -> RxReady() 1507 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) 1508 | - if urb not complete, send next IN token (ReqPkt) 1509 | | else complete urb. 1510 | | 1511 --------------------------- 1512 * 1513 * Nuances of mode 1: 1514 * For short packets, no ack (+RxPktRdy) is sent automatically 1515 * (even if AutoClear is ON) 1516 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent 1517 * automatically => major problem, as collecting the next packet becomes 1518 * difficult. Hence mode 1 is not used. 1519 * 1520 * REVISIT 1521 * All we care about at this driver level is that 1522 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; 1523 * (b) termination conditions are: short RX, or buffer full; 1524 * (c) fault modes include 1525 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. 1526 * (and that endpoint's dma queue stops immediately) 1527 * - overflow (full, PLUS more bytes in the terminal packet) 1528 * 1529 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would 1530 * thus be a great candidate for using mode 1 ... for all but the 1531 * last packet of one URB's transfer. 1532 */ 1533 1534 #endif 1535 1536 /* 1537 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, 1538 * and high-bandwidth IN transfer cases. 1539 */ 1540 void musb_host_rx(struct musb *musb, u8 epnum) 1541 { 1542 struct urb *urb; 1543 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1544 void __iomem *epio = hw_ep->regs; 1545 struct musb_qh *qh = hw_ep->in_qh; 1546 size_t xfer_len; 1547 void __iomem *mbase = musb->mregs; 1548 int pipe; 1549 u16 rx_csr, val; 1550 bool iso_err = false; 1551 bool done = false; 1552 u32 status; 1553 struct dma_channel *dma; 1554 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG; 1555 1556 musb_ep_select(mbase, epnum); 1557 1558 urb = next_urb(qh); 1559 dma = is_dma_capable() ? hw_ep->rx_channel : NULL; 1560 status = 0; 1561 xfer_len = 0; 1562 1563 rx_csr = musb_readw(epio, MUSB_RXCSR); 1564 val = rx_csr; 1565 1566 if (unlikely(!urb)) { 1567 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least 1568 * usbtest #11 (unlinks) triggers it regularly, sometimes 1569 * with fifo full. (Only with DMA??) 1570 */ 1571 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, 1572 musb_readw(epio, MUSB_RXCOUNT)); 1573 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1574 return; 1575 } 1576 1577 pipe = urb->pipe; 1578 1579 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", 1580 epnum, rx_csr, urb->actual_length, 1581 dma ? dma->actual_len : 0); 1582 1583 /* check for errors, concurrent stall & unlink is not really 1584 * handled yet! */ 1585 if (rx_csr & MUSB_RXCSR_H_RXSTALL) { 1586 dev_dbg(musb->controller, "RX end %d STALL\n", epnum); 1587 1588 /* stall; record URB status */ 1589 status = -EPIPE; 1590 1591 } else if (rx_csr & MUSB_RXCSR_H_ERROR) { 1592 dev_dbg(musb->controller, "end %d RX proto error\n", epnum); 1593 1594 status = -EPROTO; 1595 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1596 1597 } else if (rx_csr & MUSB_RXCSR_DATAERROR) { 1598 1599 if (USB_ENDPOINT_XFER_ISOC != qh->type) { 1600 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum); 1601 1602 /* NOTE: NAKing is *NOT* an error, so we want to 1603 * continue. Except ... if there's a request for 1604 * another QH, use that instead of starving it. 1605 * 1606 * Devices like Ethernet and serial adapters keep 1607 * reads posted at all times, which will starve 1608 * other devices without this logic. 1609 */ 1610 if (usb_pipebulk(urb->pipe) 1611 && qh->mux == 1 1612 && !list_is_singular(&musb->in_bulk)) { 1613 musb_bulk_nak_timeout(musb, hw_ep, 1); 1614 return; 1615 } 1616 musb_ep_select(mbase, epnum); 1617 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 1618 rx_csr &= ~MUSB_RXCSR_DATAERROR; 1619 musb_writew(epio, MUSB_RXCSR, rx_csr); 1620 1621 goto finish; 1622 } else { 1623 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum); 1624 /* packet error reported later */ 1625 iso_err = true; 1626 } 1627 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) { 1628 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n", 1629 epnum); 1630 status = -EPROTO; 1631 } 1632 1633 /* faults abort the transfer */ 1634 if (status) { 1635 /* clean up dma and collect transfer count */ 1636 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1637 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1638 (void) musb->dma_controller->channel_abort(dma); 1639 xfer_len = dma->actual_len; 1640 } 1641 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1642 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1643 done = true; 1644 goto finish; 1645 } 1646 1647 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { 1648 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ 1649 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); 1650 goto finish; 1651 } 1652 1653 /* thorough shutdown for now ... given more precise fault handling 1654 * and better queueing support, we might keep a DMA pipeline going 1655 * while processing this irq for earlier completions. 1656 */ 1657 1658 /* FIXME this is _way_ too much in-line logic for Mentor DMA */ 1659 1660 #ifndef CONFIG_USB_INVENTRA_DMA 1661 if (rx_csr & MUSB_RXCSR_H_REQPKT) { 1662 /* REVISIT this happened for a while on some short reads... 1663 * the cleanup still needs investigation... looks bad... 1664 * and also duplicates dma cleanup code above ... plus, 1665 * shouldn't this be the "half full" double buffer case? 1666 */ 1667 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1668 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1669 (void) musb->dma_controller->channel_abort(dma); 1670 xfer_len = dma->actual_len; 1671 done = true; 1672 } 1673 1674 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, 1675 xfer_len, dma ? ", dma" : ""); 1676 rx_csr &= ~MUSB_RXCSR_H_REQPKT; 1677 1678 musb_ep_select(mbase, epnum); 1679 musb_writew(epio, MUSB_RXCSR, 1680 MUSB_RXCSR_H_WZC_BITS | rx_csr); 1681 } 1682 #endif 1683 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { 1684 xfer_len = dma->actual_len; 1685 1686 val &= ~(MUSB_RXCSR_DMAENAB 1687 | MUSB_RXCSR_H_AUTOREQ 1688 | MUSB_RXCSR_AUTOCLEAR 1689 | MUSB_RXCSR_RXPKTRDY); 1690 musb_writew(hw_ep->regs, MUSB_RXCSR, val); 1691 1692 #ifdef CONFIG_USB_INVENTRA_DMA 1693 if (usb_pipeisoc(pipe)) { 1694 struct usb_iso_packet_descriptor *d; 1695 1696 d = urb->iso_frame_desc + qh->iso_idx; 1697 d->actual_length = xfer_len; 1698 1699 /* even if there was an error, we did the dma 1700 * for iso_frame_desc->length 1701 */ 1702 if (d->status != -EILSEQ && d->status != -EOVERFLOW) 1703 d->status = 0; 1704 1705 if (++qh->iso_idx >= urb->number_of_packets) 1706 done = true; 1707 else 1708 done = false; 1709 1710 } else { 1711 /* done if urb buffer is full or short packet is recd */ 1712 done = (urb->actual_length + xfer_len >= 1713 urb->transfer_buffer_length 1714 || dma->actual_len < qh->maxpacket); 1715 } 1716 1717 /* send IN token for next packet, without AUTOREQ */ 1718 if (!done) { 1719 val |= MUSB_RXCSR_H_REQPKT; 1720 musb_writew(epio, MUSB_RXCSR, 1721 MUSB_RXCSR_H_WZC_BITS | val); 1722 } 1723 1724 dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, 1725 done ? "off" : "reset", 1726 musb_readw(epio, MUSB_RXCSR), 1727 musb_readw(epio, MUSB_RXCOUNT)); 1728 #else 1729 done = true; 1730 #endif 1731 } else if (urb->status == -EINPROGRESS) { 1732 /* if no errors, be sure a packet is ready for unloading */ 1733 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { 1734 status = -EPROTO; 1735 ERR("Rx interrupt with no errors or packet!\n"); 1736 1737 /* FIXME this is another "SHOULD NEVER HAPPEN" */ 1738 1739 /* SCRUB (RX) */ 1740 /* do the proper sequence to abort the transfer */ 1741 musb_ep_select(mbase, epnum); 1742 val &= ~MUSB_RXCSR_H_REQPKT; 1743 musb_writew(epio, MUSB_RXCSR, val); 1744 goto finish; 1745 } 1746 1747 /* we are expecting IN packets */ 1748 #ifdef CONFIG_USB_INVENTRA_DMA 1749 if (dma) { 1750 struct dma_controller *c; 1751 u16 rx_count; 1752 int ret, length; 1753 dma_addr_t buf; 1754 1755 rx_count = musb_readw(epio, MUSB_RXCOUNT); 1756 1757 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n", 1758 epnum, rx_count, 1759 urb->transfer_dma 1760 + urb->actual_length, 1761 qh->offset, 1762 urb->transfer_buffer_length); 1763 1764 c = musb->dma_controller; 1765 1766 if (usb_pipeisoc(pipe)) { 1767 int d_status = 0; 1768 struct usb_iso_packet_descriptor *d; 1769 1770 d = urb->iso_frame_desc + qh->iso_idx; 1771 1772 if (iso_err) { 1773 d_status = -EILSEQ; 1774 urb->error_count++; 1775 } 1776 if (rx_count > d->length) { 1777 if (d_status == 0) { 1778 d_status = -EOVERFLOW; 1779 urb->error_count++; 1780 } 1781 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\ 1782 rx_count, d->length); 1783 1784 length = d->length; 1785 } else 1786 length = rx_count; 1787 d->status = d_status; 1788 buf = urb->transfer_dma + d->offset; 1789 } else { 1790 length = rx_count; 1791 buf = urb->transfer_dma + 1792 urb->actual_length; 1793 } 1794 1795 dma->desired_mode = 0; 1796 #ifdef USE_MODE1 1797 /* because of the issue below, mode 1 will 1798 * only rarely behave with correct semantics. 1799 */ 1800 if ((urb->transfer_flags & 1801 URB_SHORT_NOT_OK) 1802 && (urb->transfer_buffer_length - 1803 urb->actual_length) 1804 > qh->maxpacket) 1805 dma->desired_mode = 1; 1806 if (rx_count < hw_ep->max_packet_sz_rx) { 1807 length = rx_count; 1808 dma->desired_mode = 0; 1809 } else { 1810 length = urb->transfer_buffer_length; 1811 } 1812 #endif 1813 1814 /* Disadvantage of using mode 1: 1815 * It's basically usable only for mass storage class; essentially all 1816 * other protocols also terminate transfers on short packets. 1817 * 1818 * Details: 1819 * An extra IN token is sent at the end of the transfer (due to AUTOREQ) 1820 * If you try to use mode 1 for (transfer_buffer_length - 512), and try 1821 * to use the extra IN token to grab the last packet using mode 0, then 1822 * the problem is that you cannot be sure when the device will send the 1823 * last packet and RxPktRdy set. Sometimes the packet is recd too soon 1824 * such that it gets lost when RxCSR is re-set at the end of the mode 1 1825 * transfer, while sometimes it is recd just a little late so that if you 1826 * try to configure for mode 0 soon after the mode 1 transfer is 1827 * completed, you will find rxcount 0. Okay, so you might think why not 1828 * wait for an interrupt when the pkt is recd. Well, you won't get any! 1829 */ 1830 1831 val = musb_readw(epio, MUSB_RXCSR); 1832 val &= ~MUSB_RXCSR_H_REQPKT; 1833 1834 if (dma->desired_mode == 0) 1835 val &= ~MUSB_RXCSR_H_AUTOREQ; 1836 else 1837 val |= MUSB_RXCSR_H_AUTOREQ; 1838 val |= MUSB_RXCSR_DMAENAB; 1839 1840 /* autoclear shouldn't be set in high bandwidth */ 1841 if (qh->hb_mult == 1) 1842 val |= MUSB_RXCSR_AUTOCLEAR; 1843 1844 musb_writew(epio, MUSB_RXCSR, 1845 MUSB_RXCSR_H_WZC_BITS | val); 1846 1847 /* REVISIT if when actual_length != 0, 1848 * transfer_buffer_length needs to be 1849 * adjusted first... 1850 */ 1851 ret = c->channel_program( 1852 dma, qh->maxpacket, 1853 dma->desired_mode, buf, length); 1854 1855 if (!ret) { 1856 c->channel_release(dma); 1857 hw_ep->rx_channel = NULL; 1858 dma = NULL; 1859 val = musb_readw(epio, MUSB_RXCSR); 1860 val &= ~(MUSB_RXCSR_DMAENAB 1861 | MUSB_RXCSR_H_AUTOREQ 1862 | MUSB_RXCSR_AUTOCLEAR); 1863 musb_writew(epio, MUSB_RXCSR, val); 1864 } 1865 } 1866 #endif /* Mentor DMA */ 1867 1868 if (!dma) { 1869 unsigned int received_len; 1870 1871 /* Unmap the buffer so that CPU can use it */ 1872 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb); 1873 1874 /* 1875 * We need to map sg if the transfer_buffer is 1876 * NULL. 1877 */ 1878 if (!urb->transfer_buffer) { 1879 qh->use_sg = true; 1880 sg_miter_start(&qh->sg_miter, urb->sg, 1, 1881 sg_flags); 1882 } 1883 1884 if (qh->use_sg) { 1885 if (!sg_miter_next(&qh->sg_miter)) { 1886 dev_err(musb->controller, "error: sg list empty\n"); 1887 sg_miter_stop(&qh->sg_miter); 1888 status = -EINVAL; 1889 done = true; 1890 goto finish; 1891 } 1892 urb->transfer_buffer = qh->sg_miter.addr; 1893 received_len = urb->actual_length; 1894 qh->offset = 0x0; 1895 done = musb_host_packet_rx(musb, urb, epnum, 1896 iso_err); 1897 /* Calculate the number of bytes received */ 1898 received_len = urb->actual_length - 1899 received_len; 1900 qh->sg_miter.consumed = received_len; 1901 sg_miter_stop(&qh->sg_miter); 1902 } else { 1903 done = musb_host_packet_rx(musb, urb, 1904 epnum, iso_err); 1905 } 1906 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : ""); 1907 } 1908 } 1909 1910 finish: 1911 urb->actual_length += xfer_len; 1912 qh->offset += xfer_len; 1913 if (done) { 1914 if (qh->use_sg) 1915 qh->use_sg = false; 1916 1917 if (urb->status == -EINPROGRESS) 1918 urb->status = status; 1919 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); 1920 } 1921 } 1922 1923 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH. 1924 * the software schedule associates multiple such nodes with a given 1925 * host side hardware endpoint + direction; scheduling may activate 1926 * that hardware endpoint. 1927 */ 1928 static int musb_schedule( 1929 struct musb *musb, 1930 struct musb_qh *qh, 1931 int is_in) 1932 { 1933 int idle; 1934 int best_diff; 1935 int best_end, epnum; 1936 struct musb_hw_ep *hw_ep = NULL; 1937 struct list_head *head = NULL; 1938 u8 toggle; 1939 u8 txtype; 1940 struct urb *urb = next_urb(qh); 1941 1942 /* use fixed hardware for control and bulk */ 1943 if (qh->type == USB_ENDPOINT_XFER_CONTROL) { 1944 head = &musb->control; 1945 hw_ep = musb->control_ep; 1946 goto success; 1947 } 1948 1949 /* else, periodic transfers get muxed to other endpoints */ 1950 1951 /* 1952 * We know this qh hasn't been scheduled, so all we need to do 1953 * is choose which hardware endpoint to put it on ... 1954 * 1955 * REVISIT what we really want here is a regular schedule tree 1956 * like e.g. OHCI uses. 1957 */ 1958 best_diff = 4096; 1959 best_end = -1; 1960 1961 for (epnum = 1, hw_ep = musb->endpoints + 1; 1962 epnum < musb->nr_endpoints; 1963 epnum++, hw_ep++) { 1964 int diff; 1965 1966 if (musb_ep_get_qh(hw_ep, is_in) != NULL) 1967 continue; 1968 1969 if (hw_ep == musb->bulk_ep) 1970 continue; 1971 1972 if (is_in) 1973 diff = hw_ep->max_packet_sz_rx; 1974 else 1975 diff = hw_ep->max_packet_sz_tx; 1976 diff -= (qh->maxpacket * qh->hb_mult); 1977 1978 if (diff >= 0 && best_diff > diff) { 1979 1980 /* 1981 * Mentor controller has a bug in that if we schedule 1982 * a BULK Tx transfer on an endpoint that had earlier 1983 * handled ISOC then the BULK transfer has to start on 1984 * a zero toggle. If the BULK transfer starts on a 1 1985 * toggle then this transfer will fail as the mentor 1986 * controller starts the Bulk transfer on a 0 toggle 1987 * irrespective of the programming of the toggle bits 1988 * in the TXCSR register. Check for this condition 1989 * while allocating the EP for a Tx Bulk transfer. If 1990 * so skip this EP. 1991 */ 1992 hw_ep = musb->endpoints + epnum; 1993 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in); 1994 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) 1995 >> 4) & 0x3; 1996 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) && 1997 toggle && (txtype == USB_ENDPOINT_XFER_ISOC)) 1998 continue; 1999 2000 best_diff = diff; 2001 best_end = epnum; 2002 } 2003 } 2004 /* use bulk reserved ep1 if no other ep is free */ 2005 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { 2006 hw_ep = musb->bulk_ep; 2007 if (is_in) 2008 head = &musb->in_bulk; 2009 else 2010 head = &musb->out_bulk; 2011 2012 /* Enable bulk RX/TX NAK timeout scheme when bulk requests are 2013 * multiplexed. This scheme doen't work in high speed to full 2014 * speed scenario as NAK interrupts are not coming from a 2015 * full speed device connected to a high speed device. 2016 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and 2017 * 4 (8 frame or 8ms) for FS device. 2018 */ 2019 if (qh->dev) 2020 qh->intv_reg = 2021 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; 2022 goto success; 2023 } else if (best_end < 0) { 2024 return -ENOSPC; 2025 } 2026 2027 idle = 1; 2028 qh->mux = 0; 2029 hw_ep = musb->endpoints + best_end; 2030 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end); 2031 success: 2032 if (head) { 2033 idle = list_empty(head); 2034 list_add_tail(&qh->ring, head); 2035 qh->mux = 1; 2036 } 2037 qh->hw_ep = hw_ep; 2038 qh->hep->hcpriv = qh; 2039 if (idle) 2040 musb_start_urb(musb, is_in, qh); 2041 return 0; 2042 } 2043 2044 static int musb_urb_enqueue( 2045 struct usb_hcd *hcd, 2046 struct urb *urb, 2047 gfp_t mem_flags) 2048 { 2049 unsigned long flags; 2050 struct musb *musb = hcd_to_musb(hcd); 2051 struct usb_host_endpoint *hep = urb->ep; 2052 struct musb_qh *qh; 2053 struct usb_endpoint_descriptor *epd = &hep->desc; 2054 int ret; 2055 unsigned type_reg; 2056 unsigned interval; 2057 2058 /* host role must be active */ 2059 if (!is_host_active(musb) || !musb->is_active) 2060 return -ENODEV; 2061 2062 spin_lock_irqsave(&musb->lock, flags); 2063 ret = usb_hcd_link_urb_to_ep(hcd, urb); 2064 qh = ret ? NULL : hep->hcpriv; 2065 if (qh) 2066 urb->hcpriv = qh; 2067 spin_unlock_irqrestore(&musb->lock, flags); 2068 2069 /* DMA mapping was already done, if needed, and this urb is on 2070 * hep->urb_list now ... so we're done, unless hep wasn't yet 2071 * scheduled onto a live qh. 2072 * 2073 * REVISIT best to keep hep->hcpriv valid until the endpoint gets 2074 * disabled, testing for empty qh->ring and avoiding qh setup costs 2075 * except for the first urb queued after a config change. 2076 */ 2077 if (qh || ret) 2078 return ret; 2079 2080 /* Allocate and initialize qh, minimizing the work done each time 2081 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. 2082 * 2083 * REVISIT consider a dedicated qh kmem_cache, so it's harder 2084 * for bugs in other kernel code to break this driver... 2085 */ 2086 qh = kzalloc(sizeof *qh, mem_flags); 2087 if (!qh) { 2088 spin_lock_irqsave(&musb->lock, flags); 2089 usb_hcd_unlink_urb_from_ep(hcd, urb); 2090 spin_unlock_irqrestore(&musb->lock, flags); 2091 return -ENOMEM; 2092 } 2093 2094 qh->hep = hep; 2095 qh->dev = urb->dev; 2096 INIT_LIST_HEAD(&qh->ring); 2097 qh->is_ready = 1; 2098 2099 qh->maxpacket = usb_endpoint_maxp(epd); 2100 qh->type = usb_endpoint_type(epd); 2101 2102 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier. 2103 * Some musb cores don't support high bandwidth ISO transfers; and 2104 * we don't (yet!) support high bandwidth interrupt transfers. 2105 */ 2106 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03); 2107 if (qh->hb_mult > 1) { 2108 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC); 2109 2110 if (ok) 2111 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx) 2112 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx); 2113 if (!ok) { 2114 ret = -EMSGSIZE; 2115 goto done; 2116 } 2117 qh->maxpacket &= 0x7ff; 2118 } 2119 2120 qh->epnum = usb_endpoint_num(epd); 2121 2122 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ 2123 qh->addr_reg = (u8) usb_pipedevice(urb->pipe); 2124 2125 /* precompute rxtype/txtype/type0 register */ 2126 type_reg = (qh->type << 4) | qh->epnum; 2127 switch (urb->dev->speed) { 2128 case USB_SPEED_LOW: 2129 type_reg |= 0xc0; 2130 break; 2131 case USB_SPEED_FULL: 2132 type_reg |= 0x80; 2133 break; 2134 default: 2135 type_reg |= 0x40; 2136 } 2137 qh->type_reg = type_reg; 2138 2139 /* Precompute RXINTERVAL/TXINTERVAL register */ 2140 switch (qh->type) { 2141 case USB_ENDPOINT_XFER_INT: 2142 /* 2143 * Full/low speeds use the linear encoding, 2144 * high speed uses the logarithmic encoding. 2145 */ 2146 if (urb->dev->speed <= USB_SPEED_FULL) { 2147 interval = max_t(u8, epd->bInterval, 1); 2148 break; 2149 } 2150 /* FALLTHROUGH */ 2151 case USB_ENDPOINT_XFER_ISOC: 2152 /* ISO always uses logarithmic encoding */ 2153 interval = min_t(u8, epd->bInterval, 16); 2154 break; 2155 default: 2156 /* REVISIT we actually want to use NAK limits, hinting to the 2157 * transfer scheduling logic to try some other qh, e.g. try 2158 * for 2 msec first: 2159 * 2160 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; 2161 * 2162 * The downside of disabling this is that transfer scheduling 2163 * gets VERY unfair for nonperiodic transfers; a misbehaving 2164 * peripheral could make that hurt. That's perfectly normal 2165 * for reads from network or serial adapters ... so we have 2166 * partial NAKlimit support for bulk RX. 2167 * 2168 * The upside of disabling it is simpler transfer scheduling. 2169 */ 2170 interval = 0; 2171 } 2172 qh->intv_reg = interval; 2173 2174 /* precompute addressing for external hub/tt ports */ 2175 if (musb->is_multipoint) { 2176 struct usb_device *parent = urb->dev->parent; 2177 2178 if (parent != hcd->self.root_hub) { 2179 qh->h_addr_reg = (u8) parent->devnum; 2180 2181 /* set up tt info if needed */ 2182 if (urb->dev->tt) { 2183 qh->h_port_reg = (u8) urb->dev->ttport; 2184 if (urb->dev->tt->hub) 2185 qh->h_addr_reg = 2186 (u8) urb->dev->tt->hub->devnum; 2187 if (urb->dev->tt->multi) 2188 qh->h_addr_reg |= 0x80; 2189 } 2190 } 2191 } 2192 2193 /* invariant: hep->hcpriv is null OR the qh that's already scheduled. 2194 * until we get real dma queues (with an entry for each urb/buffer), 2195 * we only have work to do in the former case. 2196 */ 2197 spin_lock_irqsave(&musb->lock, flags); 2198 if (hep->hcpriv || !next_urb(qh)) { 2199 /* some concurrent activity submitted another urb to hep... 2200 * odd, rare, error prone, but legal. 2201 */ 2202 kfree(qh); 2203 qh = NULL; 2204 ret = 0; 2205 } else 2206 ret = musb_schedule(musb, qh, 2207 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); 2208 2209 if (ret == 0) { 2210 urb->hcpriv = qh; 2211 /* FIXME set urb->start_frame for iso/intr, it's tested in 2212 * musb_start_urb(), but otherwise only konicawc cares ... 2213 */ 2214 } 2215 spin_unlock_irqrestore(&musb->lock, flags); 2216 2217 done: 2218 if (ret != 0) { 2219 spin_lock_irqsave(&musb->lock, flags); 2220 usb_hcd_unlink_urb_from_ep(hcd, urb); 2221 spin_unlock_irqrestore(&musb->lock, flags); 2222 kfree(qh); 2223 } 2224 return ret; 2225 } 2226 2227 2228 /* 2229 * abort a transfer that's at the head of a hardware queue. 2230 * called with controller locked, irqs blocked 2231 * that hardware queue advances to the next transfer, unless prevented 2232 */ 2233 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) 2234 { 2235 struct musb_hw_ep *ep = qh->hw_ep; 2236 struct musb *musb = ep->musb; 2237 void __iomem *epio = ep->regs; 2238 unsigned hw_end = ep->epnum; 2239 void __iomem *regs = ep->musb->mregs; 2240 int is_in = usb_pipein(urb->pipe); 2241 int status = 0; 2242 u16 csr; 2243 2244 musb_ep_select(regs, hw_end); 2245 2246 if (is_dma_capable()) { 2247 struct dma_channel *dma; 2248 2249 dma = is_in ? ep->rx_channel : ep->tx_channel; 2250 if (dma) { 2251 status = ep->musb->dma_controller->channel_abort(dma); 2252 dev_dbg(musb->controller, 2253 "abort %cX%d DMA for urb %p --> %d\n", 2254 is_in ? 'R' : 'T', ep->epnum, 2255 urb, status); 2256 urb->actual_length += dma->actual_len; 2257 } 2258 } 2259 2260 /* turn off DMA requests, discard state, stop polling ... */ 2261 if (ep->epnum && is_in) { 2262 /* giveback saves bulk toggle */ 2263 csr = musb_h_flush_rxfifo(ep, 0); 2264 2265 /* REVISIT we still get an irq; should likely clear the 2266 * endpoint's irq status here to avoid bogus irqs. 2267 * clearing that status is platform-specific... 2268 */ 2269 } else if (ep->epnum) { 2270 musb_h_tx_flush_fifo(ep); 2271 csr = musb_readw(epio, MUSB_TXCSR); 2272 csr &= ~(MUSB_TXCSR_AUTOSET 2273 | MUSB_TXCSR_DMAENAB 2274 | MUSB_TXCSR_H_RXSTALL 2275 | MUSB_TXCSR_H_NAKTIMEOUT 2276 | MUSB_TXCSR_H_ERROR 2277 | MUSB_TXCSR_TXPKTRDY); 2278 musb_writew(epio, MUSB_TXCSR, csr); 2279 /* REVISIT may need to clear FLUSHFIFO ... */ 2280 musb_writew(epio, MUSB_TXCSR, csr); 2281 /* flush cpu writebuffer */ 2282 csr = musb_readw(epio, MUSB_TXCSR); 2283 } else { 2284 musb_h_ep0_flush_fifo(ep); 2285 } 2286 if (status == 0) 2287 musb_advance_schedule(ep->musb, urb, ep, is_in); 2288 return status; 2289 } 2290 2291 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 2292 { 2293 struct musb *musb = hcd_to_musb(hcd); 2294 struct musb_qh *qh; 2295 unsigned long flags; 2296 int is_in = usb_pipein(urb->pipe); 2297 int ret; 2298 2299 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb, 2300 usb_pipedevice(urb->pipe), 2301 usb_pipeendpoint(urb->pipe), 2302 is_in ? "in" : "out"); 2303 2304 spin_lock_irqsave(&musb->lock, flags); 2305 ret = usb_hcd_check_unlink_urb(hcd, urb, status); 2306 if (ret) 2307 goto done; 2308 2309 qh = urb->hcpriv; 2310 if (!qh) 2311 goto done; 2312 2313 /* 2314 * Any URB not actively programmed into endpoint hardware can be 2315 * immediately given back; that's any URB not at the head of an 2316 * endpoint queue, unless someday we get real DMA queues. And even 2317 * if it's at the head, it might not be known to the hardware... 2318 * 2319 * Otherwise abort current transfer, pending DMA, etc.; urb->status 2320 * has already been updated. This is a synchronous abort; it'd be 2321 * OK to hold off until after some IRQ, though. 2322 * 2323 * NOTE: qh is invalid unless !list_empty(&hep->urb_list) 2324 */ 2325 if (!qh->is_ready 2326 || urb->urb_list.prev != &qh->hep->urb_list 2327 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) { 2328 int ready = qh->is_ready; 2329 2330 qh->is_ready = 0; 2331 musb_giveback(musb, urb, 0); 2332 qh->is_ready = ready; 2333 2334 /* If nothing else (usually musb_giveback) is using it 2335 * and its URB list has emptied, recycle this qh. 2336 */ 2337 if (ready && list_empty(&qh->hep->urb_list)) { 2338 qh->hep->hcpriv = NULL; 2339 list_del(&qh->ring); 2340 kfree(qh); 2341 } 2342 } else 2343 ret = musb_cleanup_urb(urb, qh); 2344 done: 2345 spin_unlock_irqrestore(&musb->lock, flags); 2346 return ret; 2347 } 2348 2349 /* disable an endpoint */ 2350 static void 2351 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) 2352 { 2353 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN; 2354 unsigned long flags; 2355 struct musb *musb = hcd_to_musb(hcd); 2356 struct musb_qh *qh; 2357 struct urb *urb; 2358 2359 spin_lock_irqsave(&musb->lock, flags); 2360 2361 qh = hep->hcpriv; 2362 if (qh == NULL) 2363 goto exit; 2364 2365 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ 2366 2367 /* Kick the first URB off the hardware, if needed */ 2368 qh->is_ready = 0; 2369 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) { 2370 urb = next_urb(qh); 2371 2372 /* make software (then hardware) stop ASAP */ 2373 if (!urb->unlinked) 2374 urb->status = -ESHUTDOWN; 2375 2376 /* cleanup */ 2377 musb_cleanup_urb(urb, qh); 2378 2379 /* Then nuke all the others ... and advance the 2380 * queue on hw_ep (e.g. bulk ring) when we're done. 2381 */ 2382 while (!list_empty(&hep->urb_list)) { 2383 urb = next_urb(qh); 2384 urb->status = -ESHUTDOWN; 2385 musb_advance_schedule(musb, urb, qh->hw_ep, is_in); 2386 } 2387 } else { 2388 /* Just empty the queue; the hardware is busy with 2389 * other transfers, and since !qh->is_ready nothing 2390 * will activate any of these as it advances. 2391 */ 2392 while (!list_empty(&hep->urb_list)) 2393 musb_giveback(musb, next_urb(qh), -ESHUTDOWN); 2394 2395 hep->hcpriv = NULL; 2396 list_del(&qh->ring); 2397 kfree(qh); 2398 } 2399 exit: 2400 spin_unlock_irqrestore(&musb->lock, flags); 2401 } 2402 2403 static int musb_h_get_frame_number(struct usb_hcd *hcd) 2404 { 2405 struct musb *musb = hcd_to_musb(hcd); 2406 2407 return musb_readw(musb->mregs, MUSB_FRAME); 2408 } 2409 2410 static int musb_h_start(struct usb_hcd *hcd) 2411 { 2412 struct musb *musb = hcd_to_musb(hcd); 2413 2414 /* NOTE: musb_start() is called when the hub driver turns 2415 * on port power, or when (OTG) peripheral starts. 2416 */ 2417 hcd->state = HC_STATE_RUNNING; 2418 musb->port1_status = 0; 2419 return 0; 2420 } 2421 2422 static void musb_h_stop(struct usb_hcd *hcd) 2423 { 2424 musb_stop(hcd_to_musb(hcd)); 2425 hcd->state = HC_STATE_HALT; 2426 } 2427 2428 static int musb_bus_suspend(struct usb_hcd *hcd) 2429 { 2430 struct musb *musb = hcd_to_musb(hcd); 2431 u8 devctl; 2432 2433 if (!is_host_active(musb)) 2434 return 0; 2435 2436 switch (musb->xceiv->state) { 2437 case OTG_STATE_A_SUSPEND: 2438 return 0; 2439 case OTG_STATE_A_WAIT_VRISE: 2440 /* ID could be grounded even if there's no device 2441 * on the other end of the cable. NOTE that the 2442 * A_WAIT_VRISE timers are messy with MUSB... 2443 */ 2444 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2445 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 2446 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 2447 break; 2448 default: 2449 break; 2450 } 2451 2452 if (musb->is_active) { 2453 WARNING("trying to suspend as %s while active\n", 2454 usb_otg_state_string(musb->xceiv->state)); 2455 return -EBUSY; 2456 } else 2457 return 0; 2458 } 2459 2460 static int musb_bus_resume(struct usb_hcd *hcd) 2461 { 2462 /* resuming child port does the work */ 2463 return 0; 2464 } 2465 2466 2467 #ifndef CONFIG_MUSB_PIO_ONLY 2468 2469 #define MUSB_USB_DMA_ALIGN 4 2470 2471 struct musb_temp_buffer { 2472 void *kmalloc_ptr; 2473 void *old_xfer_buffer; 2474 u8 data[0]; 2475 }; 2476 2477 static void musb_free_temp_buffer(struct urb *urb) 2478 { 2479 enum dma_data_direction dir; 2480 struct musb_temp_buffer *temp; 2481 2482 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2483 return; 2484 2485 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 2486 2487 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer, 2488 data); 2489 2490 if (dir == DMA_FROM_DEVICE) { 2491 memcpy(temp->old_xfer_buffer, temp->data, 2492 urb->transfer_buffer_length); 2493 } 2494 urb->transfer_buffer = temp->old_xfer_buffer; 2495 kfree(temp->kmalloc_ptr); 2496 2497 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2498 } 2499 2500 static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) 2501 { 2502 enum dma_data_direction dir; 2503 struct musb_temp_buffer *temp; 2504 void *kmalloc_ptr; 2505 size_t kmalloc_size; 2506 2507 if (urb->num_sgs || urb->sg || 2508 urb->transfer_buffer_length == 0 || 2509 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1))) 2510 return 0; 2511 2512 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 2513 2514 /* Allocate a buffer with enough padding for alignment */ 2515 kmalloc_size = urb->transfer_buffer_length + 2516 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1; 2517 2518 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2519 if (!kmalloc_ptr) 2520 return -ENOMEM; 2521 2522 /* Position our struct temp_buffer such that data is aligned */ 2523 temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN); 2524 2525 2526 temp->kmalloc_ptr = kmalloc_ptr; 2527 temp->old_xfer_buffer = urb->transfer_buffer; 2528 if (dir == DMA_TO_DEVICE) 2529 memcpy(temp->data, urb->transfer_buffer, 2530 urb->transfer_buffer_length); 2531 urb->transfer_buffer = temp->data; 2532 2533 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2534 2535 return 0; 2536 } 2537 2538 static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2539 gfp_t mem_flags) 2540 { 2541 struct musb *musb = hcd_to_musb(hcd); 2542 int ret; 2543 2544 /* 2545 * The DMA engine in RTL1.8 and above cannot handle 2546 * DMA addresses that are not aligned to a 4 byte boundary. 2547 * For such engine implemented (un)map_urb_for_dma hooks. 2548 * Do not use these hooks for RTL<1.8 2549 */ 2550 if (musb->hwvers < MUSB_HWVERS_1800) 2551 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2552 2553 ret = musb_alloc_temp_buffer(urb, mem_flags); 2554 if (ret) 2555 return ret; 2556 2557 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2558 if (ret) 2559 musb_free_temp_buffer(urb); 2560 2561 return ret; 2562 } 2563 2564 static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2565 { 2566 struct musb *musb = hcd_to_musb(hcd); 2567 2568 usb_hcd_unmap_urb_for_dma(hcd, urb); 2569 2570 /* Do not use this hook for RTL<1.8 (see description above) */ 2571 if (musb->hwvers < MUSB_HWVERS_1800) 2572 return; 2573 2574 musb_free_temp_buffer(urb); 2575 } 2576 #endif /* !CONFIG_MUSB_PIO_ONLY */ 2577 2578 const struct hc_driver musb_hc_driver = { 2579 .description = "musb-hcd", 2580 .product_desc = "MUSB HDRC host driver", 2581 .hcd_priv_size = sizeof(struct musb), 2582 .flags = HCD_USB2 | HCD_MEMORY, 2583 2584 /* not using irq handler or reset hooks from usbcore, since 2585 * those must be shared with peripheral code for OTG configs 2586 */ 2587 2588 .start = musb_h_start, 2589 .stop = musb_h_stop, 2590 2591 .get_frame_number = musb_h_get_frame_number, 2592 2593 .urb_enqueue = musb_urb_enqueue, 2594 .urb_dequeue = musb_urb_dequeue, 2595 .endpoint_disable = musb_h_disable, 2596 2597 #ifndef CONFIG_MUSB_PIO_ONLY 2598 .map_urb_for_dma = musb_map_urb_for_dma, 2599 .unmap_urb_for_dma = musb_unmap_urb_for_dma, 2600 #endif 2601 2602 .hub_status_data = musb_hub_status_data, 2603 .hub_control = musb_hub_control, 2604 .bus_suspend = musb_bus_suspend, 2605 .bus_resume = musb_bus_resume, 2606 /* .start_port_reset = NULL, */ 2607 /* .hub_irq_enable = NULL, */ 2608 }; 2609