1 /* 2 * MUSB OTG driver host support 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <linux/module.h> 37 #include <linux/kernel.h> 38 #include <linux/delay.h> 39 #include <linux/sched.h> 40 #include <linux/slab.h> 41 #include <linux/errno.h> 42 #include <linux/init.h> 43 #include <linux/list.h> 44 #include <linux/dma-mapping.h> 45 46 #include "musb_core.h" 47 #include "musb_host.h" 48 49 50 /* MUSB HOST status 22-mar-2006 51 * 52 * - There's still lots of partial code duplication for fault paths, so 53 * they aren't handled as consistently as they need to be. 54 * 55 * - PIO mostly behaved when last tested. 56 * + including ep0, with all usbtest cases 9, 10 57 * + usbtest 14 (ep0out) doesn't seem to run at all 58 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest 59 * configurations, but otherwise double buffering passes basic tests. 60 * + for 2.6.N, for N > ~10, needs API changes for hcd framework. 61 * 62 * - DMA (CPPI) ... partially behaves, not currently recommended 63 * + about 1/15 the speed of typical EHCI implementations (PCI) 64 * + RX, all too often reqpkt seems to misbehave after tx 65 * + TX, no known issues (other than evident silicon issue) 66 * 67 * - DMA (Mentor/OMAP) ...has at least toggle update problems 68 * 69 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet 70 * starvation ... nothing yet for TX, interrupt, or bulk. 71 * 72 * - Not tested with HNP, but some SRP paths seem to behave. 73 * 74 * NOTE 24-August-2006: 75 * 76 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an 77 * extra endpoint for periodic use enabling hub + keybd + mouse. That 78 * mostly works, except that with "usbnet" it's easy to trigger cases 79 * with "ping" where RX loses. (a) ping to davinci, even "ping -f", 80 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses 81 * although ARP RX wins. (That test was done with a full speed link.) 82 */ 83 84 85 /* 86 * NOTE on endpoint usage: 87 * 88 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN 89 * and OUT endpoints ... hardware is dedicated for those "async" queue(s). 90 * (Yes, bulk _could_ use more of the endpoints than that, and would even 91 * benefit from it.) 92 * 93 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. 94 * So far that scheduling is both dumb and optimistic: the endpoint will be 95 * "claimed" until its software queue is no longer refilled. No multiplexing 96 * of transfers between endpoints, or anything clever. 97 */ 98 99 100 static void musb_ep_program(struct musb *musb, u8 epnum, 101 struct urb *urb, int is_out, 102 u8 *buf, u32 offset, u32 len); 103 104 /* 105 * Clear TX fifo. Needed to avoid BABBLE errors. 106 */ 107 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) 108 { 109 void __iomem *epio = ep->regs; 110 u16 csr; 111 u16 lastcsr = 0; 112 int retries = 1000; 113 114 csr = musb_readw(epio, MUSB_TXCSR); 115 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { 116 if (csr != lastcsr) 117 DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr); 118 lastcsr = csr; 119 csr |= MUSB_TXCSR_FLUSHFIFO; 120 musb_writew(epio, MUSB_TXCSR, csr); 121 csr = musb_readw(epio, MUSB_TXCSR); 122 if (WARN(retries-- < 1, 123 "Could not flush host TX%d fifo: csr: %04x\n", 124 ep->epnum, csr)) 125 return; 126 mdelay(1); 127 } 128 } 129 130 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) 131 { 132 void __iomem *epio = ep->regs; 133 u16 csr; 134 int retries = 5; 135 136 /* scrub any data left in the fifo */ 137 do { 138 csr = musb_readw(epio, MUSB_TXCSR); 139 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) 140 break; 141 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO); 142 csr = musb_readw(epio, MUSB_TXCSR); 143 udelay(10); 144 } while (--retries); 145 146 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", 147 ep->epnum, csr); 148 149 /* and reset for the next transfer */ 150 musb_writew(epio, MUSB_TXCSR, 0); 151 } 152 153 /* 154 * Start transmit. Caller is responsible for locking shared resources. 155 * musb must be locked. 156 */ 157 static inline void musb_h_tx_start(struct musb_hw_ep *ep) 158 { 159 u16 txcsr; 160 161 /* NOTE: no locks here; caller should lock and select EP */ 162 if (ep->epnum) { 163 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 164 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; 165 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 166 } else { 167 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; 168 musb_writew(ep->regs, MUSB_CSR0, txcsr); 169 } 170 171 } 172 173 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep) 174 { 175 u16 txcsr; 176 177 /* NOTE: no locks here; caller should lock and select EP */ 178 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 179 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; 180 if (is_cppi_enabled()) 181 txcsr |= MUSB_TXCSR_DMAMODE; 182 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 183 } 184 185 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh) 186 { 187 if (is_in != 0 || ep->is_shared_fifo) 188 ep->in_qh = qh; 189 if (is_in == 0 || ep->is_shared_fifo) 190 ep->out_qh = qh; 191 } 192 193 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in) 194 { 195 return is_in ? ep->in_qh : ep->out_qh; 196 } 197 198 /* 199 * Start the URB at the front of an endpoint's queue 200 * end must be claimed from the caller. 201 * 202 * Context: controller locked, irqs blocked 203 */ 204 static void 205 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) 206 { 207 u16 frame; 208 u32 len; 209 void __iomem *mbase = musb->mregs; 210 struct urb *urb = next_urb(qh); 211 void *buf = urb->transfer_buffer; 212 u32 offset = 0; 213 struct musb_hw_ep *hw_ep = qh->hw_ep; 214 unsigned pipe = urb->pipe; 215 u8 address = usb_pipedevice(pipe); 216 int epnum = hw_ep->epnum; 217 218 /* initialize software qh state */ 219 qh->offset = 0; 220 qh->segsize = 0; 221 222 /* gather right source of data */ 223 switch (qh->type) { 224 case USB_ENDPOINT_XFER_CONTROL: 225 /* control transfers always start with SETUP */ 226 is_in = 0; 227 musb->ep0_stage = MUSB_EP0_START; 228 buf = urb->setup_packet; 229 len = 8; 230 break; 231 case USB_ENDPOINT_XFER_ISOC: 232 qh->iso_idx = 0; 233 qh->frame = 0; 234 offset = urb->iso_frame_desc[0].offset; 235 len = urb->iso_frame_desc[0].length; 236 break; 237 default: /* bulk, interrupt */ 238 /* actual_length may be nonzero on retry paths */ 239 buf = urb->transfer_buffer + urb->actual_length; 240 len = urb->transfer_buffer_length - urb->actual_length; 241 } 242 243 DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", 244 qh, urb, address, qh->epnum, 245 is_in ? "in" : "out", 246 ({char *s; switch (qh->type) { 247 case USB_ENDPOINT_XFER_CONTROL: s = ""; break; 248 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break; 249 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break; 250 default: s = "-intr"; break; 251 }; s; }), 252 epnum, buf + offset, len); 253 254 /* Configure endpoint */ 255 musb_ep_set_qh(hw_ep, is_in, qh); 256 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len); 257 258 /* transmit may have more work: start it when it is time */ 259 if (is_in) 260 return; 261 262 /* determine if the time is right for a periodic transfer */ 263 switch (qh->type) { 264 case USB_ENDPOINT_XFER_ISOC: 265 case USB_ENDPOINT_XFER_INT: 266 DBG(3, "check whether there's still time for periodic Tx\n"); 267 frame = musb_readw(mbase, MUSB_FRAME); 268 /* FIXME this doesn't implement that scheduling policy ... 269 * or handle framecounter wrapping 270 */ 271 if ((urb->transfer_flags & URB_ISO_ASAP) 272 || (frame >= urb->start_frame)) { 273 /* REVISIT the SOF irq handler shouldn't duplicate 274 * this code; and we don't init urb->start_frame... 275 */ 276 qh->frame = 0; 277 goto start; 278 } else { 279 qh->frame = urb->start_frame; 280 /* enable SOF interrupt so we can count down */ 281 DBG(1, "SOF for %d\n", epnum); 282 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */ 283 musb_writeb(mbase, MUSB_INTRUSBE, 0xff); 284 #endif 285 } 286 break; 287 default: 288 start: 289 DBG(4, "Start TX%d %s\n", epnum, 290 hw_ep->tx_channel ? "dma" : "pio"); 291 292 if (!hw_ep->tx_channel) 293 musb_h_tx_start(hw_ep); 294 else if (is_cppi_enabled() || tusb_dma_omap()) 295 musb_h_tx_dma_start(hw_ep); 296 } 297 } 298 299 /* Context: caller owns controller lock, IRQs are blocked */ 300 static void musb_giveback(struct musb *musb, struct urb *urb, int status) 301 __releases(musb->lock) 302 __acquires(musb->lock) 303 { 304 DBG(({ int level; switch (status) { 305 case 0: 306 level = 4; 307 break; 308 /* common/boring faults */ 309 case -EREMOTEIO: 310 case -ESHUTDOWN: 311 case -ECONNRESET: 312 case -EPIPE: 313 level = 3; 314 break; 315 default: 316 level = 2; 317 break; 318 }; level; }), 319 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", 320 urb, urb->complete, status, 321 usb_pipedevice(urb->pipe), 322 usb_pipeendpoint(urb->pipe), 323 usb_pipein(urb->pipe) ? "in" : "out", 324 urb->actual_length, urb->transfer_buffer_length 325 ); 326 327 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb); 328 spin_unlock(&musb->lock); 329 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status); 330 spin_lock(&musb->lock); 331 } 332 333 /* For bulk/interrupt endpoints only */ 334 static inline void musb_save_toggle(struct musb_qh *qh, int is_in, 335 struct urb *urb) 336 { 337 void __iomem *epio = qh->hw_ep->regs; 338 u16 csr; 339 340 /* 341 * FIXME: the current Mentor DMA code seems to have 342 * problems getting toggle correct. 343 */ 344 345 if (is_in) 346 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE; 347 else 348 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE; 349 350 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0); 351 } 352 353 /* 354 * Advance this hardware endpoint's queue, completing the specified URB and 355 * advancing to either the next URB queued to that qh, or else invalidating 356 * that qh and advancing to the next qh scheduled after the current one. 357 * 358 * Context: caller owns controller lock, IRQs are blocked 359 */ 360 static void musb_advance_schedule(struct musb *musb, struct urb *urb, 361 struct musb_hw_ep *hw_ep, int is_in) 362 { 363 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in); 364 struct musb_hw_ep *ep = qh->hw_ep; 365 int ready = qh->is_ready; 366 int status; 367 368 status = (urb->status == -EINPROGRESS) ? 0 : urb->status; 369 370 /* save toggle eagerly, for paranoia */ 371 switch (qh->type) { 372 case USB_ENDPOINT_XFER_BULK: 373 case USB_ENDPOINT_XFER_INT: 374 musb_save_toggle(qh, is_in, urb); 375 break; 376 case USB_ENDPOINT_XFER_ISOC: 377 if (status == 0 && urb->error_count) 378 status = -EXDEV; 379 break; 380 } 381 382 qh->is_ready = 0; 383 musb_giveback(musb, urb, status); 384 qh->is_ready = ready; 385 386 /* reclaim resources (and bandwidth) ASAP; deschedule it, and 387 * invalidate qh as soon as list_empty(&hep->urb_list) 388 */ 389 if (list_empty(&qh->hep->urb_list)) { 390 struct list_head *head; 391 392 if (is_in) 393 ep->rx_reinit = 1; 394 else 395 ep->tx_reinit = 1; 396 397 /* Clobber old pointers to this qh */ 398 musb_ep_set_qh(ep, is_in, NULL); 399 qh->hep->hcpriv = NULL; 400 401 switch (qh->type) { 402 403 case USB_ENDPOINT_XFER_CONTROL: 404 case USB_ENDPOINT_XFER_BULK: 405 /* fifo policy for these lists, except that NAKing 406 * should rotate a qh to the end (for fairness). 407 */ 408 if (qh->mux == 1) { 409 head = qh->ring.prev; 410 list_del(&qh->ring); 411 kfree(qh); 412 qh = first_qh(head); 413 break; 414 } 415 416 case USB_ENDPOINT_XFER_ISOC: 417 case USB_ENDPOINT_XFER_INT: 418 /* this is where periodic bandwidth should be 419 * de-allocated if it's tracked and allocated; 420 * and where we'd update the schedule tree... 421 */ 422 kfree(qh); 423 qh = NULL; 424 break; 425 } 426 } 427 428 if (qh != NULL && qh->is_ready) { 429 DBG(4, "... next ep%d %cX urb %p\n", 430 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); 431 musb_start_urb(musb, is_in, qh); 432 } 433 } 434 435 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) 436 { 437 /* we don't want fifo to fill itself again; 438 * ignore dma (various models), 439 * leave toggle alone (may not have been saved yet) 440 */ 441 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; 442 csr &= ~(MUSB_RXCSR_H_REQPKT 443 | MUSB_RXCSR_H_AUTOREQ 444 | MUSB_RXCSR_AUTOCLEAR); 445 446 /* write 2x to allow double buffering */ 447 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 448 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 449 450 /* flush writebuffer */ 451 return musb_readw(hw_ep->regs, MUSB_RXCSR); 452 } 453 454 /* 455 * PIO RX for a packet (or part of it). 456 */ 457 static bool 458 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) 459 { 460 u16 rx_count; 461 u8 *buf; 462 u16 csr; 463 bool done = false; 464 u32 length; 465 int do_flush = 0; 466 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 467 void __iomem *epio = hw_ep->regs; 468 struct musb_qh *qh = hw_ep->in_qh; 469 int pipe = urb->pipe; 470 void *buffer = urb->transfer_buffer; 471 472 /* musb_ep_select(mbase, epnum); */ 473 rx_count = musb_readw(epio, MUSB_RXCOUNT); 474 DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, 475 urb->transfer_buffer, qh->offset, 476 urb->transfer_buffer_length); 477 478 /* unload FIFO */ 479 if (usb_pipeisoc(pipe)) { 480 int status = 0; 481 struct usb_iso_packet_descriptor *d; 482 483 if (iso_err) { 484 status = -EILSEQ; 485 urb->error_count++; 486 } 487 488 d = urb->iso_frame_desc + qh->iso_idx; 489 buf = buffer + d->offset; 490 length = d->length; 491 if (rx_count > length) { 492 if (status == 0) { 493 status = -EOVERFLOW; 494 urb->error_count++; 495 } 496 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); 497 do_flush = 1; 498 } else 499 length = rx_count; 500 urb->actual_length += length; 501 d->actual_length = length; 502 503 d->status = status; 504 505 /* see if we are done */ 506 done = (++qh->iso_idx >= urb->number_of_packets); 507 } else { 508 /* non-isoch */ 509 buf = buffer + qh->offset; 510 length = urb->transfer_buffer_length - qh->offset; 511 if (rx_count > length) { 512 if (urb->status == -EINPROGRESS) 513 urb->status = -EOVERFLOW; 514 DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); 515 do_flush = 1; 516 } else 517 length = rx_count; 518 urb->actual_length += length; 519 qh->offset += length; 520 521 /* see if we are done */ 522 done = (urb->actual_length == urb->transfer_buffer_length) 523 || (rx_count < qh->maxpacket) 524 || (urb->status != -EINPROGRESS); 525 if (done 526 && (urb->status == -EINPROGRESS) 527 && (urb->transfer_flags & URB_SHORT_NOT_OK) 528 && (urb->actual_length 529 < urb->transfer_buffer_length)) 530 urb->status = -EREMOTEIO; 531 } 532 533 musb_read_fifo(hw_ep, length, buf); 534 535 csr = musb_readw(epio, MUSB_RXCSR); 536 csr |= MUSB_RXCSR_H_WZC_BITS; 537 if (unlikely(do_flush)) 538 musb_h_flush_rxfifo(hw_ep, csr); 539 else { 540 /* REVISIT this assumes AUTOCLEAR is never set */ 541 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); 542 if (!done) 543 csr |= MUSB_RXCSR_H_REQPKT; 544 musb_writew(epio, MUSB_RXCSR, csr); 545 } 546 547 return done; 548 } 549 550 /* we don't always need to reinit a given side of an endpoint... 551 * when we do, use tx/rx reinit routine and then construct a new CSR 552 * to address data toggle, NYET, and DMA or PIO. 553 * 554 * it's possible that driver bugs (especially for DMA) or aborting a 555 * transfer might have left the endpoint busier than it should be. 556 * the busy/not-empty tests are basically paranoia. 557 */ 558 static void 559 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) 560 { 561 u16 csr; 562 563 /* NOTE: we know the "rx" fifo reinit never triggers for ep0. 564 * That always uses tx_reinit since ep0 repurposes TX register 565 * offsets; the initial SETUP packet is also a kind of OUT. 566 */ 567 568 /* if programmed for Tx, put it in RX mode */ 569 if (ep->is_shared_fifo) { 570 csr = musb_readw(ep->regs, MUSB_TXCSR); 571 if (csr & MUSB_TXCSR_MODE) { 572 musb_h_tx_flush_fifo(ep); 573 csr = musb_readw(ep->regs, MUSB_TXCSR); 574 musb_writew(ep->regs, MUSB_TXCSR, 575 csr | MUSB_TXCSR_FRCDATATOG); 576 } 577 578 /* 579 * Clear the MODE bit (and everything else) to enable Rx. 580 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB. 581 */ 582 if (csr & MUSB_TXCSR_DMAMODE) 583 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE); 584 musb_writew(ep->regs, MUSB_TXCSR, 0); 585 586 /* scrub all previous state, clearing toggle */ 587 } else { 588 csr = musb_readw(ep->regs, MUSB_RXCSR); 589 if (csr & MUSB_RXCSR_RXPKTRDY) 590 WARNING("rx%d, packet/%d ready?\n", ep->epnum, 591 musb_readw(ep->regs, MUSB_RXCOUNT)); 592 593 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); 594 } 595 596 /* target addr and (for multipoint) hub addr/port */ 597 if (musb->is_multipoint) { 598 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg); 599 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg); 600 musb_write_rxhubport(ep->target_regs, qh->h_port_reg); 601 602 } else 603 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); 604 605 /* protocol/endpoint, interval/NAKlimit, i/o size */ 606 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); 607 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); 608 /* NOTE: bulk combining rewrites high bits of maxpacket */ 609 /* Set RXMAXP with the FIFO size of the endpoint 610 * to disable double buffer mode. 611 */ 612 if (musb->hwvers < MUSB_HWVERS_2000) 613 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx); 614 else 615 musb_writew(ep->regs, MUSB_RXMAXP, 616 qh->maxpacket | ((qh->hb_mult - 1) << 11)); 617 618 ep->rx_reinit = 0; 619 } 620 621 static bool musb_tx_dma_program(struct dma_controller *dma, 622 struct musb_hw_ep *hw_ep, struct musb_qh *qh, 623 struct urb *urb, u32 offset, u32 length) 624 { 625 struct dma_channel *channel = hw_ep->tx_channel; 626 void __iomem *epio = hw_ep->regs; 627 u16 pkt_size = qh->maxpacket; 628 u16 csr; 629 u8 mode; 630 631 #ifdef CONFIG_USB_INVENTRA_DMA 632 if (length > channel->max_len) 633 length = channel->max_len; 634 635 csr = musb_readw(epio, MUSB_TXCSR); 636 if (length > pkt_size) { 637 mode = 1; 638 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; 639 /* autoset shouldn't be set in high bandwidth */ 640 if (qh->hb_mult == 1) 641 csr |= MUSB_TXCSR_AUTOSET; 642 } else { 643 mode = 0; 644 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); 645 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ 646 } 647 channel->desired_mode = mode; 648 musb_writew(epio, MUSB_TXCSR, csr); 649 #else 650 if (!is_cppi_enabled() && !tusb_dma_omap()) 651 return false; 652 653 channel->actual_len = 0; 654 655 /* 656 * TX uses "RNDIS" mode automatically but needs help 657 * to identify the zero-length-final-packet case. 658 */ 659 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; 660 #endif 661 662 qh->segsize = length; 663 664 /* 665 * Ensure the data reaches to main memory before starting 666 * DMA transfer 667 */ 668 wmb(); 669 670 if (!dma->channel_program(channel, pkt_size, mode, 671 urb->transfer_dma + offset, length)) { 672 dma->channel_release(channel); 673 hw_ep->tx_channel = NULL; 674 675 csr = musb_readw(epio, MUSB_TXCSR); 676 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 677 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); 678 return false; 679 } 680 return true; 681 } 682 683 /* 684 * Program an HDRC endpoint as per the given URB 685 * Context: irqs blocked, controller lock held 686 */ 687 static void musb_ep_program(struct musb *musb, u8 epnum, 688 struct urb *urb, int is_out, 689 u8 *buf, u32 offset, u32 len) 690 { 691 struct dma_controller *dma_controller; 692 struct dma_channel *dma_channel; 693 u8 dma_ok; 694 void __iomem *mbase = musb->mregs; 695 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 696 void __iomem *epio = hw_ep->regs; 697 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); 698 u16 packet_sz = qh->maxpacket; 699 700 DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s " 701 "h_addr%02x h_port%02x bytes %d\n", 702 is_out ? "-->" : "<--", 703 epnum, urb, urb->dev->speed, 704 qh->addr_reg, qh->epnum, is_out ? "out" : "in", 705 qh->h_addr_reg, qh->h_port_reg, 706 len); 707 708 musb_ep_select(mbase, epnum); 709 710 /* candidate for DMA? */ 711 dma_controller = musb->dma_controller; 712 if (is_dma_capable() && epnum && dma_controller) { 713 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; 714 if (!dma_channel) { 715 dma_channel = dma_controller->channel_alloc( 716 dma_controller, hw_ep, is_out); 717 if (is_out) 718 hw_ep->tx_channel = dma_channel; 719 else 720 hw_ep->rx_channel = dma_channel; 721 } 722 } else 723 dma_channel = NULL; 724 725 /* make sure we clear DMAEnab, autoSet bits from previous run */ 726 727 /* OUT/transmit/EP0 or IN/receive? */ 728 if (is_out) { 729 u16 csr; 730 u16 int_txe; 731 u16 load_count; 732 733 csr = musb_readw(epio, MUSB_TXCSR); 734 735 /* disable interrupt in case we flush */ 736 int_txe = musb_readw(mbase, MUSB_INTRTXE); 737 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); 738 739 /* general endpoint setup */ 740 if (epnum) { 741 /* flush all old state, set default */ 742 musb_h_tx_flush_fifo(hw_ep); 743 744 /* 745 * We must not clear the DMAMODE bit before or in 746 * the same cycle with the DMAENAB bit, so we clear 747 * the latter first... 748 */ 749 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT 750 | MUSB_TXCSR_AUTOSET 751 | MUSB_TXCSR_DMAENAB 752 | MUSB_TXCSR_FRCDATATOG 753 | MUSB_TXCSR_H_RXSTALL 754 | MUSB_TXCSR_H_ERROR 755 | MUSB_TXCSR_TXPKTRDY 756 ); 757 csr |= MUSB_TXCSR_MODE; 758 759 if (usb_gettoggle(urb->dev, qh->epnum, 1)) 760 csr |= MUSB_TXCSR_H_WR_DATATOGGLE 761 | MUSB_TXCSR_H_DATATOGGLE; 762 else 763 csr |= MUSB_TXCSR_CLRDATATOG; 764 765 musb_writew(epio, MUSB_TXCSR, csr); 766 /* REVISIT may need to clear FLUSHFIFO ... */ 767 csr &= ~MUSB_TXCSR_DMAMODE; 768 musb_writew(epio, MUSB_TXCSR, csr); 769 csr = musb_readw(epio, MUSB_TXCSR); 770 } else { 771 /* endpoint 0: just flush */ 772 musb_h_ep0_flush_fifo(hw_ep); 773 } 774 775 /* target addr and (for multipoint) hub addr/port */ 776 if (musb->is_multipoint) { 777 musb_write_txfunaddr(mbase, epnum, qh->addr_reg); 778 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg); 779 musb_write_txhubport(mbase, epnum, qh->h_port_reg); 780 /* FIXME if !epnum, do the same for RX ... */ 781 } else 782 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); 783 784 /* protocol/endpoint/interval/NAKlimit */ 785 if (epnum) { 786 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); 787 if (can_bulk_split(musb, qh->type)) 788 musb_writew(epio, MUSB_TXMAXP, 789 packet_sz 790 | ((hw_ep->max_packet_sz_tx / 791 packet_sz) - 1) << 11); 792 else 793 musb_writew(epio, MUSB_TXMAXP, 794 packet_sz); 795 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); 796 } else { 797 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); 798 if (musb->is_multipoint) 799 musb_writeb(epio, MUSB_TYPE0, 800 qh->type_reg); 801 } 802 803 if (can_bulk_split(musb, qh->type)) 804 load_count = min((u32) hw_ep->max_packet_sz_tx, 805 len); 806 else 807 load_count = min((u32) packet_sz, len); 808 809 if (dma_channel && musb_tx_dma_program(dma_controller, 810 hw_ep, qh, urb, offset, len)) 811 load_count = 0; 812 813 if (load_count) { 814 /* PIO to load FIFO */ 815 qh->segsize = load_count; 816 musb_write_fifo(hw_ep, load_count, buf); 817 } 818 819 /* re-enable interrupt */ 820 musb_writew(mbase, MUSB_INTRTXE, int_txe); 821 822 /* IN/receive */ 823 } else { 824 u16 csr; 825 826 if (hw_ep->rx_reinit) { 827 musb_rx_reinit(musb, qh, hw_ep); 828 829 /* init new state: toggle and NYET, maybe DMA later */ 830 if (usb_gettoggle(urb->dev, qh->epnum, 0)) 831 csr = MUSB_RXCSR_H_WR_DATATOGGLE 832 | MUSB_RXCSR_H_DATATOGGLE; 833 else 834 csr = 0; 835 if (qh->type == USB_ENDPOINT_XFER_INT) 836 csr |= MUSB_RXCSR_DISNYET; 837 838 } else { 839 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 840 841 if (csr & (MUSB_RXCSR_RXPKTRDY 842 | MUSB_RXCSR_DMAENAB 843 | MUSB_RXCSR_H_REQPKT)) 844 ERR("broken !rx_reinit, ep%d csr %04x\n", 845 hw_ep->epnum, csr); 846 847 /* scrub any stale state, leaving toggle alone */ 848 csr &= MUSB_RXCSR_DISNYET; 849 } 850 851 /* kick things off */ 852 853 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { 854 /* candidate for DMA */ 855 if (dma_channel) { 856 dma_channel->actual_len = 0L; 857 qh->segsize = len; 858 859 /* AUTOREQ is in a DMA register */ 860 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 861 csr = musb_readw(hw_ep->regs, 862 MUSB_RXCSR); 863 864 /* unless caller treats short rx transfers as 865 * errors, we dare not queue multiple transfers. 866 */ 867 dma_ok = dma_controller->channel_program( 868 dma_channel, packet_sz, 869 !(urb->transfer_flags 870 & URB_SHORT_NOT_OK), 871 urb->transfer_dma + offset, 872 qh->segsize); 873 if (!dma_ok) { 874 dma_controller->channel_release( 875 dma_channel); 876 hw_ep->rx_channel = NULL; 877 dma_channel = NULL; 878 } else 879 csr |= MUSB_RXCSR_DMAENAB; 880 } 881 } 882 883 csr |= MUSB_RXCSR_H_REQPKT; 884 DBG(7, "RXCSR%d := %04x\n", epnum, csr); 885 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 886 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 887 } 888 } 889 890 891 /* 892 * Service the default endpoint (ep0) as host. 893 * Return true until it's time to start the status stage. 894 */ 895 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) 896 { 897 bool more = false; 898 u8 *fifo_dest = NULL; 899 u16 fifo_count = 0; 900 struct musb_hw_ep *hw_ep = musb->control_ep; 901 struct musb_qh *qh = hw_ep->in_qh; 902 struct usb_ctrlrequest *request; 903 904 switch (musb->ep0_stage) { 905 case MUSB_EP0_IN: 906 fifo_dest = urb->transfer_buffer + urb->actual_length; 907 fifo_count = min_t(size_t, len, urb->transfer_buffer_length - 908 urb->actual_length); 909 if (fifo_count < len) 910 urb->status = -EOVERFLOW; 911 912 musb_read_fifo(hw_ep, fifo_count, fifo_dest); 913 914 urb->actual_length += fifo_count; 915 if (len < qh->maxpacket) { 916 /* always terminate on short read; it's 917 * rarely reported as an error. 918 */ 919 } else if (urb->actual_length < 920 urb->transfer_buffer_length) 921 more = true; 922 break; 923 case MUSB_EP0_START: 924 request = (struct usb_ctrlrequest *) urb->setup_packet; 925 926 if (!request->wLength) { 927 DBG(4, "start no-DATA\n"); 928 break; 929 } else if (request->bRequestType & USB_DIR_IN) { 930 DBG(4, "start IN-DATA\n"); 931 musb->ep0_stage = MUSB_EP0_IN; 932 more = true; 933 break; 934 } else { 935 DBG(4, "start OUT-DATA\n"); 936 musb->ep0_stage = MUSB_EP0_OUT; 937 more = true; 938 } 939 /* FALLTHROUGH */ 940 case MUSB_EP0_OUT: 941 fifo_count = min_t(size_t, qh->maxpacket, 942 urb->transfer_buffer_length - 943 urb->actual_length); 944 if (fifo_count) { 945 fifo_dest = (u8 *) (urb->transfer_buffer 946 + urb->actual_length); 947 DBG(3, "Sending %d byte%s to ep0 fifo %p\n", 948 fifo_count, 949 (fifo_count == 1) ? "" : "s", 950 fifo_dest); 951 musb_write_fifo(hw_ep, fifo_count, fifo_dest); 952 953 urb->actual_length += fifo_count; 954 more = true; 955 } 956 break; 957 default: 958 ERR("bogus ep0 stage %d\n", musb->ep0_stage); 959 break; 960 } 961 962 return more; 963 } 964 965 /* 966 * Handle default endpoint interrupt as host. Only called in IRQ time 967 * from musb_interrupt(). 968 * 969 * called with controller irqlocked 970 */ 971 irqreturn_t musb_h_ep0_irq(struct musb *musb) 972 { 973 struct urb *urb; 974 u16 csr, len; 975 int status = 0; 976 void __iomem *mbase = musb->mregs; 977 struct musb_hw_ep *hw_ep = musb->control_ep; 978 void __iomem *epio = hw_ep->regs; 979 struct musb_qh *qh = hw_ep->in_qh; 980 bool complete = false; 981 irqreturn_t retval = IRQ_NONE; 982 983 /* ep0 only has one queue, "in" */ 984 urb = next_urb(qh); 985 986 musb_ep_select(mbase, 0); 987 csr = musb_readw(epio, MUSB_CSR0); 988 len = (csr & MUSB_CSR0_RXPKTRDY) 989 ? musb_readb(epio, MUSB_COUNT0) 990 : 0; 991 992 DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", 993 csr, qh, len, urb, musb->ep0_stage); 994 995 /* if we just did status stage, we are done */ 996 if (MUSB_EP0_STATUS == musb->ep0_stage) { 997 retval = IRQ_HANDLED; 998 complete = true; 999 } 1000 1001 /* prepare status */ 1002 if (csr & MUSB_CSR0_H_RXSTALL) { 1003 DBG(6, "STALLING ENDPOINT\n"); 1004 status = -EPIPE; 1005 1006 } else if (csr & MUSB_CSR0_H_ERROR) { 1007 DBG(2, "no response, csr0 %04x\n", csr); 1008 status = -EPROTO; 1009 1010 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { 1011 DBG(2, "control NAK timeout\n"); 1012 1013 /* NOTE: this code path would be a good place to PAUSE a 1014 * control transfer, if another one is queued, so that 1015 * ep0 is more likely to stay busy. That's already done 1016 * for bulk RX transfers. 1017 * 1018 * if (qh->ring.next != &musb->control), then 1019 * we have a candidate... NAKing is *NOT* an error 1020 */ 1021 musb_writew(epio, MUSB_CSR0, 0); 1022 retval = IRQ_HANDLED; 1023 } 1024 1025 if (status) { 1026 DBG(6, "aborting\n"); 1027 retval = IRQ_HANDLED; 1028 if (urb) 1029 urb->status = status; 1030 complete = true; 1031 1032 /* use the proper sequence to abort the transfer */ 1033 if (csr & MUSB_CSR0_H_REQPKT) { 1034 csr &= ~MUSB_CSR0_H_REQPKT; 1035 musb_writew(epio, MUSB_CSR0, csr); 1036 csr &= ~MUSB_CSR0_H_NAKTIMEOUT; 1037 musb_writew(epio, MUSB_CSR0, csr); 1038 } else { 1039 musb_h_ep0_flush_fifo(hw_ep); 1040 } 1041 1042 musb_writeb(epio, MUSB_NAKLIMIT0, 0); 1043 1044 /* clear it */ 1045 musb_writew(epio, MUSB_CSR0, 0); 1046 } 1047 1048 if (unlikely(!urb)) { 1049 /* stop endpoint since we have no place for its data, this 1050 * SHOULD NEVER HAPPEN! */ 1051 ERR("no URB for end 0\n"); 1052 1053 musb_h_ep0_flush_fifo(hw_ep); 1054 goto done; 1055 } 1056 1057 if (!complete) { 1058 /* call common logic and prepare response */ 1059 if (musb_h_ep0_continue(musb, len, urb)) { 1060 /* more packets required */ 1061 csr = (MUSB_EP0_IN == musb->ep0_stage) 1062 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; 1063 } else { 1064 /* data transfer complete; perform status phase */ 1065 if (usb_pipeout(urb->pipe) 1066 || !urb->transfer_buffer_length) 1067 csr = MUSB_CSR0_H_STATUSPKT 1068 | MUSB_CSR0_H_REQPKT; 1069 else 1070 csr = MUSB_CSR0_H_STATUSPKT 1071 | MUSB_CSR0_TXPKTRDY; 1072 1073 /* flag status stage */ 1074 musb->ep0_stage = MUSB_EP0_STATUS; 1075 1076 DBG(5, "ep0 STATUS, csr %04x\n", csr); 1077 1078 } 1079 musb_writew(epio, MUSB_CSR0, csr); 1080 retval = IRQ_HANDLED; 1081 } else 1082 musb->ep0_stage = MUSB_EP0_IDLE; 1083 1084 /* call completion handler if done */ 1085 if (complete) 1086 musb_advance_schedule(musb, urb, hw_ep, 1); 1087 done: 1088 return retval; 1089 } 1090 1091 1092 #ifdef CONFIG_USB_INVENTRA_DMA 1093 1094 /* Host side TX (OUT) using Mentor DMA works as follows: 1095 submit_urb -> 1096 - if queue was empty, Program Endpoint 1097 - ... which starts DMA to fifo in mode 1 or 0 1098 1099 DMA Isr (transfer complete) -> TxAvail() 1100 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens 1101 only in musb_cleanup_urb) 1102 - TxPktRdy has to be set in mode 0 or for 1103 short packets in mode 1. 1104 */ 1105 1106 #endif 1107 1108 /* Service a Tx-Available or dma completion irq for the endpoint */ 1109 void musb_host_tx(struct musb *musb, u8 epnum) 1110 { 1111 int pipe; 1112 bool done = false; 1113 u16 tx_csr; 1114 size_t length = 0; 1115 size_t offset = 0; 1116 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1117 void __iomem *epio = hw_ep->regs; 1118 struct musb_qh *qh = hw_ep->out_qh; 1119 struct urb *urb = next_urb(qh); 1120 u32 status = 0; 1121 void __iomem *mbase = musb->mregs; 1122 struct dma_channel *dma; 1123 bool transfer_pending = false; 1124 1125 musb_ep_select(mbase, epnum); 1126 tx_csr = musb_readw(epio, MUSB_TXCSR); 1127 1128 /* with CPPI, DMA sometimes triggers "extra" irqs */ 1129 if (!urb) { 1130 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1131 return; 1132 } 1133 1134 pipe = urb->pipe; 1135 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; 1136 DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, 1137 dma ? ", dma" : ""); 1138 1139 /* check for errors */ 1140 if (tx_csr & MUSB_TXCSR_H_RXSTALL) { 1141 /* dma was disabled, fifo flushed */ 1142 DBG(3, "TX end %d stall\n", epnum); 1143 1144 /* stall; record URB status */ 1145 status = -EPIPE; 1146 1147 } else if (tx_csr & MUSB_TXCSR_H_ERROR) { 1148 /* (NON-ISO) dma was disabled, fifo flushed */ 1149 DBG(3, "TX 3strikes on ep=%d\n", epnum); 1150 1151 status = -ETIMEDOUT; 1152 1153 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { 1154 DBG(6, "TX end=%d device not responding\n", epnum); 1155 1156 /* NOTE: this code path would be a good place to PAUSE a 1157 * transfer, if there's some other (nonperiodic) tx urb 1158 * that could use this fifo. (dma complicates it...) 1159 * That's already done for bulk RX transfers. 1160 * 1161 * if (bulk && qh->ring.next != &musb->out_bulk), then 1162 * we have a candidate... NAKing is *NOT* an error 1163 */ 1164 musb_ep_select(mbase, epnum); 1165 musb_writew(epio, MUSB_TXCSR, 1166 MUSB_TXCSR_H_WZC_BITS 1167 | MUSB_TXCSR_TXPKTRDY); 1168 return; 1169 } 1170 1171 if (status) { 1172 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1173 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1174 (void) musb->dma_controller->channel_abort(dma); 1175 } 1176 1177 /* do the proper sequence to abort the transfer in the 1178 * usb core; the dma engine should already be stopped. 1179 */ 1180 musb_h_tx_flush_fifo(hw_ep); 1181 tx_csr &= ~(MUSB_TXCSR_AUTOSET 1182 | MUSB_TXCSR_DMAENAB 1183 | MUSB_TXCSR_H_ERROR 1184 | MUSB_TXCSR_H_RXSTALL 1185 | MUSB_TXCSR_H_NAKTIMEOUT 1186 ); 1187 1188 musb_ep_select(mbase, epnum); 1189 musb_writew(epio, MUSB_TXCSR, tx_csr); 1190 /* REVISIT may need to clear FLUSHFIFO ... */ 1191 musb_writew(epio, MUSB_TXCSR, tx_csr); 1192 musb_writeb(epio, MUSB_TXINTERVAL, 0); 1193 1194 done = true; 1195 } 1196 1197 /* second cppi case */ 1198 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1199 DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1200 return; 1201 } 1202 1203 if (is_dma_capable() && dma && !status) { 1204 /* 1205 * DMA has completed. But if we're using DMA mode 1 (multi 1206 * packet DMA), we need a terminal TXPKTRDY interrupt before 1207 * we can consider this transfer completed, lest we trash 1208 * its last packet when writing the next URB's data. So we 1209 * switch back to mode 0 to get that interrupt; we'll come 1210 * back here once it happens. 1211 */ 1212 if (tx_csr & MUSB_TXCSR_DMAMODE) { 1213 /* 1214 * We shouldn't clear DMAMODE with DMAENAB set; so 1215 * clear them in a safe order. That should be OK 1216 * once TXPKTRDY has been set (and I've never seen 1217 * it being 0 at this moment -- DMA interrupt latency 1218 * is significant) but if it hasn't been then we have 1219 * no choice but to stop being polite and ignore the 1220 * programmer's guide... :-) 1221 * 1222 * Note that we must write TXCSR with TXPKTRDY cleared 1223 * in order not to re-trigger the packet send (this bit 1224 * can't be cleared by CPU), and there's another caveat: 1225 * TXPKTRDY may be set shortly and then cleared in the 1226 * double-buffered FIFO mode, so we do an extra TXCSR 1227 * read for debouncing... 1228 */ 1229 tx_csr &= musb_readw(epio, MUSB_TXCSR); 1230 if (tx_csr & MUSB_TXCSR_TXPKTRDY) { 1231 tx_csr &= ~(MUSB_TXCSR_DMAENAB | 1232 MUSB_TXCSR_TXPKTRDY); 1233 musb_writew(epio, MUSB_TXCSR, 1234 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1235 } 1236 tx_csr &= ~(MUSB_TXCSR_DMAMODE | 1237 MUSB_TXCSR_TXPKTRDY); 1238 musb_writew(epio, MUSB_TXCSR, 1239 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1240 1241 /* 1242 * There is no guarantee that we'll get an interrupt 1243 * after clearing DMAMODE as we might have done this 1244 * too late (after TXPKTRDY was cleared by controller). 1245 * Re-read TXCSR as we have spoiled its previous value. 1246 */ 1247 tx_csr = musb_readw(epio, MUSB_TXCSR); 1248 } 1249 1250 /* 1251 * We may get here from a DMA completion or TXPKTRDY interrupt. 1252 * In any case, we must check the FIFO status here and bail out 1253 * only if the FIFO still has data -- that should prevent the 1254 * "missed" TXPKTRDY interrupts and deal with double-buffered 1255 * FIFO mode too... 1256 */ 1257 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { 1258 DBG(2, "DMA complete but packet still in FIFO, " 1259 "CSR %04x\n", tx_csr); 1260 return; 1261 } 1262 } 1263 1264 if (!status || dma || usb_pipeisoc(pipe)) { 1265 if (dma) 1266 length = dma->actual_len; 1267 else 1268 length = qh->segsize; 1269 qh->offset += length; 1270 1271 if (usb_pipeisoc(pipe)) { 1272 struct usb_iso_packet_descriptor *d; 1273 1274 d = urb->iso_frame_desc + qh->iso_idx; 1275 d->actual_length = length; 1276 d->status = status; 1277 if (++qh->iso_idx >= urb->number_of_packets) { 1278 done = true; 1279 } else { 1280 d++; 1281 offset = d->offset; 1282 length = d->length; 1283 } 1284 } else if (dma && urb->transfer_buffer_length == qh->offset) { 1285 done = true; 1286 } else { 1287 /* see if we need to send more data, or ZLP */ 1288 if (qh->segsize < qh->maxpacket) 1289 done = true; 1290 else if (qh->offset == urb->transfer_buffer_length 1291 && !(urb->transfer_flags 1292 & URB_ZERO_PACKET)) 1293 done = true; 1294 if (!done) { 1295 offset = qh->offset; 1296 length = urb->transfer_buffer_length - offset; 1297 transfer_pending = true; 1298 } 1299 } 1300 } 1301 1302 /* urb->status != -EINPROGRESS means request has been faulted, 1303 * so we must abort this transfer after cleanup 1304 */ 1305 if (urb->status != -EINPROGRESS) { 1306 done = true; 1307 if (status == 0) 1308 status = urb->status; 1309 } 1310 1311 if (done) { 1312 /* set status */ 1313 urb->status = status; 1314 urb->actual_length = qh->offset; 1315 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); 1316 return; 1317 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) { 1318 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, 1319 offset, length)) { 1320 if (is_cppi_enabled() || tusb_dma_omap()) 1321 musb_h_tx_dma_start(hw_ep); 1322 return; 1323 } 1324 } else if (tx_csr & MUSB_TXCSR_DMAENAB) { 1325 DBG(1, "not complete, but DMA enabled?\n"); 1326 return; 1327 } 1328 1329 /* 1330 * PIO: start next packet in this URB. 1331 * 1332 * REVISIT: some docs say that when hw_ep->tx_double_buffered, 1333 * (and presumably, FIFO is not half-full) we should write *two* 1334 * packets before updating TXCSR; other docs disagree... 1335 */ 1336 if (length > qh->maxpacket) 1337 length = qh->maxpacket; 1338 /* Unmap the buffer so that CPU can use it */ 1339 unmap_urb_for_dma(musb_to_hcd(musb), urb); 1340 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); 1341 qh->segsize = length; 1342 1343 musb_ep_select(mbase, epnum); 1344 musb_writew(epio, MUSB_TXCSR, 1345 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); 1346 } 1347 1348 1349 #ifdef CONFIG_USB_INVENTRA_DMA 1350 1351 /* Host side RX (IN) using Mentor DMA works as follows: 1352 submit_urb -> 1353 - if queue was empty, ProgramEndpoint 1354 - first IN token is sent out (by setting ReqPkt) 1355 LinuxIsr -> RxReady() 1356 /\ => first packet is received 1357 | - Set in mode 0 (DmaEnab, ~ReqPkt) 1358 | -> DMA Isr (transfer complete) -> RxReady() 1359 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) 1360 | - if urb not complete, send next IN token (ReqPkt) 1361 | | else complete urb. 1362 | | 1363 --------------------------- 1364 * 1365 * Nuances of mode 1: 1366 * For short packets, no ack (+RxPktRdy) is sent automatically 1367 * (even if AutoClear is ON) 1368 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent 1369 * automatically => major problem, as collecting the next packet becomes 1370 * difficult. Hence mode 1 is not used. 1371 * 1372 * REVISIT 1373 * All we care about at this driver level is that 1374 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; 1375 * (b) termination conditions are: short RX, or buffer full; 1376 * (c) fault modes include 1377 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. 1378 * (and that endpoint's dma queue stops immediately) 1379 * - overflow (full, PLUS more bytes in the terminal packet) 1380 * 1381 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would 1382 * thus be a great candidate for using mode 1 ... for all but the 1383 * last packet of one URB's transfer. 1384 */ 1385 1386 #endif 1387 1388 /* Schedule next QH from musb->in_bulk and move the current qh to 1389 * the end; avoids starvation for other endpoints. 1390 */ 1391 static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep) 1392 { 1393 struct dma_channel *dma; 1394 struct urb *urb; 1395 void __iomem *mbase = musb->mregs; 1396 void __iomem *epio = ep->regs; 1397 struct musb_qh *cur_qh, *next_qh; 1398 u16 rx_csr; 1399 1400 musb_ep_select(mbase, ep->epnum); 1401 dma = is_dma_capable() ? ep->rx_channel : NULL; 1402 1403 /* clear nak timeout bit */ 1404 rx_csr = musb_readw(epio, MUSB_RXCSR); 1405 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 1406 rx_csr &= ~MUSB_RXCSR_DATAERROR; 1407 musb_writew(epio, MUSB_RXCSR, rx_csr); 1408 1409 cur_qh = first_qh(&musb->in_bulk); 1410 if (cur_qh) { 1411 urb = next_urb(cur_qh); 1412 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1413 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1414 musb->dma_controller->channel_abort(dma); 1415 urb->actual_length += dma->actual_len; 1416 dma->actual_len = 0L; 1417 } 1418 musb_save_toggle(cur_qh, 1, urb); 1419 1420 /* move cur_qh to end of queue */ 1421 list_move_tail(&cur_qh->ring, &musb->in_bulk); 1422 1423 /* get the next qh from musb->in_bulk */ 1424 next_qh = first_qh(&musb->in_bulk); 1425 1426 /* set rx_reinit and schedule the next qh */ 1427 ep->rx_reinit = 1; 1428 musb_start_urb(musb, 1, next_qh); 1429 } 1430 } 1431 1432 /* 1433 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, 1434 * and high-bandwidth IN transfer cases. 1435 */ 1436 void musb_host_rx(struct musb *musb, u8 epnum) 1437 { 1438 struct urb *urb; 1439 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1440 void __iomem *epio = hw_ep->regs; 1441 struct musb_qh *qh = hw_ep->in_qh; 1442 size_t xfer_len; 1443 void __iomem *mbase = musb->mregs; 1444 int pipe; 1445 u16 rx_csr, val; 1446 bool iso_err = false; 1447 bool done = false; 1448 u32 status; 1449 struct dma_channel *dma; 1450 1451 musb_ep_select(mbase, epnum); 1452 1453 urb = next_urb(qh); 1454 dma = is_dma_capable() ? hw_ep->rx_channel : NULL; 1455 status = 0; 1456 xfer_len = 0; 1457 1458 rx_csr = musb_readw(epio, MUSB_RXCSR); 1459 val = rx_csr; 1460 1461 if (unlikely(!urb)) { 1462 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least 1463 * usbtest #11 (unlinks) triggers it regularly, sometimes 1464 * with fifo full. (Only with DMA??) 1465 */ 1466 DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, 1467 musb_readw(epio, MUSB_RXCOUNT)); 1468 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1469 return; 1470 } 1471 1472 pipe = urb->pipe; 1473 1474 DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", 1475 epnum, rx_csr, urb->actual_length, 1476 dma ? dma->actual_len : 0); 1477 1478 /* check for errors, concurrent stall & unlink is not really 1479 * handled yet! */ 1480 if (rx_csr & MUSB_RXCSR_H_RXSTALL) { 1481 DBG(3, "RX end %d STALL\n", epnum); 1482 1483 /* stall; record URB status */ 1484 status = -EPIPE; 1485 1486 } else if (rx_csr & MUSB_RXCSR_H_ERROR) { 1487 DBG(3, "end %d RX proto error\n", epnum); 1488 1489 status = -EPROTO; 1490 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1491 1492 } else if (rx_csr & MUSB_RXCSR_DATAERROR) { 1493 1494 if (USB_ENDPOINT_XFER_ISOC != qh->type) { 1495 DBG(6, "RX end %d NAK timeout\n", epnum); 1496 1497 /* NOTE: NAKing is *NOT* an error, so we want to 1498 * continue. Except ... if there's a request for 1499 * another QH, use that instead of starving it. 1500 * 1501 * Devices like Ethernet and serial adapters keep 1502 * reads posted at all times, which will starve 1503 * other devices without this logic. 1504 */ 1505 if (usb_pipebulk(urb->pipe) 1506 && qh->mux == 1 1507 && !list_is_singular(&musb->in_bulk)) { 1508 musb_bulk_rx_nak_timeout(musb, hw_ep); 1509 return; 1510 } 1511 musb_ep_select(mbase, epnum); 1512 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 1513 rx_csr &= ~MUSB_RXCSR_DATAERROR; 1514 musb_writew(epio, MUSB_RXCSR, rx_csr); 1515 1516 goto finish; 1517 } else { 1518 DBG(4, "RX end %d ISO data error\n", epnum); 1519 /* packet error reported later */ 1520 iso_err = true; 1521 } 1522 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) { 1523 DBG(3, "end %d high bandwidth incomplete ISO packet RX\n", 1524 epnum); 1525 status = -EPROTO; 1526 } 1527 1528 /* faults abort the transfer */ 1529 if (status) { 1530 /* clean up dma and collect transfer count */ 1531 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1532 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1533 (void) musb->dma_controller->channel_abort(dma); 1534 xfer_len = dma->actual_len; 1535 } 1536 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1537 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1538 done = true; 1539 goto finish; 1540 } 1541 1542 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { 1543 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ 1544 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); 1545 goto finish; 1546 } 1547 1548 /* thorough shutdown for now ... given more precise fault handling 1549 * and better queueing support, we might keep a DMA pipeline going 1550 * while processing this irq for earlier completions. 1551 */ 1552 1553 /* FIXME this is _way_ too much in-line logic for Mentor DMA */ 1554 1555 #ifndef CONFIG_USB_INVENTRA_DMA 1556 if (rx_csr & MUSB_RXCSR_H_REQPKT) { 1557 /* REVISIT this happened for a while on some short reads... 1558 * the cleanup still needs investigation... looks bad... 1559 * and also duplicates dma cleanup code above ... plus, 1560 * shouldn't this be the "half full" double buffer case? 1561 */ 1562 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1563 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1564 (void) musb->dma_controller->channel_abort(dma); 1565 xfer_len = dma->actual_len; 1566 done = true; 1567 } 1568 1569 DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, 1570 xfer_len, dma ? ", dma" : ""); 1571 rx_csr &= ~MUSB_RXCSR_H_REQPKT; 1572 1573 musb_ep_select(mbase, epnum); 1574 musb_writew(epio, MUSB_RXCSR, 1575 MUSB_RXCSR_H_WZC_BITS | rx_csr); 1576 } 1577 #endif 1578 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { 1579 xfer_len = dma->actual_len; 1580 1581 val &= ~(MUSB_RXCSR_DMAENAB 1582 | MUSB_RXCSR_H_AUTOREQ 1583 | MUSB_RXCSR_AUTOCLEAR 1584 | MUSB_RXCSR_RXPKTRDY); 1585 musb_writew(hw_ep->regs, MUSB_RXCSR, val); 1586 1587 #ifdef CONFIG_USB_INVENTRA_DMA 1588 if (usb_pipeisoc(pipe)) { 1589 struct usb_iso_packet_descriptor *d; 1590 1591 d = urb->iso_frame_desc + qh->iso_idx; 1592 d->actual_length = xfer_len; 1593 1594 /* even if there was an error, we did the dma 1595 * for iso_frame_desc->length 1596 */ 1597 if (d->status != EILSEQ && d->status != -EOVERFLOW) 1598 d->status = 0; 1599 1600 if (++qh->iso_idx >= urb->number_of_packets) 1601 done = true; 1602 else 1603 done = false; 1604 1605 } else { 1606 /* done if urb buffer is full or short packet is recd */ 1607 done = (urb->actual_length + xfer_len >= 1608 urb->transfer_buffer_length 1609 || dma->actual_len < qh->maxpacket); 1610 } 1611 1612 /* send IN token for next packet, without AUTOREQ */ 1613 if (!done) { 1614 val |= MUSB_RXCSR_H_REQPKT; 1615 musb_writew(epio, MUSB_RXCSR, 1616 MUSB_RXCSR_H_WZC_BITS | val); 1617 } 1618 1619 DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, 1620 done ? "off" : "reset", 1621 musb_readw(epio, MUSB_RXCSR), 1622 musb_readw(epio, MUSB_RXCOUNT)); 1623 #else 1624 done = true; 1625 #endif 1626 } else if (urb->status == -EINPROGRESS) { 1627 /* if no errors, be sure a packet is ready for unloading */ 1628 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { 1629 status = -EPROTO; 1630 ERR("Rx interrupt with no errors or packet!\n"); 1631 1632 /* FIXME this is another "SHOULD NEVER HAPPEN" */ 1633 1634 /* SCRUB (RX) */ 1635 /* do the proper sequence to abort the transfer */ 1636 musb_ep_select(mbase, epnum); 1637 val &= ~MUSB_RXCSR_H_REQPKT; 1638 musb_writew(epio, MUSB_RXCSR, val); 1639 goto finish; 1640 } 1641 1642 /* we are expecting IN packets */ 1643 #ifdef CONFIG_USB_INVENTRA_DMA 1644 if (dma) { 1645 struct dma_controller *c; 1646 u16 rx_count; 1647 int ret, length; 1648 dma_addr_t buf; 1649 1650 rx_count = musb_readw(epio, MUSB_RXCOUNT); 1651 1652 DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n", 1653 epnum, rx_count, 1654 urb->transfer_dma 1655 + urb->actual_length, 1656 qh->offset, 1657 urb->transfer_buffer_length); 1658 1659 c = musb->dma_controller; 1660 1661 if (usb_pipeisoc(pipe)) { 1662 int d_status = 0; 1663 struct usb_iso_packet_descriptor *d; 1664 1665 d = urb->iso_frame_desc + qh->iso_idx; 1666 1667 if (iso_err) { 1668 d_status = -EILSEQ; 1669 urb->error_count++; 1670 } 1671 if (rx_count > d->length) { 1672 if (d_status == 0) { 1673 d_status = -EOVERFLOW; 1674 urb->error_count++; 1675 } 1676 DBG(2, "** OVERFLOW %d into %d\n",\ 1677 rx_count, d->length); 1678 1679 length = d->length; 1680 } else 1681 length = rx_count; 1682 d->status = d_status; 1683 buf = urb->transfer_dma + d->offset; 1684 } else { 1685 length = rx_count; 1686 buf = urb->transfer_dma + 1687 urb->actual_length; 1688 } 1689 1690 dma->desired_mode = 0; 1691 #ifdef USE_MODE1 1692 /* because of the issue below, mode 1 will 1693 * only rarely behave with correct semantics. 1694 */ 1695 if ((urb->transfer_flags & 1696 URB_SHORT_NOT_OK) 1697 && (urb->transfer_buffer_length - 1698 urb->actual_length) 1699 > qh->maxpacket) 1700 dma->desired_mode = 1; 1701 if (rx_count < hw_ep->max_packet_sz_rx) { 1702 length = rx_count; 1703 dma->desired_mode = 0; 1704 } else { 1705 length = urb->transfer_buffer_length; 1706 } 1707 #endif 1708 1709 /* Disadvantage of using mode 1: 1710 * It's basically usable only for mass storage class; essentially all 1711 * other protocols also terminate transfers on short packets. 1712 * 1713 * Details: 1714 * An extra IN token is sent at the end of the transfer (due to AUTOREQ) 1715 * If you try to use mode 1 for (transfer_buffer_length - 512), and try 1716 * to use the extra IN token to grab the last packet using mode 0, then 1717 * the problem is that you cannot be sure when the device will send the 1718 * last packet and RxPktRdy set. Sometimes the packet is recd too soon 1719 * such that it gets lost when RxCSR is re-set at the end of the mode 1 1720 * transfer, while sometimes it is recd just a little late so that if you 1721 * try to configure for mode 0 soon after the mode 1 transfer is 1722 * completed, you will find rxcount 0. Okay, so you might think why not 1723 * wait for an interrupt when the pkt is recd. Well, you won't get any! 1724 */ 1725 1726 val = musb_readw(epio, MUSB_RXCSR); 1727 val &= ~MUSB_RXCSR_H_REQPKT; 1728 1729 if (dma->desired_mode == 0) 1730 val &= ~MUSB_RXCSR_H_AUTOREQ; 1731 else 1732 val |= MUSB_RXCSR_H_AUTOREQ; 1733 val |= MUSB_RXCSR_DMAENAB; 1734 1735 /* autoclear shouldn't be set in high bandwidth */ 1736 if (qh->hb_mult == 1) 1737 val |= MUSB_RXCSR_AUTOCLEAR; 1738 1739 musb_writew(epio, MUSB_RXCSR, 1740 MUSB_RXCSR_H_WZC_BITS | val); 1741 1742 /* REVISIT if when actual_length != 0, 1743 * transfer_buffer_length needs to be 1744 * adjusted first... 1745 */ 1746 ret = c->channel_program( 1747 dma, qh->maxpacket, 1748 dma->desired_mode, buf, length); 1749 1750 if (!ret) { 1751 c->channel_release(dma); 1752 hw_ep->rx_channel = NULL; 1753 dma = NULL; 1754 /* REVISIT reset CSR */ 1755 } 1756 } 1757 #endif /* Mentor DMA */ 1758 1759 if (!dma) { 1760 /* Unmap the buffer so that CPU can use it */ 1761 unmap_urb_for_dma(musb_to_hcd(musb), urb); 1762 done = musb_host_packet_rx(musb, urb, 1763 epnum, iso_err); 1764 DBG(6, "read %spacket\n", done ? "last " : ""); 1765 } 1766 } 1767 1768 finish: 1769 urb->actual_length += xfer_len; 1770 qh->offset += xfer_len; 1771 if (done) { 1772 if (urb->status == -EINPROGRESS) 1773 urb->status = status; 1774 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); 1775 } 1776 } 1777 1778 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH. 1779 * the software schedule associates multiple such nodes with a given 1780 * host side hardware endpoint + direction; scheduling may activate 1781 * that hardware endpoint. 1782 */ 1783 static int musb_schedule( 1784 struct musb *musb, 1785 struct musb_qh *qh, 1786 int is_in) 1787 { 1788 int idle; 1789 int best_diff; 1790 int best_end, epnum; 1791 struct musb_hw_ep *hw_ep = NULL; 1792 struct list_head *head = NULL; 1793 u8 toggle; 1794 u8 txtype; 1795 struct urb *urb = next_urb(qh); 1796 1797 /* use fixed hardware for control and bulk */ 1798 if (qh->type == USB_ENDPOINT_XFER_CONTROL) { 1799 head = &musb->control; 1800 hw_ep = musb->control_ep; 1801 goto success; 1802 } 1803 1804 /* else, periodic transfers get muxed to other endpoints */ 1805 1806 /* 1807 * We know this qh hasn't been scheduled, so all we need to do 1808 * is choose which hardware endpoint to put it on ... 1809 * 1810 * REVISIT what we really want here is a regular schedule tree 1811 * like e.g. OHCI uses. 1812 */ 1813 best_diff = 4096; 1814 best_end = -1; 1815 1816 for (epnum = 1, hw_ep = musb->endpoints + 1; 1817 epnum < musb->nr_endpoints; 1818 epnum++, hw_ep++) { 1819 int diff; 1820 1821 if (musb_ep_get_qh(hw_ep, is_in) != NULL) 1822 continue; 1823 1824 if (hw_ep == musb->bulk_ep) 1825 continue; 1826 1827 if (is_in) 1828 diff = hw_ep->max_packet_sz_rx; 1829 else 1830 diff = hw_ep->max_packet_sz_tx; 1831 diff -= (qh->maxpacket * qh->hb_mult); 1832 1833 if (diff >= 0 && best_diff > diff) { 1834 1835 /* 1836 * Mentor controller has a bug in that if we schedule 1837 * a BULK Tx transfer on an endpoint that had earlier 1838 * handled ISOC then the BULK transfer has to start on 1839 * a zero toggle. If the BULK transfer starts on a 1 1840 * toggle then this transfer will fail as the mentor 1841 * controller starts the Bulk transfer on a 0 toggle 1842 * irrespective of the programming of the toggle bits 1843 * in the TXCSR register. Check for this condition 1844 * while allocating the EP for a Tx Bulk transfer. If 1845 * so skip this EP. 1846 */ 1847 hw_ep = musb->endpoints + epnum; 1848 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in); 1849 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) 1850 >> 4) & 0x3; 1851 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) && 1852 toggle && (txtype == USB_ENDPOINT_XFER_ISOC)) 1853 continue; 1854 1855 best_diff = diff; 1856 best_end = epnum; 1857 } 1858 } 1859 /* use bulk reserved ep1 if no other ep is free */ 1860 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { 1861 hw_ep = musb->bulk_ep; 1862 if (is_in) 1863 head = &musb->in_bulk; 1864 else 1865 head = &musb->out_bulk; 1866 1867 /* Enable bulk RX NAK timeout scheme when bulk requests are 1868 * multiplexed. This scheme doen't work in high speed to full 1869 * speed scenario as NAK interrupts are not coming from a 1870 * full speed device connected to a high speed device. 1871 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and 1872 * 4 (8 frame or 8ms) for FS device. 1873 */ 1874 if (is_in && qh->dev) 1875 qh->intv_reg = 1876 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; 1877 goto success; 1878 } else if (best_end < 0) { 1879 return -ENOSPC; 1880 } 1881 1882 idle = 1; 1883 qh->mux = 0; 1884 hw_ep = musb->endpoints + best_end; 1885 DBG(4, "qh %p periodic slot %d\n", qh, best_end); 1886 success: 1887 if (head) { 1888 idle = list_empty(head); 1889 list_add_tail(&qh->ring, head); 1890 qh->mux = 1; 1891 } 1892 qh->hw_ep = hw_ep; 1893 qh->hep->hcpriv = qh; 1894 if (idle) 1895 musb_start_urb(musb, is_in, qh); 1896 return 0; 1897 } 1898 1899 static int musb_urb_enqueue( 1900 struct usb_hcd *hcd, 1901 struct urb *urb, 1902 gfp_t mem_flags) 1903 { 1904 unsigned long flags; 1905 struct musb *musb = hcd_to_musb(hcd); 1906 struct usb_host_endpoint *hep = urb->ep; 1907 struct musb_qh *qh; 1908 struct usb_endpoint_descriptor *epd = &hep->desc; 1909 int ret; 1910 unsigned type_reg; 1911 unsigned interval; 1912 1913 /* host role must be active */ 1914 if (!is_host_active(musb) || !musb->is_active) 1915 return -ENODEV; 1916 1917 spin_lock_irqsave(&musb->lock, flags); 1918 ret = usb_hcd_link_urb_to_ep(hcd, urb); 1919 qh = ret ? NULL : hep->hcpriv; 1920 if (qh) 1921 urb->hcpriv = qh; 1922 spin_unlock_irqrestore(&musb->lock, flags); 1923 1924 /* DMA mapping was already done, if needed, and this urb is on 1925 * hep->urb_list now ... so we're done, unless hep wasn't yet 1926 * scheduled onto a live qh. 1927 * 1928 * REVISIT best to keep hep->hcpriv valid until the endpoint gets 1929 * disabled, testing for empty qh->ring and avoiding qh setup costs 1930 * except for the first urb queued after a config change. 1931 */ 1932 if (qh || ret) 1933 return ret; 1934 1935 /* Allocate and initialize qh, minimizing the work done each time 1936 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. 1937 * 1938 * REVISIT consider a dedicated qh kmem_cache, so it's harder 1939 * for bugs in other kernel code to break this driver... 1940 */ 1941 qh = kzalloc(sizeof *qh, mem_flags); 1942 if (!qh) { 1943 spin_lock_irqsave(&musb->lock, flags); 1944 usb_hcd_unlink_urb_from_ep(hcd, urb); 1945 spin_unlock_irqrestore(&musb->lock, flags); 1946 return -ENOMEM; 1947 } 1948 1949 qh->hep = hep; 1950 qh->dev = urb->dev; 1951 INIT_LIST_HEAD(&qh->ring); 1952 qh->is_ready = 1; 1953 1954 qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize); 1955 qh->type = usb_endpoint_type(epd); 1956 1957 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier. 1958 * Some musb cores don't support high bandwidth ISO transfers; and 1959 * we don't (yet!) support high bandwidth interrupt transfers. 1960 */ 1961 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03); 1962 if (qh->hb_mult > 1) { 1963 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC); 1964 1965 if (ok) 1966 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx) 1967 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx); 1968 if (!ok) { 1969 ret = -EMSGSIZE; 1970 goto done; 1971 } 1972 qh->maxpacket &= 0x7ff; 1973 } 1974 1975 qh->epnum = usb_endpoint_num(epd); 1976 1977 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ 1978 qh->addr_reg = (u8) usb_pipedevice(urb->pipe); 1979 1980 /* precompute rxtype/txtype/type0 register */ 1981 type_reg = (qh->type << 4) | qh->epnum; 1982 switch (urb->dev->speed) { 1983 case USB_SPEED_LOW: 1984 type_reg |= 0xc0; 1985 break; 1986 case USB_SPEED_FULL: 1987 type_reg |= 0x80; 1988 break; 1989 default: 1990 type_reg |= 0x40; 1991 } 1992 qh->type_reg = type_reg; 1993 1994 /* Precompute RXINTERVAL/TXINTERVAL register */ 1995 switch (qh->type) { 1996 case USB_ENDPOINT_XFER_INT: 1997 /* 1998 * Full/low speeds use the linear encoding, 1999 * high speed uses the logarithmic encoding. 2000 */ 2001 if (urb->dev->speed <= USB_SPEED_FULL) { 2002 interval = max_t(u8, epd->bInterval, 1); 2003 break; 2004 } 2005 /* FALLTHROUGH */ 2006 case USB_ENDPOINT_XFER_ISOC: 2007 /* ISO always uses logarithmic encoding */ 2008 interval = min_t(u8, epd->bInterval, 16); 2009 break; 2010 default: 2011 /* REVISIT we actually want to use NAK limits, hinting to the 2012 * transfer scheduling logic to try some other qh, e.g. try 2013 * for 2 msec first: 2014 * 2015 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; 2016 * 2017 * The downside of disabling this is that transfer scheduling 2018 * gets VERY unfair for nonperiodic transfers; a misbehaving 2019 * peripheral could make that hurt. That's perfectly normal 2020 * for reads from network or serial adapters ... so we have 2021 * partial NAKlimit support for bulk RX. 2022 * 2023 * The upside of disabling it is simpler transfer scheduling. 2024 */ 2025 interval = 0; 2026 } 2027 qh->intv_reg = interval; 2028 2029 /* precompute addressing for external hub/tt ports */ 2030 if (musb->is_multipoint) { 2031 struct usb_device *parent = urb->dev->parent; 2032 2033 if (parent != hcd->self.root_hub) { 2034 qh->h_addr_reg = (u8) parent->devnum; 2035 2036 /* set up tt info if needed */ 2037 if (urb->dev->tt) { 2038 qh->h_port_reg = (u8) urb->dev->ttport; 2039 if (urb->dev->tt->hub) 2040 qh->h_addr_reg = 2041 (u8) urb->dev->tt->hub->devnum; 2042 if (urb->dev->tt->multi) 2043 qh->h_addr_reg |= 0x80; 2044 } 2045 } 2046 } 2047 2048 /* invariant: hep->hcpriv is null OR the qh that's already scheduled. 2049 * until we get real dma queues (with an entry for each urb/buffer), 2050 * we only have work to do in the former case. 2051 */ 2052 spin_lock_irqsave(&musb->lock, flags); 2053 if (hep->hcpriv) { 2054 /* some concurrent activity submitted another urb to hep... 2055 * odd, rare, error prone, but legal. 2056 */ 2057 kfree(qh); 2058 qh = NULL; 2059 ret = 0; 2060 } else 2061 ret = musb_schedule(musb, qh, 2062 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); 2063 2064 if (ret == 0) { 2065 urb->hcpriv = qh; 2066 /* FIXME set urb->start_frame for iso/intr, it's tested in 2067 * musb_start_urb(), but otherwise only konicawc cares ... 2068 */ 2069 } 2070 spin_unlock_irqrestore(&musb->lock, flags); 2071 2072 done: 2073 if (ret != 0) { 2074 spin_lock_irqsave(&musb->lock, flags); 2075 usb_hcd_unlink_urb_from_ep(hcd, urb); 2076 spin_unlock_irqrestore(&musb->lock, flags); 2077 kfree(qh); 2078 } 2079 return ret; 2080 } 2081 2082 2083 /* 2084 * abort a transfer that's at the head of a hardware queue. 2085 * called with controller locked, irqs blocked 2086 * that hardware queue advances to the next transfer, unless prevented 2087 */ 2088 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) 2089 { 2090 struct musb_hw_ep *ep = qh->hw_ep; 2091 void __iomem *epio = ep->regs; 2092 unsigned hw_end = ep->epnum; 2093 void __iomem *regs = ep->musb->mregs; 2094 int is_in = usb_pipein(urb->pipe); 2095 int status = 0; 2096 u16 csr; 2097 2098 musb_ep_select(regs, hw_end); 2099 2100 if (is_dma_capable()) { 2101 struct dma_channel *dma; 2102 2103 dma = is_in ? ep->rx_channel : ep->tx_channel; 2104 if (dma) { 2105 status = ep->musb->dma_controller->channel_abort(dma); 2106 DBG(status ? 1 : 3, 2107 "abort %cX%d DMA for urb %p --> %d\n", 2108 is_in ? 'R' : 'T', ep->epnum, 2109 urb, status); 2110 urb->actual_length += dma->actual_len; 2111 } 2112 } 2113 2114 /* turn off DMA requests, discard state, stop polling ... */ 2115 if (is_in) { 2116 /* giveback saves bulk toggle */ 2117 csr = musb_h_flush_rxfifo(ep, 0); 2118 2119 /* REVISIT we still get an irq; should likely clear the 2120 * endpoint's irq status here to avoid bogus irqs. 2121 * clearing that status is platform-specific... 2122 */ 2123 } else if (ep->epnum) { 2124 musb_h_tx_flush_fifo(ep); 2125 csr = musb_readw(epio, MUSB_TXCSR); 2126 csr &= ~(MUSB_TXCSR_AUTOSET 2127 | MUSB_TXCSR_DMAENAB 2128 | MUSB_TXCSR_H_RXSTALL 2129 | MUSB_TXCSR_H_NAKTIMEOUT 2130 | MUSB_TXCSR_H_ERROR 2131 | MUSB_TXCSR_TXPKTRDY); 2132 musb_writew(epio, MUSB_TXCSR, csr); 2133 /* REVISIT may need to clear FLUSHFIFO ... */ 2134 musb_writew(epio, MUSB_TXCSR, csr); 2135 /* flush cpu writebuffer */ 2136 csr = musb_readw(epio, MUSB_TXCSR); 2137 } else { 2138 musb_h_ep0_flush_fifo(ep); 2139 } 2140 if (status == 0) 2141 musb_advance_schedule(ep->musb, urb, ep, is_in); 2142 return status; 2143 } 2144 2145 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 2146 { 2147 struct musb *musb = hcd_to_musb(hcd); 2148 struct musb_qh *qh; 2149 unsigned long flags; 2150 int is_in = usb_pipein(urb->pipe); 2151 int ret; 2152 2153 DBG(4, "urb=%p, dev%d ep%d%s\n", urb, 2154 usb_pipedevice(urb->pipe), 2155 usb_pipeendpoint(urb->pipe), 2156 is_in ? "in" : "out"); 2157 2158 spin_lock_irqsave(&musb->lock, flags); 2159 ret = usb_hcd_check_unlink_urb(hcd, urb, status); 2160 if (ret) 2161 goto done; 2162 2163 qh = urb->hcpriv; 2164 if (!qh) 2165 goto done; 2166 2167 /* 2168 * Any URB not actively programmed into endpoint hardware can be 2169 * immediately given back; that's any URB not at the head of an 2170 * endpoint queue, unless someday we get real DMA queues. And even 2171 * if it's at the head, it might not be known to the hardware... 2172 * 2173 * Otherwise abort current transfer, pending DMA, etc.; urb->status 2174 * has already been updated. This is a synchronous abort; it'd be 2175 * OK to hold off until after some IRQ, though. 2176 * 2177 * NOTE: qh is invalid unless !list_empty(&hep->urb_list) 2178 */ 2179 if (!qh->is_ready 2180 || urb->urb_list.prev != &qh->hep->urb_list 2181 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) { 2182 int ready = qh->is_ready; 2183 2184 qh->is_ready = 0; 2185 musb_giveback(musb, urb, 0); 2186 qh->is_ready = ready; 2187 2188 /* If nothing else (usually musb_giveback) is using it 2189 * and its URB list has emptied, recycle this qh. 2190 */ 2191 if (ready && list_empty(&qh->hep->urb_list)) { 2192 qh->hep->hcpriv = NULL; 2193 list_del(&qh->ring); 2194 kfree(qh); 2195 } 2196 } else 2197 ret = musb_cleanup_urb(urb, qh); 2198 done: 2199 spin_unlock_irqrestore(&musb->lock, flags); 2200 return ret; 2201 } 2202 2203 /* disable an endpoint */ 2204 static void 2205 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) 2206 { 2207 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN; 2208 unsigned long flags; 2209 struct musb *musb = hcd_to_musb(hcd); 2210 struct musb_qh *qh; 2211 struct urb *urb; 2212 2213 spin_lock_irqsave(&musb->lock, flags); 2214 2215 qh = hep->hcpriv; 2216 if (qh == NULL) 2217 goto exit; 2218 2219 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ 2220 2221 /* Kick the first URB off the hardware, if needed */ 2222 qh->is_ready = 0; 2223 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) { 2224 urb = next_urb(qh); 2225 2226 /* make software (then hardware) stop ASAP */ 2227 if (!urb->unlinked) 2228 urb->status = -ESHUTDOWN; 2229 2230 /* cleanup */ 2231 musb_cleanup_urb(urb, qh); 2232 2233 /* Then nuke all the others ... and advance the 2234 * queue on hw_ep (e.g. bulk ring) when we're done. 2235 */ 2236 while (!list_empty(&hep->urb_list)) { 2237 urb = next_urb(qh); 2238 urb->status = -ESHUTDOWN; 2239 musb_advance_schedule(musb, urb, qh->hw_ep, is_in); 2240 } 2241 } else { 2242 /* Just empty the queue; the hardware is busy with 2243 * other transfers, and since !qh->is_ready nothing 2244 * will activate any of these as it advances. 2245 */ 2246 while (!list_empty(&hep->urb_list)) 2247 musb_giveback(musb, next_urb(qh), -ESHUTDOWN); 2248 2249 hep->hcpriv = NULL; 2250 list_del(&qh->ring); 2251 kfree(qh); 2252 } 2253 exit: 2254 spin_unlock_irqrestore(&musb->lock, flags); 2255 } 2256 2257 static int musb_h_get_frame_number(struct usb_hcd *hcd) 2258 { 2259 struct musb *musb = hcd_to_musb(hcd); 2260 2261 return musb_readw(musb->mregs, MUSB_FRAME); 2262 } 2263 2264 static int musb_h_start(struct usb_hcd *hcd) 2265 { 2266 struct musb *musb = hcd_to_musb(hcd); 2267 2268 /* NOTE: musb_start() is called when the hub driver turns 2269 * on port power, or when (OTG) peripheral starts. 2270 */ 2271 hcd->state = HC_STATE_RUNNING; 2272 musb->port1_status = 0; 2273 return 0; 2274 } 2275 2276 static void musb_h_stop(struct usb_hcd *hcd) 2277 { 2278 musb_stop(hcd_to_musb(hcd)); 2279 hcd->state = HC_STATE_HALT; 2280 } 2281 2282 static int musb_bus_suspend(struct usb_hcd *hcd) 2283 { 2284 struct musb *musb = hcd_to_musb(hcd); 2285 u8 devctl; 2286 2287 if (!is_host_active(musb)) 2288 return 0; 2289 2290 switch (musb->xceiv->state) { 2291 case OTG_STATE_A_SUSPEND: 2292 return 0; 2293 case OTG_STATE_A_WAIT_VRISE: 2294 /* ID could be grounded even if there's no device 2295 * on the other end of the cable. NOTE that the 2296 * A_WAIT_VRISE timers are messy with MUSB... 2297 */ 2298 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2299 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 2300 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 2301 break; 2302 default: 2303 break; 2304 } 2305 2306 if (musb->is_active) { 2307 WARNING("trying to suspend as %s while active\n", 2308 otg_state_string(musb)); 2309 return -EBUSY; 2310 } else 2311 return 0; 2312 } 2313 2314 static int musb_bus_resume(struct usb_hcd *hcd) 2315 { 2316 /* resuming child port does the work */ 2317 return 0; 2318 } 2319 2320 const struct hc_driver musb_hc_driver = { 2321 .description = "musb-hcd", 2322 .product_desc = "MUSB HDRC host driver", 2323 .hcd_priv_size = sizeof(struct musb), 2324 .flags = HCD_USB2 | HCD_MEMORY, 2325 2326 /* not using irq handler or reset hooks from usbcore, since 2327 * those must be shared with peripheral code for OTG configs 2328 */ 2329 2330 .start = musb_h_start, 2331 .stop = musb_h_stop, 2332 2333 .get_frame_number = musb_h_get_frame_number, 2334 2335 .urb_enqueue = musb_urb_enqueue, 2336 .urb_dequeue = musb_urb_dequeue, 2337 .endpoint_disable = musb_h_disable, 2338 2339 .hub_status_data = musb_hub_status_data, 2340 .hub_control = musb_hub_control, 2341 .bus_suspend = musb_bus_suspend, 2342 .bus_resume = musb_bus_resume, 2343 /* .start_port_reset = NULL, */ 2344 /* .hub_irq_enable = NULL, */ 2345 }; 2346