1 /* 2 * MUSB OTG driver host support 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <linux/module.h> 37 #include <linux/kernel.h> 38 #include <linux/delay.h> 39 #include <linux/sched.h> 40 #include <linux/slab.h> 41 #include <linux/errno.h> 42 #include <linux/init.h> 43 #include <linux/list.h> 44 #include <linux/dma-mapping.h> 45 46 #include "musb_core.h" 47 #include "musb_host.h" 48 49 /* MUSB HOST status 22-mar-2006 50 * 51 * - There's still lots of partial code duplication for fault paths, so 52 * they aren't handled as consistently as they need to be. 53 * 54 * - PIO mostly behaved when last tested. 55 * + including ep0, with all usbtest cases 9, 10 56 * + usbtest 14 (ep0out) doesn't seem to run at all 57 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest 58 * configurations, but otherwise double buffering passes basic tests. 59 * + for 2.6.N, for N > ~10, needs API changes for hcd framework. 60 * 61 * - DMA (CPPI) ... partially behaves, not currently recommended 62 * + about 1/15 the speed of typical EHCI implementations (PCI) 63 * + RX, all too often reqpkt seems to misbehave after tx 64 * + TX, no known issues (other than evident silicon issue) 65 * 66 * - DMA (Mentor/OMAP) ...has at least toggle update problems 67 * 68 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet 69 * starvation ... nothing yet for TX, interrupt, or bulk. 70 * 71 * - Not tested with HNP, but some SRP paths seem to behave. 72 * 73 * NOTE 24-August-2006: 74 * 75 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an 76 * extra endpoint for periodic use enabling hub + keybd + mouse. That 77 * mostly works, except that with "usbnet" it's easy to trigger cases 78 * with "ping" where RX loses. (a) ping to davinci, even "ping -f", 79 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses 80 * although ARP RX wins. (That test was done with a full speed link.) 81 */ 82 83 84 /* 85 * NOTE on endpoint usage: 86 * 87 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN 88 * and OUT endpoints ... hardware is dedicated for those "async" queue(s). 89 * (Yes, bulk _could_ use more of the endpoints than that, and would even 90 * benefit from it.) 91 * 92 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. 93 * So far that scheduling is both dumb and optimistic: the endpoint will be 94 * "claimed" until its software queue is no longer refilled. No multiplexing 95 * of transfers between endpoints, or anything clever. 96 */ 97 98 struct musb *hcd_to_musb(struct usb_hcd *hcd) 99 { 100 return *(struct musb **) hcd->hcd_priv; 101 } 102 103 104 static void musb_ep_program(struct musb *musb, u8 epnum, 105 struct urb *urb, int is_out, 106 u8 *buf, u32 offset, u32 len); 107 108 /* 109 * Clear TX fifo. Needed to avoid BABBLE errors. 110 */ 111 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) 112 { 113 struct musb *musb = ep->musb; 114 void __iomem *epio = ep->regs; 115 u16 csr; 116 u16 lastcsr = 0; 117 int retries = 1000; 118 119 csr = musb_readw(epio, MUSB_TXCSR); 120 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { 121 if (csr != lastcsr) 122 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr); 123 lastcsr = csr; 124 csr |= MUSB_TXCSR_FLUSHFIFO; 125 musb_writew(epio, MUSB_TXCSR, csr); 126 csr = musb_readw(epio, MUSB_TXCSR); 127 if (WARN(retries-- < 1, 128 "Could not flush host TX%d fifo: csr: %04x\n", 129 ep->epnum, csr)) 130 return; 131 mdelay(1); 132 } 133 } 134 135 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) 136 { 137 void __iomem *epio = ep->regs; 138 u16 csr; 139 int retries = 5; 140 141 /* scrub any data left in the fifo */ 142 do { 143 csr = musb_readw(epio, MUSB_TXCSR); 144 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) 145 break; 146 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO); 147 csr = musb_readw(epio, MUSB_TXCSR); 148 udelay(10); 149 } while (--retries); 150 151 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", 152 ep->epnum, csr); 153 154 /* and reset for the next transfer */ 155 musb_writew(epio, MUSB_TXCSR, 0); 156 } 157 158 /* 159 * Start transmit. Caller is responsible for locking shared resources. 160 * musb must be locked. 161 */ 162 static inline void musb_h_tx_start(struct musb_hw_ep *ep) 163 { 164 u16 txcsr; 165 166 /* NOTE: no locks here; caller should lock and select EP */ 167 if (ep->epnum) { 168 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 169 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; 170 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 171 } else { 172 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; 173 musb_writew(ep->regs, MUSB_CSR0, txcsr); 174 } 175 176 } 177 178 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep) 179 { 180 u16 txcsr; 181 182 /* NOTE: no locks here; caller should lock and select EP */ 183 txcsr = musb_readw(ep->regs, MUSB_TXCSR); 184 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; 185 if (is_cppi_enabled()) 186 txcsr |= MUSB_TXCSR_DMAMODE; 187 musb_writew(ep->regs, MUSB_TXCSR, txcsr); 188 } 189 190 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh) 191 { 192 if (is_in != 0 || ep->is_shared_fifo) 193 ep->in_qh = qh; 194 if (is_in == 0 || ep->is_shared_fifo) 195 ep->out_qh = qh; 196 } 197 198 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in) 199 { 200 return is_in ? ep->in_qh : ep->out_qh; 201 } 202 203 /* 204 * Start the URB at the front of an endpoint's queue 205 * end must be claimed from the caller. 206 * 207 * Context: controller locked, irqs blocked 208 */ 209 static void 210 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) 211 { 212 u16 frame; 213 u32 len; 214 void __iomem *mbase = musb->mregs; 215 struct urb *urb = next_urb(qh); 216 void *buf = urb->transfer_buffer; 217 u32 offset = 0; 218 struct musb_hw_ep *hw_ep = qh->hw_ep; 219 unsigned pipe = urb->pipe; 220 u8 address = usb_pipedevice(pipe); 221 int epnum = hw_ep->epnum; 222 223 /* initialize software qh state */ 224 qh->offset = 0; 225 qh->segsize = 0; 226 227 /* gather right source of data */ 228 switch (qh->type) { 229 case USB_ENDPOINT_XFER_CONTROL: 230 /* control transfers always start with SETUP */ 231 is_in = 0; 232 musb->ep0_stage = MUSB_EP0_START; 233 buf = urb->setup_packet; 234 len = 8; 235 break; 236 case USB_ENDPOINT_XFER_ISOC: 237 qh->iso_idx = 0; 238 qh->frame = 0; 239 offset = urb->iso_frame_desc[0].offset; 240 len = urb->iso_frame_desc[0].length; 241 break; 242 default: /* bulk, interrupt */ 243 /* actual_length may be nonzero on retry paths */ 244 buf = urb->transfer_buffer + urb->actual_length; 245 len = urb->transfer_buffer_length - urb->actual_length; 246 } 247 248 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", 249 qh, urb, address, qh->epnum, 250 is_in ? "in" : "out", 251 ({char *s; switch (qh->type) { 252 case USB_ENDPOINT_XFER_CONTROL: s = ""; break; 253 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break; 254 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break; 255 default: s = "-intr"; break; 256 } s; }), 257 epnum, buf + offset, len); 258 259 /* Configure endpoint */ 260 musb_ep_set_qh(hw_ep, is_in, qh); 261 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len); 262 263 /* transmit may have more work: start it when it is time */ 264 if (is_in) 265 return; 266 267 /* determine if the time is right for a periodic transfer */ 268 switch (qh->type) { 269 case USB_ENDPOINT_XFER_ISOC: 270 case USB_ENDPOINT_XFER_INT: 271 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n"); 272 frame = musb_readw(mbase, MUSB_FRAME); 273 /* FIXME this doesn't implement that scheduling policy ... 274 * or handle framecounter wrapping 275 */ 276 if (1) { /* Always assume URB_ISO_ASAP */ 277 /* REVISIT the SOF irq handler shouldn't duplicate 278 * this code; and we don't init urb->start_frame... 279 */ 280 qh->frame = 0; 281 goto start; 282 } else { 283 qh->frame = urb->start_frame; 284 /* enable SOF interrupt so we can count down */ 285 dev_dbg(musb->controller, "SOF for %d\n", epnum); 286 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */ 287 musb_writeb(mbase, MUSB_INTRUSBE, 0xff); 288 #endif 289 } 290 break; 291 default: 292 start: 293 dev_dbg(musb->controller, "Start TX%d %s\n", epnum, 294 hw_ep->tx_channel ? "dma" : "pio"); 295 296 if (!hw_ep->tx_channel) 297 musb_h_tx_start(hw_ep); 298 else if (is_cppi_enabled() || tusb_dma_omap()) 299 musb_h_tx_dma_start(hw_ep); 300 } 301 } 302 303 /* Context: caller owns controller lock, IRQs are blocked */ 304 static void musb_giveback(struct musb *musb, struct urb *urb, int status) 305 __releases(musb->lock) 306 __acquires(musb->lock) 307 { 308 dev_dbg(musb->controller, 309 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", 310 urb, urb->complete, status, 311 usb_pipedevice(urb->pipe), 312 usb_pipeendpoint(urb->pipe), 313 usb_pipein(urb->pipe) ? "in" : "out", 314 urb->actual_length, urb->transfer_buffer_length 315 ); 316 317 usb_hcd_unlink_urb_from_ep(musb->hcd, urb); 318 spin_unlock(&musb->lock); 319 usb_hcd_giveback_urb(musb->hcd, urb, status); 320 spin_lock(&musb->lock); 321 } 322 323 /* For bulk/interrupt endpoints only */ 324 static inline void musb_save_toggle(struct musb_qh *qh, int is_in, 325 struct urb *urb) 326 { 327 void __iomem *epio = qh->hw_ep->regs; 328 u16 csr; 329 330 /* 331 * FIXME: the current Mentor DMA code seems to have 332 * problems getting toggle correct. 333 */ 334 335 if (is_in) 336 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE; 337 else 338 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE; 339 340 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0); 341 } 342 343 /* 344 * Advance this hardware endpoint's queue, completing the specified URB and 345 * advancing to either the next URB queued to that qh, or else invalidating 346 * that qh and advancing to the next qh scheduled after the current one. 347 * 348 * Context: caller owns controller lock, IRQs are blocked 349 */ 350 static void musb_advance_schedule(struct musb *musb, struct urb *urb, 351 struct musb_hw_ep *hw_ep, int is_in) 352 { 353 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in); 354 struct musb_hw_ep *ep = qh->hw_ep; 355 int ready = qh->is_ready; 356 int status; 357 358 status = (urb->status == -EINPROGRESS) ? 0 : urb->status; 359 360 /* save toggle eagerly, for paranoia */ 361 switch (qh->type) { 362 case USB_ENDPOINT_XFER_BULK: 363 case USB_ENDPOINT_XFER_INT: 364 musb_save_toggle(qh, is_in, urb); 365 break; 366 case USB_ENDPOINT_XFER_ISOC: 367 if (status == 0 && urb->error_count) 368 status = -EXDEV; 369 break; 370 } 371 372 qh->is_ready = 0; 373 musb_giveback(musb, urb, status); 374 qh->is_ready = ready; 375 376 /* reclaim resources (and bandwidth) ASAP; deschedule it, and 377 * invalidate qh as soon as list_empty(&hep->urb_list) 378 */ 379 if (list_empty(&qh->hep->urb_list)) { 380 struct list_head *head; 381 struct dma_controller *dma = musb->dma_controller; 382 383 if (is_in) { 384 ep->rx_reinit = 1; 385 if (ep->rx_channel) { 386 dma->channel_release(ep->rx_channel); 387 ep->rx_channel = NULL; 388 } 389 } else { 390 ep->tx_reinit = 1; 391 if (ep->tx_channel) { 392 dma->channel_release(ep->tx_channel); 393 ep->tx_channel = NULL; 394 } 395 } 396 397 /* Clobber old pointers to this qh */ 398 musb_ep_set_qh(ep, is_in, NULL); 399 qh->hep->hcpriv = NULL; 400 401 switch (qh->type) { 402 403 case USB_ENDPOINT_XFER_CONTROL: 404 case USB_ENDPOINT_XFER_BULK: 405 /* fifo policy for these lists, except that NAKing 406 * should rotate a qh to the end (for fairness). 407 */ 408 if (qh->mux == 1) { 409 head = qh->ring.prev; 410 list_del(&qh->ring); 411 kfree(qh); 412 qh = first_qh(head); 413 break; 414 } 415 416 case USB_ENDPOINT_XFER_ISOC: 417 case USB_ENDPOINT_XFER_INT: 418 /* this is where periodic bandwidth should be 419 * de-allocated if it's tracked and allocated; 420 * and where we'd update the schedule tree... 421 */ 422 kfree(qh); 423 qh = NULL; 424 break; 425 } 426 } 427 428 if (qh != NULL && qh->is_ready) { 429 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n", 430 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); 431 musb_start_urb(musb, is_in, qh); 432 } 433 } 434 435 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) 436 { 437 /* we don't want fifo to fill itself again; 438 * ignore dma (various models), 439 * leave toggle alone (may not have been saved yet) 440 */ 441 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; 442 csr &= ~(MUSB_RXCSR_H_REQPKT 443 | MUSB_RXCSR_H_AUTOREQ 444 | MUSB_RXCSR_AUTOCLEAR); 445 446 /* write 2x to allow double buffering */ 447 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 448 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 449 450 /* flush writebuffer */ 451 return musb_readw(hw_ep->regs, MUSB_RXCSR); 452 } 453 454 /* 455 * PIO RX for a packet (or part of it). 456 */ 457 static bool 458 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) 459 { 460 u16 rx_count; 461 u8 *buf; 462 u16 csr; 463 bool done = false; 464 u32 length; 465 int do_flush = 0; 466 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 467 void __iomem *epio = hw_ep->regs; 468 struct musb_qh *qh = hw_ep->in_qh; 469 int pipe = urb->pipe; 470 void *buffer = urb->transfer_buffer; 471 472 /* musb_ep_select(mbase, epnum); */ 473 rx_count = musb_readw(epio, MUSB_RXCOUNT); 474 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, 475 urb->transfer_buffer, qh->offset, 476 urb->transfer_buffer_length); 477 478 /* unload FIFO */ 479 if (usb_pipeisoc(pipe)) { 480 int status = 0; 481 struct usb_iso_packet_descriptor *d; 482 483 if (iso_err) { 484 status = -EILSEQ; 485 urb->error_count++; 486 } 487 488 d = urb->iso_frame_desc + qh->iso_idx; 489 buf = buffer + d->offset; 490 length = d->length; 491 if (rx_count > length) { 492 if (status == 0) { 493 status = -EOVERFLOW; 494 urb->error_count++; 495 } 496 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); 497 do_flush = 1; 498 } else 499 length = rx_count; 500 urb->actual_length += length; 501 d->actual_length = length; 502 503 d->status = status; 504 505 /* see if we are done */ 506 done = (++qh->iso_idx >= urb->number_of_packets); 507 } else { 508 /* non-isoch */ 509 buf = buffer + qh->offset; 510 length = urb->transfer_buffer_length - qh->offset; 511 if (rx_count > length) { 512 if (urb->status == -EINPROGRESS) 513 urb->status = -EOVERFLOW; 514 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); 515 do_flush = 1; 516 } else 517 length = rx_count; 518 urb->actual_length += length; 519 qh->offset += length; 520 521 /* see if we are done */ 522 done = (urb->actual_length == urb->transfer_buffer_length) 523 || (rx_count < qh->maxpacket) 524 || (urb->status != -EINPROGRESS); 525 if (done 526 && (urb->status == -EINPROGRESS) 527 && (urb->transfer_flags & URB_SHORT_NOT_OK) 528 && (urb->actual_length 529 < urb->transfer_buffer_length)) 530 urb->status = -EREMOTEIO; 531 } 532 533 musb_read_fifo(hw_ep, length, buf); 534 535 csr = musb_readw(epio, MUSB_RXCSR); 536 csr |= MUSB_RXCSR_H_WZC_BITS; 537 if (unlikely(do_flush)) 538 musb_h_flush_rxfifo(hw_ep, csr); 539 else { 540 /* REVISIT this assumes AUTOCLEAR is never set */ 541 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); 542 if (!done) 543 csr |= MUSB_RXCSR_H_REQPKT; 544 musb_writew(epio, MUSB_RXCSR, csr); 545 } 546 547 return done; 548 } 549 550 /* we don't always need to reinit a given side of an endpoint... 551 * when we do, use tx/rx reinit routine and then construct a new CSR 552 * to address data toggle, NYET, and DMA or PIO. 553 * 554 * it's possible that driver bugs (especially for DMA) or aborting a 555 * transfer might have left the endpoint busier than it should be. 556 * the busy/not-empty tests are basically paranoia. 557 */ 558 static void 559 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) 560 { 561 u16 csr; 562 563 /* NOTE: we know the "rx" fifo reinit never triggers for ep0. 564 * That always uses tx_reinit since ep0 repurposes TX register 565 * offsets; the initial SETUP packet is also a kind of OUT. 566 */ 567 568 /* if programmed for Tx, put it in RX mode */ 569 if (ep->is_shared_fifo) { 570 csr = musb_readw(ep->regs, MUSB_TXCSR); 571 if (csr & MUSB_TXCSR_MODE) { 572 musb_h_tx_flush_fifo(ep); 573 csr = musb_readw(ep->regs, MUSB_TXCSR); 574 musb_writew(ep->regs, MUSB_TXCSR, 575 csr | MUSB_TXCSR_FRCDATATOG); 576 } 577 578 /* 579 * Clear the MODE bit (and everything else) to enable Rx. 580 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB. 581 */ 582 if (csr & MUSB_TXCSR_DMAMODE) 583 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE); 584 musb_writew(ep->regs, MUSB_TXCSR, 0); 585 586 /* scrub all previous state, clearing toggle */ 587 } else { 588 csr = musb_readw(ep->regs, MUSB_RXCSR); 589 if (csr & MUSB_RXCSR_RXPKTRDY) 590 WARNING("rx%d, packet/%d ready?\n", ep->epnum, 591 musb_readw(ep->regs, MUSB_RXCOUNT)); 592 593 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); 594 } 595 596 /* target addr and (for multipoint) hub addr/port */ 597 if (musb->is_multipoint) { 598 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg); 599 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg); 600 musb_write_rxhubport(ep->target_regs, qh->h_port_reg); 601 602 } else 603 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); 604 605 /* protocol/endpoint, interval/NAKlimit, i/o size */ 606 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); 607 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); 608 /* NOTE: bulk combining rewrites high bits of maxpacket */ 609 /* Set RXMAXP with the FIFO size of the endpoint 610 * to disable double buffer mode. 611 */ 612 if (musb->double_buffer_not_ok) 613 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx); 614 else 615 musb_writew(ep->regs, MUSB_RXMAXP, 616 qh->maxpacket | ((qh->hb_mult - 1) << 11)); 617 618 ep->rx_reinit = 0; 619 } 620 621 static bool musb_tx_dma_program(struct dma_controller *dma, 622 struct musb_hw_ep *hw_ep, struct musb_qh *qh, 623 struct urb *urb, u32 offset, u32 length) 624 { 625 struct dma_channel *channel = hw_ep->tx_channel; 626 void __iomem *epio = hw_ep->regs; 627 u16 pkt_size = qh->maxpacket; 628 u16 csr; 629 u8 mode; 630 631 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) 632 if (length > channel->max_len) 633 length = channel->max_len; 634 635 csr = musb_readw(epio, MUSB_TXCSR); 636 if (length > pkt_size) { 637 mode = 1; 638 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; 639 /* autoset shouldn't be set in high bandwidth */ 640 /* 641 * Enable Autoset according to table 642 * below 643 * bulk_split hb_mult Autoset_Enable 644 * 0 1 Yes(Normal) 645 * 0 >1 No(High BW ISO) 646 * 1 1 Yes(HS bulk) 647 * 1 >1 Yes(FS bulk) 648 */ 649 if (qh->hb_mult == 1 || (qh->hb_mult > 1 && 650 can_bulk_split(hw_ep->musb, qh->type))) 651 csr |= MUSB_TXCSR_AUTOSET; 652 } else { 653 mode = 0; 654 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); 655 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ 656 } 657 channel->desired_mode = mode; 658 musb_writew(epio, MUSB_TXCSR, csr); 659 #else 660 if (!is_cppi_enabled() && !tusb_dma_omap()) 661 return false; 662 663 channel->actual_len = 0; 664 665 /* 666 * TX uses "RNDIS" mode automatically but needs help 667 * to identify the zero-length-final-packet case. 668 */ 669 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; 670 #endif 671 672 qh->segsize = length; 673 674 /* 675 * Ensure the data reaches to main memory before starting 676 * DMA transfer 677 */ 678 wmb(); 679 680 if (!dma->channel_program(channel, pkt_size, mode, 681 urb->transfer_dma + offset, length)) { 682 dma->channel_release(channel); 683 hw_ep->tx_channel = NULL; 684 685 csr = musb_readw(epio, MUSB_TXCSR); 686 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 687 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); 688 return false; 689 } 690 return true; 691 } 692 693 /* 694 * Program an HDRC endpoint as per the given URB 695 * Context: irqs blocked, controller lock held 696 */ 697 static void musb_ep_program(struct musb *musb, u8 epnum, 698 struct urb *urb, int is_out, 699 u8 *buf, u32 offset, u32 len) 700 { 701 struct dma_controller *dma_controller; 702 struct dma_channel *dma_channel; 703 u8 dma_ok; 704 void __iomem *mbase = musb->mregs; 705 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 706 void __iomem *epio = hw_ep->regs; 707 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); 708 u16 packet_sz = qh->maxpacket; 709 u8 use_dma = 1; 710 u16 csr; 711 712 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s " 713 "h_addr%02x h_port%02x bytes %d\n", 714 is_out ? "-->" : "<--", 715 epnum, urb, urb->dev->speed, 716 qh->addr_reg, qh->epnum, is_out ? "out" : "in", 717 qh->h_addr_reg, qh->h_port_reg, 718 len); 719 720 musb_ep_select(mbase, epnum); 721 722 if (is_out && !len) { 723 use_dma = 0; 724 csr = musb_readw(epio, MUSB_TXCSR); 725 csr &= ~MUSB_TXCSR_DMAENAB; 726 musb_writew(epio, MUSB_TXCSR, csr); 727 hw_ep->tx_channel = NULL; 728 } 729 730 /* candidate for DMA? */ 731 dma_controller = musb->dma_controller; 732 if (use_dma && is_dma_capable() && epnum && dma_controller) { 733 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; 734 if (!dma_channel) { 735 dma_channel = dma_controller->channel_alloc( 736 dma_controller, hw_ep, is_out); 737 if (is_out) 738 hw_ep->tx_channel = dma_channel; 739 else 740 hw_ep->rx_channel = dma_channel; 741 } 742 } else 743 dma_channel = NULL; 744 745 /* make sure we clear DMAEnab, autoSet bits from previous run */ 746 747 /* OUT/transmit/EP0 or IN/receive? */ 748 if (is_out) { 749 u16 csr; 750 u16 int_txe; 751 u16 load_count; 752 753 csr = musb_readw(epio, MUSB_TXCSR); 754 755 /* disable interrupt in case we flush */ 756 int_txe = musb->intrtxe; 757 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); 758 759 /* general endpoint setup */ 760 if (epnum) { 761 /* flush all old state, set default */ 762 /* 763 * We could be flushing valid 764 * packets in double buffering 765 * case 766 */ 767 if (!hw_ep->tx_double_buffered) 768 musb_h_tx_flush_fifo(hw_ep); 769 770 /* 771 * We must not clear the DMAMODE bit before or in 772 * the same cycle with the DMAENAB bit, so we clear 773 * the latter first... 774 */ 775 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT 776 | MUSB_TXCSR_AUTOSET 777 | MUSB_TXCSR_DMAENAB 778 | MUSB_TXCSR_FRCDATATOG 779 | MUSB_TXCSR_H_RXSTALL 780 | MUSB_TXCSR_H_ERROR 781 | MUSB_TXCSR_TXPKTRDY 782 ); 783 csr |= MUSB_TXCSR_MODE; 784 785 if (!hw_ep->tx_double_buffered) { 786 if (usb_gettoggle(urb->dev, qh->epnum, 1)) 787 csr |= MUSB_TXCSR_H_WR_DATATOGGLE 788 | MUSB_TXCSR_H_DATATOGGLE; 789 else 790 csr |= MUSB_TXCSR_CLRDATATOG; 791 } 792 793 musb_writew(epio, MUSB_TXCSR, csr); 794 /* REVISIT may need to clear FLUSHFIFO ... */ 795 csr &= ~MUSB_TXCSR_DMAMODE; 796 musb_writew(epio, MUSB_TXCSR, csr); 797 csr = musb_readw(epio, MUSB_TXCSR); 798 } else { 799 /* endpoint 0: just flush */ 800 musb_h_ep0_flush_fifo(hw_ep); 801 } 802 803 /* target addr and (for multipoint) hub addr/port */ 804 if (musb->is_multipoint) { 805 musb_write_txfunaddr(mbase, epnum, qh->addr_reg); 806 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg); 807 musb_write_txhubport(mbase, epnum, qh->h_port_reg); 808 /* FIXME if !epnum, do the same for RX ... */ 809 } else 810 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); 811 812 /* protocol/endpoint/interval/NAKlimit */ 813 if (epnum) { 814 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); 815 if (musb->double_buffer_not_ok) { 816 musb_writew(epio, MUSB_TXMAXP, 817 hw_ep->max_packet_sz_tx); 818 } else if (can_bulk_split(musb, qh->type)) { 819 qh->hb_mult = hw_ep->max_packet_sz_tx 820 / packet_sz; 821 musb_writew(epio, MUSB_TXMAXP, packet_sz 822 | ((qh->hb_mult) - 1) << 11); 823 } else { 824 musb_writew(epio, MUSB_TXMAXP, 825 qh->maxpacket | 826 ((qh->hb_mult - 1) << 11)); 827 } 828 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); 829 } else { 830 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); 831 if (musb->is_multipoint) 832 musb_writeb(epio, MUSB_TYPE0, 833 qh->type_reg); 834 } 835 836 if (can_bulk_split(musb, qh->type)) 837 load_count = min((u32) hw_ep->max_packet_sz_tx, 838 len); 839 else 840 load_count = min((u32) packet_sz, len); 841 842 if (dma_channel && musb_tx_dma_program(dma_controller, 843 hw_ep, qh, urb, offset, len)) 844 load_count = 0; 845 846 if (load_count) { 847 /* PIO to load FIFO */ 848 qh->segsize = load_count; 849 if (!buf) { 850 sg_miter_start(&qh->sg_miter, urb->sg, 1, 851 SG_MITER_ATOMIC 852 | SG_MITER_FROM_SG); 853 if (!sg_miter_next(&qh->sg_miter)) { 854 dev_err(musb->controller, 855 "error: sg" 856 "list empty\n"); 857 sg_miter_stop(&qh->sg_miter); 858 goto finish; 859 } 860 buf = qh->sg_miter.addr + urb->sg->offset + 861 urb->actual_length; 862 load_count = min_t(u32, load_count, 863 qh->sg_miter.length); 864 musb_write_fifo(hw_ep, load_count, buf); 865 qh->sg_miter.consumed = load_count; 866 sg_miter_stop(&qh->sg_miter); 867 } else 868 musb_write_fifo(hw_ep, load_count, buf); 869 } 870 finish: 871 /* re-enable interrupt */ 872 musb_writew(mbase, MUSB_INTRTXE, int_txe); 873 874 /* IN/receive */ 875 } else { 876 u16 csr; 877 878 if (hw_ep->rx_reinit) { 879 musb_rx_reinit(musb, qh, hw_ep); 880 881 /* init new state: toggle and NYET, maybe DMA later */ 882 if (usb_gettoggle(urb->dev, qh->epnum, 0)) 883 csr = MUSB_RXCSR_H_WR_DATATOGGLE 884 | MUSB_RXCSR_H_DATATOGGLE; 885 else 886 csr = 0; 887 if (qh->type == USB_ENDPOINT_XFER_INT) 888 csr |= MUSB_RXCSR_DISNYET; 889 890 } else { 891 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 892 893 if (csr & (MUSB_RXCSR_RXPKTRDY 894 | MUSB_RXCSR_DMAENAB 895 | MUSB_RXCSR_H_REQPKT)) 896 ERR("broken !rx_reinit, ep%d csr %04x\n", 897 hw_ep->epnum, csr); 898 899 /* scrub any stale state, leaving toggle alone */ 900 csr &= MUSB_RXCSR_DISNYET; 901 } 902 903 /* kick things off */ 904 905 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { 906 /* Candidate for DMA */ 907 dma_channel->actual_len = 0L; 908 qh->segsize = len; 909 910 /* AUTOREQ is in a DMA register */ 911 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 912 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 913 914 /* 915 * Unless caller treats short RX transfers as 916 * errors, we dare not queue multiple transfers. 917 */ 918 dma_ok = dma_controller->channel_program(dma_channel, 919 packet_sz, !(urb->transfer_flags & 920 URB_SHORT_NOT_OK), 921 urb->transfer_dma + offset, 922 qh->segsize); 923 if (!dma_ok) { 924 dma_controller->channel_release(dma_channel); 925 hw_ep->rx_channel = dma_channel = NULL; 926 } else 927 csr |= MUSB_RXCSR_DMAENAB; 928 } 929 930 csr |= MUSB_RXCSR_H_REQPKT; 931 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr); 932 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); 933 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 934 } 935 } 936 937 /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to 938 * the end; avoids starvation for other endpoints. 939 */ 940 static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep, 941 int is_in) 942 { 943 struct dma_channel *dma; 944 struct urb *urb; 945 void __iomem *mbase = musb->mregs; 946 void __iomem *epio = ep->regs; 947 struct musb_qh *cur_qh, *next_qh; 948 u16 rx_csr, tx_csr; 949 950 musb_ep_select(mbase, ep->epnum); 951 if (is_in) { 952 dma = is_dma_capable() ? ep->rx_channel : NULL; 953 954 /* clear nak timeout bit */ 955 rx_csr = musb_readw(epio, MUSB_RXCSR); 956 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 957 rx_csr &= ~MUSB_RXCSR_DATAERROR; 958 musb_writew(epio, MUSB_RXCSR, rx_csr); 959 960 cur_qh = first_qh(&musb->in_bulk); 961 } else { 962 dma = is_dma_capable() ? ep->tx_channel : NULL; 963 964 /* clear nak timeout bit */ 965 tx_csr = musb_readw(epio, MUSB_TXCSR); 966 tx_csr |= MUSB_TXCSR_H_WZC_BITS; 967 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT; 968 musb_writew(epio, MUSB_TXCSR, tx_csr); 969 970 cur_qh = first_qh(&musb->out_bulk); 971 } 972 if (cur_qh) { 973 urb = next_urb(cur_qh); 974 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 975 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 976 musb->dma_controller->channel_abort(dma); 977 urb->actual_length += dma->actual_len; 978 dma->actual_len = 0L; 979 } 980 musb_save_toggle(cur_qh, is_in, urb); 981 982 if (is_in) { 983 /* move cur_qh to end of queue */ 984 list_move_tail(&cur_qh->ring, &musb->in_bulk); 985 986 /* get the next qh from musb->in_bulk */ 987 next_qh = first_qh(&musb->in_bulk); 988 989 /* set rx_reinit and schedule the next qh */ 990 ep->rx_reinit = 1; 991 } else { 992 /* move cur_qh to end of queue */ 993 list_move_tail(&cur_qh->ring, &musb->out_bulk); 994 995 /* get the next qh from musb->out_bulk */ 996 next_qh = first_qh(&musb->out_bulk); 997 998 /* set tx_reinit and schedule the next qh */ 999 ep->tx_reinit = 1; 1000 } 1001 musb_start_urb(musb, is_in, next_qh); 1002 } 1003 } 1004 1005 /* 1006 * Service the default endpoint (ep0) as host. 1007 * Return true until it's time to start the status stage. 1008 */ 1009 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) 1010 { 1011 bool more = false; 1012 u8 *fifo_dest = NULL; 1013 u16 fifo_count = 0; 1014 struct musb_hw_ep *hw_ep = musb->control_ep; 1015 struct musb_qh *qh = hw_ep->in_qh; 1016 struct usb_ctrlrequest *request; 1017 1018 switch (musb->ep0_stage) { 1019 case MUSB_EP0_IN: 1020 fifo_dest = urb->transfer_buffer + urb->actual_length; 1021 fifo_count = min_t(size_t, len, urb->transfer_buffer_length - 1022 urb->actual_length); 1023 if (fifo_count < len) 1024 urb->status = -EOVERFLOW; 1025 1026 musb_read_fifo(hw_ep, fifo_count, fifo_dest); 1027 1028 urb->actual_length += fifo_count; 1029 if (len < qh->maxpacket) { 1030 /* always terminate on short read; it's 1031 * rarely reported as an error. 1032 */ 1033 } else if (urb->actual_length < 1034 urb->transfer_buffer_length) 1035 more = true; 1036 break; 1037 case MUSB_EP0_START: 1038 request = (struct usb_ctrlrequest *) urb->setup_packet; 1039 1040 if (!request->wLength) { 1041 dev_dbg(musb->controller, "start no-DATA\n"); 1042 break; 1043 } else if (request->bRequestType & USB_DIR_IN) { 1044 dev_dbg(musb->controller, "start IN-DATA\n"); 1045 musb->ep0_stage = MUSB_EP0_IN; 1046 more = true; 1047 break; 1048 } else { 1049 dev_dbg(musb->controller, "start OUT-DATA\n"); 1050 musb->ep0_stage = MUSB_EP0_OUT; 1051 more = true; 1052 } 1053 /* FALLTHROUGH */ 1054 case MUSB_EP0_OUT: 1055 fifo_count = min_t(size_t, qh->maxpacket, 1056 urb->transfer_buffer_length - 1057 urb->actual_length); 1058 if (fifo_count) { 1059 fifo_dest = (u8 *) (urb->transfer_buffer 1060 + urb->actual_length); 1061 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n", 1062 fifo_count, 1063 (fifo_count == 1) ? "" : "s", 1064 fifo_dest); 1065 musb_write_fifo(hw_ep, fifo_count, fifo_dest); 1066 1067 urb->actual_length += fifo_count; 1068 more = true; 1069 } 1070 break; 1071 default: 1072 ERR("bogus ep0 stage %d\n", musb->ep0_stage); 1073 break; 1074 } 1075 1076 return more; 1077 } 1078 1079 /* 1080 * Handle default endpoint interrupt as host. Only called in IRQ time 1081 * from musb_interrupt(). 1082 * 1083 * called with controller irqlocked 1084 */ 1085 irqreturn_t musb_h_ep0_irq(struct musb *musb) 1086 { 1087 struct urb *urb; 1088 u16 csr, len; 1089 int status = 0; 1090 void __iomem *mbase = musb->mregs; 1091 struct musb_hw_ep *hw_ep = musb->control_ep; 1092 void __iomem *epio = hw_ep->regs; 1093 struct musb_qh *qh = hw_ep->in_qh; 1094 bool complete = false; 1095 irqreturn_t retval = IRQ_NONE; 1096 1097 /* ep0 only has one queue, "in" */ 1098 urb = next_urb(qh); 1099 1100 musb_ep_select(mbase, 0); 1101 csr = musb_readw(epio, MUSB_CSR0); 1102 len = (csr & MUSB_CSR0_RXPKTRDY) 1103 ? musb_readb(epio, MUSB_COUNT0) 1104 : 0; 1105 1106 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", 1107 csr, qh, len, urb, musb->ep0_stage); 1108 1109 /* if we just did status stage, we are done */ 1110 if (MUSB_EP0_STATUS == musb->ep0_stage) { 1111 retval = IRQ_HANDLED; 1112 complete = true; 1113 } 1114 1115 /* prepare status */ 1116 if (csr & MUSB_CSR0_H_RXSTALL) { 1117 dev_dbg(musb->controller, "STALLING ENDPOINT\n"); 1118 status = -EPIPE; 1119 1120 } else if (csr & MUSB_CSR0_H_ERROR) { 1121 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr); 1122 status = -EPROTO; 1123 1124 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { 1125 dev_dbg(musb->controller, "control NAK timeout\n"); 1126 1127 /* NOTE: this code path would be a good place to PAUSE a 1128 * control transfer, if another one is queued, so that 1129 * ep0 is more likely to stay busy. That's already done 1130 * for bulk RX transfers. 1131 * 1132 * if (qh->ring.next != &musb->control), then 1133 * we have a candidate... NAKing is *NOT* an error 1134 */ 1135 musb_writew(epio, MUSB_CSR0, 0); 1136 retval = IRQ_HANDLED; 1137 } 1138 1139 if (status) { 1140 dev_dbg(musb->controller, "aborting\n"); 1141 retval = IRQ_HANDLED; 1142 if (urb) 1143 urb->status = status; 1144 complete = true; 1145 1146 /* use the proper sequence to abort the transfer */ 1147 if (csr & MUSB_CSR0_H_REQPKT) { 1148 csr &= ~MUSB_CSR0_H_REQPKT; 1149 musb_writew(epio, MUSB_CSR0, csr); 1150 csr &= ~MUSB_CSR0_H_NAKTIMEOUT; 1151 musb_writew(epio, MUSB_CSR0, csr); 1152 } else { 1153 musb_h_ep0_flush_fifo(hw_ep); 1154 } 1155 1156 musb_writeb(epio, MUSB_NAKLIMIT0, 0); 1157 1158 /* clear it */ 1159 musb_writew(epio, MUSB_CSR0, 0); 1160 } 1161 1162 if (unlikely(!urb)) { 1163 /* stop endpoint since we have no place for its data, this 1164 * SHOULD NEVER HAPPEN! */ 1165 ERR("no URB for end 0\n"); 1166 1167 musb_h_ep0_flush_fifo(hw_ep); 1168 goto done; 1169 } 1170 1171 if (!complete) { 1172 /* call common logic and prepare response */ 1173 if (musb_h_ep0_continue(musb, len, urb)) { 1174 /* more packets required */ 1175 csr = (MUSB_EP0_IN == musb->ep0_stage) 1176 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; 1177 } else { 1178 /* data transfer complete; perform status phase */ 1179 if (usb_pipeout(urb->pipe) 1180 || !urb->transfer_buffer_length) 1181 csr = MUSB_CSR0_H_STATUSPKT 1182 | MUSB_CSR0_H_REQPKT; 1183 else 1184 csr = MUSB_CSR0_H_STATUSPKT 1185 | MUSB_CSR0_TXPKTRDY; 1186 1187 /* flag status stage */ 1188 musb->ep0_stage = MUSB_EP0_STATUS; 1189 1190 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr); 1191 1192 } 1193 musb_writew(epio, MUSB_CSR0, csr); 1194 retval = IRQ_HANDLED; 1195 } else 1196 musb->ep0_stage = MUSB_EP0_IDLE; 1197 1198 /* call completion handler if done */ 1199 if (complete) 1200 musb_advance_schedule(musb, urb, hw_ep, 1); 1201 done: 1202 return retval; 1203 } 1204 1205 1206 #ifdef CONFIG_USB_INVENTRA_DMA 1207 1208 /* Host side TX (OUT) using Mentor DMA works as follows: 1209 submit_urb -> 1210 - if queue was empty, Program Endpoint 1211 - ... which starts DMA to fifo in mode 1 or 0 1212 1213 DMA Isr (transfer complete) -> TxAvail() 1214 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens 1215 only in musb_cleanup_urb) 1216 - TxPktRdy has to be set in mode 0 or for 1217 short packets in mode 1. 1218 */ 1219 1220 #endif 1221 1222 /* Service a Tx-Available or dma completion irq for the endpoint */ 1223 void musb_host_tx(struct musb *musb, u8 epnum) 1224 { 1225 int pipe; 1226 bool done = false; 1227 u16 tx_csr; 1228 size_t length = 0; 1229 size_t offset = 0; 1230 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1231 void __iomem *epio = hw_ep->regs; 1232 struct musb_qh *qh = hw_ep->out_qh; 1233 struct urb *urb = next_urb(qh); 1234 u32 status = 0; 1235 void __iomem *mbase = musb->mregs; 1236 struct dma_channel *dma; 1237 bool transfer_pending = false; 1238 1239 musb_ep_select(mbase, epnum); 1240 tx_csr = musb_readw(epio, MUSB_TXCSR); 1241 1242 /* with CPPI, DMA sometimes triggers "extra" irqs */ 1243 if (!urb) { 1244 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1245 return; 1246 } 1247 1248 pipe = urb->pipe; 1249 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; 1250 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, 1251 dma ? ", dma" : ""); 1252 1253 /* check for errors */ 1254 if (tx_csr & MUSB_TXCSR_H_RXSTALL) { 1255 /* dma was disabled, fifo flushed */ 1256 dev_dbg(musb->controller, "TX end %d stall\n", epnum); 1257 1258 /* stall; record URB status */ 1259 status = -EPIPE; 1260 1261 } else if (tx_csr & MUSB_TXCSR_H_ERROR) { 1262 /* (NON-ISO) dma was disabled, fifo flushed */ 1263 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum); 1264 1265 status = -ETIMEDOUT; 1266 1267 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { 1268 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1 1269 && !list_is_singular(&musb->out_bulk)) { 1270 dev_dbg(musb->controller, 1271 "NAK timeout on TX%d ep\n", epnum); 1272 musb_bulk_nak_timeout(musb, hw_ep, 0); 1273 } else { 1274 dev_dbg(musb->controller, 1275 "TX end=%d device not responding\n", epnum); 1276 /* NOTE: this code path would be a good place to PAUSE a 1277 * transfer, if there's some other (nonperiodic) tx urb 1278 * that could use this fifo. (dma complicates it...) 1279 * That's already done for bulk RX transfers. 1280 * 1281 * if (bulk && qh->ring.next != &musb->out_bulk), then 1282 * we have a candidate... NAKing is *NOT* an error 1283 */ 1284 musb_ep_select(mbase, epnum); 1285 musb_writew(epio, MUSB_TXCSR, 1286 MUSB_TXCSR_H_WZC_BITS 1287 | MUSB_TXCSR_TXPKTRDY); 1288 } 1289 return; 1290 } 1291 1292 done: 1293 if (status) { 1294 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1295 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1296 (void) musb->dma_controller->channel_abort(dma); 1297 } 1298 1299 /* do the proper sequence to abort the transfer in the 1300 * usb core; the dma engine should already be stopped. 1301 */ 1302 musb_h_tx_flush_fifo(hw_ep); 1303 tx_csr &= ~(MUSB_TXCSR_AUTOSET 1304 | MUSB_TXCSR_DMAENAB 1305 | MUSB_TXCSR_H_ERROR 1306 | MUSB_TXCSR_H_RXSTALL 1307 | MUSB_TXCSR_H_NAKTIMEOUT 1308 ); 1309 1310 musb_ep_select(mbase, epnum); 1311 musb_writew(epio, MUSB_TXCSR, tx_csr); 1312 /* REVISIT may need to clear FLUSHFIFO ... */ 1313 musb_writew(epio, MUSB_TXCSR, tx_csr); 1314 musb_writeb(epio, MUSB_TXINTERVAL, 0); 1315 1316 done = true; 1317 } 1318 1319 /* second cppi case */ 1320 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1321 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); 1322 return; 1323 } 1324 1325 if (is_dma_capable() && dma && !status) { 1326 /* 1327 * DMA has completed. But if we're using DMA mode 1 (multi 1328 * packet DMA), we need a terminal TXPKTRDY interrupt before 1329 * we can consider this transfer completed, lest we trash 1330 * its last packet when writing the next URB's data. So we 1331 * switch back to mode 0 to get that interrupt; we'll come 1332 * back here once it happens. 1333 */ 1334 if (tx_csr & MUSB_TXCSR_DMAMODE) { 1335 /* 1336 * We shouldn't clear DMAMODE with DMAENAB set; so 1337 * clear them in a safe order. That should be OK 1338 * once TXPKTRDY has been set (and I've never seen 1339 * it being 0 at this moment -- DMA interrupt latency 1340 * is significant) but if it hasn't been then we have 1341 * no choice but to stop being polite and ignore the 1342 * programmer's guide... :-) 1343 * 1344 * Note that we must write TXCSR with TXPKTRDY cleared 1345 * in order not to re-trigger the packet send (this bit 1346 * can't be cleared by CPU), and there's another caveat: 1347 * TXPKTRDY may be set shortly and then cleared in the 1348 * double-buffered FIFO mode, so we do an extra TXCSR 1349 * read for debouncing... 1350 */ 1351 tx_csr &= musb_readw(epio, MUSB_TXCSR); 1352 if (tx_csr & MUSB_TXCSR_TXPKTRDY) { 1353 tx_csr &= ~(MUSB_TXCSR_DMAENAB | 1354 MUSB_TXCSR_TXPKTRDY); 1355 musb_writew(epio, MUSB_TXCSR, 1356 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1357 } 1358 tx_csr &= ~(MUSB_TXCSR_DMAMODE | 1359 MUSB_TXCSR_TXPKTRDY); 1360 musb_writew(epio, MUSB_TXCSR, 1361 tx_csr | MUSB_TXCSR_H_WZC_BITS); 1362 1363 /* 1364 * There is no guarantee that we'll get an interrupt 1365 * after clearing DMAMODE as we might have done this 1366 * too late (after TXPKTRDY was cleared by controller). 1367 * Re-read TXCSR as we have spoiled its previous value. 1368 */ 1369 tx_csr = musb_readw(epio, MUSB_TXCSR); 1370 } 1371 1372 /* 1373 * We may get here from a DMA completion or TXPKTRDY interrupt. 1374 * In any case, we must check the FIFO status here and bail out 1375 * only if the FIFO still has data -- that should prevent the 1376 * "missed" TXPKTRDY interrupts and deal with double-buffered 1377 * FIFO mode too... 1378 */ 1379 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { 1380 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, " 1381 "CSR %04x\n", tx_csr); 1382 return; 1383 } 1384 } 1385 1386 if (!status || dma || usb_pipeisoc(pipe)) { 1387 if (dma) 1388 length = dma->actual_len; 1389 else 1390 length = qh->segsize; 1391 qh->offset += length; 1392 1393 if (usb_pipeisoc(pipe)) { 1394 struct usb_iso_packet_descriptor *d; 1395 1396 d = urb->iso_frame_desc + qh->iso_idx; 1397 d->actual_length = length; 1398 d->status = status; 1399 if (++qh->iso_idx >= urb->number_of_packets) { 1400 done = true; 1401 } else { 1402 d++; 1403 offset = d->offset; 1404 length = d->length; 1405 } 1406 } else if (dma && urb->transfer_buffer_length == qh->offset) { 1407 done = true; 1408 } else { 1409 /* see if we need to send more data, or ZLP */ 1410 if (qh->segsize < qh->maxpacket) 1411 done = true; 1412 else if (qh->offset == urb->transfer_buffer_length 1413 && !(urb->transfer_flags 1414 & URB_ZERO_PACKET)) 1415 done = true; 1416 if (!done) { 1417 offset = qh->offset; 1418 length = urb->transfer_buffer_length - offset; 1419 transfer_pending = true; 1420 } 1421 } 1422 } 1423 1424 /* urb->status != -EINPROGRESS means request has been faulted, 1425 * so we must abort this transfer after cleanup 1426 */ 1427 if (urb->status != -EINPROGRESS) { 1428 done = true; 1429 if (status == 0) 1430 status = urb->status; 1431 } 1432 1433 if (done) { 1434 /* set status */ 1435 urb->status = status; 1436 urb->actual_length = qh->offset; 1437 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); 1438 return; 1439 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) { 1440 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, 1441 offset, length)) { 1442 if (is_cppi_enabled() || tusb_dma_omap()) 1443 musb_h_tx_dma_start(hw_ep); 1444 return; 1445 } 1446 } else if (tx_csr & MUSB_TXCSR_DMAENAB) { 1447 dev_dbg(musb->controller, "not complete, but DMA enabled?\n"); 1448 return; 1449 } 1450 1451 /* 1452 * PIO: start next packet in this URB. 1453 * 1454 * REVISIT: some docs say that when hw_ep->tx_double_buffered, 1455 * (and presumably, FIFO is not half-full) we should write *two* 1456 * packets before updating TXCSR; other docs disagree... 1457 */ 1458 if (length > qh->maxpacket) 1459 length = qh->maxpacket; 1460 /* Unmap the buffer so that CPU can use it */ 1461 usb_hcd_unmap_urb_for_dma(musb->hcd, urb); 1462 1463 /* 1464 * We need to map sg if the transfer_buffer is 1465 * NULL. 1466 */ 1467 if (!urb->transfer_buffer) 1468 qh->use_sg = true; 1469 1470 if (qh->use_sg) { 1471 /* sg_miter_start is already done in musb_ep_program */ 1472 if (!sg_miter_next(&qh->sg_miter)) { 1473 dev_err(musb->controller, "error: sg list empty\n"); 1474 sg_miter_stop(&qh->sg_miter); 1475 status = -EINVAL; 1476 goto done; 1477 } 1478 urb->transfer_buffer = qh->sg_miter.addr; 1479 length = min_t(u32, length, qh->sg_miter.length); 1480 musb_write_fifo(hw_ep, length, urb->transfer_buffer); 1481 qh->sg_miter.consumed = length; 1482 sg_miter_stop(&qh->sg_miter); 1483 } else { 1484 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); 1485 } 1486 1487 qh->segsize = length; 1488 1489 if (qh->use_sg) { 1490 if (offset + length >= urb->transfer_buffer_length) 1491 qh->use_sg = false; 1492 } 1493 1494 musb_ep_select(mbase, epnum); 1495 musb_writew(epio, MUSB_TXCSR, 1496 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); 1497 } 1498 1499 1500 #ifdef CONFIG_USB_INVENTRA_DMA 1501 1502 /* Host side RX (IN) using Mentor DMA works as follows: 1503 submit_urb -> 1504 - if queue was empty, ProgramEndpoint 1505 - first IN token is sent out (by setting ReqPkt) 1506 LinuxIsr -> RxReady() 1507 /\ => first packet is received 1508 | - Set in mode 0 (DmaEnab, ~ReqPkt) 1509 | -> DMA Isr (transfer complete) -> RxReady() 1510 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) 1511 | - if urb not complete, send next IN token (ReqPkt) 1512 | | else complete urb. 1513 | | 1514 --------------------------- 1515 * 1516 * Nuances of mode 1: 1517 * For short packets, no ack (+RxPktRdy) is sent automatically 1518 * (even if AutoClear is ON) 1519 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent 1520 * automatically => major problem, as collecting the next packet becomes 1521 * difficult. Hence mode 1 is not used. 1522 * 1523 * REVISIT 1524 * All we care about at this driver level is that 1525 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; 1526 * (b) termination conditions are: short RX, or buffer full; 1527 * (c) fault modes include 1528 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. 1529 * (and that endpoint's dma queue stops immediately) 1530 * - overflow (full, PLUS more bytes in the terminal packet) 1531 * 1532 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would 1533 * thus be a great candidate for using mode 1 ... for all but the 1534 * last packet of one URB's transfer. 1535 */ 1536 1537 #endif 1538 1539 /* 1540 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, 1541 * and high-bandwidth IN transfer cases. 1542 */ 1543 void musb_host_rx(struct musb *musb, u8 epnum) 1544 { 1545 struct urb *urb; 1546 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1547 void __iomem *epio = hw_ep->regs; 1548 struct musb_qh *qh = hw_ep->in_qh; 1549 size_t xfer_len; 1550 void __iomem *mbase = musb->mregs; 1551 int pipe; 1552 u16 rx_csr, val; 1553 bool iso_err = false; 1554 bool done = false; 1555 u32 status; 1556 struct dma_channel *dma; 1557 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG; 1558 1559 musb_ep_select(mbase, epnum); 1560 1561 urb = next_urb(qh); 1562 dma = is_dma_capable() ? hw_ep->rx_channel : NULL; 1563 status = 0; 1564 xfer_len = 0; 1565 1566 rx_csr = musb_readw(epio, MUSB_RXCSR); 1567 val = rx_csr; 1568 1569 if (unlikely(!urb)) { 1570 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least 1571 * usbtest #11 (unlinks) triggers it regularly, sometimes 1572 * with fifo full. (Only with DMA??) 1573 */ 1574 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, 1575 musb_readw(epio, MUSB_RXCOUNT)); 1576 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1577 return; 1578 } 1579 1580 pipe = urb->pipe; 1581 1582 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", 1583 epnum, rx_csr, urb->actual_length, 1584 dma ? dma->actual_len : 0); 1585 1586 /* check for errors, concurrent stall & unlink is not really 1587 * handled yet! */ 1588 if (rx_csr & MUSB_RXCSR_H_RXSTALL) { 1589 dev_dbg(musb->controller, "RX end %d STALL\n", epnum); 1590 1591 /* stall; record URB status */ 1592 status = -EPIPE; 1593 1594 } else if (rx_csr & MUSB_RXCSR_H_ERROR) { 1595 dev_dbg(musb->controller, "end %d RX proto error\n", epnum); 1596 1597 status = -EPROTO; 1598 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1599 1600 } else if (rx_csr & MUSB_RXCSR_DATAERROR) { 1601 1602 if (USB_ENDPOINT_XFER_ISOC != qh->type) { 1603 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum); 1604 1605 /* NOTE: NAKing is *NOT* an error, so we want to 1606 * continue. Except ... if there's a request for 1607 * another QH, use that instead of starving it. 1608 * 1609 * Devices like Ethernet and serial adapters keep 1610 * reads posted at all times, which will starve 1611 * other devices without this logic. 1612 */ 1613 if (usb_pipebulk(urb->pipe) 1614 && qh->mux == 1 1615 && !list_is_singular(&musb->in_bulk)) { 1616 musb_bulk_nak_timeout(musb, hw_ep, 1); 1617 return; 1618 } 1619 musb_ep_select(mbase, epnum); 1620 rx_csr |= MUSB_RXCSR_H_WZC_BITS; 1621 rx_csr &= ~MUSB_RXCSR_DATAERROR; 1622 musb_writew(epio, MUSB_RXCSR, rx_csr); 1623 1624 goto finish; 1625 } else { 1626 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum); 1627 /* packet error reported later */ 1628 iso_err = true; 1629 } 1630 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) { 1631 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n", 1632 epnum); 1633 status = -EPROTO; 1634 } 1635 1636 /* faults abort the transfer */ 1637 if (status) { 1638 /* clean up dma and collect transfer count */ 1639 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1640 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1641 (void) musb->dma_controller->channel_abort(dma); 1642 xfer_len = dma->actual_len; 1643 } 1644 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); 1645 musb_writeb(epio, MUSB_RXINTERVAL, 0); 1646 done = true; 1647 goto finish; 1648 } 1649 1650 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { 1651 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ 1652 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); 1653 goto finish; 1654 } 1655 1656 /* thorough shutdown for now ... given more precise fault handling 1657 * and better queueing support, we might keep a DMA pipeline going 1658 * while processing this irq for earlier completions. 1659 */ 1660 1661 /* FIXME this is _way_ too much in-line logic for Mentor DMA */ 1662 1663 #if !defined(CONFIG_USB_INVENTRA_DMA) && !defined(CONFIG_USB_UX500_DMA) 1664 if (rx_csr & MUSB_RXCSR_H_REQPKT) { 1665 /* REVISIT this happened for a while on some short reads... 1666 * the cleanup still needs investigation... looks bad... 1667 * and also duplicates dma cleanup code above ... plus, 1668 * shouldn't this be the "half full" double buffer case? 1669 */ 1670 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 1671 dma->status = MUSB_DMA_STATUS_CORE_ABORT; 1672 (void) musb->dma_controller->channel_abort(dma); 1673 xfer_len = dma->actual_len; 1674 done = true; 1675 } 1676 1677 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, 1678 xfer_len, dma ? ", dma" : ""); 1679 rx_csr &= ~MUSB_RXCSR_H_REQPKT; 1680 1681 musb_ep_select(mbase, epnum); 1682 musb_writew(epio, MUSB_RXCSR, 1683 MUSB_RXCSR_H_WZC_BITS | rx_csr); 1684 } 1685 #endif 1686 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { 1687 xfer_len = dma->actual_len; 1688 1689 val &= ~(MUSB_RXCSR_DMAENAB 1690 | MUSB_RXCSR_H_AUTOREQ 1691 | MUSB_RXCSR_AUTOCLEAR 1692 | MUSB_RXCSR_RXPKTRDY); 1693 musb_writew(hw_ep->regs, MUSB_RXCSR, val); 1694 1695 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) 1696 if (usb_pipeisoc(pipe)) { 1697 struct usb_iso_packet_descriptor *d; 1698 1699 d = urb->iso_frame_desc + qh->iso_idx; 1700 d->actual_length = xfer_len; 1701 1702 /* even if there was an error, we did the dma 1703 * for iso_frame_desc->length 1704 */ 1705 if (d->status != -EILSEQ && d->status != -EOVERFLOW) 1706 d->status = 0; 1707 1708 if (++qh->iso_idx >= urb->number_of_packets) 1709 done = true; 1710 else 1711 done = false; 1712 1713 } else { 1714 /* done if urb buffer is full or short packet is recd */ 1715 done = (urb->actual_length + xfer_len >= 1716 urb->transfer_buffer_length 1717 || dma->actual_len < qh->maxpacket); 1718 } 1719 1720 /* send IN token for next packet, without AUTOREQ */ 1721 if (!done) { 1722 val |= MUSB_RXCSR_H_REQPKT; 1723 musb_writew(epio, MUSB_RXCSR, 1724 MUSB_RXCSR_H_WZC_BITS | val); 1725 } 1726 1727 dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, 1728 done ? "off" : "reset", 1729 musb_readw(epio, MUSB_RXCSR), 1730 musb_readw(epio, MUSB_RXCOUNT)); 1731 #else 1732 done = true; 1733 #endif 1734 } else if (urb->status == -EINPROGRESS) { 1735 /* if no errors, be sure a packet is ready for unloading */ 1736 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { 1737 status = -EPROTO; 1738 ERR("Rx interrupt with no errors or packet!\n"); 1739 1740 /* FIXME this is another "SHOULD NEVER HAPPEN" */ 1741 1742 /* SCRUB (RX) */ 1743 /* do the proper sequence to abort the transfer */ 1744 musb_ep_select(mbase, epnum); 1745 val &= ~MUSB_RXCSR_H_REQPKT; 1746 musb_writew(epio, MUSB_RXCSR, val); 1747 goto finish; 1748 } 1749 1750 /* we are expecting IN packets */ 1751 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) 1752 if (dma) { 1753 struct dma_controller *c; 1754 u16 rx_count; 1755 int ret, length; 1756 dma_addr_t buf; 1757 1758 rx_count = musb_readw(epio, MUSB_RXCOUNT); 1759 1760 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%llx len %d/%d\n", 1761 epnum, rx_count, 1762 (unsigned long long) urb->transfer_dma 1763 + urb->actual_length, 1764 qh->offset, 1765 urb->transfer_buffer_length); 1766 1767 c = musb->dma_controller; 1768 1769 if (usb_pipeisoc(pipe)) { 1770 int d_status = 0; 1771 struct usb_iso_packet_descriptor *d; 1772 1773 d = urb->iso_frame_desc + qh->iso_idx; 1774 1775 if (iso_err) { 1776 d_status = -EILSEQ; 1777 urb->error_count++; 1778 } 1779 if (rx_count > d->length) { 1780 if (d_status == 0) { 1781 d_status = -EOVERFLOW; 1782 urb->error_count++; 1783 } 1784 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\ 1785 rx_count, d->length); 1786 1787 length = d->length; 1788 } else 1789 length = rx_count; 1790 d->status = d_status; 1791 buf = urb->transfer_dma + d->offset; 1792 } else { 1793 length = rx_count; 1794 buf = urb->transfer_dma + 1795 urb->actual_length; 1796 } 1797 1798 dma->desired_mode = 0; 1799 #ifdef USE_MODE1 1800 /* because of the issue below, mode 1 will 1801 * only rarely behave with correct semantics. 1802 */ 1803 if ((urb->transfer_flags & 1804 URB_SHORT_NOT_OK) 1805 && (urb->transfer_buffer_length - 1806 urb->actual_length) 1807 > qh->maxpacket) 1808 dma->desired_mode = 1; 1809 if (rx_count < hw_ep->max_packet_sz_rx) { 1810 length = rx_count; 1811 dma->desired_mode = 0; 1812 } else { 1813 length = urb->transfer_buffer_length; 1814 } 1815 #endif 1816 1817 /* Disadvantage of using mode 1: 1818 * It's basically usable only for mass storage class; essentially all 1819 * other protocols also terminate transfers on short packets. 1820 * 1821 * Details: 1822 * An extra IN token is sent at the end of the transfer (due to AUTOREQ) 1823 * If you try to use mode 1 for (transfer_buffer_length - 512), and try 1824 * to use the extra IN token to grab the last packet using mode 0, then 1825 * the problem is that you cannot be sure when the device will send the 1826 * last packet and RxPktRdy set. Sometimes the packet is recd too soon 1827 * such that it gets lost when RxCSR is re-set at the end of the mode 1 1828 * transfer, while sometimes it is recd just a little late so that if you 1829 * try to configure for mode 0 soon after the mode 1 transfer is 1830 * completed, you will find rxcount 0. Okay, so you might think why not 1831 * wait for an interrupt when the pkt is recd. Well, you won't get any! 1832 */ 1833 1834 val = musb_readw(epio, MUSB_RXCSR); 1835 val &= ~MUSB_RXCSR_H_REQPKT; 1836 1837 if (dma->desired_mode == 0) 1838 val &= ~MUSB_RXCSR_H_AUTOREQ; 1839 else 1840 val |= MUSB_RXCSR_H_AUTOREQ; 1841 val |= MUSB_RXCSR_DMAENAB; 1842 1843 /* autoclear shouldn't be set in high bandwidth */ 1844 if (qh->hb_mult == 1) 1845 val |= MUSB_RXCSR_AUTOCLEAR; 1846 1847 musb_writew(epio, MUSB_RXCSR, 1848 MUSB_RXCSR_H_WZC_BITS | val); 1849 1850 /* REVISIT if when actual_length != 0, 1851 * transfer_buffer_length needs to be 1852 * adjusted first... 1853 */ 1854 ret = c->channel_program( 1855 dma, qh->maxpacket, 1856 dma->desired_mode, buf, length); 1857 1858 if (!ret) { 1859 c->channel_release(dma); 1860 hw_ep->rx_channel = NULL; 1861 dma = NULL; 1862 val = musb_readw(epio, MUSB_RXCSR); 1863 val &= ~(MUSB_RXCSR_DMAENAB 1864 | MUSB_RXCSR_H_AUTOREQ 1865 | MUSB_RXCSR_AUTOCLEAR); 1866 musb_writew(epio, MUSB_RXCSR, val); 1867 } 1868 } 1869 #endif /* Mentor DMA */ 1870 1871 if (!dma) { 1872 unsigned int received_len; 1873 1874 /* Unmap the buffer so that CPU can use it */ 1875 usb_hcd_unmap_urb_for_dma(musb->hcd, urb); 1876 1877 /* 1878 * We need to map sg if the transfer_buffer is 1879 * NULL. 1880 */ 1881 if (!urb->transfer_buffer) { 1882 qh->use_sg = true; 1883 sg_miter_start(&qh->sg_miter, urb->sg, 1, 1884 sg_flags); 1885 } 1886 1887 if (qh->use_sg) { 1888 if (!sg_miter_next(&qh->sg_miter)) { 1889 dev_err(musb->controller, "error: sg list empty\n"); 1890 sg_miter_stop(&qh->sg_miter); 1891 status = -EINVAL; 1892 done = true; 1893 goto finish; 1894 } 1895 urb->transfer_buffer = qh->sg_miter.addr; 1896 received_len = urb->actual_length; 1897 qh->offset = 0x0; 1898 done = musb_host_packet_rx(musb, urb, epnum, 1899 iso_err); 1900 /* Calculate the number of bytes received */ 1901 received_len = urb->actual_length - 1902 received_len; 1903 qh->sg_miter.consumed = received_len; 1904 sg_miter_stop(&qh->sg_miter); 1905 } else { 1906 done = musb_host_packet_rx(musb, urb, 1907 epnum, iso_err); 1908 } 1909 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : ""); 1910 } 1911 } 1912 1913 finish: 1914 urb->actual_length += xfer_len; 1915 qh->offset += xfer_len; 1916 if (done) { 1917 if (qh->use_sg) 1918 qh->use_sg = false; 1919 1920 if (urb->status == -EINPROGRESS) 1921 urb->status = status; 1922 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); 1923 } 1924 } 1925 1926 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH. 1927 * the software schedule associates multiple such nodes with a given 1928 * host side hardware endpoint + direction; scheduling may activate 1929 * that hardware endpoint. 1930 */ 1931 static int musb_schedule( 1932 struct musb *musb, 1933 struct musb_qh *qh, 1934 int is_in) 1935 { 1936 int idle; 1937 int best_diff; 1938 int best_end, epnum; 1939 struct musb_hw_ep *hw_ep = NULL; 1940 struct list_head *head = NULL; 1941 u8 toggle; 1942 u8 txtype; 1943 struct urb *urb = next_urb(qh); 1944 1945 /* use fixed hardware for control and bulk */ 1946 if (qh->type == USB_ENDPOINT_XFER_CONTROL) { 1947 head = &musb->control; 1948 hw_ep = musb->control_ep; 1949 goto success; 1950 } 1951 1952 /* else, periodic transfers get muxed to other endpoints */ 1953 1954 /* 1955 * We know this qh hasn't been scheduled, so all we need to do 1956 * is choose which hardware endpoint to put it on ... 1957 * 1958 * REVISIT what we really want here is a regular schedule tree 1959 * like e.g. OHCI uses. 1960 */ 1961 best_diff = 4096; 1962 best_end = -1; 1963 1964 for (epnum = 1, hw_ep = musb->endpoints + 1; 1965 epnum < musb->nr_endpoints; 1966 epnum++, hw_ep++) { 1967 int diff; 1968 1969 if (musb_ep_get_qh(hw_ep, is_in) != NULL) 1970 continue; 1971 1972 if (hw_ep == musb->bulk_ep) 1973 continue; 1974 1975 if (is_in) 1976 diff = hw_ep->max_packet_sz_rx; 1977 else 1978 diff = hw_ep->max_packet_sz_tx; 1979 diff -= (qh->maxpacket * qh->hb_mult); 1980 1981 if (diff >= 0 && best_diff > diff) { 1982 1983 /* 1984 * Mentor controller has a bug in that if we schedule 1985 * a BULK Tx transfer on an endpoint that had earlier 1986 * handled ISOC then the BULK transfer has to start on 1987 * a zero toggle. If the BULK transfer starts on a 1 1988 * toggle then this transfer will fail as the mentor 1989 * controller starts the Bulk transfer on a 0 toggle 1990 * irrespective of the programming of the toggle bits 1991 * in the TXCSR register. Check for this condition 1992 * while allocating the EP for a Tx Bulk transfer. If 1993 * so skip this EP. 1994 */ 1995 hw_ep = musb->endpoints + epnum; 1996 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in); 1997 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) 1998 >> 4) & 0x3; 1999 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) && 2000 toggle && (txtype == USB_ENDPOINT_XFER_ISOC)) 2001 continue; 2002 2003 best_diff = diff; 2004 best_end = epnum; 2005 } 2006 } 2007 /* use bulk reserved ep1 if no other ep is free */ 2008 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { 2009 hw_ep = musb->bulk_ep; 2010 if (is_in) 2011 head = &musb->in_bulk; 2012 else 2013 head = &musb->out_bulk; 2014 2015 /* Enable bulk RX/TX NAK timeout scheme when bulk requests are 2016 * multiplexed. This scheme doen't work in high speed to full 2017 * speed scenario as NAK interrupts are not coming from a 2018 * full speed device connected to a high speed device. 2019 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and 2020 * 4 (8 frame or 8ms) for FS device. 2021 */ 2022 if (qh->dev) 2023 qh->intv_reg = 2024 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; 2025 goto success; 2026 } else if (best_end < 0) { 2027 return -ENOSPC; 2028 } 2029 2030 idle = 1; 2031 qh->mux = 0; 2032 hw_ep = musb->endpoints + best_end; 2033 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end); 2034 success: 2035 if (head) { 2036 idle = list_empty(head); 2037 list_add_tail(&qh->ring, head); 2038 qh->mux = 1; 2039 } 2040 qh->hw_ep = hw_ep; 2041 qh->hep->hcpriv = qh; 2042 if (idle) 2043 musb_start_urb(musb, is_in, qh); 2044 return 0; 2045 } 2046 2047 static int musb_urb_enqueue( 2048 struct usb_hcd *hcd, 2049 struct urb *urb, 2050 gfp_t mem_flags) 2051 { 2052 unsigned long flags; 2053 struct musb *musb = hcd_to_musb(hcd); 2054 struct usb_host_endpoint *hep = urb->ep; 2055 struct musb_qh *qh; 2056 struct usb_endpoint_descriptor *epd = &hep->desc; 2057 int ret; 2058 unsigned type_reg; 2059 unsigned interval; 2060 2061 /* host role must be active */ 2062 if (!is_host_active(musb) || !musb->is_active) 2063 return -ENODEV; 2064 2065 spin_lock_irqsave(&musb->lock, flags); 2066 ret = usb_hcd_link_urb_to_ep(hcd, urb); 2067 qh = ret ? NULL : hep->hcpriv; 2068 if (qh) 2069 urb->hcpriv = qh; 2070 spin_unlock_irqrestore(&musb->lock, flags); 2071 2072 /* DMA mapping was already done, if needed, and this urb is on 2073 * hep->urb_list now ... so we're done, unless hep wasn't yet 2074 * scheduled onto a live qh. 2075 * 2076 * REVISIT best to keep hep->hcpriv valid until the endpoint gets 2077 * disabled, testing for empty qh->ring and avoiding qh setup costs 2078 * except for the first urb queued after a config change. 2079 */ 2080 if (qh || ret) 2081 return ret; 2082 2083 /* Allocate and initialize qh, minimizing the work done each time 2084 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. 2085 * 2086 * REVISIT consider a dedicated qh kmem_cache, so it's harder 2087 * for bugs in other kernel code to break this driver... 2088 */ 2089 qh = kzalloc(sizeof *qh, mem_flags); 2090 if (!qh) { 2091 spin_lock_irqsave(&musb->lock, flags); 2092 usb_hcd_unlink_urb_from_ep(hcd, urb); 2093 spin_unlock_irqrestore(&musb->lock, flags); 2094 return -ENOMEM; 2095 } 2096 2097 qh->hep = hep; 2098 qh->dev = urb->dev; 2099 INIT_LIST_HEAD(&qh->ring); 2100 qh->is_ready = 1; 2101 2102 qh->maxpacket = usb_endpoint_maxp(epd); 2103 qh->type = usb_endpoint_type(epd); 2104 2105 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier. 2106 * Some musb cores don't support high bandwidth ISO transfers; and 2107 * we don't (yet!) support high bandwidth interrupt transfers. 2108 */ 2109 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03); 2110 if (qh->hb_mult > 1) { 2111 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC); 2112 2113 if (ok) 2114 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx) 2115 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx); 2116 if (!ok) { 2117 ret = -EMSGSIZE; 2118 goto done; 2119 } 2120 qh->maxpacket &= 0x7ff; 2121 } 2122 2123 qh->epnum = usb_endpoint_num(epd); 2124 2125 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ 2126 qh->addr_reg = (u8) usb_pipedevice(urb->pipe); 2127 2128 /* precompute rxtype/txtype/type0 register */ 2129 type_reg = (qh->type << 4) | qh->epnum; 2130 switch (urb->dev->speed) { 2131 case USB_SPEED_LOW: 2132 type_reg |= 0xc0; 2133 break; 2134 case USB_SPEED_FULL: 2135 type_reg |= 0x80; 2136 break; 2137 default: 2138 type_reg |= 0x40; 2139 } 2140 qh->type_reg = type_reg; 2141 2142 /* Precompute RXINTERVAL/TXINTERVAL register */ 2143 switch (qh->type) { 2144 case USB_ENDPOINT_XFER_INT: 2145 /* 2146 * Full/low speeds use the linear encoding, 2147 * high speed uses the logarithmic encoding. 2148 */ 2149 if (urb->dev->speed <= USB_SPEED_FULL) { 2150 interval = max_t(u8, epd->bInterval, 1); 2151 break; 2152 } 2153 /* FALLTHROUGH */ 2154 case USB_ENDPOINT_XFER_ISOC: 2155 /* ISO always uses logarithmic encoding */ 2156 interval = min_t(u8, epd->bInterval, 16); 2157 break; 2158 default: 2159 /* REVISIT we actually want to use NAK limits, hinting to the 2160 * transfer scheduling logic to try some other qh, e.g. try 2161 * for 2 msec first: 2162 * 2163 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; 2164 * 2165 * The downside of disabling this is that transfer scheduling 2166 * gets VERY unfair for nonperiodic transfers; a misbehaving 2167 * peripheral could make that hurt. That's perfectly normal 2168 * for reads from network or serial adapters ... so we have 2169 * partial NAKlimit support for bulk RX. 2170 * 2171 * The upside of disabling it is simpler transfer scheduling. 2172 */ 2173 interval = 0; 2174 } 2175 qh->intv_reg = interval; 2176 2177 /* precompute addressing for external hub/tt ports */ 2178 if (musb->is_multipoint) { 2179 struct usb_device *parent = urb->dev->parent; 2180 2181 if (parent != hcd->self.root_hub) { 2182 qh->h_addr_reg = (u8) parent->devnum; 2183 2184 /* set up tt info if needed */ 2185 if (urb->dev->tt) { 2186 qh->h_port_reg = (u8) urb->dev->ttport; 2187 if (urb->dev->tt->hub) 2188 qh->h_addr_reg = 2189 (u8) urb->dev->tt->hub->devnum; 2190 if (urb->dev->tt->multi) 2191 qh->h_addr_reg |= 0x80; 2192 } 2193 } 2194 } 2195 2196 /* invariant: hep->hcpriv is null OR the qh that's already scheduled. 2197 * until we get real dma queues (with an entry for each urb/buffer), 2198 * we only have work to do in the former case. 2199 */ 2200 spin_lock_irqsave(&musb->lock, flags); 2201 if (hep->hcpriv || !next_urb(qh)) { 2202 /* some concurrent activity submitted another urb to hep... 2203 * odd, rare, error prone, but legal. 2204 */ 2205 kfree(qh); 2206 qh = NULL; 2207 ret = 0; 2208 } else 2209 ret = musb_schedule(musb, qh, 2210 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); 2211 2212 if (ret == 0) { 2213 urb->hcpriv = qh; 2214 /* FIXME set urb->start_frame for iso/intr, it's tested in 2215 * musb_start_urb(), but otherwise only konicawc cares ... 2216 */ 2217 } 2218 spin_unlock_irqrestore(&musb->lock, flags); 2219 2220 done: 2221 if (ret != 0) { 2222 spin_lock_irqsave(&musb->lock, flags); 2223 usb_hcd_unlink_urb_from_ep(hcd, urb); 2224 spin_unlock_irqrestore(&musb->lock, flags); 2225 kfree(qh); 2226 } 2227 return ret; 2228 } 2229 2230 2231 /* 2232 * abort a transfer that's at the head of a hardware queue. 2233 * called with controller locked, irqs blocked 2234 * that hardware queue advances to the next transfer, unless prevented 2235 */ 2236 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) 2237 { 2238 struct musb_hw_ep *ep = qh->hw_ep; 2239 struct musb *musb = ep->musb; 2240 void __iomem *epio = ep->regs; 2241 unsigned hw_end = ep->epnum; 2242 void __iomem *regs = ep->musb->mregs; 2243 int is_in = usb_pipein(urb->pipe); 2244 int status = 0; 2245 u16 csr; 2246 2247 musb_ep_select(regs, hw_end); 2248 2249 if (is_dma_capable()) { 2250 struct dma_channel *dma; 2251 2252 dma = is_in ? ep->rx_channel : ep->tx_channel; 2253 if (dma) { 2254 status = ep->musb->dma_controller->channel_abort(dma); 2255 dev_dbg(musb->controller, 2256 "abort %cX%d DMA for urb %p --> %d\n", 2257 is_in ? 'R' : 'T', ep->epnum, 2258 urb, status); 2259 urb->actual_length += dma->actual_len; 2260 } 2261 } 2262 2263 /* turn off DMA requests, discard state, stop polling ... */ 2264 if (ep->epnum && is_in) { 2265 /* giveback saves bulk toggle */ 2266 csr = musb_h_flush_rxfifo(ep, 0); 2267 2268 /* REVISIT we still get an irq; should likely clear the 2269 * endpoint's irq status here to avoid bogus irqs. 2270 * clearing that status is platform-specific... 2271 */ 2272 } else if (ep->epnum) { 2273 musb_h_tx_flush_fifo(ep); 2274 csr = musb_readw(epio, MUSB_TXCSR); 2275 csr &= ~(MUSB_TXCSR_AUTOSET 2276 | MUSB_TXCSR_DMAENAB 2277 | MUSB_TXCSR_H_RXSTALL 2278 | MUSB_TXCSR_H_NAKTIMEOUT 2279 | MUSB_TXCSR_H_ERROR 2280 | MUSB_TXCSR_TXPKTRDY); 2281 musb_writew(epio, MUSB_TXCSR, csr); 2282 /* REVISIT may need to clear FLUSHFIFO ... */ 2283 musb_writew(epio, MUSB_TXCSR, csr); 2284 /* flush cpu writebuffer */ 2285 csr = musb_readw(epio, MUSB_TXCSR); 2286 } else { 2287 musb_h_ep0_flush_fifo(ep); 2288 } 2289 if (status == 0) 2290 musb_advance_schedule(ep->musb, urb, ep, is_in); 2291 return status; 2292 } 2293 2294 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 2295 { 2296 struct musb *musb = hcd_to_musb(hcd); 2297 struct musb_qh *qh; 2298 unsigned long flags; 2299 int is_in = usb_pipein(urb->pipe); 2300 int ret; 2301 2302 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb, 2303 usb_pipedevice(urb->pipe), 2304 usb_pipeendpoint(urb->pipe), 2305 is_in ? "in" : "out"); 2306 2307 spin_lock_irqsave(&musb->lock, flags); 2308 ret = usb_hcd_check_unlink_urb(hcd, urb, status); 2309 if (ret) 2310 goto done; 2311 2312 qh = urb->hcpriv; 2313 if (!qh) 2314 goto done; 2315 2316 /* 2317 * Any URB not actively programmed into endpoint hardware can be 2318 * immediately given back; that's any URB not at the head of an 2319 * endpoint queue, unless someday we get real DMA queues. And even 2320 * if it's at the head, it might not be known to the hardware... 2321 * 2322 * Otherwise abort current transfer, pending DMA, etc.; urb->status 2323 * has already been updated. This is a synchronous abort; it'd be 2324 * OK to hold off until after some IRQ, though. 2325 * 2326 * NOTE: qh is invalid unless !list_empty(&hep->urb_list) 2327 */ 2328 if (!qh->is_ready 2329 || urb->urb_list.prev != &qh->hep->urb_list 2330 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) { 2331 int ready = qh->is_ready; 2332 2333 qh->is_ready = 0; 2334 musb_giveback(musb, urb, 0); 2335 qh->is_ready = ready; 2336 2337 /* If nothing else (usually musb_giveback) is using it 2338 * and its URB list has emptied, recycle this qh. 2339 */ 2340 if (ready && list_empty(&qh->hep->urb_list)) { 2341 qh->hep->hcpriv = NULL; 2342 list_del(&qh->ring); 2343 kfree(qh); 2344 } 2345 } else 2346 ret = musb_cleanup_urb(urb, qh); 2347 done: 2348 spin_unlock_irqrestore(&musb->lock, flags); 2349 return ret; 2350 } 2351 2352 /* disable an endpoint */ 2353 static void 2354 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) 2355 { 2356 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN; 2357 unsigned long flags; 2358 struct musb *musb = hcd_to_musb(hcd); 2359 struct musb_qh *qh; 2360 struct urb *urb; 2361 2362 spin_lock_irqsave(&musb->lock, flags); 2363 2364 qh = hep->hcpriv; 2365 if (qh == NULL) 2366 goto exit; 2367 2368 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ 2369 2370 /* Kick the first URB off the hardware, if needed */ 2371 qh->is_ready = 0; 2372 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) { 2373 urb = next_urb(qh); 2374 2375 /* make software (then hardware) stop ASAP */ 2376 if (!urb->unlinked) 2377 urb->status = -ESHUTDOWN; 2378 2379 /* cleanup */ 2380 musb_cleanup_urb(urb, qh); 2381 2382 /* Then nuke all the others ... and advance the 2383 * queue on hw_ep (e.g. bulk ring) when we're done. 2384 */ 2385 while (!list_empty(&hep->urb_list)) { 2386 urb = next_urb(qh); 2387 urb->status = -ESHUTDOWN; 2388 musb_advance_schedule(musb, urb, qh->hw_ep, is_in); 2389 } 2390 } else { 2391 /* Just empty the queue; the hardware is busy with 2392 * other transfers, and since !qh->is_ready nothing 2393 * will activate any of these as it advances. 2394 */ 2395 while (!list_empty(&hep->urb_list)) 2396 musb_giveback(musb, next_urb(qh), -ESHUTDOWN); 2397 2398 hep->hcpriv = NULL; 2399 list_del(&qh->ring); 2400 kfree(qh); 2401 } 2402 exit: 2403 spin_unlock_irqrestore(&musb->lock, flags); 2404 } 2405 2406 static int musb_h_get_frame_number(struct usb_hcd *hcd) 2407 { 2408 struct musb *musb = hcd_to_musb(hcd); 2409 2410 return musb_readw(musb->mregs, MUSB_FRAME); 2411 } 2412 2413 static int musb_h_start(struct usb_hcd *hcd) 2414 { 2415 struct musb *musb = hcd_to_musb(hcd); 2416 2417 /* NOTE: musb_start() is called when the hub driver turns 2418 * on port power, or when (OTG) peripheral starts. 2419 */ 2420 hcd->state = HC_STATE_RUNNING; 2421 musb->port1_status = 0; 2422 return 0; 2423 } 2424 2425 static void musb_h_stop(struct usb_hcd *hcd) 2426 { 2427 musb_stop(hcd_to_musb(hcd)); 2428 hcd->state = HC_STATE_HALT; 2429 } 2430 2431 static int musb_bus_suspend(struct usb_hcd *hcd) 2432 { 2433 struct musb *musb = hcd_to_musb(hcd); 2434 u8 devctl; 2435 2436 if (!is_host_active(musb)) 2437 return 0; 2438 2439 switch (musb->xceiv->state) { 2440 case OTG_STATE_A_SUSPEND: 2441 return 0; 2442 case OTG_STATE_A_WAIT_VRISE: 2443 /* ID could be grounded even if there's no device 2444 * on the other end of the cable. NOTE that the 2445 * A_WAIT_VRISE timers are messy with MUSB... 2446 */ 2447 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2448 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 2449 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 2450 break; 2451 default: 2452 break; 2453 } 2454 2455 if (musb->is_active) { 2456 WARNING("trying to suspend as %s while active\n", 2457 usb_otg_state_string(musb->xceiv->state)); 2458 return -EBUSY; 2459 } else 2460 return 0; 2461 } 2462 2463 static int musb_bus_resume(struct usb_hcd *hcd) 2464 { 2465 /* resuming child port does the work */ 2466 return 0; 2467 } 2468 2469 #ifndef CONFIG_MUSB_PIO_ONLY 2470 2471 #define MUSB_USB_DMA_ALIGN 4 2472 2473 struct musb_temp_buffer { 2474 void *kmalloc_ptr; 2475 void *old_xfer_buffer; 2476 u8 data[0]; 2477 }; 2478 2479 static void musb_free_temp_buffer(struct urb *urb) 2480 { 2481 enum dma_data_direction dir; 2482 struct musb_temp_buffer *temp; 2483 2484 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2485 return; 2486 2487 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 2488 2489 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer, 2490 data); 2491 2492 if (dir == DMA_FROM_DEVICE) { 2493 memcpy(temp->old_xfer_buffer, temp->data, 2494 urb->transfer_buffer_length); 2495 } 2496 urb->transfer_buffer = temp->old_xfer_buffer; 2497 kfree(temp->kmalloc_ptr); 2498 2499 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2500 } 2501 2502 static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) 2503 { 2504 enum dma_data_direction dir; 2505 struct musb_temp_buffer *temp; 2506 void *kmalloc_ptr; 2507 size_t kmalloc_size; 2508 2509 if (urb->num_sgs || urb->sg || 2510 urb->transfer_buffer_length == 0 || 2511 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1))) 2512 return 0; 2513 2514 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 2515 2516 /* Allocate a buffer with enough padding for alignment */ 2517 kmalloc_size = urb->transfer_buffer_length + 2518 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1; 2519 2520 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2521 if (!kmalloc_ptr) 2522 return -ENOMEM; 2523 2524 /* Position our struct temp_buffer such that data is aligned */ 2525 temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN); 2526 2527 2528 temp->kmalloc_ptr = kmalloc_ptr; 2529 temp->old_xfer_buffer = urb->transfer_buffer; 2530 if (dir == DMA_TO_DEVICE) 2531 memcpy(temp->data, urb->transfer_buffer, 2532 urb->transfer_buffer_length); 2533 urb->transfer_buffer = temp->data; 2534 2535 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2536 2537 return 0; 2538 } 2539 2540 static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2541 gfp_t mem_flags) 2542 { 2543 struct musb *musb = hcd_to_musb(hcd); 2544 int ret; 2545 2546 /* 2547 * The DMA engine in RTL1.8 and above cannot handle 2548 * DMA addresses that are not aligned to a 4 byte boundary. 2549 * For such engine implemented (un)map_urb_for_dma hooks. 2550 * Do not use these hooks for RTL<1.8 2551 */ 2552 if (musb->hwvers < MUSB_HWVERS_1800) 2553 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2554 2555 ret = musb_alloc_temp_buffer(urb, mem_flags); 2556 if (ret) 2557 return ret; 2558 2559 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2560 if (ret) 2561 musb_free_temp_buffer(urb); 2562 2563 return ret; 2564 } 2565 2566 static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2567 { 2568 struct musb *musb = hcd_to_musb(hcd); 2569 2570 usb_hcd_unmap_urb_for_dma(hcd, urb); 2571 2572 /* Do not use this hook for RTL<1.8 (see description above) */ 2573 if (musb->hwvers < MUSB_HWVERS_1800) 2574 return; 2575 2576 musb_free_temp_buffer(urb); 2577 } 2578 #endif /* !CONFIG_MUSB_PIO_ONLY */ 2579 2580 static const struct hc_driver musb_hc_driver = { 2581 .description = "musb-hcd", 2582 .product_desc = "MUSB HDRC host driver", 2583 .hcd_priv_size = sizeof(struct musb *), 2584 .flags = HCD_USB2 | HCD_MEMORY, 2585 2586 /* not using irq handler or reset hooks from usbcore, since 2587 * those must be shared with peripheral code for OTG configs 2588 */ 2589 2590 .start = musb_h_start, 2591 .stop = musb_h_stop, 2592 2593 .get_frame_number = musb_h_get_frame_number, 2594 2595 .urb_enqueue = musb_urb_enqueue, 2596 .urb_dequeue = musb_urb_dequeue, 2597 .endpoint_disable = musb_h_disable, 2598 2599 #ifndef CONFIG_MUSB_PIO_ONLY 2600 .map_urb_for_dma = musb_map_urb_for_dma, 2601 .unmap_urb_for_dma = musb_unmap_urb_for_dma, 2602 #endif 2603 2604 .hub_status_data = musb_hub_status_data, 2605 .hub_control = musb_hub_control, 2606 .bus_suspend = musb_bus_suspend, 2607 .bus_resume = musb_bus_resume, 2608 /* .start_port_reset = NULL, */ 2609 /* .hub_irq_enable = NULL, */ 2610 }; 2611 2612 int musb_host_alloc(struct musb *musb) 2613 { 2614 struct device *dev = musb->controller; 2615 2616 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ 2617 musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); 2618 if (!musb->hcd) 2619 return -EINVAL; 2620 2621 *musb->hcd->hcd_priv = (unsigned long) musb; 2622 musb->hcd->self.uses_pio_for_control = 1; 2623 musb->hcd->uses_new_polling = 1; 2624 musb->hcd->has_tt = 1; 2625 2626 return 0; 2627 } 2628 2629 void musb_host_cleanup(struct musb *musb) 2630 { 2631 if (musb->port_mode == MUSB_PORT_MODE_GADGET) 2632 return; 2633 usb_remove_hcd(musb->hcd); 2634 musb->hcd = NULL; 2635 } 2636 2637 void musb_host_free(struct musb *musb) 2638 { 2639 usb_put_hcd(musb->hcd); 2640 } 2641 2642 int musb_host_setup(struct musb *musb, int power_budget) 2643 { 2644 int ret; 2645 struct usb_hcd *hcd = musb->hcd; 2646 2647 MUSB_HST_MODE(musb); 2648 musb->xceiv->otg->default_a = 1; 2649 musb->xceiv->state = OTG_STATE_A_IDLE; 2650 2651 otg_set_host(musb->xceiv->otg, &hcd->self); 2652 hcd->self.otg_port = 1; 2653 musb->xceiv->otg->host = &hcd->self; 2654 hcd->power_budget = 2 * (power_budget ? : 250); 2655 2656 ret = usb_add_hcd(hcd, 0, 0); 2657 if (ret < 0) 2658 return ret; 2659 2660 return 0; 2661 } 2662 2663 void musb_host_resume_root_hub(struct musb *musb) 2664 { 2665 usb_hcd_resume_root_hub(musb->hcd); 2666 } 2667 2668 void musb_host_poke_root_hub(struct musb *musb) 2669 { 2670 MUSB_HST_MODE(musb); 2671 if (musb->hcd->status_urb) 2672 usb_hcd_poll_rh_status(musb->hcd); 2673 else 2674 usb_hcd_resume_root_hub(musb->hcd); 2675 } 2676