1 /* 2 * MUSB OTG driver peripheral support 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <linux/kernel.h> 37 #include <linux/list.h> 38 #include <linux/timer.h> 39 #include <linux/module.h> 40 #include <linux/smp.h> 41 #include <linux/spinlock.h> 42 #include <linux/delay.h> 43 #include <linux/moduleparam.h> 44 #include <linux/stat.h> 45 #include <linux/dma-mapping.h> 46 47 #include "musb_core.h" 48 49 50 /* MUSB PERIPHERAL status 3-mar-2006: 51 * 52 * - EP0 seems solid. It passes both USBCV and usbtest control cases. 53 * Minor glitches: 54 * 55 * + remote wakeup to Linux hosts work, but saw USBCV failures; 56 * in one test run (operator error?) 57 * + endpoint halt tests -- in both usbtest and usbcv -- seem 58 * to break when dma is enabled ... is something wrongly 59 * clearing SENDSTALL? 60 * 61 * - Mass storage behaved ok when last tested. Network traffic patterns 62 * (with lots of short transfers etc) need retesting; they turn up the 63 * worst cases of the DMA, since short packets are typical but are not 64 * required. 65 * 66 * - TX/IN 67 * + both pio and dma behave in with network and g_zero tests 68 * + no cppi throughput issues other than no-hw-queueing 69 * + failed with FLAT_REG (DaVinci) 70 * + seems to behave with double buffering, PIO -and- CPPI 71 * + with gadgetfs + AIO, requests got lost? 72 * 73 * - RX/OUT 74 * + both pio and dma behave in with network and g_zero tests 75 * + dma is slow in typical case (short_not_ok is clear) 76 * + double buffering ok with PIO 77 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes 78 * + request lossage observed with gadgetfs 79 * 80 * - ISO not tested ... might work, but only weakly isochronous 81 * 82 * - Gadget driver disabling of softconnect during bind() is ignored; so 83 * drivers can't hold off host requests until userspace is ready. 84 * (Workaround: they can turn it off later.) 85 * 86 * - PORTABILITY (assumes PIO works): 87 * + DaVinci, basically works with cppi dma 88 * + OMAP 2430, ditto with mentor dma 89 * + TUSB 6010, platform-specific dma in the works 90 */ 91 92 /* ----------------------------------------------------------------------- */ 93 94 /* 95 * Immediately complete a request. 96 * 97 * @param request the request to complete 98 * @param status the status to complete the request with 99 * Context: controller locked, IRQs blocked. 100 */ 101 void musb_g_giveback( 102 struct musb_ep *ep, 103 struct usb_request *request, 104 int status) 105 __releases(ep->musb->lock) 106 __acquires(ep->musb->lock) 107 { 108 struct musb_request *req; 109 struct musb *musb; 110 int busy = ep->busy; 111 112 req = to_musb_request(request); 113 114 list_del(&request->list); 115 if (req->request.status == -EINPROGRESS) 116 req->request.status = status; 117 musb = req->musb; 118 119 ep->busy = 1; 120 spin_unlock(&musb->lock); 121 if (is_dma_capable()) { 122 if (req->mapped) { 123 dma_unmap_single(musb->controller, 124 req->request.dma, 125 req->request.length, 126 req->tx 127 ? DMA_TO_DEVICE 128 : DMA_FROM_DEVICE); 129 req->request.dma = DMA_ADDR_INVALID; 130 req->mapped = 0; 131 } else if (req->request.dma != DMA_ADDR_INVALID) 132 dma_sync_single_for_cpu(musb->controller, 133 req->request.dma, 134 req->request.length, 135 req->tx 136 ? DMA_TO_DEVICE 137 : DMA_FROM_DEVICE); 138 } 139 if (request->status == 0) 140 DBG(5, "%s done request %p, %d/%d\n", 141 ep->end_point.name, request, 142 req->request.actual, req->request.length); 143 else 144 DBG(2, "%s request %p, %d/%d fault %d\n", 145 ep->end_point.name, request, 146 req->request.actual, req->request.length, 147 request->status); 148 req->request.complete(&req->ep->end_point, &req->request); 149 spin_lock(&musb->lock); 150 ep->busy = busy; 151 } 152 153 /* ----------------------------------------------------------------------- */ 154 155 /* 156 * Abort requests queued to an endpoint using the status. Synchronous. 157 * caller locked controller and blocked irqs, and selected this ep. 158 */ 159 static void nuke(struct musb_ep *ep, const int status) 160 { 161 struct musb_request *req = NULL; 162 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; 163 164 ep->busy = 1; 165 166 if (is_dma_capable() && ep->dma) { 167 struct dma_controller *c = ep->musb->dma_controller; 168 int value; 169 170 if (ep->is_in) { 171 /* 172 * The programming guide says that we must not clear 173 * the DMAMODE bit before DMAENAB, so we only 174 * clear it in the second write... 175 */ 176 musb_writew(epio, MUSB_TXCSR, 177 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); 178 musb_writew(epio, MUSB_TXCSR, 179 0 | MUSB_TXCSR_FLUSHFIFO); 180 } else { 181 musb_writew(epio, MUSB_RXCSR, 182 0 | MUSB_RXCSR_FLUSHFIFO); 183 musb_writew(epio, MUSB_RXCSR, 184 0 | MUSB_RXCSR_FLUSHFIFO); 185 } 186 187 value = c->channel_abort(ep->dma); 188 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value); 189 c->channel_release(ep->dma); 190 ep->dma = NULL; 191 } 192 193 while (!list_empty(&(ep->req_list))) { 194 req = container_of(ep->req_list.next, struct musb_request, 195 request.list); 196 musb_g_giveback(ep, &req->request, status); 197 } 198 } 199 200 /* ----------------------------------------------------------------------- */ 201 202 /* Data transfers - pure PIO, pure DMA, or mixed mode */ 203 204 /* 205 * This assumes the separate CPPI engine is responding to DMA requests 206 * from the usb core ... sequenced a bit differently from mentor dma. 207 */ 208 209 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) 210 { 211 if (can_bulk_split(musb, ep->type)) 212 return ep->hw_ep->max_packet_sz_tx; 213 else 214 return ep->packet_sz; 215 } 216 217 218 #ifdef CONFIG_USB_INVENTRA_DMA 219 220 /* Peripheral tx (IN) using Mentor DMA works as follows: 221 Only mode 0 is used for transfers <= wPktSize, 222 mode 1 is used for larger transfers, 223 224 One of the following happens: 225 - Host sends IN token which causes an endpoint interrupt 226 -> TxAvail 227 -> if DMA is currently busy, exit. 228 -> if queue is non-empty, txstate(). 229 230 - Request is queued by the gadget driver. 231 -> if queue was previously empty, txstate() 232 233 txstate() 234 -> start 235 /\ -> setup DMA 236 | (data is transferred to the FIFO, then sent out when 237 | IN token(s) are recd from Host. 238 | -> DMA interrupt on completion 239 | calls TxAvail. 240 | -> stop DMA, ~DMAENAB, 241 | -> set TxPktRdy for last short pkt or zlp 242 | -> Complete Request 243 | -> Continue next request (call txstate) 244 |___________________________________| 245 246 * Non-Mentor DMA engines can of course work differently, such as by 247 * upleveling from irq-per-packet to irq-per-buffer. 248 */ 249 250 #endif 251 252 /* 253 * An endpoint is transmitting data. This can be called either from 254 * the IRQ routine or from ep.queue() to kickstart a request on an 255 * endpoint. 256 * 257 * Context: controller locked, IRQs blocked, endpoint selected 258 */ 259 static void txstate(struct musb *musb, struct musb_request *req) 260 { 261 u8 epnum = req->epnum; 262 struct musb_ep *musb_ep; 263 void __iomem *epio = musb->endpoints[epnum].regs; 264 struct usb_request *request; 265 u16 fifo_count = 0, csr; 266 int use_dma = 0; 267 268 musb_ep = req->ep; 269 270 /* we shouldn't get here while DMA is active ... but we do ... */ 271 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 272 DBG(4, "dma pending...\n"); 273 return; 274 } 275 276 /* read TXCSR before */ 277 csr = musb_readw(epio, MUSB_TXCSR); 278 279 request = &req->request; 280 fifo_count = min(max_ep_writesize(musb, musb_ep), 281 (int)(request->length - request->actual)); 282 283 if (csr & MUSB_TXCSR_TXPKTRDY) { 284 DBG(5, "%s old packet still ready , txcsr %03x\n", 285 musb_ep->end_point.name, csr); 286 return; 287 } 288 289 if (csr & MUSB_TXCSR_P_SENDSTALL) { 290 DBG(5, "%s stalling, txcsr %03x\n", 291 musb_ep->end_point.name, csr); 292 return; 293 } 294 295 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", 296 epnum, musb_ep->packet_sz, fifo_count, 297 csr); 298 299 #ifndef CONFIG_MUSB_PIO_ONLY 300 if (is_dma_capable() && musb_ep->dma) { 301 struct dma_controller *c = musb->dma_controller; 302 303 use_dma = (request->dma != DMA_ADDR_INVALID); 304 305 /* MUSB_TXCSR_P_ISO is still set correctly */ 306 307 #ifdef CONFIG_USB_INVENTRA_DMA 308 { 309 size_t request_size; 310 311 /* setup DMA, then program endpoint CSR */ 312 request_size = min_t(size_t, request->length, 313 musb_ep->dma->max_len); 314 if (request_size < musb_ep->packet_sz) 315 musb_ep->dma->desired_mode = 0; 316 else 317 musb_ep->dma->desired_mode = 1; 318 319 use_dma = use_dma && c->channel_program( 320 musb_ep->dma, musb_ep->packet_sz, 321 musb_ep->dma->desired_mode, 322 request->dma + request->actual, request_size); 323 if (use_dma) { 324 if (musb_ep->dma->desired_mode == 0) { 325 /* 326 * We must not clear the DMAMODE bit 327 * before the DMAENAB bit -- and the 328 * latter doesn't always get cleared 329 * before we get here... 330 */ 331 csr &= ~(MUSB_TXCSR_AUTOSET 332 | MUSB_TXCSR_DMAENAB); 333 musb_writew(epio, MUSB_TXCSR, csr 334 | MUSB_TXCSR_P_WZC_BITS); 335 csr &= ~MUSB_TXCSR_DMAMODE; 336 csr |= (MUSB_TXCSR_DMAENAB | 337 MUSB_TXCSR_MODE); 338 /* against programming guide */ 339 } else 340 csr |= (MUSB_TXCSR_AUTOSET 341 | MUSB_TXCSR_DMAENAB 342 | MUSB_TXCSR_DMAMODE 343 | MUSB_TXCSR_MODE); 344 345 csr &= ~MUSB_TXCSR_P_UNDERRUN; 346 musb_writew(epio, MUSB_TXCSR, csr); 347 } 348 } 349 350 #elif defined(CONFIG_USB_TI_CPPI_DMA) 351 /* program endpoint CSR first, then setup DMA */ 352 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 353 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | 354 MUSB_TXCSR_MODE; 355 musb_writew(epio, MUSB_TXCSR, 356 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN) 357 | csr); 358 359 /* ensure writebuffer is empty */ 360 csr = musb_readw(epio, MUSB_TXCSR); 361 362 /* NOTE host side sets DMAENAB later than this; both are 363 * OK since the transfer dma glue (between CPPI and Mentor 364 * fifos) just tells CPPI it could start. Data only moves 365 * to the USB TX fifo when both fifos are ready. 366 */ 367 368 /* "mode" is irrelevant here; handle terminating ZLPs like 369 * PIO does, since the hardware RNDIS mode seems unreliable 370 * except for the last-packet-is-already-short case. 371 */ 372 use_dma = use_dma && c->channel_program( 373 musb_ep->dma, musb_ep->packet_sz, 374 0, 375 request->dma, 376 request->length); 377 if (!use_dma) { 378 c->channel_release(musb_ep->dma); 379 musb_ep->dma = NULL; 380 csr &= ~MUSB_TXCSR_DMAENAB; 381 musb_writew(epio, MUSB_TXCSR, csr); 382 /* invariant: prequest->buf is non-null */ 383 } 384 #elif defined(CONFIG_USB_TUSB_OMAP_DMA) 385 use_dma = use_dma && c->channel_program( 386 musb_ep->dma, musb_ep->packet_sz, 387 request->zero, 388 request->dma, 389 request->length); 390 #endif 391 } 392 #endif 393 394 if (!use_dma) { 395 musb_write_fifo(musb_ep->hw_ep, fifo_count, 396 (u8 *) (request->buf + request->actual)); 397 request->actual += fifo_count; 398 csr |= MUSB_TXCSR_TXPKTRDY; 399 csr &= ~MUSB_TXCSR_P_UNDERRUN; 400 musb_writew(epio, MUSB_TXCSR, csr); 401 } 402 403 /* host may already have the data when this message shows... */ 404 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", 405 musb_ep->end_point.name, use_dma ? "dma" : "pio", 406 request->actual, request->length, 407 musb_readw(epio, MUSB_TXCSR), 408 fifo_count, 409 musb_readw(epio, MUSB_TXMAXP)); 410 } 411 412 /* 413 * FIFO state update (e.g. data ready). 414 * Called from IRQ, with controller locked. 415 */ 416 void musb_g_tx(struct musb *musb, u8 epnum) 417 { 418 u16 csr; 419 struct usb_request *request; 420 u8 __iomem *mbase = musb->mregs; 421 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; 422 void __iomem *epio = musb->endpoints[epnum].regs; 423 struct dma_channel *dma; 424 425 musb_ep_select(mbase, epnum); 426 request = next_request(musb_ep); 427 428 csr = musb_readw(epio, MUSB_TXCSR); 429 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); 430 431 dma = is_dma_capable() ? musb_ep->dma : NULL; 432 433 /* 434 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX 435 * probably rates reporting as a host error. 436 */ 437 if (csr & MUSB_TXCSR_P_SENTSTALL) { 438 csr |= MUSB_TXCSR_P_WZC_BITS; 439 csr &= ~MUSB_TXCSR_P_SENTSTALL; 440 musb_writew(epio, MUSB_TXCSR, csr); 441 return; 442 } 443 444 if (csr & MUSB_TXCSR_P_UNDERRUN) { 445 /* We NAKed, no big deal... little reason to care. */ 446 csr |= MUSB_TXCSR_P_WZC_BITS; 447 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 448 musb_writew(epio, MUSB_TXCSR, csr); 449 DBG(20, "underrun on ep%d, req %p\n", epnum, request); 450 } 451 452 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 453 /* 454 * SHOULD NOT HAPPEN... has with CPPI though, after 455 * changing SENDSTALL (and other cases); harmless? 456 */ 457 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name); 458 return; 459 } 460 461 if (request) { 462 u8 is_dma = 0; 463 464 if (dma && (csr & MUSB_TXCSR_DMAENAB)) { 465 is_dma = 1; 466 csr |= MUSB_TXCSR_P_WZC_BITS; 467 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | 468 MUSB_TXCSR_TXPKTRDY); 469 musb_writew(epio, MUSB_TXCSR, csr); 470 /* Ensure writebuffer is empty. */ 471 csr = musb_readw(epio, MUSB_TXCSR); 472 request->actual += musb_ep->dma->actual_len; 473 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n", 474 epnum, csr, musb_ep->dma->actual_len, request); 475 } 476 477 if (is_dma || request->actual == request->length) { 478 /* 479 * First, maybe a terminating short packet. Some DMA 480 * engines might handle this by themselves. 481 */ 482 if ((request->zero && request->length 483 && request->length % musb_ep->packet_sz == 0) 484 #ifdef CONFIG_USB_INVENTRA_DMA 485 || (is_dma && (!dma->desired_mode || 486 (request->actual & 487 (musb_ep->packet_sz - 1)))) 488 #endif 489 ) { 490 /* 491 * On DMA completion, FIFO may not be 492 * available yet... 493 */ 494 if (csr & MUSB_TXCSR_TXPKTRDY) 495 return; 496 497 DBG(4, "sending zero pkt\n"); 498 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE 499 | MUSB_TXCSR_TXPKTRDY); 500 request->zero = 0; 501 } 502 503 /* ... or if not, then complete it. */ 504 musb_g_giveback(musb_ep, request, 0); 505 506 /* 507 * Kickstart next transfer if appropriate; 508 * the packet that just completed might not 509 * be transmitted for hours or days. 510 * REVISIT for double buffering... 511 * FIXME revisit for stalls too... 512 */ 513 musb_ep_select(mbase, epnum); 514 csr = musb_readw(epio, MUSB_TXCSR); 515 if (csr & MUSB_TXCSR_FIFONOTEMPTY) 516 return; 517 518 request = musb_ep->desc ? next_request(musb_ep) : NULL; 519 if (!request) { 520 DBG(4, "%s idle now\n", 521 musb_ep->end_point.name); 522 return; 523 } 524 } 525 526 txstate(musb, to_musb_request(request)); 527 } 528 } 529 530 /* ------------------------------------------------------------ */ 531 532 #ifdef CONFIG_USB_INVENTRA_DMA 533 534 /* Peripheral rx (OUT) using Mentor DMA works as follows: 535 - Only mode 0 is used. 536 537 - Request is queued by the gadget class driver. 538 -> if queue was previously empty, rxstate() 539 540 - Host sends OUT token which causes an endpoint interrupt 541 /\ -> RxReady 542 | -> if request queued, call rxstate 543 | /\ -> setup DMA 544 | | -> DMA interrupt on completion 545 | | -> RxReady 546 | | -> stop DMA 547 | | -> ack the read 548 | | -> if data recd = max expected 549 | | by the request, or host 550 | | sent a short packet, 551 | | complete the request, 552 | | and start the next one. 553 | |_____________________________________| 554 | else just wait for the host 555 | to send the next OUT token. 556 |__________________________________________________| 557 558 * Non-Mentor DMA engines can of course work differently. 559 */ 560 561 #endif 562 563 /* 564 * Context: controller locked, IRQs blocked, endpoint selected 565 */ 566 static void rxstate(struct musb *musb, struct musb_request *req) 567 { 568 const u8 epnum = req->epnum; 569 struct usb_request *request = &req->request; 570 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out; 571 void __iomem *epio = musb->endpoints[epnum].regs; 572 unsigned fifo_count = 0; 573 u16 len = musb_ep->packet_sz; 574 u16 csr = musb_readw(epio, MUSB_RXCSR); 575 576 /* We shouldn't get here while DMA is active, but we do... */ 577 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 578 DBG(4, "DMA pending...\n"); 579 return; 580 } 581 582 if (csr & MUSB_RXCSR_P_SENDSTALL) { 583 DBG(5, "%s stalling, RXCSR %04x\n", 584 musb_ep->end_point.name, csr); 585 return; 586 } 587 588 if (is_cppi_enabled() && musb_ep->dma) { 589 struct dma_controller *c = musb->dma_controller; 590 struct dma_channel *channel = musb_ep->dma; 591 592 /* NOTE: CPPI won't actually stop advancing the DMA 593 * queue after short packet transfers, so this is almost 594 * always going to run as IRQ-per-packet DMA so that 595 * faults will be handled correctly. 596 */ 597 if (c->channel_program(channel, 598 musb_ep->packet_sz, 599 !request->short_not_ok, 600 request->dma + request->actual, 601 request->length - request->actual)) { 602 603 /* make sure that if an rxpkt arrived after the irq, 604 * the cppi engine will be ready to take it as soon 605 * as DMA is enabled 606 */ 607 csr &= ~(MUSB_RXCSR_AUTOCLEAR 608 | MUSB_RXCSR_DMAMODE); 609 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; 610 musb_writew(epio, MUSB_RXCSR, csr); 611 return; 612 } 613 } 614 615 if (csr & MUSB_RXCSR_RXPKTRDY) { 616 len = musb_readw(epio, MUSB_RXCOUNT); 617 if (request->actual < request->length) { 618 #ifdef CONFIG_USB_INVENTRA_DMA 619 if (is_dma_capable() && musb_ep->dma) { 620 struct dma_controller *c; 621 struct dma_channel *channel; 622 int use_dma = 0; 623 624 c = musb->dma_controller; 625 channel = musb_ep->dma; 626 627 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in 628 * mode 0 only. So we do not get endpoint interrupts due to DMA 629 * completion. We only get interrupts from DMA controller. 630 * 631 * We could operate in DMA mode 1 if we knew the size of the tranfer 632 * in advance. For mass storage class, request->length = what the host 633 * sends, so that'd work. But for pretty much everything else, 634 * request->length is routinely more than what the host sends. For 635 * most these gadgets, end of is signified either by a short packet, 636 * or filling the last byte of the buffer. (Sending extra data in 637 * that last pckate should trigger an overflow fault.) But in mode 1, 638 * we don't get DMA completion interrrupt for short packets. 639 * 640 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), 641 * to get endpoint interrupt on every DMA req, but that didn't seem 642 * to work reliably. 643 * 644 * REVISIT an updated g_file_storage can set req->short_not_ok, which 645 * then becomes usable as a runtime "use mode 1" hint... 646 */ 647 648 csr |= MUSB_RXCSR_DMAENAB; 649 #ifdef USE_MODE1 650 csr |= MUSB_RXCSR_AUTOCLEAR; 651 /* csr |= MUSB_RXCSR_DMAMODE; */ 652 653 /* this special sequence (enabling and then 654 * disabling MUSB_RXCSR_DMAMODE) is required 655 * to get DMAReq to activate 656 */ 657 musb_writew(epio, MUSB_RXCSR, 658 csr | MUSB_RXCSR_DMAMODE); 659 #endif 660 musb_writew(epio, MUSB_RXCSR, csr); 661 662 if (request->actual < request->length) { 663 int transfer_size = 0; 664 #ifdef USE_MODE1 665 transfer_size = min(request->length, 666 channel->max_len); 667 #else 668 transfer_size = len; 669 #endif 670 if (transfer_size <= musb_ep->packet_sz) 671 musb_ep->dma->desired_mode = 0; 672 else 673 musb_ep->dma->desired_mode = 1; 674 675 use_dma = c->channel_program( 676 channel, 677 musb_ep->packet_sz, 678 channel->desired_mode, 679 request->dma 680 + request->actual, 681 transfer_size); 682 } 683 684 if (use_dma) 685 return; 686 } 687 #endif /* Mentor's DMA */ 688 689 fifo_count = request->length - request->actual; 690 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", 691 musb_ep->end_point.name, 692 len, fifo_count, 693 musb_ep->packet_sz); 694 695 fifo_count = min_t(unsigned, len, fifo_count); 696 697 #ifdef CONFIG_USB_TUSB_OMAP_DMA 698 if (tusb_dma_omap() && musb_ep->dma) { 699 struct dma_controller *c = musb->dma_controller; 700 struct dma_channel *channel = musb_ep->dma; 701 u32 dma_addr = request->dma + request->actual; 702 int ret; 703 704 ret = c->channel_program(channel, 705 musb_ep->packet_sz, 706 channel->desired_mode, 707 dma_addr, 708 fifo_count); 709 if (ret) 710 return; 711 } 712 #endif 713 714 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) 715 (request->buf + request->actual)); 716 request->actual += fifo_count; 717 718 /* REVISIT if we left anything in the fifo, flush 719 * it and report -EOVERFLOW 720 */ 721 722 /* ack the read! */ 723 csr |= MUSB_RXCSR_P_WZC_BITS; 724 csr &= ~MUSB_RXCSR_RXPKTRDY; 725 musb_writew(epio, MUSB_RXCSR, csr); 726 } 727 } 728 729 /* reach the end or short packet detected */ 730 if (request->actual == request->length || len < musb_ep->packet_sz) 731 musb_g_giveback(musb_ep, request, 0); 732 } 733 734 /* 735 * Data ready for a request; called from IRQ 736 */ 737 void musb_g_rx(struct musb *musb, u8 epnum) 738 { 739 u16 csr; 740 struct usb_request *request; 741 void __iomem *mbase = musb->mregs; 742 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out; 743 void __iomem *epio = musb->endpoints[epnum].regs; 744 struct dma_channel *dma; 745 746 musb_ep_select(mbase, epnum); 747 748 request = next_request(musb_ep); 749 if (!request) 750 return; 751 752 csr = musb_readw(epio, MUSB_RXCSR); 753 dma = is_dma_capable() ? musb_ep->dma : NULL; 754 755 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, 756 csr, dma ? " (dma)" : "", request); 757 758 if (csr & MUSB_RXCSR_P_SENTSTALL) { 759 csr |= MUSB_RXCSR_P_WZC_BITS; 760 csr &= ~MUSB_RXCSR_P_SENTSTALL; 761 musb_writew(epio, MUSB_RXCSR, csr); 762 return; 763 } 764 765 if (csr & MUSB_RXCSR_P_OVERRUN) { 766 /* csr |= MUSB_RXCSR_P_WZC_BITS; */ 767 csr &= ~MUSB_RXCSR_P_OVERRUN; 768 musb_writew(epio, MUSB_RXCSR, csr); 769 770 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request); 771 if (request && request->status == -EINPROGRESS) 772 request->status = -EOVERFLOW; 773 } 774 if (csr & MUSB_RXCSR_INCOMPRX) { 775 /* REVISIT not necessarily an error */ 776 DBG(4, "%s, incomprx\n", musb_ep->end_point.name); 777 } 778 779 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 780 /* "should not happen"; likely RXPKTRDY pending for DMA */ 781 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1, 782 "%s busy, csr %04x\n", 783 musb_ep->end_point.name, csr); 784 return; 785 } 786 787 if (dma && (csr & MUSB_RXCSR_DMAENAB)) { 788 csr &= ~(MUSB_RXCSR_AUTOCLEAR 789 | MUSB_RXCSR_DMAENAB 790 | MUSB_RXCSR_DMAMODE); 791 musb_writew(epio, MUSB_RXCSR, 792 MUSB_RXCSR_P_WZC_BITS | csr); 793 794 request->actual += musb_ep->dma->actual_len; 795 796 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", 797 epnum, csr, 798 musb_readw(epio, MUSB_RXCSR), 799 musb_ep->dma->actual_len, request); 800 801 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) 802 /* Autoclear doesn't clear RxPktRdy for short packets */ 803 if ((dma->desired_mode == 0) 804 || (dma->actual_len 805 & (musb_ep->packet_sz - 1))) { 806 /* ack the read! */ 807 csr &= ~MUSB_RXCSR_RXPKTRDY; 808 musb_writew(epio, MUSB_RXCSR, csr); 809 } 810 811 /* incomplete, and not short? wait for next IN packet */ 812 if ((request->actual < request->length) 813 && (musb_ep->dma->actual_len 814 == musb_ep->packet_sz)) 815 return; 816 #endif 817 musb_g_giveback(musb_ep, request, 0); 818 819 request = next_request(musb_ep); 820 if (!request) 821 return; 822 } 823 824 /* analyze request if the ep is hot */ 825 if (request) 826 rxstate(musb, to_musb_request(request)); 827 else 828 DBG(3, "packet waiting for %s%s request\n", 829 musb_ep->desc ? "" : "inactive ", 830 musb_ep->end_point.name); 831 return; 832 } 833 834 /* ------------------------------------------------------------ */ 835 836 static int musb_gadget_enable(struct usb_ep *ep, 837 const struct usb_endpoint_descriptor *desc) 838 { 839 unsigned long flags; 840 struct musb_ep *musb_ep; 841 struct musb_hw_ep *hw_ep; 842 void __iomem *regs; 843 struct musb *musb; 844 void __iomem *mbase; 845 u8 epnum; 846 u16 csr; 847 unsigned tmp; 848 int status = -EINVAL; 849 850 if (!ep || !desc) 851 return -EINVAL; 852 853 musb_ep = to_musb_ep(ep); 854 hw_ep = musb_ep->hw_ep; 855 regs = hw_ep->regs; 856 musb = musb_ep->musb; 857 mbase = musb->mregs; 858 epnum = musb_ep->current_epnum; 859 860 spin_lock_irqsave(&musb->lock, flags); 861 862 if (musb_ep->desc) { 863 status = -EBUSY; 864 goto fail; 865 } 866 musb_ep->type = usb_endpoint_type(desc); 867 868 /* check direction and (later) maxpacket size against endpoint */ 869 if (usb_endpoint_num(desc) != epnum) 870 goto fail; 871 872 /* REVISIT this rules out high bandwidth periodic transfers */ 873 tmp = le16_to_cpu(desc->wMaxPacketSize); 874 if (tmp & ~0x07ff) 875 goto fail; 876 musb_ep->packet_sz = tmp; 877 878 /* enable the interrupts for the endpoint, set the endpoint 879 * packet size (or fail), set the mode, clear the fifo 880 */ 881 musb_ep_select(mbase, epnum); 882 if (usb_endpoint_dir_in(desc)) { 883 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE); 884 885 if (hw_ep->is_shared_fifo) 886 musb_ep->is_in = 1; 887 if (!musb_ep->is_in) 888 goto fail; 889 if (tmp > hw_ep->max_packet_sz_tx) 890 goto fail; 891 892 int_txe |= (1 << epnum); 893 musb_writew(mbase, MUSB_INTRTXE, int_txe); 894 895 /* REVISIT if can_bulk_split(), use by updating "tmp"; 896 * likewise high bandwidth periodic tx 897 */ 898 musb_writew(regs, MUSB_TXMAXP, tmp); 899 900 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; 901 if (musb_readw(regs, MUSB_TXCSR) 902 & MUSB_TXCSR_FIFONOTEMPTY) 903 csr |= MUSB_TXCSR_FLUSHFIFO; 904 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) 905 csr |= MUSB_TXCSR_P_ISO; 906 907 /* set twice in case of double buffering */ 908 musb_writew(regs, MUSB_TXCSR, csr); 909 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ 910 musb_writew(regs, MUSB_TXCSR, csr); 911 912 } else { 913 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE); 914 915 if (hw_ep->is_shared_fifo) 916 musb_ep->is_in = 0; 917 if (musb_ep->is_in) 918 goto fail; 919 if (tmp > hw_ep->max_packet_sz_rx) 920 goto fail; 921 922 int_rxe |= (1 << epnum); 923 musb_writew(mbase, MUSB_INTRRXE, int_rxe); 924 925 /* REVISIT if can_bulk_combine() use by updating "tmp" 926 * likewise high bandwidth periodic rx 927 */ 928 musb_writew(regs, MUSB_RXMAXP, tmp); 929 930 /* force shared fifo to OUT-only mode */ 931 if (hw_ep->is_shared_fifo) { 932 csr = musb_readw(regs, MUSB_TXCSR); 933 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); 934 musb_writew(regs, MUSB_TXCSR, csr); 935 } 936 937 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; 938 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) 939 csr |= MUSB_RXCSR_P_ISO; 940 else if (musb_ep->type == USB_ENDPOINT_XFER_INT) 941 csr |= MUSB_RXCSR_DISNYET; 942 943 /* set twice in case of double buffering */ 944 musb_writew(regs, MUSB_RXCSR, csr); 945 musb_writew(regs, MUSB_RXCSR, csr); 946 } 947 948 /* NOTE: all the I/O code _should_ work fine without DMA, in case 949 * for some reason you run out of channels here. 950 */ 951 if (is_dma_capable() && musb->dma_controller) { 952 struct dma_controller *c = musb->dma_controller; 953 954 musb_ep->dma = c->channel_alloc(c, hw_ep, 955 (desc->bEndpointAddress & USB_DIR_IN)); 956 } else 957 musb_ep->dma = NULL; 958 959 musb_ep->desc = desc; 960 musb_ep->busy = 0; 961 musb_ep->wedged = 0; 962 status = 0; 963 964 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", 965 musb_driver_name, musb_ep->end_point.name, 966 ({ char *s; switch (musb_ep->type) { 967 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; 968 case USB_ENDPOINT_XFER_INT: s = "int"; break; 969 default: s = "iso"; break; 970 }; s; }), 971 musb_ep->is_in ? "IN" : "OUT", 972 musb_ep->dma ? "dma, " : "", 973 musb_ep->packet_sz); 974 975 schedule_work(&musb->irq_work); 976 977 fail: 978 spin_unlock_irqrestore(&musb->lock, flags); 979 return status; 980 } 981 982 /* 983 * Disable an endpoint flushing all requests queued. 984 */ 985 static int musb_gadget_disable(struct usb_ep *ep) 986 { 987 unsigned long flags; 988 struct musb *musb; 989 u8 epnum; 990 struct musb_ep *musb_ep; 991 void __iomem *epio; 992 int status = 0; 993 994 musb_ep = to_musb_ep(ep); 995 musb = musb_ep->musb; 996 epnum = musb_ep->current_epnum; 997 epio = musb->endpoints[epnum].regs; 998 999 spin_lock_irqsave(&musb->lock, flags); 1000 musb_ep_select(musb->mregs, epnum); 1001 1002 /* zero the endpoint sizes */ 1003 if (musb_ep->is_in) { 1004 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE); 1005 int_txe &= ~(1 << epnum); 1006 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe); 1007 musb_writew(epio, MUSB_TXMAXP, 0); 1008 } else { 1009 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE); 1010 int_rxe &= ~(1 << epnum); 1011 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe); 1012 musb_writew(epio, MUSB_RXMAXP, 0); 1013 } 1014 1015 musb_ep->desc = NULL; 1016 1017 /* abort all pending DMA and requests */ 1018 nuke(musb_ep, -ESHUTDOWN); 1019 1020 schedule_work(&musb->irq_work); 1021 1022 spin_unlock_irqrestore(&(musb->lock), flags); 1023 1024 DBG(2, "%s\n", musb_ep->end_point.name); 1025 1026 return status; 1027 } 1028 1029 /* 1030 * Allocate a request for an endpoint. 1031 * Reused by ep0 code. 1032 */ 1033 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) 1034 { 1035 struct musb_ep *musb_ep = to_musb_ep(ep); 1036 struct musb_request *request = NULL; 1037 1038 request = kzalloc(sizeof *request, gfp_flags); 1039 if (request) { 1040 INIT_LIST_HEAD(&request->request.list); 1041 request->request.dma = DMA_ADDR_INVALID; 1042 request->epnum = musb_ep->current_epnum; 1043 request->ep = musb_ep; 1044 } 1045 1046 return &request->request; 1047 } 1048 1049 /* 1050 * Free a request 1051 * Reused by ep0 code. 1052 */ 1053 void musb_free_request(struct usb_ep *ep, struct usb_request *req) 1054 { 1055 kfree(to_musb_request(req)); 1056 } 1057 1058 static LIST_HEAD(buffers); 1059 1060 struct free_record { 1061 struct list_head list; 1062 struct device *dev; 1063 unsigned bytes; 1064 dma_addr_t dma; 1065 }; 1066 1067 /* 1068 * Context: controller locked, IRQs blocked. 1069 */ 1070 static void musb_ep_restart(struct musb *musb, struct musb_request *req) 1071 { 1072 DBG(3, "<== %s request %p len %u on hw_ep%d\n", 1073 req->tx ? "TX/IN" : "RX/OUT", 1074 &req->request, req->request.length, req->epnum); 1075 1076 musb_ep_select(musb->mregs, req->epnum); 1077 if (req->tx) 1078 txstate(musb, req); 1079 else 1080 rxstate(musb, req); 1081 } 1082 1083 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, 1084 gfp_t gfp_flags) 1085 { 1086 struct musb_ep *musb_ep; 1087 struct musb_request *request; 1088 struct musb *musb; 1089 int status = 0; 1090 unsigned long lockflags; 1091 1092 if (!ep || !req) 1093 return -EINVAL; 1094 if (!req->buf) 1095 return -ENODATA; 1096 1097 musb_ep = to_musb_ep(ep); 1098 musb = musb_ep->musb; 1099 1100 request = to_musb_request(req); 1101 request->musb = musb; 1102 1103 if (request->ep != musb_ep) 1104 return -EINVAL; 1105 1106 DBG(4, "<== to %s request=%p\n", ep->name, req); 1107 1108 /* request is mine now... */ 1109 request->request.actual = 0; 1110 request->request.status = -EINPROGRESS; 1111 request->epnum = musb_ep->current_epnum; 1112 request->tx = musb_ep->is_in; 1113 1114 if (is_dma_capable() && musb_ep->dma) { 1115 if (request->request.dma == DMA_ADDR_INVALID) { 1116 request->request.dma = dma_map_single( 1117 musb->controller, 1118 request->request.buf, 1119 request->request.length, 1120 request->tx 1121 ? DMA_TO_DEVICE 1122 : DMA_FROM_DEVICE); 1123 request->mapped = 1; 1124 } else { 1125 dma_sync_single_for_device(musb->controller, 1126 request->request.dma, 1127 request->request.length, 1128 request->tx 1129 ? DMA_TO_DEVICE 1130 : DMA_FROM_DEVICE); 1131 request->mapped = 0; 1132 } 1133 } else if (!req->buf) { 1134 return -ENODATA; 1135 } else 1136 request->mapped = 0; 1137 1138 spin_lock_irqsave(&musb->lock, lockflags); 1139 1140 /* don't queue if the ep is down */ 1141 if (!musb_ep->desc) { 1142 DBG(4, "req %p queued to %s while ep %s\n", 1143 req, ep->name, "disabled"); 1144 status = -ESHUTDOWN; 1145 goto cleanup; 1146 } 1147 1148 /* add request to the list */ 1149 list_add_tail(&(request->request.list), &(musb_ep->req_list)); 1150 1151 /* it this is the head of the queue, start i/o ... */ 1152 if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next) 1153 musb_ep_restart(musb, request); 1154 1155 cleanup: 1156 spin_unlock_irqrestore(&musb->lock, lockflags); 1157 return status; 1158 } 1159 1160 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) 1161 { 1162 struct musb_ep *musb_ep = to_musb_ep(ep); 1163 struct usb_request *r; 1164 unsigned long flags; 1165 int status = 0; 1166 struct musb *musb = musb_ep->musb; 1167 1168 if (!ep || !request || to_musb_request(request)->ep != musb_ep) 1169 return -EINVAL; 1170 1171 spin_lock_irqsave(&musb->lock, flags); 1172 1173 list_for_each_entry(r, &musb_ep->req_list, list) { 1174 if (r == request) 1175 break; 1176 } 1177 if (r != request) { 1178 DBG(3, "request %p not queued to %s\n", request, ep->name); 1179 status = -EINVAL; 1180 goto done; 1181 } 1182 1183 /* if the hardware doesn't have the request, easy ... */ 1184 if (musb_ep->req_list.next != &request->list || musb_ep->busy) 1185 musb_g_giveback(musb_ep, request, -ECONNRESET); 1186 1187 /* ... else abort the dma transfer ... */ 1188 else if (is_dma_capable() && musb_ep->dma) { 1189 struct dma_controller *c = musb->dma_controller; 1190 1191 musb_ep_select(musb->mregs, musb_ep->current_epnum); 1192 if (c->channel_abort) 1193 status = c->channel_abort(musb_ep->dma); 1194 else 1195 status = -EBUSY; 1196 if (status == 0) 1197 musb_g_giveback(musb_ep, request, -ECONNRESET); 1198 } else { 1199 /* NOTE: by sticking to easily tested hardware/driver states, 1200 * we leave counting of in-flight packets imprecise. 1201 */ 1202 musb_g_giveback(musb_ep, request, -ECONNRESET); 1203 } 1204 1205 done: 1206 spin_unlock_irqrestore(&musb->lock, flags); 1207 return status; 1208 } 1209 1210 /* 1211 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any 1212 * data but will queue requests. 1213 * 1214 * exported to ep0 code 1215 */ 1216 static int musb_gadget_set_halt(struct usb_ep *ep, int value) 1217 { 1218 struct musb_ep *musb_ep = to_musb_ep(ep); 1219 u8 epnum = musb_ep->current_epnum; 1220 struct musb *musb = musb_ep->musb; 1221 void __iomem *epio = musb->endpoints[epnum].regs; 1222 void __iomem *mbase; 1223 unsigned long flags; 1224 u16 csr; 1225 struct musb_request *request; 1226 int status = 0; 1227 1228 if (!ep) 1229 return -EINVAL; 1230 mbase = musb->mregs; 1231 1232 spin_lock_irqsave(&musb->lock, flags); 1233 1234 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { 1235 status = -EINVAL; 1236 goto done; 1237 } 1238 1239 musb_ep_select(mbase, epnum); 1240 1241 request = to_musb_request(next_request(musb_ep)); 1242 if (value) { 1243 if (request) { 1244 DBG(3, "request in progress, cannot halt %s\n", 1245 ep->name); 1246 status = -EAGAIN; 1247 goto done; 1248 } 1249 /* Cannot portably stall with non-empty FIFO */ 1250 if (musb_ep->is_in) { 1251 csr = musb_readw(epio, MUSB_TXCSR); 1252 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1253 DBG(3, "FIFO busy, cannot halt %s\n", ep->name); 1254 status = -EAGAIN; 1255 goto done; 1256 } 1257 } 1258 } else 1259 musb_ep->wedged = 0; 1260 1261 /* set/clear the stall and toggle bits */ 1262 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear"); 1263 if (musb_ep->is_in) { 1264 csr = musb_readw(epio, MUSB_TXCSR); 1265 csr |= MUSB_TXCSR_P_WZC_BITS 1266 | MUSB_TXCSR_CLRDATATOG; 1267 if (value) 1268 csr |= MUSB_TXCSR_P_SENDSTALL; 1269 else 1270 csr &= ~(MUSB_TXCSR_P_SENDSTALL 1271 | MUSB_TXCSR_P_SENTSTALL); 1272 csr &= ~MUSB_TXCSR_TXPKTRDY; 1273 musb_writew(epio, MUSB_TXCSR, csr); 1274 } else { 1275 csr = musb_readw(epio, MUSB_RXCSR); 1276 csr |= MUSB_RXCSR_P_WZC_BITS 1277 | MUSB_RXCSR_FLUSHFIFO 1278 | MUSB_RXCSR_CLRDATATOG; 1279 if (value) 1280 csr |= MUSB_RXCSR_P_SENDSTALL; 1281 else 1282 csr &= ~(MUSB_RXCSR_P_SENDSTALL 1283 | MUSB_RXCSR_P_SENTSTALL); 1284 musb_writew(epio, MUSB_RXCSR, csr); 1285 } 1286 1287 /* maybe start the first request in the queue */ 1288 if (!musb_ep->busy && !value && request) { 1289 DBG(3, "restarting the request\n"); 1290 musb_ep_restart(musb, request); 1291 } 1292 1293 done: 1294 spin_unlock_irqrestore(&musb->lock, flags); 1295 return status; 1296 } 1297 1298 /* 1299 * Sets the halt feature with the clear requests ignored 1300 */ 1301 static int musb_gadget_set_wedge(struct usb_ep *ep) 1302 { 1303 struct musb_ep *musb_ep = to_musb_ep(ep); 1304 1305 if (!ep) 1306 return -EINVAL; 1307 1308 musb_ep->wedged = 1; 1309 1310 return usb_ep_set_halt(ep); 1311 } 1312 1313 static int musb_gadget_fifo_status(struct usb_ep *ep) 1314 { 1315 struct musb_ep *musb_ep = to_musb_ep(ep); 1316 void __iomem *epio = musb_ep->hw_ep->regs; 1317 int retval = -EINVAL; 1318 1319 if (musb_ep->desc && !musb_ep->is_in) { 1320 struct musb *musb = musb_ep->musb; 1321 int epnum = musb_ep->current_epnum; 1322 void __iomem *mbase = musb->mregs; 1323 unsigned long flags; 1324 1325 spin_lock_irqsave(&musb->lock, flags); 1326 1327 musb_ep_select(mbase, epnum); 1328 /* FIXME return zero unless RXPKTRDY is set */ 1329 retval = musb_readw(epio, MUSB_RXCOUNT); 1330 1331 spin_unlock_irqrestore(&musb->lock, flags); 1332 } 1333 return retval; 1334 } 1335 1336 static void musb_gadget_fifo_flush(struct usb_ep *ep) 1337 { 1338 struct musb_ep *musb_ep = to_musb_ep(ep); 1339 struct musb *musb = musb_ep->musb; 1340 u8 epnum = musb_ep->current_epnum; 1341 void __iomem *epio = musb->endpoints[epnum].regs; 1342 void __iomem *mbase; 1343 unsigned long flags; 1344 u16 csr, int_txe; 1345 1346 mbase = musb->mregs; 1347 1348 spin_lock_irqsave(&musb->lock, flags); 1349 musb_ep_select(mbase, (u8) epnum); 1350 1351 /* disable interrupts */ 1352 int_txe = musb_readw(mbase, MUSB_INTRTXE); 1353 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); 1354 1355 if (musb_ep->is_in) { 1356 csr = musb_readw(epio, MUSB_TXCSR); 1357 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1358 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; 1359 musb_writew(epio, MUSB_TXCSR, csr); 1360 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ 1361 musb_writew(epio, MUSB_TXCSR, csr); 1362 } 1363 } else { 1364 csr = musb_readw(epio, MUSB_RXCSR); 1365 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; 1366 musb_writew(epio, MUSB_RXCSR, csr); 1367 musb_writew(epio, MUSB_RXCSR, csr); 1368 } 1369 1370 /* re-enable interrupt */ 1371 musb_writew(mbase, MUSB_INTRTXE, int_txe); 1372 spin_unlock_irqrestore(&musb->lock, flags); 1373 } 1374 1375 static const struct usb_ep_ops musb_ep_ops = { 1376 .enable = musb_gadget_enable, 1377 .disable = musb_gadget_disable, 1378 .alloc_request = musb_alloc_request, 1379 .free_request = musb_free_request, 1380 .queue = musb_gadget_queue, 1381 .dequeue = musb_gadget_dequeue, 1382 .set_halt = musb_gadget_set_halt, 1383 .set_wedge = musb_gadget_set_wedge, 1384 .fifo_status = musb_gadget_fifo_status, 1385 .fifo_flush = musb_gadget_fifo_flush 1386 }; 1387 1388 /* ----------------------------------------------------------------------- */ 1389 1390 static int musb_gadget_get_frame(struct usb_gadget *gadget) 1391 { 1392 struct musb *musb = gadget_to_musb(gadget); 1393 1394 return (int)musb_readw(musb->mregs, MUSB_FRAME); 1395 } 1396 1397 static int musb_gadget_wakeup(struct usb_gadget *gadget) 1398 { 1399 struct musb *musb = gadget_to_musb(gadget); 1400 void __iomem *mregs = musb->mregs; 1401 unsigned long flags; 1402 int status = -EINVAL; 1403 u8 power, devctl; 1404 int retries; 1405 1406 spin_lock_irqsave(&musb->lock, flags); 1407 1408 switch (musb->xceiv->state) { 1409 case OTG_STATE_B_PERIPHERAL: 1410 /* NOTE: OTG state machine doesn't include B_SUSPENDED; 1411 * that's part of the standard usb 1.1 state machine, and 1412 * doesn't affect OTG transitions. 1413 */ 1414 if (musb->may_wakeup && musb->is_suspended) 1415 break; 1416 goto done; 1417 case OTG_STATE_B_IDLE: 1418 /* Start SRP ... OTG not required. */ 1419 devctl = musb_readb(mregs, MUSB_DEVCTL); 1420 DBG(2, "Sending SRP: devctl: %02x\n", devctl); 1421 devctl |= MUSB_DEVCTL_SESSION; 1422 musb_writeb(mregs, MUSB_DEVCTL, devctl); 1423 devctl = musb_readb(mregs, MUSB_DEVCTL); 1424 retries = 100; 1425 while (!(devctl & MUSB_DEVCTL_SESSION)) { 1426 devctl = musb_readb(mregs, MUSB_DEVCTL); 1427 if (retries-- < 1) 1428 break; 1429 } 1430 retries = 10000; 1431 while (devctl & MUSB_DEVCTL_SESSION) { 1432 devctl = musb_readb(mregs, MUSB_DEVCTL); 1433 if (retries-- < 1) 1434 break; 1435 } 1436 1437 /* Block idling for at least 1s */ 1438 musb_platform_try_idle(musb, 1439 jiffies + msecs_to_jiffies(1 * HZ)); 1440 1441 status = 0; 1442 goto done; 1443 default: 1444 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb)); 1445 goto done; 1446 } 1447 1448 status = 0; 1449 1450 power = musb_readb(mregs, MUSB_POWER); 1451 power |= MUSB_POWER_RESUME; 1452 musb_writeb(mregs, MUSB_POWER, power); 1453 DBG(2, "issue wakeup\n"); 1454 1455 /* FIXME do this next chunk in a timer callback, no udelay */ 1456 mdelay(2); 1457 1458 power = musb_readb(mregs, MUSB_POWER); 1459 power &= ~MUSB_POWER_RESUME; 1460 musb_writeb(mregs, MUSB_POWER, power); 1461 done: 1462 spin_unlock_irqrestore(&musb->lock, flags); 1463 return status; 1464 } 1465 1466 static int 1467 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) 1468 { 1469 struct musb *musb = gadget_to_musb(gadget); 1470 1471 musb->is_self_powered = !!is_selfpowered; 1472 return 0; 1473 } 1474 1475 static void musb_pullup(struct musb *musb, int is_on) 1476 { 1477 u8 power; 1478 1479 power = musb_readb(musb->mregs, MUSB_POWER); 1480 if (is_on) 1481 power |= MUSB_POWER_SOFTCONN; 1482 else 1483 power &= ~MUSB_POWER_SOFTCONN; 1484 1485 /* FIXME if on, HdrcStart; if off, HdrcStop */ 1486 1487 DBG(3, "gadget %s D+ pullup %s\n", 1488 musb->gadget_driver->function, is_on ? "on" : "off"); 1489 musb_writeb(musb->mregs, MUSB_POWER, power); 1490 } 1491 1492 #if 0 1493 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) 1494 { 1495 DBG(2, "<= %s =>\n", __func__); 1496 1497 /* 1498 * FIXME iff driver's softconnect flag is set (as it is during probe, 1499 * though that can clear it), just musb_pullup(). 1500 */ 1501 1502 return -EINVAL; 1503 } 1504 #endif 1505 1506 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) 1507 { 1508 struct musb *musb = gadget_to_musb(gadget); 1509 1510 if (!musb->xceiv->set_power) 1511 return -EOPNOTSUPP; 1512 return otg_set_power(musb->xceiv, mA); 1513 } 1514 1515 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) 1516 { 1517 struct musb *musb = gadget_to_musb(gadget); 1518 unsigned long flags; 1519 1520 is_on = !!is_on; 1521 1522 /* NOTE: this assumes we are sensing vbus; we'd rather 1523 * not pullup unless the B-session is active. 1524 */ 1525 spin_lock_irqsave(&musb->lock, flags); 1526 if (is_on != musb->softconnect) { 1527 musb->softconnect = is_on; 1528 musb_pullup(musb, is_on); 1529 } 1530 spin_unlock_irqrestore(&musb->lock, flags); 1531 return 0; 1532 } 1533 1534 static const struct usb_gadget_ops musb_gadget_operations = { 1535 .get_frame = musb_gadget_get_frame, 1536 .wakeup = musb_gadget_wakeup, 1537 .set_selfpowered = musb_gadget_set_self_powered, 1538 /* .vbus_session = musb_gadget_vbus_session, */ 1539 .vbus_draw = musb_gadget_vbus_draw, 1540 .pullup = musb_gadget_pullup, 1541 }; 1542 1543 /* ----------------------------------------------------------------------- */ 1544 1545 /* Registration */ 1546 1547 /* Only this registration code "knows" the rule (from USB standards) 1548 * about there being only one external upstream port. It assumes 1549 * all peripheral ports are external... 1550 */ 1551 static struct musb *the_gadget; 1552 1553 static void musb_gadget_release(struct device *dev) 1554 { 1555 /* kref_put(WHAT) */ 1556 dev_dbg(dev, "%s\n", __func__); 1557 } 1558 1559 1560 static void __init 1561 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) 1562 { 1563 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1564 1565 memset(ep, 0, sizeof *ep); 1566 1567 ep->current_epnum = epnum; 1568 ep->musb = musb; 1569 ep->hw_ep = hw_ep; 1570 ep->is_in = is_in; 1571 1572 INIT_LIST_HEAD(&ep->req_list); 1573 1574 sprintf(ep->name, "ep%d%s", epnum, 1575 (!epnum || hw_ep->is_shared_fifo) ? "" : ( 1576 is_in ? "in" : "out")); 1577 ep->end_point.name = ep->name; 1578 INIT_LIST_HEAD(&ep->end_point.ep_list); 1579 if (!epnum) { 1580 ep->end_point.maxpacket = 64; 1581 ep->end_point.ops = &musb_g_ep0_ops; 1582 musb->g.ep0 = &ep->end_point; 1583 } else { 1584 if (is_in) 1585 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx; 1586 else 1587 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx; 1588 ep->end_point.ops = &musb_ep_ops; 1589 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); 1590 } 1591 } 1592 1593 /* 1594 * Initialize the endpoints exposed to peripheral drivers, with backlinks 1595 * to the rest of the driver state. 1596 */ 1597 static inline void __init musb_g_init_endpoints(struct musb *musb) 1598 { 1599 u8 epnum; 1600 struct musb_hw_ep *hw_ep; 1601 unsigned count = 0; 1602 1603 /* intialize endpoint list just once */ 1604 INIT_LIST_HEAD(&(musb->g.ep_list)); 1605 1606 for (epnum = 0, hw_ep = musb->endpoints; 1607 epnum < musb->nr_endpoints; 1608 epnum++, hw_ep++) { 1609 if (hw_ep->is_shared_fifo /* || !epnum */) { 1610 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); 1611 count++; 1612 } else { 1613 if (hw_ep->max_packet_sz_tx) { 1614 init_peripheral_ep(musb, &hw_ep->ep_in, 1615 epnum, 1); 1616 count++; 1617 } 1618 if (hw_ep->max_packet_sz_rx) { 1619 init_peripheral_ep(musb, &hw_ep->ep_out, 1620 epnum, 0); 1621 count++; 1622 } 1623 } 1624 } 1625 } 1626 1627 /* called once during driver setup to initialize and link into 1628 * the driver model; memory is zeroed. 1629 */ 1630 int __init musb_gadget_setup(struct musb *musb) 1631 { 1632 int status; 1633 1634 /* REVISIT minor race: if (erroneously) setting up two 1635 * musb peripherals at the same time, only the bus lock 1636 * is probably held. 1637 */ 1638 if (the_gadget) 1639 return -EBUSY; 1640 the_gadget = musb; 1641 1642 musb->g.ops = &musb_gadget_operations; 1643 musb->g.is_dualspeed = 1; 1644 musb->g.speed = USB_SPEED_UNKNOWN; 1645 1646 /* this "gadget" abstracts/virtualizes the controller */ 1647 dev_set_name(&musb->g.dev, "gadget"); 1648 musb->g.dev.parent = musb->controller; 1649 musb->g.dev.dma_mask = musb->controller->dma_mask; 1650 musb->g.dev.release = musb_gadget_release; 1651 musb->g.name = musb_driver_name; 1652 1653 if (is_otg_enabled(musb)) 1654 musb->g.is_otg = 1; 1655 1656 musb_g_init_endpoints(musb); 1657 1658 musb->is_active = 0; 1659 musb_platform_try_idle(musb, 0); 1660 1661 status = device_register(&musb->g.dev); 1662 if (status != 0) 1663 the_gadget = NULL; 1664 return status; 1665 } 1666 1667 void musb_gadget_cleanup(struct musb *musb) 1668 { 1669 if (musb != the_gadget) 1670 return; 1671 1672 device_unregister(&musb->g.dev); 1673 the_gadget = NULL; 1674 } 1675 1676 /* 1677 * Register the gadget driver. Used by gadget drivers when 1678 * registering themselves with the controller. 1679 * 1680 * -EINVAL something went wrong (not driver) 1681 * -EBUSY another gadget is already using the controller 1682 * -ENOMEM no memeory to perform the operation 1683 * 1684 * @param driver the gadget driver 1685 * @return <0 if error, 0 if everything is fine 1686 */ 1687 int usb_gadget_register_driver(struct usb_gadget_driver *driver) 1688 { 1689 int retval; 1690 unsigned long flags; 1691 struct musb *musb = the_gadget; 1692 1693 if (!driver 1694 || driver->speed != USB_SPEED_HIGH 1695 || !driver->bind 1696 || !driver->setup) 1697 return -EINVAL; 1698 1699 /* driver must be initialized to support peripheral mode */ 1700 if (!musb || !(musb->board_mode == MUSB_OTG 1701 || musb->board_mode != MUSB_OTG)) { 1702 DBG(1, "%s, no dev??\n", __func__); 1703 return -ENODEV; 1704 } 1705 1706 DBG(3, "registering driver %s\n", driver->function); 1707 spin_lock_irqsave(&musb->lock, flags); 1708 1709 if (musb->gadget_driver) { 1710 DBG(1, "%s is already bound to %s\n", 1711 musb_driver_name, 1712 musb->gadget_driver->driver.name); 1713 retval = -EBUSY; 1714 } else { 1715 musb->gadget_driver = driver; 1716 musb->g.dev.driver = &driver->driver; 1717 driver->driver.bus = NULL; 1718 musb->softconnect = 1; 1719 retval = 0; 1720 } 1721 1722 spin_unlock_irqrestore(&musb->lock, flags); 1723 1724 if (retval == 0) { 1725 retval = driver->bind(&musb->g); 1726 if (retval != 0) { 1727 DBG(3, "bind to driver %s failed --> %d\n", 1728 driver->driver.name, retval); 1729 musb->gadget_driver = NULL; 1730 musb->g.dev.driver = NULL; 1731 } 1732 1733 spin_lock_irqsave(&musb->lock, flags); 1734 1735 otg_set_peripheral(musb->xceiv, &musb->g); 1736 musb->xceiv->state = OTG_STATE_B_IDLE; 1737 musb->is_active = 1; 1738 1739 /* FIXME this ignores the softconnect flag. Drivers are 1740 * allowed hold the peripheral inactive until for example 1741 * userspace hooks up printer hardware or DSP codecs, so 1742 * hosts only see fully functional devices. 1743 */ 1744 1745 if (!is_otg_enabled(musb)) 1746 musb_start(musb); 1747 1748 otg_set_peripheral(musb->xceiv, &musb->g); 1749 1750 spin_unlock_irqrestore(&musb->lock, flags); 1751 1752 if (is_otg_enabled(musb)) { 1753 DBG(3, "OTG startup...\n"); 1754 1755 /* REVISIT: funcall to other code, which also 1756 * handles power budgeting ... this way also 1757 * ensures HdrcStart is indirectly called. 1758 */ 1759 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); 1760 if (retval < 0) { 1761 DBG(1, "add_hcd failed, %d\n", retval); 1762 spin_lock_irqsave(&musb->lock, flags); 1763 otg_set_peripheral(musb->xceiv, NULL); 1764 musb->gadget_driver = NULL; 1765 musb->g.dev.driver = NULL; 1766 spin_unlock_irqrestore(&musb->lock, flags); 1767 } 1768 } 1769 } 1770 1771 return retval; 1772 } 1773 EXPORT_SYMBOL(usb_gadget_register_driver); 1774 1775 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver) 1776 { 1777 int i; 1778 struct musb_hw_ep *hw_ep; 1779 1780 /* don't disconnect if it's not connected */ 1781 if (musb->g.speed == USB_SPEED_UNKNOWN) 1782 driver = NULL; 1783 else 1784 musb->g.speed = USB_SPEED_UNKNOWN; 1785 1786 /* deactivate the hardware */ 1787 if (musb->softconnect) { 1788 musb->softconnect = 0; 1789 musb_pullup(musb, 0); 1790 } 1791 musb_stop(musb); 1792 1793 /* killing any outstanding requests will quiesce the driver; 1794 * then report disconnect 1795 */ 1796 if (driver) { 1797 for (i = 0, hw_ep = musb->endpoints; 1798 i < musb->nr_endpoints; 1799 i++, hw_ep++) { 1800 musb_ep_select(musb->mregs, i); 1801 if (hw_ep->is_shared_fifo /* || !epnum */) { 1802 nuke(&hw_ep->ep_in, -ESHUTDOWN); 1803 } else { 1804 if (hw_ep->max_packet_sz_tx) 1805 nuke(&hw_ep->ep_in, -ESHUTDOWN); 1806 if (hw_ep->max_packet_sz_rx) 1807 nuke(&hw_ep->ep_out, -ESHUTDOWN); 1808 } 1809 } 1810 1811 spin_unlock(&musb->lock); 1812 driver->disconnect(&musb->g); 1813 spin_lock(&musb->lock); 1814 } 1815 } 1816 1817 /* 1818 * Unregister the gadget driver. Used by gadget drivers when 1819 * unregistering themselves from the controller. 1820 * 1821 * @param driver the gadget driver to unregister 1822 */ 1823 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) 1824 { 1825 unsigned long flags; 1826 int retval = 0; 1827 struct musb *musb = the_gadget; 1828 1829 if (!driver || !driver->unbind || !musb) 1830 return -EINVAL; 1831 1832 /* REVISIT always use otg_set_peripheral() here too; 1833 * this needs to shut down the OTG engine. 1834 */ 1835 1836 spin_lock_irqsave(&musb->lock, flags); 1837 1838 #ifdef CONFIG_USB_MUSB_OTG 1839 musb_hnp_stop(musb); 1840 #endif 1841 1842 if (musb->gadget_driver == driver) { 1843 1844 (void) musb_gadget_vbus_draw(&musb->g, 0); 1845 1846 musb->xceiv->state = OTG_STATE_UNDEFINED; 1847 stop_activity(musb, driver); 1848 otg_set_peripheral(musb->xceiv, NULL); 1849 1850 DBG(3, "unregistering driver %s\n", driver->function); 1851 spin_unlock_irqrestore(&musb->lock, flags); 1852 driver->unbind(&musb->g); 1853 spin_lock_irqsave(&musb->lock, flags); 1854 1855 musb->gadget_driver = NULL; 1856 musb->g.dev.driver = NULL; 1857 1858 musb->is_active = 0; 1859 musb_platform_try_idle(musb, 0); 1860 } else 1861 retval = -EINVAL; 1862 spin_unlock_irqrestore(&musb->lock, flags); 1863 1864 if (is_otg_enabled(musb) && retval == 0) { 1865 usb_remove_hcd(musb_to_hcd(musb)); 1866 /* FIXME we need to be able to register another 1867 * gadget driver here and have everything work; 1868 * that currently misbehaves. 1869 */ 1870 } 1871 1872 return retval; 1873 } 1874 EXPORT_SYMBOL(usb_gadget_unregister_driver); 1875 1876 1877 /* ----------------------------------------------------------------------- */ 1878 1879 /* lifecycle operations called through plat_uds.c */ 1880 1881 void musb_g_resume(struct musb *musb) 1882 { 1883 musb->is_suspended = 0; 1884 switch (musb->xceiv->state) { 1885 case OTG_STATE_B_IDLE: 1886 break; 1887 case OTG_STATE_B_WAIT_ACON: 1888 case OTG_STATE_B_PERIPHERAL: 1889 musb->is_active = 1; 1890 if (musb->gadget_driver && musb->gadget_driver->resume) { 1891 spin_unlock(&musb->lock); 1892 musb->gadget_driver->resume(&musb->g); 1893 spin_lock(&musb->lock); 1894 } 1895 break; 1896 default: 1897 WARNING("unhandled RESUME transition (%s)\n", 1898 otg_state_string(musb)); 1899 } 1900 } 1901 1902 /* called when SOF packets stop for 3+ msec */ 1903 void musb_g_suspend(struct musb *musb) 1904 { 1905 u8 devctl; 1906 1907 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 1908 DBG(3, "devctl %02x\n", devctl); 1909 1910 switch (musb->xceiv->state) { 1911 case OTG_STATE_B_IDLE: 1912 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 1913 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 1914 break; 1915 case OTG_STATE_B_PERIPHERAL: 1916 musb->is_suspended = 1; 1917 if (musb->gadget_driver && musb->gadget_driver->suspend) { 1918 spin_unlock(&musb->lock); 1919 musb->gadget_driver->suspend(&musb->g); 1920 spin_lock(&musb->lock); 1921 } 1922 break; 1923 default: 1924 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; 1925 * A_PERIPHERAL may need care too 1926 */ 1927 WARNING("unhandled SUSPEND transition (%s)\n", 1928 otg_state_string(musb)); 1929 } 1930 } 1931 1932 /* Called during SRP */ 1933 void musb_g_wakeup(struct musb *musb) 1934 { 1935 musb_gadget_wakeup(&musb->g); 1936 } 1937 1938 /* called when VBUS drops below session threshold, and in other cases */ 1939 void musb_g_disconnect(struct musb *musb) 1940 { 1941 void __iomem *mregs = musb->mregs; 1942 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 1943 1944 DBG(3, "devctl %02x\n", devctl); 1945 1946 /* clear HR */ 1947 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); 1948 1949 /* don't draw vbus until new b-default session */ 1950 (void) musb_gadget_vbus_draw(&musb->g, 0); 1951 1952 musb->g.speed = USB_SPEED_UNKNOWN; 1953 if (musb->gadget_driver && musb->gadget_driver->disconnect) { 1954 spin_unlock(&musb->lock); 1955 musb->gadget_driver->disconnect(&musb->g); 1956 spin_lock(&musb->lock); 1957 } 1958 1959 switch (musb->xceiv->state) { 1960 default: 1961 #ifdef CONFIG_USB_MUSB_OTG 1962 DBG(2, "Unhandled disconnect %s, setting a_idle\n", 1963 otg_state_string(musb)); 1964 musb->xceiv->state = OTG_STATE_A_IDLE; 1965 MUSB_HST_MODE(musb); 1966 break; 1967 case OTG_STATE_A_PERIPHERAL: 1968 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 1969 MUSB_HST_MODE(musb); 1970 break; 1971 case OTG_STATE_B_WAIT_ACON: 1972 case OTG_STATE_B_HOST: 1973 #endif 1974 case OTG_STATE_B_PERIPHERAL: 1975 case OTG_STATE_B_IDLE: 1976 musb->xceiv->state = OTG_STATE_B_IDLE; 1977 break; 1978 case OTG_STATE_B_SRP_INIT: 1979 break; 1980 } 1981 1982 musb->is_active = 0; 1983 } 1984 1985 void musb_g_reset(struct musb *musb) 1986 __releases(musb->lock) 1987 __acquires(musb->lock) 1988 { 1989 void __iomem *mbase = musb->mregs; 1990 u8 devctl = musb_readb(mbase, MUSB_DEVCTL); 1991 u8 power; 1992 1993 DBG(3, "<== %s addr=%x driver '%s'\n", 1994 (devctl & MUSB_DEVCTL_BDEVICE) 1995 ? "B-Device" : "A-Device", 1996 musb_readb(mbase, MUSB_FADDR), 1997 musb->gadget_driver 1998 ? musb->gadget_driver->driver.name 1999 : NULL 2000 ); 2001 2002 /* report disconnect, if we didn't already (flushing EP state) */ 2003 if (musb->g.speed != USB_SPEED_UNKNOWN) 2004 musb_g_disconnect(musb); 2005 2006 /* clear HR */ 2007 else if (devctl & MUSB_DEVCTL_HR) 2008 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 2009 2010 2011 /* what speed did we negotiate? */ 2012 power = musb_readb(mbase, MUSB_POWER); 2013 musb->g.speed = (power & MUSB_POWER_HSMODE) 2014 ? USB_SPEED_HIGH : USB_SPEED_FULL; 2015 2016 /* start in USB_STATE_DEFAULT */ 2017 musb->is_active = 1; 2018 musb->is_suspended = 0; 2019 MUSB_DEV_MODE(musb); 2020 musb->address = 0; 2021 musb->ep0_state = MUSB_EP0_STAGE_SETUP; 2022 2023 musb->may_wakeup = 0; 2024 musb->g.b_hnp_enable = 0; 2025 musb->g.a_alt_hnp_support = 0; 2026 musb->g.a_hnp_support = 0; 2027 2028 /* Normal reset, as B-Device; 2029 * or else after HNP, as A-Device 2030 */ 2031 if (devctl & MUSB_DEVCTL_BDEVICE) { 2032 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 2033 musb->g.is_a_peripheral = 0; 2034 } else if (is_otg_enabled(musb)) { 2035 musb->xceiv->state = OTG_STATE_A_PERIPHERAL; 2036 musb->g.is_a_peripheral = 1; 2037 } else 2038 WARN_ON(1); 2039 2040 /* start with default limits on VBUS power draw */ 2041 (void) musb_gadget_vbus_draw(&musb->g, 2042 is_otg_enabled(musb) ? 8 : 100); 2043 } 2044