1 /* 2 * MUSB OTG driver peripheral support 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <linux/kernel.h> 37 #include <linux/list.h> 38 #include <linux/timer.h> 39 #include <linux/module.h> 40 #include <linux/smp.h> 41 #include <linux/spinlock.h> 42 #include <linux/delay.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 46 #include "musb_core.h" 47 #include "musb_trace.h" 48 49 50 /* ----------------------------------------------------------------------- */ 51 52 #define is_buffer_mapped(req) (is_dma_capable() && \ 53 (req->map_state != UN_MAPPED)) 54 55 /* Maps the buffer to dma */ 56 57 static inline void map_dma_buffer(struct musb_request *request, 58 struct musb *musb, struct musb_ep *musb_ep) 59 { 60 int compatible = true; 61 struct dma_controller *dma = musb->dma_controller; 62 63 request->map_state = UN_MAPPED; 64 65 if (!is_dma_capable() || !musb_ep->dma) 66 return; 67 68 /* Check if DMA engine can handle this request. 69 * DMA code must reject the USB request explicitly. 70 * Default behaviour is to map the request. 71 */ 72 if (dma->is_compatible) 73 compatible = dma->is_compatible(musb_ep->dma, 74 musb_ep->packet_sz, request->request.buf, 75 request->request.length); 76 if (!compatible) 77 return; 78 79 if (request->request.dma == DMA_ADDR_INVALID) { 80 dma_addr_t dma_addr; 81 int ret; 82 83 dma_addr = dma_map_single( 84 musb->controller, 85 request->request.buf, 86 request->request.length, 87 request->tx 88 ? DMA_TO_DEVICE 89 : DMA_FROM_DEVICE); 90 ret = dma_mapping_error(musb->controller, dma_addr); 91 if (ret) 92 return; 93 94 request->request.dma = dma_addr; 95 request->map_state = MUSB_MAPPED; 96 } else { 97 dma_sync_single_for_device(musb->controller, 98 request->request.dma, 99 request->request.length, 100 request->tx 101 ? DMA_TO_DEVICE 102 : DMA_FROM_DEVICE); 103 request->map_state = PRE_MAPPED; 104 } 105 } 106 107 /* Unmap the buffer from dma and maps it back to cpu */ 108 static inline void unmap_dma_buffer(struct musb_request *request, 109 struct musb *musb) 110 { 111 struct musb_ep *musb_ep = request->ep; 112 113 if (!is_buffer_mapped(request) || !musb_ep->dma) 114 return; 115 116 if (request->request.dma == DMA_ADDR_INVALID) { 117 dev_vdbg(musb->controller, 118 "not unmapping a never mapped buffer\n"); 119 return; 120 } 121 if (request->map_state == MUSB_MAPPED) { 122 dma_unmap_single(musb->controller, 123 request->request.dma, 124 request->request.length, 125 request->tx 126 ? DMA_TO_DEVICE 127 : DMA_FROM_DEVICE); 128 request->request.dma = DMA_ADDR_INVALID; 129 } else { /* PRE_MAPPED */ 130 dma_sync_single_for_cpu(musb->controller, 131 request->request.dma, 132 request->request.length, 133 request->tx 134 ? DMA_TO_DEVICE 135 : DMA_FROM_DEVICE); 136 } 137 request->map_state = UN_MAPPED; 138 } 139 140 /* 141 * Immediately complete a request. 142 * 143 * @param request the request to complete 144 * @param status the status to complete the request with 145 * Context: controller locked, IRQs blocked. 146 */ 147 void musb_g_giveback( 148 struct musb_ep *ep, 149 struct usb_request *request, 150 int status) 151 __releases(ep->musb->lock) 152 __acquires(ep->musb->lock) 153 { 154 struct musb_request *req; 155 struct musb *musb; 156 int busy = ep->busy; 157 158 req = to_musb_request(request); 159 160 list_del(&req->list); 161 if (req->request.status == -EINPROGRESS) 162 req->request.status = status; 163 musb = req->musb; 164 165 ep->busy = 1; 166 spin_unlock(&musb->lock); 167 168 if (!dma_mapping_error(&musb->g.dev, request->dma)) 169 unmap_dma_buffer(req, musb); 170 171 trace_musb_req_gb(req); 172 usb_gadget_giveback_request(&req->ep->end_point, &req->request); 173 spin_lock(&musb->lock); 174 ep->busy = busy; 175 } 176 177 /* ----------------------------------------------------------------------- */ 178 179 /* 180 * Abort requests queued to an endpoint using the status. Synchronous. 181 * caller locked controller and blocked irqs, and selected this ep. 182 */ 183 static void nuke(struct musb_ep *ep, const int status) 184 { 185 struct musb *musb = ep->musb; 186 struct musb_request *req = NULL; 187 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; 188 189 ep->busy = 1; 190 191 if (is_dma_capable() && ep->dma) { 192 struct dma_controller *c = ep->musb->dma_controller; 193 int value; 194 195 if (ep->is_in) { 196 /* 197 * The programming guide says that we must not clear 198 * the DMAMODE bit before DMAENAB, so we only 199 * clear it in the second write... 200 */ 201 musb_writew(epio, MUSB_TXCSR, 202 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); 203 musb_writew(epio, MUSB_TXCSR, 204 0 | MUSB_TXCSR_FLUSHFIFO); 205 } else { 206 musb_writew(epio, MUSB_RXCSR, 207 0 | MUSB_RXCSR_FLUSHFIFO); 208 musb_writew(epio, MUSB_RXCSR, 209 0 | MUSB_RXCSR_FLUSHFIFO); 210 } 211 212 value = c->channel_abort(ep->dma); 213 musb_dbg(musb, "%s: abort DMA --> %d", ep->name, value); 214 c->channel_release(ep->dma); 215 ep->dma = NULL; 216 } 217 218 while (!list_empty(&ep->req_list)) { 219 req = list_first_entry(&ep->req_list, struct musb_request, list); 220 musb_g_giveback(ep, &req->request, status); 221 } 222 } 223 224 /* ----------------------------------------------------------------------- */ 225 226 /* Data transfers - pure PIO, pure DMA, or mixed mode */ 227 228 /* 229 * This assumes the separate CPPI engine is responding to DMA requests 230 * from the usb core ... sequenced a bit differently from mentor dma. 231 */ 232 233 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) 234 { 235 if (can_bulk_split(musb, ep->type)) 236 return ep->hw_ep->max_packet_sz_tx; 237 else 238 return ep->packet_sz; 239 } 240 241 /* 242 * An endpoint is transmitting data. This can be called either from 243 * the IRQ routine or from ep.queue() to kickstart a request on an 244 * endpoint. 245 * 246 * Context: controller locked, IRQs blocked, endpoint selected 247 */ 248 static void txstate(struct musb *musb, struct musb_request *req) 249 { 250 u8 epnum = req->epnum; 251 struct musb_ep *musb_ep; 252 void __iomem *epio = musb->endpoints[epnum].regs; 253 struct usb_request *request; 254 u16 fifo_count = 0, csr; 255 int use_dma = 0; 256 257 musb_ep = req->ep; 258 259 /* Check if EP is disabled */ 260 if (!musb_ep->desc) { 261 musb_dbg(musb, "ep:%s disabled - ignore request", 262 musb_ep->end_point.name); 263 return; 264 } 265 266 /* we shouldn't get here while DMA is active ... but we do ... */ 267 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 268 musb_dbg(musb, "dma pending..."); 269 return; 270 } 271 272 /* read TXCSR before */ 273 csr = musb_readw(epio, MUSB_TXCSR); 274 275 request = &req->request; 276 fifo_count = min(max_ep_writesize(musb, musb_ep), 277 (int)(request->length - request->actual)); 278 279 if (csr & MUSB_TXCSR_TXPKTRDY) { 280 musb_dbg(musb, "%s old packet still ready , txcsr %03x", 281 musb_ep->end_point.name, csr); 282 return; 283 } 284 285 if (csr & MUSB_TXCSR_P_SENDSTALL) { 286 musb_dbg(musb, "%s stalling, txcsr %03x", 287 musb_ep->end_point.name, csr); 288 return; 289 } 290 291 musb_dbg(musb, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x", 292 epnum, musb_ep->packet_sz, fifo_count, 293 csr); 294 295 #ifndef CONFIG_MUSB_PIO_ONLY 296 if (is_buffer_mapped(req)) { 297 struct dma_controller *c = musb->dma_controller; 298 size_t request_size; 299 300 /* setup DMA, then program endpoint CSR */ 301 request_size = min_t(size_t, request->length - request->actual, 302 musb_ep->dma->max_len); 303 304 use_dma = (request->dma != DMA_ADDR_INVALID && request_size); 305 306 /* MUSB_TXCSR_P_ISO is still set correctly */ 307 308 if (musb_dma_inventra(musb) || musb_dma_ux500(musb)) { 309 if (request_size < musb_ep->packet_sz) 310 musb_ep->dma->desired_mode = 0; 311 else 312 musb_ep->dma->desired_mode = 1; 313 314 use_dma = use_dma && c->channel_program( 315 musb_ep->dma, musb_ep->packet_sz, 316 musb_ep->dma->desired_mode, 317 request->dma + request->actual, request_size); 318 if (use_dma) { 319 if (musb_ep->dma->desired_mode == 0) { 320 /* 321 * We must not clear the DMAMODE bit 322 * before the DMAENAB bit -- and the 323 * latter doesn't always get cleared 324 * before we get here... 325 */ 326 csr &= ~(MUSB_TXCSR_AUTOSET 327 | MUSB_TXCSR_DMAENAB); 328 musb_writew(epio, MUSB_TXCSR, csr 329 | MUSB_TXCSR_P_WZC_BITS); 330 csr &= ~MUSB_TXCSR_DMAMODE; 331 csr |= (MUSB_TXCSR_DMAENAB | 332 MUSB_TXCSR_MODE); 333 /* against programming guide */ 334 } else { 335 csr |= (MUSB_TXCSR_DMAENAB 336 | MUSB_TXCSR_DMAMODE 337 | MUSB_TXCSR_MODE); 338 /* 339 * Enable Autoset according to table 340 * below 341 * bulk_split hb_mult Autoset_Enable 342 * 0 0 Yes(Normal) 343 * 0 >0 No(High BW ISO) 344 * 1 0 Yes(HS bulk) 345 * 1 >0 Yes(FS bulk) 346 */ 347 if (!musb_ep->hb_mult || 348 can_bulk_split(musb, 349 musb_ep->type)) 350 csr |= MUSB_TXCSR_AUTOSET; 351 } 352 csr &= ~MUSB_TXCSR_P_UNDERRUN; 353 354 musb_writew(epio, MUSB_TXCSR, csr); 355 } 356 } 357 358 if (is_cppi_enabled(musb)) { 359 /* program endpoint CSR first, then setup DMA */ 360 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 361 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | 362 MUSB_TXCSR_MODE; 363 musb_writew(epio, MUSB_TXCSR, (MUSB_TXCSR_P_WZC_BITS & 364 ~MUSB_TXCSR_P_UNDERRUN) | csr); 365 366 /* ensure writebuffer is empty */ 367 csr = musb_readw(epio, MUSB_TXCSR); 368 369 /* 370 * NOTE host side sets DMAENAB later than this; both are 371 * OK since the transfer dma glue (between CPPI and 372 * Mentor fifos) just tells CPPI it could start. Data 373 * only moves to the USB TX fifo when both fifos are 374 * ready. 375 */ 376 /* 377 * "mode" is irrelevant here; handle terminating ZLPs 378 * like PIO does, since the hardware RNDIS mode seems 379 * unreliable except for the 380 * last-packet-is-already-short case. 381 */ 382 use_dma = use_dma && c->channel_program( 383 musb_ep->dma, musb_ep->packet_sz, 384 0, 385 request->dma + request->actual, 386 request_size); 387 if (!use_dma) { 388 c->channel_release(musb_ep->dma); 389 musb_ep->dma = NULL; 390 csr &= ~MUSB_TXCSR_DMAENAB; 391 musb_writew(epio, MUSB_TXCSR, csr); 392 /* invariant: prequest->buf is non-null */ 393 } 394 } else if (tusb_dma_omap(musb)) 395 use_dma = use_dma && c->channel_program( 396 musb_ep->dma, musb_ep->packet_sz, 397 request->zero, 398 request->dma + request->actual, 399 request_size); 400 } 401 #endif 402 403 if (!use_dma) { 404 /* 405 * Unmap the dma buffer back to cpu if dma channel 406 * programming fails 407 */ 408 unmap_dma_buffer(req, musb); 409 410 musb_write_fifo(musb_ep->hw_ep, fifo_count, 411 (u8 *) (request->buf + request->actual)); 412 request->actual += fifo_count; 413 csr |= MUSB_TXCSR_TXPKTRDY; 414 csr &= ~MUSB_TXCSR_P_UNDERRUN; 415 musb_writew(epio, MUSB_TXCSR, csr); 416 } 417 418 /* host may already have the data when this message shows... */ 419 musb_dbg(musb, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d", 420 musb_ep->end_point.name, use_dma ? "dma" : "pio", 421 request->actual, request->length, 422 musb_readw(epio, MUSB_TXCSR), 423 fifo_count, 424 musb_readw(epio, MUSB_TXMAXP)); 425 } 426 427 /* 428 * FIFO state update (e.g. data ready). 429 * Called from IRQ, with controller locked. 430 */ 431 void musb_g_tx(struct musb *musb, u8 epnum) 432 { 433 u16 csr; 434 struct musb_request *req; 435 struct usb_request *request; 436 u8 __iomem *mbase = musb->mregs; 437 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; 438 void __iomem *epio = musb->endpoints[epnum].regs; 439 struct dma_channel *dma; 440 441 musb_ep_select(mbase, epnum); 442 req = next_request(musb_ep); 443 request = &req->request; 444 445 trace_musb_req_tx(req); 446 csr = musb_readw(epio, MUSB_TXCSR); 447 musb_dbg(musb, "<== %s, txcsr %04x", musb_ep->end_point.name, csr); 448 449 dma = is_dma_capable() ? musb_ep->dma : NULL; 450 451 /* 452 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX 453 * probably rates reporting as a host error. 454 */ 455 if (csr & MUSB_TXCSR_P_SENTSTALL) { 456 csr |= MUSB_TXCSR_P_WZC_BITS; 457 csr &= ~MUSB_TXCSR_P_SENTSTALL; 458 musb_writew(epio, MUSB_TXCSR, csr); 459 return; 460 } 461 462 if (csr & MUSB_TXCSR_P_UNDERRUN) { 463 /* We NAKed, no big deal... little reason to care. */ 464 csr |= MUSB_TXCSR_P_WZC_BITS; 465 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 466 musb_writew(epio, MUSB_TXCSR, csr); 467 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n", 468 epnum, request); 469 } 470 471 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 472 /* 473 * SHOULD NOT HAPPEN... has with CPPI though, after 474 * changing SENDSTALL (and other cases); harmless? 475 */ 476 musb_dbg(musb, "%s dma still busy?", musb_ep->end_point.name); 477 return; 478 } 479 480 if (request) { 481 u8 is_dma = 0; 482 bool short_packet = false; 483 484 if (dma && (csr & MUSB_TXCSR_DMAENAB)) { 485 is_dma = 1; 486 csr |= MUSB_TXCSR_P_WZC_BITS; 487 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | 488 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET); 489 musb_writew(epio, MUSB_TXCSR, csr); 490 /* Ensure writebuffer is empty. */ 491 csr = musb_readw(epio, MUSB_TXCSR); 492 request->actual += musb_ep->dma->actual_len; 493 musb_dbg(musb, "TXCSR%d %04x, DMA off, len %zu, req %p", 494 epnum, csr, musb_ep->dma->actual_len, request); 495 } 496 497 /* 498 * First, maybe a terminating short packet. Some DMA 499 * engines might handle this by themselves. 500 */ 501 if ((request->zero && request->length) 502 && (request->length % musb_ep->packet_sz == 0) 503 && (request->actual == request->length)) 504 short_packet = true; 505 506 if ((musb_dma_inventra(musb) || musb_dma_ux500(musb)) && 507 (is_dma && (!dma->desired_mode || 508 (request->actual & 509 (musb_ep->packet_sz - 1))))) 510 short_packet = true; 511 512 if (short_packet) { 513 /* 514 * On DMA completion, FIFO may not be 515 * available yet... 516 */ 517 if (csr & MUSB_TXCSR_TXPKTRDY) 518 return; 519 520 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE 521 | MUSB_TXCSR_TXPKTRDY); 522 request->zero = 0; 523 } 524 525 if (request->actual == request->length) { 526 musb_g_giveback(musb_ep, request, 0); 527 /* 528 * In the giveback function the MUSB lock is 529 * released and acquired after sometime. During 530 * this time period the INDEX register could get 531 * changed by the gadget_queue function especially 532 * on SMP systems. Reselect the INDEX to be sure 533 * we are reading/modifying the right registers 534 */ 535 musb_ep_select(mbase, epnum); 536 req = musb_ep->desc ? next_request(musb_ep) : NULL; 537 if (!req) { 538 musb_dbg(musb, "%s idle now", 539 musb_ep->end_point.name); 540 return; 541 } 542 } 543 544 txstate(musb, req); 545 } 546 } 547 548 /* ------------------------------------------------------------ */ 549 550 /* 551 * Context: controller locked, IRQs blocked, endpoint selected 552 */ 553 static void rxstate(struct musb *musb, struct musb_request *req) 554 { 555 const u8 epnum = req->epnum; 556 struct usb_request *request = &req->request; 557 struct musb_ep *musb_ep; 558 void __iomem *epio = musb->endpoints[epnum].regs; 559 unsigned len = 0; 560 u16 fifo_count; 561 u16 csr = musb_readw(epio, MUSB_RXCSR); 562 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; 563 u8 use_mode_1; 564 565 if (hw_ep->is_shared_fifo) 566 musb_ep = &hw_ep->ep_in; 567 else 568 musb_ep = &hw_ep->ep_out; 569 570 fifo_count = musb_ep->packet_sz; 571 572 /* Check if EP is disabled */ 573 if (!musb_ep->desc) { 574 musb_dbg(musb, "ep:%s disabled - ignore request", 575 musb_ep->end_point.name); 576 return; 577 } 578 579 /* We shouldn't get here while DMA is active, but we do... */ 580 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 581 musb_dbg(musb, "DMA pending..."); 582 return; 583 } 584 585 if (csr & MUSB_RXCSR_P_SENDSTALL) { 586 musb_dbg(musb, "%s stalling, RXCSR %04x", 587 musb_ep->end_point.name, csr); 588 return; 589 } 590 591 if (is_cppi_enabled(musb) && is_buffer_mapped(req)) { 592 struct dma_controller *c = musb->dma_controller; 593 struct dma_channel *channel = musb_ep->dma; 594 595 /* NOTE: CPPI won't actually stop advancing the DMA 596 * queue after short packet transfers, so this is almost 597 * always going to run as IRQ-per-packet DMA so that 598 * faults will be handled correctly. 599 */ 600 if (c->channel_program(channel, 601 musb_ep->packet_sz, 602 !request->short_not_ok, 603 request->dma + request->actual, 604 request->length - request->actual)) { 605 606 /* make sure that if an rxpkt arrived after the irq, 607 * the cppi engine will be ready to take it as soon 608 * as DMA is enabled 609 */ 610 csr &= ~(MUSB_RXCSR_AUTOCLEAR 611 | MUSB_RXCSR_DMAMODE); 612 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; 613 musb_writew(epio, MUSB_RXCSR, csr); 614 return; 615 } 616 } 617 618 if (csr & MUSB_RXCSR_RXPKTRDY) { 619 fifo_count = musb_readw(epio, MUSB_RXCOUNT); 620 621 /* 622 * Enable Mode 1 on RX transfers only when short_not_ok flag 623 * is set. Currently short_not_ok flag is set only from 624 * file_storage and f_mass_storage drivers 625 */ 626 627 if (request->short_not_ok && fifo_count == musb_ep->packet_sz) 628 use_mode_1 = 1; 629 else 630 use_mode_1 = 0; 631 632 if (request->actual < request->length) { 633 if (!is_buffer_mapped(req)) 634 goto buffer_aint_mapped; 635 636 if (musb_dma_inventra(musb)) { 637 struct dma_controller *c; 638 struct dma_channel *channel; 639 int use_dma = 0; 640 unsigned int transfer_size; 641 642 c = musb->dma_controller; 643 channel = musb_ep->dma; 644 645 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in 646 * mode 0 only. So we do not get endpoint interrupts due to DMA 647 * completion. We only get interrupts from DMA controller. 648 * 649 * We could operate in DMA mode 1 if we knew the size of the tranfer 650 * in advance. For mass storage class, request->length = what the host 651 * sends, so that'd work. But for pretty much everything else, 652 * request->length is routinely more than what the host sends. For 653 * most these gadgets, end of is signified either by a short packet, 654 * or filling the last byte of the buffer. (Sending extra data in 655 * that last pckate should trigger an overflow fault.) But in mode 1, 656 * we don't get DMA completion interrupt for short packets. 657 * 658 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), 659 * to get endpoint interrupt on every DMA req, but that didn't seem 660 * to work reliably. 661 * 662 * REVISIT an updated g_file_storage can set req->short_not_ok, which 663 * then becomes usable as a runtime "use mode 1" hint... 664 */ 665 666 /* Experimental: Mode1 works with mass storage use cases */ 667 if (use_mode_1) { 668 csr |= MUSB_RXCSR_AUTOCLEAR; 669 musb_writew(epio, MUSB_RXCSR, csr); 670 csr |= MUSB_RXCSR_DMAENAB; 671 musb_writew(epio, MUSB_RXCSR, csr); 672 673 /* 674 * this special sequence (enabling and then 675 * disabling MUSB_RXCSR_DMAMODE) is required 676 * to get DMAReq to activate 677 */ 678 musb_writew(epio, MUSB_RXCSR, 679 csr | MUSB_RXCSR_DMAMODE); 680 musb_writew(epio, MUSB_RXCSR, csr); 681 682 transfer_size = min_t(unsigned int, 683 request->length - 684 request->actual, 685 channel->max_len); 686 musb_ep->dma->desired_mode = 1; 687 } else { 688 if (!musb_ep->hb_mult && 689 musb_ep->hw_ep->rx_double_buffered) 690 csr |= MUSB_RXCSR_AUTOCLEAR; 691 csr |= MUSB_RXCSR_DMAENAB; 692 musb_writew(epio, MUSB_RXCSR, csr); 693 694 transfer_size = min(request->length - request->actual, 695 (unsigned)fifo_count); 696 musb_ep->dma->desired_mode = 0; 697 } 698 699 use_dma = c->channel_program( 700 channel, 701 musb_ep->packet_sz, 702 channel->desired_mode, 703 request->dma 704 + request->actual, 705 transfer_size); 706 707 if (use_dma) 708 return; 709 } 710 711 if ((musb_dma_ux500(musb)) && 712 (request->actual < request->length)) { 713 714 struct dma_controller *c; 715 struct dma_channel *channel; 716 unsigned int transfer_size = 0; 717 718 c = musb->dma_controller; 719 channel = musb_ep->dma; 720 721 /* In case first packet is short */ 722 if (fifo_count < musb_ep->packet_sz) 723 transfer_size = fifo_count; 724 else if (request->short_not_ok) 725 transfer_size = min_t(unsigned int, 726 request->length - 727 request->actual, 728 channel->max_len); 729 else 730 transfer_size = min_t(unsigned int, 731 request->length - 732 request->actual, 733 (unsigned)fifo_count); 734 735 csr &= ~MUSB_RXCSR_DMAMODE; 736 csr |= (MUSB_RXCSR_DMAENAB | 737 MUSB_RXCSR_AUTOCLEAR); 738 739 musb_writew(epio, MUSB_RXCSR, csr); 740 741 if (transfer_size <= musb_ep->packet_sz) { 742 musb_ep->dma->desired_mode = 0; 743 } else { 744 musb_ep->dma->desired_mode = 1; 745 /* Mode must be set after DMAENAB */ 746 csr |= MUSB_RXCSR_DMAMODE; 747 musb_writew(epio, MUSB_RXCSR, csr); 748 } 749 750 if (c->channel_program(channel, 751 musb_ep->packet_sz, 752 channel->desired_mode, 753 request->dma 754 + request->actual, 755 transfer_size)) 756 757 return; 758 } 759 760 len = request->length - request->actual; 761 musb_dbg(musb, "%s OUT/RX pio fifo %d/%d, maxpacket %d", 762 musb_ep->end_point.name, 763 fifo_count, len, 764 musb_ep->packet_sz); 765 766 fifo_count = min_t(unsigned, len, fifo_count); 767 768 if (tusb_dma_omap(musb)) { 769 struct dma_controller *c = musb->dma_controller; 770 struct dma_channel *channel = musb_ep->dma; 771 u32 dma_addr = request->dma + request->actual; 772 int ret; 773 774 ret = c->channel_program(channel, 775 musb_ep->packet_sz, 776 channel->desired_mode, 777 dma_addr, 778 fifo_count); 779 if (ret) 780 return; 781 } 782 783 /* 784 * Unmap the dma buffer back to cpu if dma channel 785 * programming fails. This buffer is mapped if the 786 * channel allocation is successful 787 */ 788 unmap_dma_buffer(req, musb); 789 790 /* 791 * Clear DMAENAB and AUTOCLEAR for the 792 * PIO mode transfer 793 */ 794 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR); 795 musb_writew(epio, MUSB_RXCSR, csr); 796 797 buffer_aint_mapped: 798 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) 799 (request->buf + request->actual)); 800 request->actual += fifo_count; 801 802 /* REVISIT if we left anything in the fifo, flush 803 * it and report -EOVERFLOW 804 */ 805 806 /* ack the read! */ 807 csr |= MUSB_RXCSR_P_WZC_BITS; 808 csr &= ~MUSB_RXCSR_RXPKTRDY; 809 musb_writew(epio, MUSB_RXCSR, csr); 810 } 811 } 812 813 /* reach the end or short packet detected */ 814 if (request->actual == request->length || 815 fifo_count < musb_ep->packet_sz) 816 musb_g_giveback(musb_ep, request, 0); 817 } 818 819 /* 820 * Data ready for a request; called from IRQ 821 */ 822 void musb_g_rx(struct musb *musb, u8 epnum) 823 { 824 u16 csr; 825 struct musb_request *req; 826 struct usb_request *request; 827 void __iomem *mbase = musb->mregs; 828 struct musb_ep *musb_ep; 829 void __iomem *epio = musb->endpoints[epnum].regs; 830 struct dma_channel *dma; 831 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; 832 833 if (hw_ep->is_shared_fifo) 834 musb_ep = &hw_ep->ep_in; 835 else 836 musb_ep = &hw_ep->ep_out; 837 838 musb_ep_select(mbase, epnum); 839 840 req = next_request(musb_ep); 841 if (!req) 842 return; 843 844 trace_musb_req_rx(req); 845 request = &req->request; 846 847 csr = musb_readw(epio, MUSB_RXCSR); 848 dma = is_dma_capable() ? musb_ep->dma : NULL; 849 850 musb_dbg(musb, "<== %s, rxcsr %04x%s %p", musb_ep->end_point.name, 851 csr, dma ? " (dma)" : "", request); 852 853 if (csr & MUSB_RXCSR_P_SENTSTALL) { 854 csr |= MUSB_RXCSR_P_WZC_BITS; 855 csr &= ~MUSB_RXCSR_P_SENTSTALL; 856 musb_writew(epio, MUSB_RXCSR, csr); 857 return; 858 } 859 860 if (csr & MUSB_RXCSR_P_OVERRUN) { 861 /* csr |= MUSB_RXCSR_P_WZC_BITS; */ 862 csr &= ~MUSB_RXCSR_P_OVERRUN; 863 musb_writew(epio, MUSB_RXCSR, csr); 864 865 musb_dbg(musb, "%s iso overrun on %p", musb_ep->name, request); 866 if (request->status == -EINPROGRESS) 867 request->status = -EOVERFLOW; 868 } 869 if (csr & MUSB_RXCSR_INCOMPRX) { 870 /* REVISIT not necessarily an error */ 871 musb_dbg(musb, "%s, incomprx", musb_ep->end_point.name); 872 } 873 874 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 875 /* "should not happen"; likely RXPKTRDY pending for DMA */ 876 musb_dbg(musb, "%s busy, csr %04x", 877 musb_ep->end_point.name, csr); 878 return; 879 } 880 881 if (dma && (csr & MUSB_RXCSR_DMAENAB)) { 882 csr &= ~(MUSB_RXCSR_AUTOCLEAR 883 | MUSB_RXCSR_DMAENAB 884 | MUSB_RXCSR_DMAMODE); 885 musb_writew(epio, MUSB_RXCSR, 886 MUSB_RXCSR_P_WZC_BITS | csr); 887 888 request->actual += musb_ep->dma->actual_len; 889 890 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ 891 defined(CONFIG_USB_UX500_DMA) 892 /* Autoclear doesn't clear RxPktRdy for short packets */ 893 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered) 894 || (dma->actual_len 895 & (musb_ep->packet_sz - 1))) { 896 /* ack the read! */ 897 csr &= ~MUSB_RXCSR_RXPKTRDY; 898 musb_writew(epio, MUSB_RXCSR, csr); 899 } 900 901 /* incomplete, and not short? wait for next IN packet */ 902 if ((request->actual < request->length) 903 && (musb_ep->dma->actual_len 904 == musb_ep->packet_sz)) { 905 /* In double buffer case, continue to unload fifo if 906 * there is Rx packet in FIFO. 907 **/ 908 csr = musb_readw(epio, MUSB_RXCSR); 909 if ((csr & MUSB_RXCSR_RXPKTRDY) && 910 hw_ep->rx_double_buffered) 911 goto exit; 912 return; 913 } 914 #endif 915 musb_g_giveback(musb_ep, request, 0); 916 /* 917 * In the giveback function the MUSB lock is 918 * released and acquired after sometime. During 919 * this time period the INDEX register could get 920 * changed by the gadget_queue function especially 921 * on SMP systems. Reselect the INDEX to be sure 922 * we are reading/modifying the right registers 923 */ 924 musb_ep_select(mbase, epnum); 925 926 req = next_request(musb_ep); 927 if (!req) 928 return; 929 } 930 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ 931 defined(CONFIG_USB_UX500_DMA) 932 exit: 933 #endif 934 /* Analyze request */ 935 rxstate(musb, req); 936 } 937 938 /* ------------------------------------------------------------ */ 939 940 static int musb_gadget_enable(struct usb_ep *ep, 941 const struct usb_endpoint_descriptor *desc) 942 { 943 unsigned long flags; 944 struct musb_ep *musb_ep; 945 struct musb_hw_ep *hw_ep; 946 void __iomem *regs; 947 struct musb *musb; 948 void __iomem *mbase; 949 u8 epnum; 950 u16 csr; 951 unsigned tmp; 952 int status = -EINVAL; 953 954 if (!ep || !desc) 955 return -EINVAL; 956 957 musb_ep = to_musb_ep(ep); 958 hw_ep = musb_ep->hw_ep; 959 regs = hw_ep->regs; 960 musb = musb_ep->musb; 961 mbase = musb->mregs; 962 epnum = musb_ep->current_epnum; 963 964 spin_lock_irqsave(&musb->lock, flags); 965 966 if (musb_ep->desc) { 967 status = -EBUSY; 968 goto fail; 969 } 970 musb_ep->type = usb_endpoint_type(desc); 971 972 /* check direction and (later) maxpacket size against endpoint */ 973 if (usb_endpoint_num(desc) != epnum) 974 goto fail; 975 976 /* REVISIT this rules out high bandwidth periodic transfers */ 977 tmp = usb_endpoint_maxp_mult(desc) - 1; 978 if (tmp) { 979 int ok; 980 981 if (usb_endpoint_dir_in(desc)) 982 ok = musb->hb_iso_tx; 983 else 984 ok = musb->hb_iso_rx; 985 986 if (!ok) { 987 musb_dbg(musb, "no support for high bandwidth ISO"); 988 goto fail; 989 } 990 musb_ep->hb_mult = tmp; 991 } else { 992 musb_ep->hb_mult = 0; 993 } 994 995 musb_ep->packet_sz = usb_endpoint_maxp(desc); 996 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1); 997 998 /* enable the interrupts for the endpoint, set the endpoint 999 * packet size (or fail), set the mode, clear the fifo 1000 */ 1001 musb_ep_select(mbase, epnum); 1002 if (usb_endpoint_dir_in(desc)) { 1003 1004 if (hw_ep->is_shared_fifo) 1005 musb_ep->is_in = 1; 1006 if (!musb_ep->is_in) 1007 goto fail; 1008 1009 if (tmp > hw_ep->max_packet_sz_tx) { 1010 musb_dbg(musb, "packet size beyond hardware FIFO size"); 1011 goto fail; 1012 } 1013 1014 musb->intrtxe |= (1 << epnum); 1015 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe); 1016 1017 /* REVISIT if can_bulk_split(), use by updating "tmp"; 1018 * likewise high bandwidth periodic tx 1019 */ 1020 /* Set TXMAXP with the FIFO size of the endpoint 1021 * to disable double buffering mode. 1022 */ 1023 if (musb->double_buffer_not_ok) { 1024 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx); 1025 } else { 1026 if (can_bulk_split(musb, musb_ep->type)) 1027 musb_ep->hb_mult = (hw_ep->max_packet_sz_tx / 1028 musb_ep->packet_sz) - 1; 1029 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz 1030 | (musb_ep->hb_mult << 11)); 1031 } 1032 1033 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; 1034 if (musb_readw(regs, MUSB_TXCSR) 1035 & MUSB_TXCSR_FIFONOTEMPTY) 1036 csr |= MUSB_TXCSR_FLUSHFIFO; 1037 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) 1038 csr |= MUSB_TXCSR_P_ISO; 1039 1040 /* set twice in case of double buffering */ 1041 musb_writew(regs, MUSB_TXCSR, csr); 1042 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ 1043 musb_writew(regs, MUSB_TXCSR, csr); 1044 1045 } else { 1046 1047 if (hw_ep->is_shared_fifo) 1048 musb_ep->is_in = 0; 1049 if (musb_ep->is_in) 1050 goto fail; 1051 1052 if (tmp > hw_ep->max_packet_sz_rx) { 1053 musb_dbg(musb, "packet size beyond hardware FIFO size"); 1054 goto fail; 1055 } 1056 1057 musb->intrrxe |= (1 << epnum); 1058 musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe); 1059 1060 /* REVISIT if can_bulk_combine() use by updating "tmp" 1061 * likewise high bandwidth periodic rx 1062 */ 1063 /* Set RXMAXP with the FIFO size of the endpoint 1064 * to disable double buffering mode. 1065 */ 1066 if (musb->double_buffer_not_ok) 1067 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx); 1068 else 1069 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz 1070 | (musb_ep->hb_mult << 11)); 1071 1072 /* force shared fifo to OUT-only mode */ 1073 if (hw_ep->is_shared_fifo) { 1074 csr = musb_readw(regs, MUSB_TXCSR); 1075 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); 1076 musb_writew(regs, MUSB_TXCSR, csr); 1077 } 1078 1079 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; 1080 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) 1081 csr |= MUSB_RXCSR_P_ISO; 1082 else if (musb_ep->type == USB_ENDPOINT_XFER_INT) 1083 csr |= MUSB_RXCSR_DISNYET; 1084 1085 /* set twice in case of double buffering */ 1086 musb_writew(regs, MUSB_RXCSR, csr); 1087 musb_writew(regs, MUSB_RXCSR, csr); 1088 } 1089 1090 /* NOTE: all the I/O code _should_ work fine without DMA, in case 1091 * for some reason you run out of channels here. 1092 */ 1093 if (is_dma_capable() && musb->dma_controller) { 1094 struct dma_controller *c = musb->dma_controller; 1095 1096 musb_ep->dma = c->channel_alloc(c, hw_ep, 1097 (desc->bEndpointAddress & USB_DIR_IN)); 1098 } else 1099 musb_ep->dma = NULL; 1100 1101 musb_ep->desc = desc; 1102 musb_ep->busy = 0; 1103 musb_ep->wedged = 0; 1104 status = 0; 1105 1106 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", 1107 musb_driver_name, musb_ep->end_point.name, 1108 ({ char *s; switch (musb_ep->type) { 1109 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; 1110 case USB_ENDPOINT_XFER_INT: s = "int"; break; 1111 default: s = "iso"; break; 1112 } s; }), 1113 musb_ep->is_in ? "IN" : "OUT", 1114 musb_ep->dma ? "dma, " : "", 1115 musb_ep->packet_sz); 1116 1117 schedule_delayed_work(&musb->irq_work, 0); 1118 1119 fail: 1120 spin_unlock_irqrestore(&musb->lock, flags); 1121 return status; 1122 } 1123 1124 /* 1125 * Disable an endpoint flushing all requests queued. 1126 */ 1127 static int musb_gadget_disable(struct usb_ep *ep) 1128 { 1129 unsigned long flags; 1130 struct musb *musb; 1131 u8 epnum; 1132 struct musb_ep *musb_ep; 1133 void __iomem *epio; 1134 int status = 0; 1135 1136 musb_ep = to_musb_ep(ep); 1137 musb = musb_ep->musb; 1138 epnum = musb_ep->current_epnum; 1139 epio = musb->endpoints[epnum].regs; 1140 1141 spin_lock_irqsave(&musb->lock, flags); 1142 musb_ep_select(musb->mregs, epnum); 1143 1144 /* zero the endpoint sizes */ 1145 if (musb_ep->is_in) { 1146 musb->intrtxe &= ~(1 << epnum); 1147 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); 1148 musb_writew(epio, MUSB_TXMAXP, 0); 1149 } else { 1150 musb->intrrxe &= ~(1 << epnum); 1151 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); 1152 musb_writew(epio, MUSB_RXMAXP, 0); 1153 } 1154 1155 /* abort all pending DMA and requests */ 1156 nuke(musb_ep, -ESHUTDOWN); 1157 1158 musb_ep->desc = NULL; 1159 musb_ep->end_point.desc = NULL; 1160 1161 schedule_delayed_work(&musb->irq_work, 0); 1162 1163 spin_unlock_irqrestore(&(musb->lock), flags); 1164 1165 musb_dbg(musb, "%s", musb_ep->end_point.name); 1166 1167 return status; 1168 } 1169 1170 /* 1171 * Allocate a request for an endpoint. 1172 * Reused by ep0 code. 1173 */ 1174 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) 1175 { 1176 struct musb_ep *musb_ep = to_musb_ep(ep); 1177 struct musb_request *request = NULL; 1178 1179 request = kzalloc(sizeof *request, gfp_flags); 1180 if (!request) 1181 return NULL; 1182 1183 request->request.dma = DMA_ADDR_INVALID; 1184 request->epnum = musb_ep->current_epnum; 1185 request->ep = musb_ep; 1186 1187 trace_musb_req_alloc(request); 1188 return &request->request; 1189 } 1190 1191 /* 1192 * Free a request 1193 * Reused by ep0 code. 1194 */ 1195 void musb_free_request(struct usb_ep *ep, struct usb_request *req) 1196 { 1197 struct musb_request *request = to_musb_request(req); 1198 1199 trace_musb_req_free(request); 1200 kfree(request); 1201 } 1202 1203 static LIST_HEAD(buffers); 1204 1205 struct free_record { 1206 struct list_head list; 1207 struct device *dev; 1208 unsigned bytes; 1209 dma_addr_t dma; 1210 }; 1211 1212 /* 1213 * Context: controller locked, IRQs blocked. 1214 */ 1215 void musb_ep_restart(struct musb *musb, struct musb_request *req) 1216 { 1217 trace_musb_req_start(req); 1218 musb_ep_select(musb->mregs, req->epnum); 1219 if (req->tx) 1220 txstate(musb, req); 1221 else 1222 rxstate(musb, req); 1223 } 1224 1225 static int musb_ep_restart_resume_work(struct musb *musb, void *data) 1226 { 1227 struct musb_request *req = data; 1228 1229 musb_ep_restart(musb, req); 1230 1231 return 0; 1232 } 1233 1234 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, 1235 gfp_t gfp_flags) 1236 { 1237 struct musb_ep *musb_ep; 1238 struct musb_request *request; 1239 struct musb *musb; 1240 int status; 1241 unsigned long lockflags; 1242 1243 if (!ep || !req) 1244 return -EINVAL; 1245 if (!req->buf) 1246 return -ENODATA; 1247 1248 musb_ep = to_musb_ep(ep); 1249 musb = musb_ep->musb; 1250 1251 request = to_musb_request(req); 1252 request->musb = musb; 1253 1254 if (request->ep != musb_ep) 1255 return -EINVAL; 1256 1257 status = pm_runtime_get(musb->controller); 1258 if ((status != -EINPROGRESS) && status < 0) { 1259 dev_err(musb->controller, 1260 "pm runtime get failed in %s\n", 1261 __func__); 1262 pm_runtime_put_noidle(musb->controller); 1263 1264 return status; 1265 } 1266 status = 0; 1267 1268 trace_musb_req_enq(request); 1269 1270 /* request is mine now... */ 1271 request->request.actual = 0; 1272 request->request.status = -EINPROGRESS; 1273 request->epnum = musb_ep->current_epnum; 1274 request->tx = musb_ep->is_in; 1275 1276 map_dma_buffer(request, musb, musb_ep); 1277 1278 spin_lock_irqsave(&musb->lock, lockflags); 1279 1280 /* don't queue if the ep is down */ 1281 if (!musb_ep->desc) { 1282 musb_dbg(musb, "req %p queued to %s while ep %s", 1283 req, ep->name, "disabled"); 1284 status = -ESHUTDOWN; 1285 unmap_dma_buffer(request, musb); 1286 goto unlock; 1287 } 1288 1289 /* add request to the list */ 1290 list_add_tail(&request->list, &musb_ep->req_list); 1291 1292 /* it this is the head of the queue, start i/o ... */ 1293 if (!musb_ep->busy && &request->list == musb_ep->req_list.next) { 1294 status = musb_queue_resume_work(musb, 1295 musb_ep_restart_resume_work, 1296 request); 1297 if (status < 0) 1298 dev_err(musb->controller, "%s resume work: %i\n", 1299 __func__, status); 1300 } 1301 1302 unlock: 1303 spin_unlock_irqrestore(&musb->lock, lockflags); 1304 pm_runtime_mark_last_busy(musb->controller); 1305 pm_runtime_put_autosuspend(musb->controller); 1306 1307 return status; 1308 } 1309 1310 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) 1311 { 1312 struct musb_ep *musb_ep = to_musb_ep(ep); 1313 struct musb_request *req = to_musb_request(request); 1314 struct musb_request *r; 1315 unsigned long flags; 1316 int status = 0; 1317 struct musb *musb = musb_ep->musb; 1318 1319 if (!ep || !request || req->ep != musb_ep) 1320 return -EINVAL; 1321 1322 trace_musb_req_deq(req); 1323 1324 spin_lock_irqsave(&musb->lock, flags); 1325 1326 list_for_each_entry(r, &musb_ep->req_list, list) { 1327 if (r == req) 1328 break; 1329 } 1330 if (r != req) { 1331 dev_err(musb->controller, "request %p not queued to %s\n", 1332 request, ep->name); 1333 status = -EINVAL; 1334 goto done; 1335 } 1336 1337 /* if the hardware doesn't have the request, easy ... */ 1338 if (musb_ep->req_list.next != &req->list || musb_ep->busy) 1339 musb_g_giveback(musb_ep, request, -ECONNRESET); 1340 1341 /* ... else abort the dma transfer ... */ 1342 else if (is_dma_capable() && musb_ep->dma) { 1343 struct dma_controller *c = musb->dma_controller; 1344 1345 musb_ep_select(musb->mregs, musb_ep->current_epnum); 1346 if (c->channel_abort) 1347 status = c->channel_abort(musb_ep->dma); 1348 else 1349 status = -EBUSY; 1350 if (status == 0) 1351 musb_g_giveback(musb_ep, request, -ECONNRESET); 1352 } else { 1353 /* NOTE: by sticking to easily tested hardware/driver states, 1354 * we leave counting of in-flight packets imprecise. 1355 */ 1356 musb_g_giveback(musb_ep, request, -ECONNRESET); 1357 } 1358 1359 done: 1360 spin_unlock_irqrestore(&musb->lock, flags); 1361 return status; 1362 } 1363 1364 /* 1365 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any 1366 * data but will queue requests. 1367 * 1368 * exported to ep0 code 1369 */ 1370 static int musb_gadget_set_halt(struct usb_ep *ep, int value) 1371 { 1372 struct musb_ep *musb_ep = to_musb_ep(ep); 1373 u8 epnum = musb_ep->current_epnum; 1374 struct musb *musb = musb_ep->musb; 1375 void __iomem *epio = musb->endpoints[epnum].regs; 1376 void __iomem *mbase; 1377 unsigned long flags; 1378 u16 csr; 1379 struct musb_request *request; 1380 int status = 0; 1381 1382 if (!ep) 1383 return -EINVAL; 1384 mbase = musb->mregs; 1385 1386 spin_lock_irqsave(&musb->lock, flags); 1387 1388 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { 1389 status = -EINVAL; 1390 goto done; 1391 } 1392 1393 musb_ep_select(mbase, epnum); 1394 1395 request = next_request(musb_ep); 1396 if (value) { 1397 if (request) { 1398 musb_dbg(musb, "request in progress, cannot halt %s", 1399 ep->name); 1400 status = -EAGAIN; 1401 goto done; 1402 } 1403 /* Cannot portably stall with non-empty FIFO */ 1404 if (musb_ep->is_in) { 1405 csr = musb_readw(epio, MUSB_TXCSR); 1406 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1407 musb_dbg(musb, "FIFO busy, cannot halt %s", 1408 ep->name); 1409 status = -EAGAIN; 1410 goto done; 1411 } 1412 } 1413 } else 1414 musb_ep->wedged = 0; 1415 1416 /* set/clear the stall and toggle bits */ 1417 musb_dbg(musb, "%s: %s stall", ep->name, value ? "set" : "clear"); 1418 if (musb_ep->is_in) { 1419 csr = musb_readw(epio, MUSB_TXCSR); 1420 csr |= MUSB_TXCSR_P_WZC_BITS 1421 | MUSB_TXCSR_CLRDATATOG; 1422 if (value) 1423 csr |= MUSB_TXCSR_P_SENDSTALL; 1424 else 1425 csr &= ~(MUSB_TXCSR_P_SENDSTALL 1426 | MUSB_TXCSR_P_SENTSTALL); 1427 csr &= ~MUSB_TXCSR_TXPKTRDY; 1428 musb_writew(epio, MUSB_TXCSR, csr); 1429 } else { 1430 csr = musb_readw(epio, MUSB_RXCSR); 1431 csr |= MUSB_RXCSR_P_WZC_BITS 1432 | MUSB_RXCSR_FLUSHFIFO 1433 | MUSB_RXCSR_CLRDATATOG; 1434 if (value) 1435 csr |= MUSB_RXCSR_P_SENDSTALL; 1436 else 1437 csr &= ~(MUSB_RXCSR_P_SENDSTALL 1438 | MUSB_RXCSR_P_SENTSTALL); 1439 musb_writew(epio, MUSB_RXCSR, csr); 1440 } 1441 1442 /* maybe start the first request in the queue */ 1443 if (!musb_ep->busy && !value && request) { 1444 musb_dbg(musb, "restarting the request"); 1445 musb_ep_restart(musb, request); 1446 } 1447 1448 done: 1449 spin_unlock_irqrestore(&musb->lock, flags); 1450 return status; 1451 } 1452 1453 /* 1454 * Sets the halt feature with the clear requests ignored 1455 */ 1456 static int musb_gadget_set_wedge(struct usb_ep *ep) 1457 { 1458 struct musb_ep *musb_ep = to_musb_ep(ep); 1459 1460 if (!ep) 1461 return -EINVAL; 1462 1463 musb_ep->wedged = 1; 1464 1465 return usb_ep_set_halt(ep); 1466 } 1467 1468 static int musb_gadget_fifo_status(struct usb_ep *ep) 1469 { 1470 struct musb_ep *musb_ep = to_musb_ep(ep); 1471 void __iomem *epio = musb_ep->hw_ep->regs; 1472 int retval = -EINVAL; 1473 1474 if (musb_ep->desc && !musb_ep->is_in) { 1475 struct musb *musb = musb_ep->musb; 1476 int epnum = musb_ep->current_epnum; 1477 void __iomem *mbase = musb->mregs; 1478 unsigned long flags; 1479 1480 spin_lock_irqsave(&musb->lock, flags); 1481 1482 musb_ep_select(mbase, epnum); 1483 /* FIXME return zero unless RXPKTRDY is set */ 1484 retval = musb_readw(epio, MUSB_RXCOUNT); 1485 1486 spin_unlock_irqrestore(&musb->lock, flags); 1487 } 1488 return retval; 1489 } 1490 1491 static void musb_gadget_fifo_flush(struct usb_ep *ep) 1492 { 1493 struct musb_ep *musb_ep = to_musb_ep(ep); 1494 struct musb *musb = musb_ep->musb; 1495 u8 epnum = musb_ep->current_epnum; 1496 void __iomem *epio = musb->endpoints[epnum].regs; 1497 void __iomem *mbase; 1498 unsigned long flags; 1499 u16 csr; 1500 1501 mbase = musb->mregs; 1502 1503 spin_lock_irqsave(&musb->lock, flags); 1504 musb_ep_select(mbase, (u8) epnum); 1505 1506 /* disable interrupts */ 1507 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum)); 1508 1509 if (musb_ep->is_in) { 1510 csr = musb_readw(epio, MUSB_TXCSR); 1511 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1512 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; 1513 /* 1514 * Setting both TXPKTRDY and FLUSHFIFO makes controller 1515 * to interrupt current FIFO loading, but not flushing 1516 * the already loaded ones. 1517 */ 1518 csr &= ~MUSB_TXCSR_TXPKTRDY; 1519 musb_writew(epio, MUSB_TXCSR, csr); 1520 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ 1521 musb_writew(epio, MUSB_TXCSR, csr); 1522 } 1523 } else { 1524 csr = musb_readw(epio, MUSB_RXCSR); 1525 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; 1526 musb_writew(epio, MUSB_RXCSR, csr); 1527 musb_writew(epio, MUSB_RXCSR, csr); 1528 } 1529 1530 /* re-enable interrupt */ 1531 musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe); 1532 spin_unlock_irqrestore(&musb->lock, flags); 1533 } 1534 1535 static const struct usb_ep_ops musb_ep_ops = { 1536 .enable = musb_gadget_enable, 1537 .disable = musb_gadget_disable, 1538 .alloc_request = musb_alloc_request, 1539 .free_request = musb_free_request, 1540 .queue = musb_gadget_queue, 1541 .dequeue = musb_gadget_dequeue, 1542 .set_halt = musb_gadget_set_halt, 1543 .set_wedge = musb_gadget_set_wedge, 1544 .fifo_status = musb_gadget_fifo_status, 1545 .fifo_flush = musb_gadget_fifo_flush 1546 }; 1547 1548 /* ----------------------------------------------------------------------- */ 1549 1550 static int musb_gadget_get_frame(struct usb_gadget *gadget) 1551 { 1552 struct musb *musb = gadget_to_musb(gadget); 1553 1554 return (int)musb_readw(musb->mregs, MUSB_FRAME); 1555 } 1556 1557 static int musb_gadget_wakeup(struct usb_gadget *gadget) 1558 { 1559 struct musb *musb = gadget_to_musb(gadget); 1560 void __iomem *mregs = musb->mregs; 1561 unsigned long flags; 1562 int status = -EINVAL; 1563 u8 power, devctl; 1564 int retries; 1565 1566 spin_lock_irqsave(&musb->lock, flags); 1567 1568 switch (musb->xceiv->otg->state) { 1569 case OTG_STATE_B_PERIPHERAL: 1570 /* NOTE: OTG state machine doesn't include B_SUSPENDED; 1571 * that's part of the standard usb 1.1 state machine, and 1572 * doesn't affect OTG transitions. 1573 */ 1574 if (musb->may_wakeup && musb->is_suspended) 1575 break; 1576 goto done; 1577 case OTG_STATE_B_IDLE: 1578 /* Start SRP ... OTG not required. */ 1579 devctl = musb_readb(mregs, MUSB_DEVCTL); 1580 musb_dbg(musb, "Sending SRP: devctl: %02x", devctl); 1581 devctl |= MUSB_DEVCTL_SESSION; 1582 musb_writeb(mregs, MUSB_DEVCTL, devctl); 1583 devctl = musb_readb(mregs, MUSB_DEVCTL); 1584 retries = 100; 1585 while (!(devctl & MUSB_DEVCTL_SESSION)) { 1586 devctl = musb_readb(mregs, MUSB_DEVCTL); 1587 if (retries-- < 1) 1588 break; 1589 } 1590 retries = 10000; 1591 while (devctl & MUSB_DEVCTL_SESSION) { 1592 devctl = musb_readb(mregs, MUSB_DEVCTL); 1593 if (retries-- < 1) 1594 break; 1595 } 1596 1597 spin_unlock_irqrestore(&musb->lock, flags); 1598 otg_start_srp(musb->xceiv->otg); 1599 spin_lock_irqsave(&musb->lock, flags); 1600 1601 /* Block idling for at least 1s */ 1602 musb_platform_try_idle(musb, 1603 jiffies + msecs_to_jiffies(1 * HZ)); 1604 1605 status = 0; 1606 goto done; 1607 default: 1608 musb_dbg(musb, "Unhandled wake: %s", 1609 usb_otg_state_string(musb->xceiv->otg->state)); 1610 goto done; 1611 } 1612 1613 status = 0; 1614 1615 power = musb_readb(mregs, MUSB_POWER); 1616 power |= MUSB_POWER_RESUME; 1617 musb_writeb(mregs, MUSB_POWER, power); 1618 musb_dbg(musb, "issue wakeup"); 1619 1620 /* FIXME do this next chunk in a timer callback, no udelay */ 1621 mdelay(2); 1622 1623 power = musb_readb(mregs, MUSB_POWER); 1624 power &= ~MUSB_POWER_RESUME; 1625 musb_writeb(mregs, MUSB_POWER, power); 1626 done: 1627 spin_unlock_irqrestore(&musb->lock, flags); 1628 return status; 1629 } 1630 1631 static int 1632 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) 1633 { 1634 gadget->is_selfpowered = !!is_selfpowered; 1635 return 0; 1636 } 1637 1638 static void musb_pullup(struct musb *musb, int is_on) 1639 { 1640 u8 power; 1641 1642 power = musb_readb(musb->mregs, MUSB_POWER); 1643 if (is_on) 1644 power |= MUSB_POWER_SOFTCONN; 1645 else 1646 power &= ~MUSB_POWER_SOFTCONN; 1647 1648 /* FIXME if on, HdrcStart; if off, HdrcStop */ 1649 1650 musb_dbg(musb, "gadget D+ pullup %s", 1651 is_on ? "on" : "off"); 1652 musb_writeb(musb->mregs, MUSB_POWER, power); 1653 } 1654 1655 #if 0 1656 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) 1657 { 1658 musb_dbg(musb, "<= %s =>\n", __func__); 1659 1660 /* 1661 * FIXME iff driver's softconnect flag is set (as it is during probe, 1662 * though that can clear it), just musb_pullup(). 1663 */ 1664 1665 return -EINVAL; 1666 } 1667 #endif 1668 1669 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) 1670 { 1671 struct musb *musb = gadget_to_musb(gadget); 1672 1673 if (!musb->xceiv->set_power) 1674 return -EOPNOTSUPP; 1675 return usb_phy_set_power(musb->xceiv, mA); 1676 } 1677 1678 static void musb_gadget_work(struct work_struct *work) 1679 { 1680 struct musb *musb; 1681 unsigned long flags; 1682 1683 musb = container_of(work, struct musb, gadget_work.work); 1684 pm_runtime_get_sync(musb->controller); 1685 spin_lock_irqsave(&musb->lock, flags); 1686 musb_pullup(musb, musb->softconnect); 1687 spin_unlock_irqrestore(&musb->lock, flags); 1688 pm_runtime_mark_last_busy(musb->controller); 1689 pm_runtime_put_autosuspend(musb->controller); 1690 } 1691 1692 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) 1693 { 1694 struct musb *musb = gadget_to_musb(gadget); 1695 unsigned long flags; 1696 1697 is_on = !!is_on; 1698 1699 /* NOTE: this assumes we are sensing vbus; we'd rather 1700 * not pullup unless the B-session is active. 1701 */ 1702 spin_lock_irqsave(&musb->lock, flags); 1703 if (is_on != musb->softconnect) { 1704 musb->softconnect = is_on; 1705 schedule_delayed_work(&musb->gadget_work, 0); 1706 } 1707 spin_unlock_irqrestore(&musb->lock, flags); 1708 1709 return 0; 1710 } 1711 1712 #ifdef CONFIG_BLACKFIN 1713 static struct usb_ep *musb_match_ep(struct usb_gadget *g, 1714 struct usb_endpoint_descriptor *desc, 1715 struct usb_ss_ep_comp_descriptor *ep_comp) 1716 { 1717 struct usb_ep *ep = NULL; 1718 1719 switch (usb_endpoint_type(desc)) { 1720 case USB_ENDPOINT_XFER_ISOC: 1721 case USB_ENDPOINT_XFER_BULK: 1722 if (usb_endpoint_dir_in(desc)) 1723 ep = gadget_find_ep_by_name(g, "ep5in"); 1724 else 1725 ep = gadget_find_ep_by_name(g, "ep6out"); 1726 break; 1727 case USB_ENDPOINT_XFER_INT: 1728 if (usb_endpoint_dir_in(desc)) 1729 ep = gadget_find_ep_by_name(g, "ep1in"); 1730 else 1731 ep = gadget_find_ep_by_name(g, "ep2out"); 1732 break; 1733 default: 1734 break; 1735 } 1736 1737 if (ep && usb_gadget_ep_match_desc(g, ep, desc, ep_comp)) 1738 return ep; 1739 1740 return NULL; 1741 } 1742 #else 1743 #define musb_match_ep NULL 1744 #endif 1745 1746 static int musb_gadget_start(struct usb_gadget *g, 1747 struct usb_gadget_driver *driver); 1748 static int musb_gadget_stop(struct usb_gadget *g); 1749 1750 static const struct usb_gadget_ops musb_gadget_operations = { 1751 .get_frame = musb_gadget_get_frame, 1752 .wakeup = musb_gadget_wakeup, 1753 .set_selfpowered = musb_gadget_set_self_powered, 1754 /* .vbus_session = musb_gadget_vbus_session, */ 1755 .vbus_draw = musb_gadget_vbus_draw, 1756 .pullup = musb_gadget_pullup, 1757 .udc_start = musb_gadget_start, 1758 .udc_stop = musb_gadget_stop, 1759 .match_ep = musb_match_ep, 1760 }; 1761 1762 /* ----------------------------------------------------------------------- */ 1763 1764 /* Registration */ 1765 1766 /* Only this registration code "knows" the rule (from USB standards) 1767 * about there being only one external upstream port. It assumes 1768 * all peripheral ports are external... 1769 */ 1770 1771 static void 1772 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) 1773 { 1774 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1775 1776 memset(ep, 0, sizeof *ep); 1777 1778 ep->current_epnum = epnum; 1779 ep->musb = musb; 1780 ep->hw_ep = hw_ep; 1781 ep->is_in = is_in; 1782 1783 INIT_LIST_HEAD(&ep->req_list); 1784 1785 sprintf(ep->name, "ep%d%s", epnum, 1786 (!epnum || hw_ep->is_shared_fifo) ? "" : ( 1787 is_in ? "in" : "out")); 1788 ep->end_point.name = ep->name; 1789 INIT_LIST_HEAD(&ep->end_point.ep_list); 1790 if (!epnum) { 1791 usb_ep_set_maxpacket_limit(&ep->end_point, 64); 1792 ep->end_point.caps.type_control = true; 1793 ep->end_point.ops = &musb_g_ep0_ops; 1794 musb->g.ep0 = &ep->end_point; 1795 } else { 1796 if (is_in) 1797 usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_tx); 1798 else 1799 usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_rx); 1800 ep->end_point.caps.type_iso = true; 1801 ep->end_point.caps.type_bulk = true; 1802 ep->end_point.caps.type_int = true; 1803 ep->end_point.ops = &musb_ep_ops; 1804 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); 1805 } 1806 1807 if (!epnum || hw_ep->is_shared_fifo) { 1808 ep->end_point.caps.dir_in = true; 1809 ep->end_point.caps.dir_out = true; 1810 } else if (is_in) 1811 ep->end_point.caps.dir_in = true; 1812 else 1813 ep->end_point.caps.dir_out = true; 1814 } 1815 1816 /* 1817 * Initialize the endpoints exposed to peripheral drivers, with backlinks 1818 * to the rest of the driver state. 1819 */ 1820 static inline void musb_g_init_endpoints(struct musb *musb) 1821 { 1822 u8 epnum; 1823 struct musb_hw_ep *hw_ep; 1824 unsigned count = 0; 1825 1826 /* initialize endpoint list just once */ 1827 INIT_LIST_HEAD(&(musb->g.ep_list)); 1828 1829 for (epnum = 0, hw_ep = musb->endpoints; 1830 epnum < musb->nr_endpoints; 1831 epnum++, hw_ep++) { 1832 if (hw_ep->is_shared_fifo /* || !epnum */) { 1833 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); 1834 count++; 1835 } else { 1836 if (hw_ep->max_packet_sz_tx) { 1837 init_peripheral_ep(musb, &hw_ep->ep_in, 1838 epnum, 1); 1839 count++; 1840 } 1841 if (hw_ep->max_packet_sz_rx) { 1842 init_peripheral_ep(musb, &hw_ep->ep_out, 1843 epnum, 0); 1844 count++; 1845 } 1846 } 1847 } 1848 } 1849 1850 /* called once during driver setup to initialize and link into 1851 * the driver model; memory is zeroed. 1852 */ 1853 int musb_gadget_setup(struct musb *musb) 1854 { 1855 int status; 1856 1857 /* REVISIT minor race: if (erroneously) setting up two 1858 * musb peripherals at the same time, only the bus lock 1859 * is probably held. 1860 */ 1861 1862 musb->g.ops = &musb_gadget_operations; 1863 musb->g.max_speed = USB_SPEED_HIGH; 1864 musb->g.speed = USB_SPEED_UNKNOWN; 1865 1866 MUSB_DEV_MODE(musb); 1867 musb->xceiv->otg->default_a = 0; 1868 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 1869 1870 /* this "gadget" abstracts/virtualizes the controller */ 1871 musb->g.name = musb_driver_name; 1872 #if IS_ENABLED(CONFIG_USB_MUSB_DUAL_ROLE) 1873 musb->g.is_otg = 1; 1874 #elif IS_ENABLED(CONFIG_USB_MUSB_GADGET) 1875 musb->g.is_otg = 0; 1876 #endif 1877 INIT_DELAYED_WORK(&musb->gadget_work, musb_gadget_work); 1878 musb_g_init_endpoints(musb); 1879 1880 musb->is_active = 0; 1881 musb_platform_try_idle(musb, 0); 1882 1883 status = usb_add_gadget_udc(musb->controller, &musb->g); 1884 if (status) 1885 goto err; 1886 1887 return 0; 1888 err: 1889 musb->g.dev.parent = NULL; 1890 device_unregister(&musb->g.dev); 1891 return status; 1892 } 1893 1894 void musb_gadget_cleanup(struct musb *musb) 1895 { 1896 if (musb->port_mode == MUSB_PORT_MODE_HOST) 1897 return; 1898 1899 cancel_delayed_work_sync(&musb->gadget_work); 1900 usb_del_gadget_udc(&musb->g); 1901 } 1902 1903 /* 1904 * Register the gadget driver. Used by gadget drivers when 1905 * registering themselves with the controller. 1906 * 1907 * -EINVAL something went wrong (not driver) 1908 * -EBUSY another gadget is already using the controller 1909 * -ENOMEM no memory to perform the operation 1910 * 1911 * @param driver the gadget driver 1912 * @return <0 if error, 0 if everything is fine 1913 */ 1914 static int musb_gadget_start(struct usb_gadget *g, 1915 struct usb_gadget_driver *driver) 1916 { 1917 struct musb *musb = gadget_to_musb(g); 1918 struct usb_otg *otg = musb->xceiv->otg; 1919 unsigned long flags; 1920 int retval = 0; 1921 1922 if (driver->max_speed < USB_SPEED_HIGH) { 1923 retval = -EINVAL; 1924 goto err; 1925 } 1926 1927 pm_runtime_get_sync(musb->controller); 1928 1929 musb->softconnect = 0; 1930 musb->gadget_driver = driver; 1931 1932 spin_lock_irqsave(&musb->lock, flags); 1933 musb->is_active = 1; 1934 1935 otg_set_peripheral(otg, &musb->g); 1936 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 1937 spin_unlock_irqrestore(&musb->lock, flags); 1938 1939 musb_start(musb); 1940 1941 /* REVISIT: funcall to other code, which also 1942 * handles power budgeting ... this way also 1943 * ensures HdrcStart is indirectly called. 1944 */ 1945 if (musb->xceiv->last_event == USB_EVENT_ID) 1946 musb_platform_set_vbus(musb, 1); 1947 1948 pm_runtime_mark_last_busy(musb->controller); 1949 pm_runtime_put_autosuspend(musb->controller); 1950 1951 return 0; 1952 1953 err: 1954 return retval; 1955 } 1956 1957 /* 1958 * Unregister the gadget driver. Used by gadget drivers when 1959 * unregistering themselves from the controller. 1960 * 1961 * @param driver the gadget driver to unregister 1962 */ 1963 static int musb_gadget_stop(struct usb_gadget *g) 1964 { 1965 struct musb *musb = gadget_to_musb(g); 1966 unsigned long flags; 1967 1968 pm_runtime_get_sync(musb->controller); 1969 1970 /* 1971 * REVISIT always use otg_set_peripheral() here too; 1972 * this needs to shut down the OTG engine. 1973 */ 1974 1975 spin_lock_irqsave(&musb->lock, flags); 1976 1977 musb_hnp_stop(musb); 1978 1979 (void) musb_gadget_vbus_draw(&musb->g, 0); 1980 1981 musb->xceiv->otg->state = OTG_STATE_UNDEFINED; 1982 musb_stop(musb); 1983 otg_set_peripheral(musb->xceiv->otg, NULL); 1984 1985 musb->is_active = 0; 1986 musb->gadget_driver = NULL; 1987 musb_platform_try_idle(musb, 0); 1988 spin_unlock_irqrestore(&musb->lock, flags); 1989 1990 /* 1991 * FIXME we need to be able to register another 1992 * gadget driver here and have everything work; 1993 * that currently misbehaves. 1994 */ 1995 1996 /* Force check of devctl register for PM runtime */ 1997 schedule_delayed_work(&musb->irq_work, 0); 1998 1999 pm_runtime_mark_last_busy(musb->controller); 2000 pm_runtime_put_autosuspend(musb->controller); 2001 2002 return 0; 2003 } 2004 2005 /* ----------------------------------------------------------------------- */ 2006 2007 /* lifecycle operations called through plat_uds.c */ 2008 2009 void musb_g_resume(struct musb *musb) 2010 { 2011 musb->is_suspended = 0; 2012 switch (musb->xceiv->otg->state) { 2013 case OTG_STATE_B_IDLE: 2014 break; 2015 case OTG_STATE_B_WAIT_ACON: 2016 case OTG_STATE_B_PERIPHERAL: 2017 musb->is_active = 1; 2018 if (musb->gadget_driver && musb->gadget_driver->resume) { 2019 spin_unlock(&musb->lock); 2020 musb->gadget_driver->resume(&musb->g); 2021 spin_lock(&musb->lock); 2022 } 2023 break; 2024 default: 2025 WARNING("unhandled RESUME transition (%s)\n", 2026 usb_otg_state_string(musb->xceiv->otg->state)); 2027 } 2028 } 2029 2030 /* called when SOF packets stop for 3+ msec */ 2031 void musb_g_suspend(struct musb *musb) 2032 { 2033 u8 devctl; 2034 2035 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2036 musb_dbg(musb, "musb_g_suspend: devctl %02x", devctl); 2037 2038 switch (musb->xceiv->otg->state) { 2039 case OTG_STATE_B_IDLE: 2040 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 2041 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 2042 break; 2043 case OTG_STATE_B_PERIPHERAL: 2044 musb->is_suspended = 1; 2045 if (musb->gadget_driver && musb->gadget_driver->suspend) { 2046 spin_unlock(&musb->lock); 2047 musb->gadget_driver->suspend(&musb->g); 2048 spin_lock(&musb->lock); 2049 } 2050 break; 2051 default: 2052 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; 2053 * A_PERIPHERAL may need care too 2054 */ 2055 WARNING("unhandled SUSPEND transition (%s)", 2056 usb_otg_state_string(musb->xceiv->otg->state)); 2057 } 2058 } 2059 2060 /* Called during SRP */ 2061 void musb_g_wakeup(struct musb *musb) 2062 { 2063 musb_gadget_wakeup(&musb->g); 2064 } 2065 2066 /* called when VBUS drops below session threshold, and in other cases */ 2067 void musb_g_disconnect(struct musb *musb) 2068 { 2069 void __iomem *mregs = musb->mregs; 2070 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 2071 2072 musb_dbg(musb, "musb_g_disconnect: devctl %02x", devctl); 2073 2074 /* clear HR */ 2075 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); 2076 2077 /* don't draw vbus until new b-default session */ 2078 (void) musb_gadget_vbus_draw(&musb->g, 0); 2079 2080 musb->g.speed = USB_SPEED_UNKNOWN; 2081 if (musb->gadget_driver && musb->gadget_driver->disconnect) { 2082 spin_unlock(&musb->lock); 2083 musb->gadget_driver->disconnect(&musb->g); 2084 spin_lock(&musb->lock); 2085 } 2086 2087 switch (musb->xceiv->otg->state) { 2088 default: 2089 musb_dbg(musb, "Unhandled disconnect %s, setting a_idle", 2090 usb_otg_state_string(musb->xceiv->otg->state)); 2091 musb->xceiv->otg->state = OTG_STATE_A_IDLE; 2092 MUSB_HST_MODE(musb); 2093 break; 2094 case OTG_STATE_A_PERIPHERAL: 2095 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; 2096 MUSB_HST_MODE(musb); 2097 break; 2098 case OTG_STATE_B_WAIT_ACON: 2099 case OTG_STATE_B_HOST: 2100 case OTG_STATE_B_PERIPHERAL: 2101 case OTG_STATE_B_IDLE: 2102 musb->xceiv->otg->state = OTG_STATE_B_IDLE; 2103 break; 2104 case OTG_STATE_B_SRP_INIT: 2105 break; 2106 } 2107 2108 musb->is_active = 0; 2109 } 2110 2111 void musb_g_reset(struct musb *musb) 2112 __releases(musb->lock) 2113 __acquires(musb->lock) 2114 { 2115 void __iomem *mbase = musb->mregs; 2116 u8 devctl = musb_readb(mbase, MUSB_DEVCTL); 2117 u8 power; 2118 2119 musb_dbg(musb, "<== %s driver '%s'", 2120 (devctl & MUSB_DEVCTL_BDEVICE) 2121 ? "B-Device" : "A-Device", 2122 musb->gadget_driver 2123 ? musb->gadget_driver->driver.name 2124 : NULL 2125 ); 2126 2127 /* report reset, if we didn't already (flushing EP state) */ 2128 if (musb->gadget_driver && musb->g.speed != USB_SPEED_UNKNOWN) { 2129 spin_unlock(&musb->lock); 2130 usb_gadget_udc_reset(&musb->g, musb->gadget_driver); 2131 spin_lock(&musb->lock); 2132 } 2133 2134 /* clear HR */ 2135 else if (devctl & MUSB_DEVCTL_HR) 2136 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 2137 2138 2139 /* what speed did we negotiate? */ 2140 power = musb_readb(mbase, MUSB_POWER); 2141 musb->g.speed = (power & MUSB_POWER_HSMODE) 2142 ? USB_SPEED_HIGH : USB_SPEED_FULL; 2143 2144 /* start in USB_STATE_DEFAULT */ 2145 musb->is_active = 1; 2146 musb->is_suspended = 0; 2147 MUSB_DEV_MODE(musb); 2148 musb->address = 0; 2149 musb->ep0_state = MUSB_EP0_STAGE_SETUP; 2150 2151 musb->may_wakeup = 0; 2152 musb->g.b_hnp_enable = 0; 2153 musb->g.a_alt_hnp_support = 0; 2154 musb->g.a_hnp_support = 0; 2155 musb->g.quirk_zlp_not_supp = 1; 2156 2157 /* Normal reset, as B-Device; 2158 * or else after HNP, as A-Device 2159 */ 2160 if (!musb->g.is_otg) { 2161 /* USB device controllers that are not OTG compatible 2162 * may not have DEVCTL register in silicon. 2163 * In that case, do not rely on devctl for setting 2164 * peripheral mode. 2165 */ 2166 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 2167 musb->g.is_a_peripheral = 0; 2168 } else if (devctl & MUSB_DEVCTL_BDEVICE) { 2169 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; 2170 musb->g.is_a_peripheral = 0; 2171 } else { 2172 musb->xceiv->otg->state = OTG_STATE_A_PERIPHERAL; 2173 musb->g.is_a_peripheral = 1; 2174 } 2175 2176 /* start with default limits on VBUS power draw */ 2177 (void) musb_gadget_vbus_draw(&musb->g, 8); 2178 } 2179