1 /* 2 * MUSB OTG driver peripheral support 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2006 by Texas Instruments 6 * Copyright (C) 2006-2007 Nokia Corporation 7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * version 2 as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 21 * 02110-1301 USA 22 * 23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 #include <linux/kernel.h> 37 #include <linux/list.h> 38 #include <linux/timer.h> 39 #include <linux/module.h> 40 #include <linux/smp.h> 41 #include <linux/spinlock.h> 42 #include <linux/delay.h> 43 #include <linux/moduleparam.h> 44 #include <linux/stat.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/slab.h> 47 48 #include "musb_core.h" 49 50 51 /* MUSB PERIPHERAL status 3-mar-2006: 52 * 53 * - EP0 seems solid. It passes both USBCV and usbtest control cases. 54 * Minor glitches: 55 * 56 * + remote wakeup to Linux hosts work, but saw USBCV failures; 57 * in one test run (operator error?) 58 * + endpoint halt tests -- in both usbtest and usbcv -- seem 59 * to break when dma is enabled ... is something wrongly 60 * clearing SENDSTALL? 61 * 62 * - Mass storage behaved ok when last tested. Network traffic patterns 63 * (with lots of short transfers etc) need retesting; they turn up the 64 * worst cases of the DMA, since short packets are typical but are not 65 * required. 66 * 67 * - TX/IN 68 * + both pio and dma behave in with network and g_zero tests 69 * + no cppi throughput issues other than no-hw-queueing 70 * + failed with FLAT_REG (DaVinci) 71 * + seems to behave with double buffering, PIO -and- CPPI 72 * + with gadgetfs + AIO, requests got lost? 73 * 74 * - RX/OUT 75 * + both pio and dma behave in with network and g_zero tests 76 * + dma is slow in typical case (short_not_ok is clear) 77 * + double buffering ok with PIO 78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes 79 * + request lossage observed with gadgetfs 80 * 81 * - ISO not tested ... might work, but only weakly isochronous 82 * 83 * - Gadget driver disabling of softconnect during bind() is ignored; so 84 * drivers can't hold off host requests until userspace is ready. 85 * (Workaround: they can turn it off later.) 86 * 87 * - PORTABILITY (assumes PIO works): 88 * + DaVinci, basically works with cppi dma 89 * + OMAP 2430, ditto with mentor dma 90 * + TUSB 6010, platform-specific dma in the works 91 */ 92 93 /* ----------------------------------------------------------------------- */ 94 95 #define is_buffer_mapped(req) (is_dma_capable() && \ 96 (req->map_state != UN_MAPPED)) 97 98 /* Maps the buffer to dma */ 99 100 static inline void map_dma_buffer(struct musb_request *request, 101 struct musb *musb, struct musb_ep *musb_ep) 102 { 103 int compatible = true; 104 struct dma_controller *dma = musb->dma_controller; 105 106 request->map_state = UN_MAPPED; 107 108 if (!is_dma_capable() || !musb_ep->dma) 109 return; 110 111 /* Check if DMA engine can handle this request. 112 * DMA code must reject the USB request explicitly. 113 * Default behaviour is to map the request. 114 */ 115 if (dma->is_compatible) 116 compatible = dma->is_compatible(musb_ep->dma, 117 musb_ep->packet_sz, request->request.buf, 118 request->request.length); 119 if (!compatible) 120 return; 121 122 if (request->request.dma == DMA_ADDR_INVALID) { 123 request->request.dma = dma_map_single( 124 musb->controller, 125 request->request.buf, 126 request->request.length, 127 request->tx 128 ? DMA_TO_DEVICE 129 : DMA_FROM_DEVICE); 130 request->map_state = MUSB_MAPPED; 131 } else { 132 dma_sync_single_for_device(musb->controller, 133 request->request.dma, 134 request->request.length, 135 request->tx 136 ? DMA_TO_DEVICE 137 : DMA_FROM_DEVICE); 138 request->map_state = PRE_MAPPED; 139 } 140 } 141 142 /* Unmap the buffer from dma and maps it back to cpu */ 143 static inline void unmap_dma_buffer(struct musb_request *request, 144 struct musb *musb) 145 { 146 if (!is_buffer_mapped(request)) 147 return; 148 149 if (request->request.dma == DMA_ADDR_INVALID) { 150 dev_vdbg(musb->controller, 151 "not unmapping a never mapped buffer\n"); 152 return; 153 } 154 if (request->map_state == MUSB_MAPPED) { 155 dma_unmap_single(musb->controller, 156 request->request.dma, 157 request->request.length, 158 request->tx 159 ? DMA_TO_DEVICE 160 : DMA_FROM_DEVICE); 161 request->request.dma = DMA_ADDR_INVALID; 162 } else { /* PRE_MAPPED */ 163 dma_sync_single_for_cpu(musb->controller, 164 request->request.dma, 165 request->request.length, 166 request->tx 167 ? DMA_TO_DEVICE 168 : DMA_FROM_DEVICE); 169 } 170 request->map_state = UN_MAPPED; 171 } 172 173 /* 174 * Immediately complete a request. 175 * 176 * @param request the request to complete 177 * @param status the status to complete the request with 178 * Context: controller locked, IRQs blocked. 179 */ 180 void musb_g_giveback( 181 struct musb_ep *ep, 182 struct usb_request *request, 183 int status) 184 __releases(ep->musb->lock) 185 __acquires(ep->musb->lock) 186 { 187 struct musb_request *req; 188 struct musb *musb; 189 int busy = ep->busy; 190 191 req = to_musb_request(request); 192 193 list_del(&req->list); 194 if (req->request.status == -EINPROGRESS) 195 req->request.status = status; 196 musb = req->musb; 197 198 ep->busy = 1; 199 spin_unlock(&musb->lock); 200 unmap_dma_buffer(req, musb); 201 if (request->status == 0) 202 dev_dbg(musb->controller, "%s done request %p, %d/%d\n", 203 ep->end_point.name, request, 204 req->request.actual, req->request.length); 205 else 206 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n", 207 ep->end_point.name, request, 208 req->request.actual, req->request.length, 209 request->status); 210 req->request.complete(&req->ep->end_point, &req->request); 211 spin_lock(&musb->lock); 212 ep->busy = busy; 213 } 214 215 /* ----------------------------------------------------------------------- */ 216 217 /* 218 * Abort requests queued to an endpoint using the status. Synchronous. 219 * caller locked controller and blocked irqs, and selected this ep. 220 */ 221 static void nuke(struct musb_ep *ep, const int status) 222 { 223 struct musb *musb = ep->musb; 224 struct musb_request *req = NULL; 225 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; 226 227 ep->busy = 1; 228 229 if (is_dma_capable() && ep->dma) { 230 struct dma_controller *c = ep->musb->dma_controller; 231 int value; 232 233 if (ep->is_in) { 234 /* 235 * The programming guide says that we must not clear 236 * the DMAMODE bit before DMAENAB, so we only 237 * clear it in the second write... 238 */ 239 musb_writew(epio, MUSB_TXCSR, 240 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); 241 musb_writew(epio, MUSB_TXCSR, 242 0 | MUSB_TXCSR_FLUSHFIFO); 243 } else { 244 musb_writew(epio, MUSB_RXCSR, 245 0 | MUSB_RXCSR_FLUSHFIFO); 246 musb_writew(epio, MUSB_RXCSR, 247 0 | MUSB_RXCSR_FLUSHFIFO); 248 } 249 250 value = c->channel_abort(ep->dma); 251 dev_dbg(musb->controller, "%s: abort DMA --> %d\n", 252 ep->name, value); 253 c->channel_release(ep->dma); 254 ep->dma = NULL; 255 } 256 257 while (!list_empty(&ep->req_list)) { 258 req = list_first_entry(&ep->req_list, struct musb_request, list); 259 musb_g_giveback(ep, &req->request, status); 260 } 261 } 262 263 /* ----------------------------------------------------------------------- */ 264 265 /* Data transfers - pure PIO, pure DMA, or mixed mode */ 266 267 /* 268 * This assumes the separate CPPI engine is responding to DMA requests 269 * from the usb core ... sequenced a bit differently from mentor dma. 270 */ 271 272 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) 273 { 274 if (can_bulk_split(musb, ep->type)) 275 return ep->hw_ep->max_packet_sz_tx; 276 else 277 return ep->packet_sz; 278 } 279 280 281 #ifdef CONFIG_USB_INVENTRA_DMA 282 283 /* Peripheral tx (IN) using Mentor DMA works as follows: 284 Only mode 0 is used for transfers <= wPktSize, 285 mode 1 is used for larger transfers, 286 287 One of the following happens: 288 - Host sends IN token which causes an endpoint interrupt 289 -> TxAvail 290 -> if DMA is currently busy, exit. 291 -> if queue is non-empty, txstate(). 292 293 - Request is queued by the gadget driver. 294 -> if queue was previously empty, txstate() 295 296 txstate() 297 -> start 298 /\ -> setup DMA 299 | (data is transferred to the FIFO, then sent out when 300 | IN token(s) are recd from Host. 301 | -> DMA interrupt on completion 302 | calls TxAvail. 303 | -> stop DMA, ~DMAENAB, 304 | -> set TxPktRdy for last short pkt or zlp 305 | -> Complete Request 306 | -> Continue next request (call txstate) 307 |___________________________________| 308 309 * Non-Mentor DMA engines can of course work differently, such as by 310 * upleveling from irq-per-packet to irq-per-buffer. 311 */ 312 313 #endif 314 315 /* 316 * An endpoint is transmitting data. This can be called either from 317 * the IRQ routine or from ep.queue() to kickstart a request on an 318 * endpoint. 319 * 320 * Context: controller locked, IRQs blocked, endpoint selected 321 */ 322 static void txstate(struct musb *musb, struct musb_request *req) 323 { 324 u8 epnum = req->epnum; 325 struct musb_ep *musb_ep; 326 void __iomem *epio = musb->endpoints[epnum].regs; 327 struct usb_request *request; 328 u16 fifo_count = 0, csr; 329 int use_dma = 0; 330 331 musb_ep = req->ep; 332 333 /* we shouldn't get here while DMA is active ... but we do ... */ 334 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 335 dev_dbg(musb->controller, "dma pending...\n"); 336 return; 337 } 338 339 /* read TXCSR before */ 340 csr = musb_readw(epio, MUSB_TXCSR); 341 342 request = &req->request; 343 fifo_count = min(max_ep_writesize(musb, musb_ep), 344 (int)(request->length - request->actual)); 345 346 if (csr & MUSB_TXCSR_TXPKTRDY) { 347 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n", 348 musb_ep->end_point.name, csr); 349 return; 350 } 351 352 if (csr & MUSB_TXCSR_P_SENDSTALL) { 353 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n", 354 musb_ep->end_point.name, csr); 355 return; 356 } 357 358 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", 359 epnum, musb_ep->packet_sz, fifo_count, 360 csr); 361 362 #ifndef CONFIG_MUSB_PIO_ONLY 363 if (is_buffer_mapped(req)) { 364 struct dma_controller *c = musb->dma_controller; 365 size_t request_size; 366 367 /* setup DMA, then program endpoint CSR */ 368 request_size = min_t(size_t, request->length - request->actual, 369 musb_ep->dma->max_len); 370 371 use_dma = (request->dma != DMA_ADDR_INVALID); 372 373 /* MUSB_TXCSR_P_ISO is still set correctly */ 374 375 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) 376 { 377 if (request_size < musb_ep->packet_sz) 378 musb_ep->dma->desired_mode = 0; 379 else 380 musb_ep->dma->desired_mode = 1; 381 382 use_dma = use_dma && c->channel_program( 383 musb_ep->dma, musb_ep->packet_sz, 384 musb_ep->dma->desired_mode, 385 request->dma + request->actual, request_size); 386 if (use_dma) { 387 if (musb_ep->dma->desired_mode == 0) { 388 /* 389 * We must not clear the DMAMODE bit 390 * before the DMAENAB bit -- and the 391 * latter doesn't always get cleared 392 * before we get here... 393 */ 394 csr &= ~(MUSB_TXCSR_AUTOSET 395 | MUSB_TXCSR_DMAENAB); 396 musb_writew(epio, MUSB_TXCSR, csr 397 | MUSB_TXCSR_P_WZC_BITS); 398 csr &= ~MUSB_TXCSR_DMAMODE; 399 csr |= (MUSB_TXCSR_DMAENAB | 400 MUSB_TXCSR_MODE); 401 /* against programming guide */ 402 } else { 403 csr |= (MUSB_TXCSR_DMAENAB 404 | MUSB_TXCSR_DMAMODE 405 | MUSB_TXCSR_MODE); 406 if (!musb_ep->hb_mult) 407 csr |= MUSB_TXCSR_AUTOSET; 408 } 409 csr &= ~MUSB_TXCSR_P_UNDERRUN; 410 411 musb_writew(epio, MUSB_TXCSR, csr); 412 } 413 } 414 415 #elif defined(CONFIG_USB_TI_CPPI_DMA) 416 /* program endpoint CSR first, then setup DMA */ 417 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 418 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | 419 MUSB_TXCSR_MODE; 420 musb_writew(epio, MUSB_TXCSR, 421 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN) 422 | csr); 423 424 /* ensure writebuffer is empty */ 425 csr = musb_readw(epio, MUSB_TXCSR); 426 427 /* NOTE host side sets DMAENAB later than this; both are 428 * OK since the transfer dma glue (between CPPI and Mentor 429 * fifos) just tells CPPI it could start. Data only moves 430 * to the USB TX fifo when both fifos are ready. 431 */ 432 433 /* "mode" is irrelevant here; handle terminating ZLPs like 434 * PIO does, since the hardware RNDIS mode seems unreliable 435 * except for the last-packet-is-already-short case. 436 */ 437 use_dma = use_dma && c->channel_program( 438 musb_ep->dma, musb_ep->packet_sz, 439 0, 440 request->dma + request->actual, 441 request_size); 442 if (!use_dma) { 443 c->channel_release(musb_ep->dma); 444 musb_ep->dma = NULL; 445 csr &= ~MUSB_TXCSR_DMAENAB; 446 musb_writew(epio, MUSB_TXCSR, csr); 447 /* invariant: prequest->buf is non-null */ 448 } 449 #elif defined(CONFIG_USB_TUSB_OMAP_DMA) 450 use_dma = use_dma && c->channel_program( 451 musb_ep->dma, musb_ep->packet_sz, 452 request->zero, 453 request->dma + request->actual, 454 request_size); 455 #endif 456 } 457 #endif 458 459 if (!use_dma) { 460 /* 461 * Unmap the dma buffer back to cpu if dma channel 462 * programming fails 463 */ 464 unmap_dma_buffer(req, musb); 465 466 musb_write_fifo(musb_ep->hw_ep, fifo_count, 467 (u8 *) (request->buf + request->actual)); 468 request->actual += fifo_count; 469 csr |= MUSB_TXCSR_TXPKTRDY; 470 csr &= ~MUSB_TXCSR_P_UNDERRUN; 471 musb_writew(epio, MUSB_TXCSR, csr); 472 } 473 474 /* host may already have the data when this message shows... */ 475 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", 476 musb_ep->end_point.name, use_dma ? "dma" : "pio", 477 request->actual, request->length, 478 musb_readw(epio, MUSB_TXCSR), 479 fifo_count, 480 musb_readw(epio, MUSB_TXMAXP)); 481 } 482 483 /* 484 * FIFO state update (e.g. data ready). 485 * Called from IRQ, with controller locked. 486 */ 487 void musb_g_tx(struct musb *musb, u8 epnum) 488 { 489 u16 csr; 490 struct musb_request *req; 491 struct usb_request *request; 492 u8 __iomem *mbase = musb->mregs; 493 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; 494 void __iomem *epio = musb->endpoints[epnum].regs; 495 struct dma_channel *dma; 496 497 musb_ep_select(mbase, epnum); 498 req = next_request(musb_ep); 499 request = &req->request; 500 501 csr = musb_readw(epio, MUSB_TXCSR); 502 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); 503 504 dma = is_dma_capable() ? musb_ep->dma : NULL; 505 506 /* 507 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX 508 * probably rates reporting as a host error. 509 */ 510 if (csr & MUSB_TXCSR_P_SENTSTALL) { 511 csr |= MUSB_TXCSR_P_WZC_BITS; 512 csr &= ~MUSB_TXCSR_P_SENTSTALL; 513 musb_writew(epio, MUSB_TXCSR, csr); 514 return; 515 } 516 517 if (csr & MUSB_TXCSR_P_UNDERRUN) { 518 /* We NAKed, no big deal... little reason to care. */ 519 csr |= MUSB_TXCSR_P_WZC_BITS; 520 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); 521 musb_writew(epio, MUSB_TXCSR, csr); 522 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n", 523 epnum, request); 524 } 525 526 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 527 /* 528 * SHOULD NOT HAPPEN... has with CPPI though, after 529 * changing SENDSTALL (and other cases); harmless? 530 */ 531 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name); 532 return; 533 } 534 535 if (request) { 536 u8 is_dma = 0; 537 538 if (dma && (csr & MUSB_TXCSR_DMAENAB)) { 539 is_dma = 1; 540 csr |= MUSB_TXCSR_P_WZC_BITS; 541 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | 542 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET); 543 musb_writew(epio, MUSB_TXCSR, csr); 544 /* Ensure writebuffer is empty. */ 545 csr = musb_readw(epio, MUSB_TXCSR); 546 request->actual += musb_ep->dma->actual_len; 547 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n", 548 epnum, csr, musb_ep->dma->actual_len, request); 549 } 550 551 /* 552 * First, maybe a terminating short packet. Some DMA 553 * engines might handle this by themselves. 554 */ 555 if ((request->zero && request->length 556 && (request->length % musb_ep->packet_sz == 0) 557 && (request->actual == request->length)) 558 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) 559 || (is_dma && (!dma->desired_mode || 560 (request->actual & 561 (musb_ep->packet_sz - 1)))) 562 #endif 563 ) { 564 /* 565 * On DMA completion, FIFO may not be 566 * available yet... 567 */ 568 if (csr & MUSB_TXCSR_TXPKTRDY) 569 return; 570 571 dev_dbg(musb->controller, "sending zero pkt\n"); 572 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE 573 | MUSB_TXCSR_TXPKTRDY); 574 request->zero = 0; 575 } 576 577 if (request->actual == request->length) { 578 musb_g_giveback(musb_ep, request, 0); 579 req = musb_ep->desc ? next_request(musb_ep) : NULL; 580 if (!req) { 581 dev_dbg(musb->controller, "%s idle now\n", 582 musb_ep->end_point.name); 583 return; 584 } 585 } 586 587 txstate(musb, req); 588 } 589 } 590 591 /* ------------------------------------------------------------ */ 592 593 #ifdef CONFIG_USB_INVENTRA_DMA 594 595 /* Peripheral rx (OUT) using Mentor DMA works as follows: 596 - Only mode 0 is used. 597 598 - Request is queued by the gadget class driver. 599 -> if queue was previously empty, rxstate() 600 601 - Host sends OUT token which causes an endpoint interrupt 602 /\ -> RxReady 603 | -> if request queued, call rxstate 604 | /\ -> setup DMA 605 | | -> DMA interrupt on completion 606 | | -> RxReady 607 | | -> stop DMA 608 | | -> ack the read 609 | | -> if data recd = max expected 610 | | by the request, or host 611 | | sent a short packet, 612 | | complete the request, 613 | | and start the next one. 614 | |_____________________________________| 615 | else just wait for the host 616 | to send the next OUT token. 617 |__________________________________________________| 618 619 * Non-Mentor DMA engines can of course work differently. 620 */ 621 622 #endif 623 624 /* 625 * Context: controller locked, IRQs blocked, endpoint selected 626 */ 627 static void rxstate(struct musb *musb, struct musb_request *req) 628 { 629 const u8 epnum = req->epnum; 630 struct usb_request *request = &req->request; 631 struct musb_ep *musb_ep; 632 void __iomem *epio = musb->endpoints[epnum].regs; 633 unsigned fifo_count = 0; 634 u16 len; 635 u16 csr = musb_readw(epio, MUSB_RXCSR); 636 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; 637 638 if (hw_ep->is_shared_fifo) 639 musb_ep = &hw_ep->ep_in; 640 else 641 musb_ep = &hw_ep->ep_out; 642 643 len = musb_ep->packet_sz; 644 645 /* We shouldn't get here while DMA is active, but we do... */ 646 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { 647 dev_dbg(musb->controller, "DMA pending...\n"); 648 return; 649 } 650 651 if (csr & MUSB_RXCSR_P_SENDSTALL) { 652 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n", 653 musb_ep->end_point.name, csr); 654 return; 655 } 656 657 if (is_cppi_enabled() && is_buffer_mapped(req)) { 658 struct dma_controller *c = musb->dma_controller; 659 struct dma_channel *channel = musb_ep->dma; 660 661 /* NOTE: CPPI won't actually stop advancing the DMA 662 * queue after short packet transfers, so this is almost 663 * always going to run as IRQ-per-packet DMA so that 664 * faults will be handled correctly. 665 */ 666 if (c->channel_program(channel, 667 musb_ep->packet_sz, 668 !request->short_not_ok, 669 request->dma + request->actual, 670 request->length - request->actual)) { 671 672 /* make sure that if an rxpkt arrived after the irq, 673 * the cppi engine will be ready to take it as soon 674 * as DMA is enabled 675 */ 676 csr &= ~(MUSB_RXCSR_AUTOCLEAR 677 | MUSB_RXCSR_DMAMODE); 678 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; 679 musb_writew(epio, MUSB_RXCSR, csr); 680 return; 681 } 682 } 683 684 if (csr & MUSB_RXCSR_RXPKTRDY) { 685 len = musb_readw(epio, MUSB_RXCOUNT); 686 if (request->actual < request->length) { 687 #ifdef CONFIG_USB_INVENTRA_DMA 688 if (is_buffer_mapped(req)) { 689 struct dma_controller *c; 690 struct dma_channel *channel; 691 int use_dma = 0; 692 693 c = musb->dma_controller; 694 channel = musb_ep->dma; 695 696 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in 697 * mode 0 only. So we do not get endpoint interrupts due to DMA 698 * completion. We only get interrupts from DMA controller. 699 * 700 * We could operate in DMA mode 1 if we knew the size of the tranfer 701 * in advance. For mass storage class, request->length = what the host 702 * sends, so that'd work. But for pretty much everything else, 703 * request->length is routinely more than what the host sends. For 704 * most these gadgets, end of is signified either by a short packet, 705 * or filling the last byte of the buffer. (Sending extra data in 706 * that last pckate should trigger an overflow fault.) But in mode 1, 707 * we don't get DMA completion interrrupt for short packets. 708 * 709 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), 710 * to get endpoint interrupt on every DMA req, but that didn't seem 711 * to work reliably. 712 * 713 * REVISIT an updated g_file_storage can set req->short_not_ok, which 714 * then becomes usable as a runtime "use mode 1" hint... 715 */ 716 717 csr |= MUSB_RXCSR_DMAENAB; 718 #ifdef USE_MODE1 719 csr |= MUSB_RXCSR_AUTOCLEAR; 720 /* csr |= MUSB_RXCSR_DMAMODE; */ 721 722 /* this special sequence (enabling and then 723 * disabling MUSB_RXCSR_DMAMODE) is required 724 * to get DMAReq to activate 725 */ 726 musb_writew(epio, MUSB_RXCSR, 727 csr | MUSB_RXCSR_DMAMODE); 728 #else 729 if (!musb_ep->hb_mult && 730 musb_ep->hw_ep->rx_double_buffered) 731 csr |= MUSB_RXCSR_AUTOCLEAR; 732 #endif 733 musb_writew(epio, MUSB_RXCSR, csr); 734 735 if (request->actual < request->length) { 736 int transfer_size = 0; 737 #ifdef USE_MODE1 738 transfer_size = min(request->length - request->actual, 739 channel->max_len); 740 #else 741 transfer_size = min(request->length - request->actual, 742 (unsigned)len); 743 #endif 744 if (transfer_size <= musb_ep->packet_sz) 745 musb_ep->dma->desired_mode = 0; 746 else 747 musb_ep->dma->desired_mode = 1; 748 749 use_dma = c->channel_program( 750 channel, 751 musb_ep->packet_sz, 752 channel->desired_mode, 753 request->dma 754 + request->actual, 755 transfer_size); 756 } 757 758 if (use_dma) 759 return; 760 } 761 #elif defined(CONFIG_USB_UX500_DMA) 762 if ((is_buffer_mapped(req)) && 763 (request->actual < request->length)) { 764 765 struct dma_controller *c; 766 struct dma_channel *channel; 767 int transfer_size = 0; 768 769 c = musb->dma_controller; 770 channel = musb_ep->dma; 771 772 /* In case first packet is short */ 773 if (len < musb_ep->packet_sz) 774 transfer_size = len; 775 else if (request->short_not_ok) 776 transfer_size = min(request->length - 777 request->actual, 778 channel->max_len); 779 else 780 transfer_size = min(request->length - 781 request->actual, 782 (unsigned)len); 783 784 csr &= ~MUSB_RXCSR_DMAMODE; 785 csr |= (MUSB_RXCSR_DMAENAB | 786 MUSB_RXCSR_AUTOCLEAR); 787 788 musb_writew(epio, MUSB_RXCSR, csr); 789 790 if (transfer_size <= musb_ep->packet_sz) { 791 musb_ep->dma->desired_mode = 0; 792 } else { 793 musb_ep->dma->desired_mode = 1; 794 /* Mode must be set after DMAENAB */ 795 csr |= MUSB_RXCSR_DMAMODE; 796 musb_writew(epio, MUSB_RXCSR, csr); 797 } 798 799 if (c->channel_program(channel, 800 musb_ep->packet_sz, 801 channel->desired_mode, 802 request->dma 803 + request->actual, 804 transfer_size)) 805 806 return; 807 } 808 #endif /* Mentor's DMA */ 809 810 fifo_count = request->length - request->actual; 811 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", 812 musb_ep->end_point.name, 813 len, fifo_count, 814 musb_ep->packet_sz); 815 816 fifo_count = min_t(unsigned, len, fifo_count); 817 818 #ifdef CONFIG_USB_TUSB_OMAP_DMA 819 if (tusb_dma_omap() && is_buffer_mapped(req)) { 820 struct dma_controller *c = musb->dma_controller; 821 struct dma_channel *channel = musb_ep->dma; 822 u32 dma_addr = request->dma + request->actual; 823 int ret; 824 825 ret = c->channel_program(channel, 826 musb_ep->packet_sz, 827 channel->desired_mode, 828 dma_addr, 829 fifo_count); 830 if (ret) 831 return; 832 } 833 #endif 834 /* 835 * Unmap the dma buffer back to cpu if dma channel 836 * programming fails. This buffer is mapped if the 837 * channel allocation is successful 838 */ 839 if (is_buffer_mapped(req)) { 840 unmap_dma_buffer(req, musb); 841 842 /* 843 * Clear DMAENAB and AUTOCLEAR for the 844 * PIO mode transfer 845 */ 846 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR); 847 musb_writew(epio, MUSB_RXCSR, csr); 848 } 849 850 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) 851 (request->buf + request->actual)); 852 request->actual += fifo_count; 853 854 /* REVISIT if we left anything in the fifo, flush 855 * it and report -EOVERFLOW 856 */ 857 858 /* ack the read! */ 859 csr |= MUSB_RXCSR_P_WZC_BITS; 860 csr &= ~MUSB_RXCSR_RXPKTRDY; 861 musb_writew(epio, MUSB_RXCSR, csr); 862 } 863 } 864 865 /* reach the end or short packet detected */ 866 if (request->actual == request->length || len < musb_ep->packet_sz) 867 musb_g_giveback(musb_ep, request, 0); 868 } 869 870 /* 871 * Data ready for a request; called from IRQ 872 */ 873 void musb_g_rx(struct musb *musb, u8 epnum) 874 { 875 u16 csr; 876 struct musb_request *req; 877 struct usb_request *request; 878 void __iomem *mbase = musb->mregs; 879 struct musb_ep *musb_ep; 880 void __iomem *epio = musb->endpoints[epnum].regs; 881 struct dma_channel *dma; 882 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; 883 884 if (hw_ep->is_shared_fifo) 885 musb_ep = &hw_ep->ep_in; 886 else 887 musb_ep = &hw_ep->ep_out; 888 889 musb_ep_select(mbase, epnum); 890 891 req = next_request(musb_ep); 892 if (!req) 893 return; 894 895 request = &req->request; 896 897 csr = musb_readw(epio, MUSB_RXCSR); 898 dma = is_dma_capable() ? musb_ep->dma : NULL; 899 900 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, 901 csr, dma ? " (dma)" : "", request); 902 903 if (csr & MUSB_RXCSR_P_SENTSTALL) { 904 csr |= MUSB_RXCSR_P_WZC_BITS; 905 csr &= ~MUSB_RXCSR_P_SENTSTALL; 906 musb_writew(epio, MUSB_RXCSR, csr); 907 return; 908 } 909 910 if (csr & MUSB_RXCSR_P_OVERRUN) { 911 /* csr |= MUSB_RXCSR_P_WZC_BITS; */ 912 csr &= ~MUSB_RXCSR_P_OVERRUN; 913 musb_writew(epio, MUSB_RXCSR, csr); 914 915 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request); 916 if (request->status == -EINPROGRESS) 917 request->status = -EOVERFLOW; 918 } 919 if (csr & MUSB_RXCSR_INCOMPRX) { 920 /* REVISIT not necessarily an error */ 921 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name); 922 } 923 924 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { 925 /* "should not happen"; likely RXPKTRDY pending for DMA */ 926 dev_dbg(musb->controller, "%s busy, csr %04x\n", 927 musb_ep->end_point.name, csr); 928 return; 929 } 930 931 if (dma && (csr & MUSB_RXCSR_DMAENAB)) { 932 csr &= ~(MUSB_RXCSR_AUTOCLEAR 933 | MUSB_RXCSR_DMAENAB 934 | MUSB_RXCSR_DMAMODE); 935 musb_writew(epio, MUSB_RXCSR, 936 MUSB_RXCSR_P_WZC_BITS | csr); 937 938 request->actual += musb_ep->dma->actual_len; 939 940 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", 941 epnum, csr, 942 musb_readw(epio, MUSB_RXCSR), 943 musb_ep->dma->actual_len, request); 944 945 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ 946 defined(CONFIG_USB_UX500_DMA) 947 /* Autoclear doesn't clear RxPktRdy for short packets */ 948 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered) 949 || (dma->actual_len 950 & (musb_ep->packet_sz - 1))) { 951 /* ack the read! */ 952 csr &= ~MUSB_RXCSR_RXPKTRDY; 953 musb_writew(epio, MUSB_RXCSR, csr); 954 } 955 956 /* incomplete, and not short? wait for next IN packet */ 957 if ((request->actual < request->length) 958 && (musb_ep->dma->actual_len 959 == musb_ep->packet_sz)) { 960 /* In double buffer case, continue to unload fifo if 961 * there is Rx packet in FIFO. 962 **/ 963 csr = musb_readw(epio, MUSB_RXCSR); 964 if ((csr & MUSB_RXCSR_RXPKTRDY) && 965 hw_ep->rx_double_buffered) 966 goto exit; 967 return; 968 } 969 #endif 970 musb_g_giveback(musb_ep, request, 0); 971 972 req = next_request(musb_ep); 973 if (!req) 974 return; 975 } 976 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ 977 defined(CONFIG_USB_UX500_DMA) 978 exit: 979 #endif 980 /* Analyze request */ 981 rxstate(musb, req); 982 } 983 984 /* ------------------------------------------------------------ */ 985 986 static int musb_gadget_enable(struct usb_ep *ep, 987 const struct usb_endpoint_descriptor *desc) 988 { 989 unsigned long flags; 990 struct musb_ep *musb_ep; 991 struct musb_hw_ep *hw_ep; 992 void __iomem *regs; 993 struct musb *musb; 994 void __iomem *mbase; 995 u8 epnum; 996 u16 csr; 997 unsigned tmp; 998 int status = -EINVAL; 999 1000 if (!ep || !desc) 1001 return -EINVAL; 1002 1003 musb_ep = to_musb_ep(ep); 1004 hw_ep = musb_ep->hw_ep; 1005 regs = hw_ep->regs; 1006 musb = musb_ep->musb; 1007 mbase = musb->mregs; 1008 epnum = musb_ep->current_epnum; 1009 1010 spin_lock_irqsave(&musb->lock, flags); 1011 1012 if (musb_ep->desc) { 1013 status = -EBUSY; 1014 goto fail; 1015 } 1016 musb_ep->type = usb_endpoint_type(desc); 1017 1018 /* check direction and (later) maxpacket size against endpoint */ 1019 if (usb_endpoint_num(desc) != epnum) 1020 goto fail; 1021 1022 /* REVISIT this rules out high bandwidth periodic transfers */ 1023 tmp = le16_to_cpu(desc->wMaxPacketSize); 1024 if (tmp & ~0x07ff) { 1025 int ok; 1026 1027 if (usb_endpoint_dir_in(desc)) 1028 ok = musb->hb_iso_tx; 1029 else 1030 ok = musb->hb_iso_rx; 1031 1032 if (!ok) { 1033 dev_dbg(musb->controller, "no support for high bandwidth ISO\n"); 1034 goto fail; 1035 } 1036 musb_ep->hb_mult = (tmp >> 11) & 3; 1037 } else { 1038 musb_ep->hb_mult = 0; 1039 } 1040 1041 musb_ep->packet_sz = tmp & 0x7ff; 1042 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1); 1043 1044 /* enable the interrupts for the endpoint, set the endpoint 1045 * packet size (or fail), set the mode, clear the fifo 1046 */ 1047 musb_ep_select(mbase, epnum); 1048 if (usb_endpoint_dir_in(desc)) { 1049 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE); 1050 1051 if (hw_ep->is_shared_fifo) 1052 musb_ep->is_in = 1; 1053 if (!musb_ep->is_in) 1054 goto fail; 1055 1056 if (tmp > hw_ep->max_packet_sz_tx) { 1057 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n"); 1058 goto fail; 1059 } 1060 1061 int_txe |= (1 << epnum); 1062 musb_writew(mbase, MUSB_INTRTXE, int_txe); 1063 1064 /* REVISIT if can_bulk_split(), use by updating "tmp"; 1065 * likewise high bandwidth periodic tx 1066 */ 1067 /* Set TXMAXP with the FIFO size of the endpoint 1068 * to disable double buffering mode. 1069 */ 1070 if (musb->double_buffer_not_ok) 1071 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx); 1072 else 1073 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz 1074 | (musb_ep->hb_mult << 11)); 1075 1076 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; 1077 if (musb_readw(regs, MUSB_TXCSR) 1078 & MUSB_TXCSR_FIFONOTEMPTY) 1079 csr |= MUSB_TXCSR_FLUSHFIFO; 1080 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) 1081 csr |= MUSB_TXCSR_P_ISO; 1082 1083 /* set twice in case of double buffering */ 1084 musb_writew(regs, MUSB_TXCSR, csr); 1085 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ 1086 musb_writew(regs, MUSB_TXCSR, csr); 1087 1088 } else { 1089 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE); 1090 1091 if (hw_ep->is_shared_fifo) 1092 musb_ep->is_in = 0; 1093 if (musb_ep->is_in) 1094 goto fail; 1095 1096 if (tmp > hw_ep->max_packet_sz_rx) { 1097 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n"); 1098 goto fail; 1099 } 1100 1101 int_rxe |= (1 << epnum); 1102 musb_writew(mbase, MUSB_INTRRXE, int_rxe); 1103 1104 /* REVISIT if can_bulk_combine() use by updating "tmp" 1105 * likewise high bandwidth periodic rx 1106 */ 1107 /* Set RXMAXP with the FIFO size of the endpoint 1108 * to disable double buffering mode. 1109 */ 1110 if (musb->double_buffer_not_ok) 1111 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx); 1112 else 1113 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz 1114 | (musb_ep->hb_mult << 11)); 1115 1116 /* force shared fifo to OUT-only mode */ 1117 if (hw_ep->is_shared_fifo) { 1118 csr = musb_readw(regs, MUSB_TXCSR); 1119 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); 1120 musb_writew(regs, MUSB_TXCSR, csr); 1121 } 1122 1123 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; 1124 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) 1125 csr |= MUSB_RXCSR_P_ISO; 1126 else if (musb_ep->type == USB_ENDPOINT_XFER_INT) 1127 csr |= MUSB_RXCSR_DISNYET; 1128 1129 /* set twice in case of double buffering */ 1130 musb_writew(regs, MUSB_RXCSR, csr); 1131 musb_writew(regs, MUSB_RXCSR, csr); 1132 } 1133 1134 /* NOTE: all the I/O code _should_ work fine without DMA, in case 1135 * for some reason you run out of channels here. 1136 */ 1137 if (is_dma_capable() && musb->dma_controller) { 1138 struct dma_controller *c = musb->dma_controller; 1139 1140 musb_ep->dma = c->channel_alloc(c, hw_ep, 1141 (desc->bEndpointAddress & USB_DIR_IN)); 1142 } else 1143 musb_ep->dma = NULL; 1144 1145 musb_ep->desc = desc; 1146 musb_ep->busy = 0; 1147 musb_ep->wedged = 0; 1148 status = 0; 1149 1150 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", 1151 musb_driver_name, musb_ep->end_point.name, 1152 ({ char *s; switch (musb_ep->type) { 1153 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; 1154 case USB_ENDPOINT_XFER_INT: s = "int"; break; 1155 default: s = "iso"; break; 1156 }; s; }), 1157 musb_ep->is_in ? "IN" : "OUT", 1158 musb_ep->dma ? "dma, " : "", 1159 musb_ep->packet_sz); 1160 1161 schedule_work(&musb->irq_work); 1162 1163 fail: 1164 spin_unlock_irqrestore(&musb->lock, flags); 1165 return status; 1166 } 1167 1168 /* 1169 * Disable an endpoint flushing all requests queued. 1170 */ 1171 static int musb_gadget_disable(struct usb_ep *ep) 1172 { 1173 unsigned long flags; 1174 struct musb *musb; 1175 u8 epnum; 1176 struct musb_ep *musb_ep; 1177 void __iomem *epio; 1178 int status = 0; 1179 1180 musb_ep = to_musb_ep(ep); 1181 musb = musb_ep->musb; 1182 epnum = musb_ep->current_epnum; 1183 epio = musb->endpoints[epnum].regs; 1184 1185 spin_lock_irqsave(&musb->lock, flags); 1186 musb_ep_select(musb->mregs, epnum); 1187 1188 /* zero the endpoint sizes */ 1189 if (musb_ep->is_in) { 1190 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE); 1191 int_txe &= ~(1 << epnum); 1192 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe); 1193 musb_writew(epio, MUSB_TXMAXP, 0); 1194 } else { 1195 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE); 1196 int_rxe &= ~(1 << epnum); 1197 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe); 1198 musb_writew(epio, MUSB_RXMAXP, 0); 1199 } 1200 1201 musb_ep->desc = NULL; 1202 1203 /* abort all pending DMA and requests */ 1204 nuke(musb_ep, -ESHUTDOWN); 1205 1206 schedule_work(&musb->irq_work); 1207 1208 spin_unlock_irqrestore(&(musb->lock), flags); 1209 1210 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name); 1211 1212 return status; 1213 } 1214 1215 /* 1216 * Allocate a request for an endpoint. 1217 * Reused by ep0 code. 1218 */ 1219 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) 1220 { 1221 struct musb_ep *musb_ep = to_musb_ep(ep); 1222 struct musb *musb = musb_ep->musb; 1223 struct musb_request *request = NULL; 1224 1225 request = kzalloc(sizeof *request, gfp_flags); 1226 if (!request) { 1227 dev_dbg(musb->controller, "not enough memory\n"); 1228 return NULL; 1229 } 1230 1231 request->request.dma = DMA_ADDR_INVALID; 1232 request->epnum = musb_ep->current_epnum; 1233 request->ep = musb_ep; 1234 1235 return &request->request; 1236 } 1237 1238 /* 1239 * Free a request 1240 * Reused by ep0 code. 1241 */ 1242 void musb_free_request(struct usb_ep *ep, struct usb_request *req) 1243 { 1244 kfree(to_musb_request(req)); 1245 } 1246 1247 static LIST_HEAD(buffers); 1248 1249 struct free_record { 1250 struct list_head list; 1251 struct device *dev; 1252 unsigned bytes; 1253 dma_addr_t dma; 1254 }; 1255 1256 /* 1257 * Context: controller locked, IRQs blocked. 1258 */ 1259 void musb_ep_restart(struct musb *musb, struct musb_request *req) 1260 { 1261 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n", 1262 req->tx ? "TX/IN" : "RX/OUT", 1263 &req->request, req->request.length, req->epnum); 1264 1265 musb_ep_select(musb->mregs, req->epnum); 1266 if (req->tx) 1267 txstate(musb, req); 1268 else 1269 rxstate(musb, req); 1270 } 1271 1272 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, 1273 gfp_t gfp_flags) 1274 { 1275 struct musb_ep *musb_ep; 1276 struct musb_request *request; 1277 struct musb *musb; 1278 int status = 0; 1279 unsigned long lockflags; 1280 1281 if (!ep || !req) 1282 return -EINVAL; 1283 if (!req->buf) 1284 return -ENODATA; 1285 1286 musb_ep = to_musb_ep(ep); 1287 musb = musb_ep->musb; 1288 1289 request = to_musb_request(req); 1290 request->musb = musb; 1291 1292 if (request->ep != musb_ep) 1293 return -EINVAL; 1294 1295 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req); 1296 1297 /* request is mine now... */ 1298 request->request.actual = 0; 1299 request->request.status = -EINPROGRESS; 1300 request->epnum = musb_ep->current_epnum; 1301 request->tx = musb_ep->is_in; 1302 1303 map_dma_buffer(request, musb, musb_ep); 1304 1305 spin_lock_irqsave(&musb->lock, lockflags); 1306 1307 /* don't queue if the ep is down */ 1308 if (!musb_ep->desc) { 1309 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n", 1310 req, ep->name, "disabled"); 1311 status = -ESHUTDOWN; 1312 goto cleanup; 1313 } 1314 1315 /* add request to the list */ 1316 list_add_tail(&request->list, &musb_ep->req_list); 1317 1318 /* it this is the head of the queue, start i/o ... */ 1319 if (!musb_ep->busy && &request->list == musb_ep->req_list.next) 1320 musb_ep_restart(musb, request); 1321 1322 cleanup: 1323 spin_unlock_irqrestore(&musb->lock, lockflags); 1324 return status; 1325 } 1326 1327 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) 1328 { 1329 struct musb_ep *musb_ep = to_musb_ep(ep); 1330 struct musb_request *req = to_musb_request(request); 1331 struct musb_request *r; 1332 unsigned long flags; 1333 int status = 0; 1334 struct musb *musb = musb_ep->musb; 1335 1336 if (!ep || !request || to_musb_request(request)->ep != musb_ep) 1337 return -EINVAL; 1338 1339 spin_lock_irqsave(&musb->lock, flags); 1340 1341 list_for_each_entry(r, &musb_ep->req_list, list) { 1342 if (r == req) 1343 break; 1344 } 1345 if (r != req) { 1346 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name); 1347 status = -EINVAL; 1348 goto done; 1349 } 1350 1351 /* if the hardware doesn't have the request, easy ... */ 1352 if (musb_ep->req_list.next != &req->list || musb_ep->busy) 1353 musb_g_giveback(musb_ep, request, -ECONNRESET); 1354 1355 /* ... else abort the dma transfer ... */ 1356 else if (is_dma_capable() && musb_ep->dma) { 1357 struct dma_controller *c = musb->dma_controller; 1358 1359 musb_ep_select(musb->mregs, musb_ep->current_epnum); 1360 if (c->channel_abort) 1361 status = c->channel_abort(musb_ep->dma); 1362 else 1363 status = -EBUSY; 1364 if (status == 0) 1365 musb_g_giveback(musb_ep, request, -ECONNRESET); 1366 } else { 1367 /* NOTE: by sticking to easily tested hardware/driver states, 1368 * we leave counting of in-flight packets imprecise. 1369 */ 1370 musb_g_giveback(musb_ep, request, -ECONNRESET); 1371 } 1372 1373 done: 1374 spin_unlock_irqrestore(&musb->lock, flags); 1375 return status; 1376 } 1377 1378 /* 1379 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any 1380 * data but will queue requests. 1381 * 1382 * exported to ep0 code 1383 */ 1384 static int musb_gadget_set_halt(struct usb_ep *ep, int value) 1385 { 1386 struct musb_ep *musb_ep = to_musb_ep(ep); 1387 u8 epnum = musb_ep->current_epnum; 1388 struct musb *musb = musb_ep->musb; 1389 void __iomem *epio = musb->endpoints[epnum].regs; 1390 void __iomem *mbase; 1391 unsigned long flags; 1392 u16 csr; 1393 struct musb_request *request; 1394 int status = 0; 1395 1396 if (!ep) 1397 return -EINVAL; 1398 mbase = musb->mregs; 1399 1400 spin_lock_irqsave(&musb->lock, flags); 1401 1402 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { 1403 status = -EINVAL; 1404 goto done; 1405 } 1406 1407 musb_ep_select(mbase, epnum); 1408 1409 request = next_request(musb_ep); 1410 if (value) { 1411 if (request) { 1412 dev_dbg(musb->controller, "request in progress, cannot halt %s\n", 1413 ep->name); 1414 status = -EAGAIN; 1415 goto done; 1416 } 1417 /* Cannot portably stall with non-empty FIFO */ 1418 if (musb_ep->is_in) { 1419 csr = musb_readw(epio, MUSB_TXCSR); 1420 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1421 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name); 1422 status = -EAGAIN; 1423 goto done; 1424 } 1425 } 1426 } else 1427 musb_ep->wedged = 0; 1428 1429 /* set/clear the stall and toggle bits */ 1430 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear"); 1431 if (musb_ep->is_in) { 1432 csr = musb_readw(epio, MUSB_TXCSR); 1433 csr |= MUSB_TXCSR_P_WZC_BITS 1434 | MUSB_TXCSR_CLRDATATOG; 1435 if (value) 1436 csr |= MUSB_TXCSR_P_SENDSTALL; 1437 else 1438 csr &= ~(MUSB_TXCSR_P_SENDSTALL 1439 | MUSB_TXCSR_P_SENTSTALL); 1440 csr &= ~MUSB_TXCSR_TXPKTRDY; 1441 musb_writew(epio, MUSB_TXCSR, csr); 1442 } else { 1443 csr = musb_readw(epio, MUSB_RXCSR); 1444 csr |= MUSB_RXCSR_P_WZC_BITS 1445 | MUSB_RXCSR_FLUSHFIFO 1446 | MUSB_RXCSR_CLRDATATOG; 1447 if (value) 1448 csr |= MUSB_RXCSR_P_SENDSTALL; 1449 else 1450 csr &= ~(MUSB_RXCSR_P_SENDSTALL 1451 | MUSB_RXCSR_P_SENTSTALL); 1452 musb_writew(epio, MUSB_RXCSR, csr); 1453 } 1454 1455 /* maybe start the first request in the queue */ 1456 if (!musb_ep->busy && !value && request) { 1457 dev_dbg(musb->controller, "restarting the request\n"); 1458 musb_ep_restart(musb, request); 1459 } 1460 1461 done: 1462 spin_unlock_irqrestore(&musb->lock, flags); 1463 return status; 1464 } 1465 1466 /* 1467 * Sets the halt feature with the clear requests ignored 1468 */ 1469 static int musb_gadget_set_wedge(struct usb_ep *ep) 1470 { 1471 struct musb_ep *musb_ep = to_musb_ep(ep); 1472 1473 if (!ep) 1474 return -EINVAL; 1475 1476 musb_ep->wedged = 1; 1477 1478 return usb_ep_set_halt(ep); 1479 } 1480 1481 static int musb_gadget_fifo_status(struct usb_ep *ep) 1482 { 1483 struct musb_ep *musb_ep = to_musb_ep(ep); 1484 void __iomem *epio = musb_ep->hw_ep->regs; 1485 int retval = -EINVAL; 1486 1487 if (musb_ep->desc && !musb_ep->is_in) { 1488 struct musb *musb = musb_ep->musb; 1489 int epnum = musb_ep->current_epnum; 1490 void __iomem *mbase = musb->mregs; 1491 unsigned long flags; 1492 1493 spin_lock_irqsave(&musb->lock, flags); 1494 1495 musb_ep_select(mbase, epnum); 1496 /* FIXME return zero unless RXPKTRDY is set */ 1497 retval = musb_readw(epio, MUSB_RXCOUNT); 1498 1499 spin_unlock_irqrestore(&musb->lock, flags); 1500 } 1501 return retval; 1502 } 1503 1504 static void musb_gadget_fifo_flush(struct usb_ep *ep) 1505 { 1506 struct musb_ep *musb_ep = to_musb_ep(ep); 1507 struct musb *musb = musb_ep->musb; 1508 u8 epnum = musb_ep->current_epnum; 1509 void __iomem *epio = musb->endpoints[epnum].regs; 1510 void __iomem *mbase; 1511 unsigned long flags; 1512 u16 csr, int_txe; 1513 1514 mbase = musb->mregs; 1515 1516 spin_lock_irqsave(&musb->lock, flags); 1517 musb_ep_select(mbase, (u8) epnum); 1518 1519 /* disable interrupts */ 1520 int_txe = musb_readw(mbase, MUSB_INTRTXE); 1521 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); 1522 1523 if (musb_ep->is_in) { 1524 csr = musb_readw(epio, MUSB_TXCSR); 1525 if (csr & MUSB_TXCSR_FIFONOTEMPTY) { 1526 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; 1527 /* 1528 * Setting both TXPKTRDY and FLUSHFIFO makes controller 1529 * to interrupt current FIFO loading, but not flushing 1530 * the already loaded ones. 1531 */ 1532 csr &= ~MUSB_TXCSR_TXPKTRDY; 1533 musb_writew(epio, MUSB_TXCSR, csr); 1534 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ 1535 musb_writew(epio, MUSB_TXCSR, csr); 1536 } 1537 } else { 1538 csr = musb_readw(epio, MUSB_RXCSR); 1539 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; 1540 musb_writew(epio, MUSB_RXCSR, csr); 1541 musb_writew(epio, MUSB_RXCSR, csr); 1542 } 1543 1544 /* re-enable interrupt */ 1545 musb_writew(mbase, MUSB_INTRTXE, int_txe); 1546 spin_unlock_irqrestore(&musb->lock, flags); 1547 } 1548 1549 static const struct usb_ep_ops musb_ep_ops = { 1550 .enable = musb_gadget_enable, 1551 .disable = musb_gadget_disable, 1552 .alloc_request = musb_alloc_request, 1553 .free_request = musb_free_request, 1554 .queue = musb_gadget_queue, 1555 .dequeue = musb_gadget_dequeue, 1556 .set_halt = musb_gadget_set_halt, 1557 .set_wedge = musb_gadget_set_wedge, 1558 .fifo_status = musb_gadget_fifo_status, 1559 .fifo_flush = musb_gadget_fifo_flush 1560 }; 1561 1562 /* ----------------------------------------------------------------------- */ 1563 1564 static int musb_gadget_get_frame(struct usb_gadget *gadget) 1565 { 1566 struct musb *musb = gadget_to_musb(gadget); 1567 1568 return (int)musb_readw(musb->mregs, MUSB_FRAME); 1569 } 1570 1571 static int musb_gadget_wakeup(struct usb_gadget *gadget) 1572 { 1573 struct musb *musb = gadget_to_musb(gadget); 1574 void __iomem *mregs = musb->mregs; 1575 unsigned long flags; 1576 int status = -EINVAL; 1577 u8 power, devctl; 1578 int retries; 1579 1580 spin_lock_irqsave(&musb->lock, flags); 1581 1582 switch (musb->xceiv->state) { 1583 case OTG_STATE_B_PERIPHERAL: 1584 /* NOTE: OTG state machine doesn't include B_SUSPENDED; 1585 * that's part of the standard usb 1.1 state machine, and 1586 * doesn't affect OTG transitions. 1587 */ 1588 if (musb->may_wakeup && musb->is_suspended) 1589 break; 1590 goto done; 1591 case OTG_STATE_B_IDLE: 1592 /* Start SRP ... OTG not required. */ 1593 devctl = musb_readb(mregs, MUSB_DEVCTL); 1594 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl); 1595 devctl |= MUSB_DEVCTL_SESSION; 1596 musb_writeb(mregs, MUSB_DEVCTL, devctl); 1597 devctl = musb_readb(mregs, MUSB_DEVCTL); 1598 retries = 100; 1599 while (!(devctl & MUSB_DEVCTL_SESSION)) { 1600 devctl = musb_readb(mregs, MUSB_DEVCTL); 1601 if (retries-- < 1) 1602 break; 1603 } 1604 retries = 10000; 1605 while (devctl & MUSB_DEVCTL_SESSION) { 1606 devctl = musb_readb(mregs, MUSB_DEVCTL); 1607 if (retries-- < 1) 1608 break; 1609 } 1610 1611 spin_unlock_irqrestore(&musb->lock, flags); 1612 otg_start_srp(musb->xceiv); 1613 spin_lock_irqsave(&musb->lock, flags); 1614 1615 /* Block idling for at least 1s */ 1616 musb_platform_try_idle(musb, 1617 jiffies + msecs_to_jiffies(1 * HZ)); 1618 1619 status = 0; 1620 goto done; 1621 default: 1622 dev_dbg(musb->controller, "Unhandled wake: %s\n", 1623 otg_state_string(musb->xceiv->state)); 1624 goto done; 1625 } 1626 1627 status = 0; 1628 1629 power = musb_readb(mregs, MUSB_POWER); 1630 power |= MUSB_POWER_RESUME; 1631 musb_writeb(mregs, MUSB_POWER, power); 1632 dev_dbg(musb->controller, "issue wakeup\n"); 1633 1634 /* FIXME do this next chunk in a timer callback, no udelay */ 1635 mdelay(2); 1636 1637 power = musb_readb(mregs, MUSB_POWER); 1638 power &= ~MUSB_POWER_RESUME; 1639 musb_writeb(mregs, MUSB_POWER, power); 1640 done: 1641 spin_unlock_irqrestore(&musb->lock, flags); 1642 return status; 1643 } 1644 1645 static int 1646 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) 1647 { 1648 struct musb *musb = gadget_to_musb(gadget); 1649 1650 musb->is_self_powered = !!is_selfpowered; 1651 return 0; 1652 } 1653 1654 static void musb_pullup(struct musb *musb, int is_on) 1655 { 1656 u8 power; 1657 1658 power = musb_readb(musb->mregs, MUSB_POWER); 1659 if (is_on) 1660 power |= MUSB_POWER_SOFTCONN; 1661 else 1662 power &= ~MUSB_POWER_SOFTCONN; 1663 1664 /* FIXME if on, HdrcStart; if off, HdrcStop */ 1665 1666 dev_dbg(musb->controller, "gadget %s D+ pullup %s\n", 1667 musb->gadget_driver->function, is_on ? "on" : "off"); 1668 musb_writeb(musb->mregs, MUSB_POWER, power); 1669 } 1670 1671 #if 0 1672 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) 1673 { 1674 dev_dbg(musb->controller, "<= %s =>\n", __func__); 1675 1676 /* 1677 * FIXME iff driver's softconnect flag is set (as it is during probe, 1678 * though that can clear it), just musb_pullup(). 1679 */ 1680 1681 return -EINVAL; 1682 } 1683 #endif 1684 1685 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) 1686 { 1687 struct musb *musb = gadget_to_musb(gadget); 1688 1689 if (!musb->xceiv->set_power) 1690 return -EOPNOTSUPP; 1691 return otg_set_power(musb->xceiv, mA); 1692 } 1693 1694 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) 1695 { 1696 struct musb *musb = gadget_to_musb(gadget); 1697 unsigned long flags; 1698 1699 is_on = !!is_on; 1700 1701 /* NOTE: this assumes we are sensing vbus; we'd rather 1702 * not pullup unless the B-session is active. 1703 */ 1704 spin_lock_irqsave(&musb->lock, flags); 1705 if (is_on != musb->softconnect) { 1706 musb->softconnect = is_on; 1707 musb_pullup(musb, is_on); 1708 } 1709 spin_unlock_irqrestore(&musb->lock, flags); 1710 return 0; 1711 } 1712 1713 static const struct usb_gadget_ops musb_gadget_operations = { 1714 .get_frame = musb_gadget_get_frame, 1715 .wakeup = musb_gadget_wakeup, 1716 .set_selfpowered = musb_gadget_set_self_powered, 1717 /* .vbus_session = musb_gadget_vbus_session, */ 1718 .vbus_draw = musb_gadget_vbus_draw, 1719 .pullup = musb_gadget_pullup, 1720 }; 1721 1722 /* ----------------------------------------------------------------------- */ 1723 1724 /* Registration */ 1725 1726 /* Only this registration code "knows" the rule (from USB standards) 1727 * about there being only one external upstream port. It assumes 1728 * all peripheral ports are external... 1729 */ 1730 static struct musb *the_gadget; 1731 1732 static void musb_gadget_release(struct device *dev) 1733 { 1734 /* kref_put(WHAT) */ 1735 dev_dbg(dev, "%s\n", __func__); 1736 } 1737 1738 1739 static void __init 1740 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) 1741 { 1742 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; 1743 1744 memset(ep, 0, sizeof *ep); 1745 1746 ep->current_epnum = epnum; 1747 ep->musb = musb; 1748 ep->hw_ep = hw_ep; 1749 ep->is_in = is_in; 1750 1751 INIT_LIST_HEAD(&ep->req_list); 1752 1753 sprintf(ep->name, "ep%d%s", epnum, 1754 (!epnum || hw_ep->is_shared_fifo) ? "" : ( 1755 is_in ? "in" : "out")); 1756 ep->end_point.name = ep->name; 1757 INIT_LIST_HEAD(&ep->end_point.ep_list); 1758 if (!epnum) { 1759 ep->end_point.maxpacket = 64; 1760 ep->end_point.ops = &musb_g_ep0_ops; 1761 musb->g.ep0 = &ep->end_point; 1762 } else { 1763 if (is_in) 1764 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx; 1765 else 1766 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx; 1767 ep->end_point.ops = &musb_ep_ops; 1768 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); 1769 } 1770 } 1771 1772 /* 1773 * Initialize the endpoints exposed to peripheral drivers, with backlinks 1774 * to the rest of the driver state. 1775 */ 1776 static inline void __init musb_g_init_endpoints(struct musb *musb) 1777 { 1778 u8 epnum; 1779 struct musb_hw_ep *hw_ep; 1780 unsigned count = 0; 1781 1782 /* initialize endpoint list just once */ 1783 INIT_LIST_HEAD(&(musb->g.ep_list)); 1784 1785 for (epnum = 0, hw_ep = musb->endpoints; 1786 epnum < musb->nr_endpoints; 1787 epnum++, hw_ep++) { 1788 if (hw_ep->is_shared_fifo /* || !epnum */) { 1789 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); 1790 count++; 1791 } else { 1792 if (hw_ep->max_packet_sz_tx) { 1793 init_peripheral_ep(musb, &hw_ep->ep_in, 1794 epnum, 1); 1795 count++; 1796 } 1797 if (hw_ep->max_packet_sz_rx) { 1798 init_peripheral_ep(musb, &hw_ep->ep_out, 1799 epnum, 0); 1800 count++; 1801 } 1802 } 1803 } 1804 } 1805 1806 /* called once during driver setup to initialize and link into 1807 * the driver model; memory is zeroed. 1808 */ 1809 int __init musb_gadget_setup(struct musb *musb) 1810 { 1811 int status; 1812 1813 /* REVISIT minor race: if (erroneously) setting up two 1814 * musb peripherals at the same time, only the bus lock 1815 * is probably held. 1816 */ 1817 if (the_gadget) 1818 return -EBUSY; 1819 the_gadget = musb; 1820 1821 musb->g.ops = &musb_gadget_operations; 1822 musb->g.is_dualspeed = 1; 1823 musb->g.speed = USB_SPEED_UNKNOWN; 1824 1825 /* this "gadget" abstracts/virtualizes the controller */ 1826 dev_set_name(&musb->g.dev, "gadget"); 1827 musb->g.dev.parent = musb->controller; 1828 musb->g.dev.dma_mask = musb->controller->dma_mask; 1829 musb->g.dev.release = musb_gadget_release; 1830 musb->g.name = musb_driver_name; 1831 1832 if (is_otg_enabled(musb)) 1833 musb->g.is_otg = 1; 1834 1835 musb_g_init_endpoints(musb); 1836 1837 musb->is_active = 0; 1838 musb_platform_try_idle(musb, 0); 1839 1840 status = device_register(&musb->g.dev); 1841 if (status != 0) { 1842 put_device(&musb->g.dev); 1843 the_gadget = NULL; 1844 } 1845 return status; 1846 } 1847 1848 void musb_gadget_cleanup(struct musb *musb) 1849 { 1850 if (musb != the_gadget) 1851 return; 1852 1853 device_unregister(&musb->g.dev); 1854 the_gadget = NULL; 1855 } 1856 1857 /* 1858 * Register the gadget driver. Used by gadget drivers when 1859 * registering themselves with the controller. 1860 * 1861 * -EINVAL something went wrong (not driver) 1862 * -EBUSY another gadget is already using the controller 1863 * -ENOMEM no memory to perform the operation 1864 * 1865 * @param driver the gadget driver 1866 * @param bind the driver's bind function 1867 * @return <0 if error, 0 if everything is fine 1868 */ 1869 int usb_gadget_probe_driver(struct usb_gadget_driver *driver, 1870 int (*bind)(struct usb_gadget *)) 1871 { 1872 struct musb *musb = the_gadget; 1873 unsigned long flags; 1874 int retval = -EINVAL; 1875 1876 if (!driver 1877 || driver->speed != USB_SPEED_HIGH 1878 || !bind || !driver->setup) 1879 goto err0; 1880 1881 /* driver must be initialized to support peripheral mode */ 1882 if (!musb) { 1883 dev_dbg(musb->controller, "no dev??\n"); 1884 retval = -ENODEV; 1885 goto err0; 1886 } 1887 1888 pm_runtime_get_sync(musb->controller); 1889 1890 dev_dbg(musb->controller, "registering driver %s\n", driver->function); 1891 1892 if (musb->gadget_driver) { 1893 dev_dbg(musb->controller, "%s is already bound to %s\n", 1894 musb_driver_name, 1895 musb->gadget_driver->driver.name); 1896 retval = -EBUSY; 1897 goto err0; 1898 } 1899 1900 spin_lock_irqsave(&musb->lock, flags); 1901 musb->gadget_driver = driver; 1902 musb->g.dev.driver = &driver->driver; 1903 driver->driver.bus = NULL; 1904 musb->softconnect = 1; 1905 spin_unlock_irqrestore(&musb->lock, flags); 1906 1907 retval = bind(&musb->g); 1908 if (retval) { 1909 dev_dbg(musb->controller, "bind to driver %s failed --> %d\n", 1910 driver->driver.name, retval); 1911 goto err1; 1912 } 1913 1914 spin_lock_irqsave(&musb->lock, flags); 1915 1916 otg_set_peripheral(musb->xceiv, &musb->g); 1917 musb->xceiv->state = OTG_STATE_B_IDLE; 1918 musb->is_active = 1; 1919 1920 /* 1921 * FIXME this ignores the softconnect flag. Drivers are 1922 * allowed hold the peripheral inactive until for example 1923 * userspace hooks up printer hardware or DSP codecs, so 1924 * hosts only see fully functional devices. 1925 */ 1926 1927 if (!is_otg_enabled(musb)) 1928 musb_start(musb); 1929 1930 otg_set_peripheral(musb->xceiv, &musb->g); 1931 1932 spin_unlock_irqrestore(&musb->lock, flags); 1933 1934 if (is_otg_enabled(musb)) { 1935 struct usb_hcd *hcd = musb_to_hcd(musb); 1936 1937 dev_dbg(musb->controller, "OTG startup...\n"); 1938 1939 /* REVISIT: funcall to other code, which also 1940 * handles power budgeting ... this way also 1941 * ensures HdrcStart is indirectly called. 1942 */ 1943 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); 1944 if (retval < 0) { 1945 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval); 1946 goto err2; 1947 } 1948 1949 if ((musb->xceiv->last_event == USB_EVENT_ID) 1950 && musb->xceiv->set_vbus) 1951 otg_set_vbus(musb->xceiv, 1); 1952 1953 hcd->self.uses_pio_for_control = 1; 1954 } 1955 if (musb->xceiv->last_event == USB_EVENT_NONE) 1956 pm_runtime_put(musb->controller); 1957 1958 return 0; 1959 1960 err2: 1961 if (!is_otg_enabled(musb)) 1962 musb_stop(musb); 1963 1964 err1: 1965 musb->gadget_driver = NULL; 1966 musb->g.dev.driver = NULL; 1967 1968 err0: 1969 return retval; 1970 } 1971 EXPORT_SYMBOL(usb_gadget_probe_driver); 1972 1973 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver) 1974 { 1975 int i; 1976 struct musb_hw_ep *hw_ep; 1977 1978 /* don't disconnect if it's not connected */ 1979 if (musb->g.speed == USB_SPEED_UNKNOWN) 1980 driver = NULL; 1981 else 1982 musb->g.speed = USB_SPEED_UNKNOWN; 1983 1984 /* deactivate the hardware */ 1985 if (musb->softconnect) { 1986 musb->softconnect = 0; 1987 musb_pullup(musb, 0); 1988 } 1989 musb_stop(musb); 1990 1991 /* killing any outstanding requests will quiesce the driver; 1992 * then report disconnect 1993 */ 1994 if (driver) { 1995 for (i = 0, hw_ep = musb->endpoints; 1996 i < musb->nr_endpoints; 1997 i++, hw_ep++) { 1998 musb_ep_select(musb->mregs, i); 1999 if (hw_ep->is_shared_fifo /* || !epnum */) { 2000 nuke(&hw_ep->ep_in, -ESHUTDOWN); 2001 } else { 2002 if (hw_ep->max_packet_sz_tx) 2003 nuke(&hw_ep->ep_in, -ESHUTDOWN); 2004 if (hw_ep->max_packet_sz_rx) 2005 nuke(&hw_ep->ep_out, -ESHUTDOWN); 2006 } 2007 } 2008 2009 spin_unlock(&musb->lock); 2010 driver->disconnect(&musb->g); 2011 spin_lock(&musb->lock); 2012 } 2013 } 2014 2015 /* 2016 * Unregister the gadget driver. Used by gadget drivers when 2017 * unregistering themselves from the controller. 2018 * 2019 * @param driver the gadget driver to unregister 2020 */ 2021 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) 2022 { 2023 struct musb *musb = the_gadget; 2024 unsigned long flags; 2025 2026 if (!driver || !driver->unbind || !musb) 2027 return -EINVAL; 2028 2029 if (!musb->gadget_driver) 2030 return -EINVAL; 2031 2032 if (musb->xceiv->last_event == USB_EVENT_NONE) 2033 pm_runtime_get_sync(musb->controller); 2034 2035 /* 2036 * REVISIT always use otg_set_peripheral() here too; 2037 * this needs to shut down the OTG engine. 2038 */ 2039 2040 spin_lock_irqsave(&musb->lock, flags); 2041 2042 #ifdef CONFIG_USB_MUSB_OTG 2043 musb_hnp_stop(musb); 2044 #endif 2045 2046 (void) musb_gadget_vbus_draw(&musb->g, 0); 2047 2048 musb->xceiv->state = OTG_STATE_UNDEFINED; 2049 stop_activity(musb, driver); 2050 otg_set_peripheral(musb->xceiv, NULL); 2051 2052 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function); 2053 2054 spin_unlock_irqrestore(&musb->lock, flags); 2055 driver->unbind(&musb->g); 2056 spin_lock_irqsave(&musb->lock, flags); 2057 2058 musb->gadget_driver = NULL; 2059 musb->g.dev.driver = NULL; 2060 2061 musb->is_active = 0; 2062 musb_platform_try_idle(musb, 0); 2063 spin_unlock_irqrestore(&musb->lock, flags); 2064 2065 if (is_otg_enabled(musb)) { 2066 usb_remove_hcd(musb_to_hcd(musb)); 2067 /* FIXME we need to be able to register another 2068 * gadget driver here and have everything work; 2069 * that currently misbehaves. 2070 */ 2071 } 2072 2073 if (!is_otg_enabled(musb)) 2074 musb_stop(musb); 2075 2076 pm_runtime_put(musb->controller); 2077 2078 return 0; 2079 } 2080 EXPORT_SYMBOL(usb_gadget_unregister_driver); 2081 2082 2083 /* ----------------------------------------------------------------------- */ 2084 2085 /* lifecycle operations called through plat_uds.c */ 2086 2087 void musb_g_resume(struct musb *musb) 2088 { 2089 musb->is_suspended = 0; 2090 switch (musb->xceiv->state) { 2091 case OTG_STATE_B_IDLE: 2092 break; 2093 case OTG_STATE_B_WAIT_ACON: 2094 case OTG_STATE_B_PERIPHERAL: 2095 musb->is_active = 1; 2096 if (musb->gadget_driver && musb->gadget_driver->resume) { 2097 spin_unlock(&musb->lock); 2098 musb->gadget_driver->resume(&musb->g); 2099 spin_lock(&musb->lock); 2100 } 2101 break; 2102 default: 2103 WARNING("unhandled RESUME transition (%s)\n", 2104 otg_state_string(musb->xceiv->state)); 2105 } 2106 } 2107 2108 /* called when SOF packets stop for 3+ msec */ 2109 void musb_g_suspend(struct musb *musb) 2110 { 2111 u8 devctl; 2112 2113 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); 2114 dev_dbg(musb->controller, "devctl %02x\n", devctl); 2115 2116 switch (musb->xceiv->state) { 2117 case OTG_STATE_B_IDLE: 2118 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) 2119 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 2120 break; 2121 case OTG_STATE_B_PERIPHERAL: 2122 musb->is_suspended = 1; 2123 if (musb->gadget_driver && musb->gadget_driver->suspend) { 2124 spin_unlock(&musb->lock); 2125 musb->gadget_driver->suspend(&musb->g); 2126 spin_lock(&musb->lock); 2127 } 2128 break; 2129 default: 2130 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; 2131 * A_PERIPHERAL may need care too 2132 */ 2133 WARNING("unhandled SUSPEND transition (%s)\n", 2134 otg_state_string(musb->xceiv->state)); 2135 } 2136 } 2137 2138 /* Called during SRP */ 2139 void musb_g_wakeup(struct musb *musb) 2140 { 2141 musb_gadget_wakeup(&musb->g); 2142 } 2143 2144 /* called when VBUS drops below session threshold, and in other cases */ 2145 void musb_g_disconnect(struct musb *musb) 2146 { 2147 void __iomem *mregs = musb->mregs; 2148 u8 devctl = musb_readb(mregs, MUSB_DEVCTL); 2149 2150 dev_dbg(musb->controller, "devctl %02x\n", devctl); 2151 2152 /* clear HR */ 2153 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); 2154 2155 /* don't draw vbus until new b-default session */ 2156 (void) musb_gadget_vbus_draw(&musb->g, 0); 2157 2158 musb->g.speed = USB_SPEED_UNKNOWN; 2159 if (musb->gadget_driver && musb->gadget_driver->disconnect) { 2160 spin_unlock(&musb->lock); 2161 musb->gadget_driver->disconnect(&musb->g); 2162 spin_lock(&musb->lock); 2163 } 2164 2165 switch (musb->xceiv->state) { 2166 default: 2167 #ifdef CONFIG_USB_MUSB_OTG 2168 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n", 2169 otg_state_string(musb->xceiv->state)); 2170 musb->xceiv->state = OTG_STATE_A_IDLE; 2171 MUSB_HST_MODE(musb); 2172 break; 2173 case OTG_STATE_A_PERIPHERAL: 2174 musb->xceiv->state = OTG_STATE_A_WAIT_BCON; 2175 MUSB_HST_MODE(musb); 2176 break; 2177 case OTG_STATE_B_WAIT_ACON: 2178 case OTG_STATE_B_HOST: 2179 #endif 2180 case OTG_STATE_B_PERIPHERAL: 2181 case OTG_STATE_B_IDLE: 2182 musb->xceiv->state = OTG_STATE_B_IDLE; 2183 break; 2184 case OTG_STATE_B_SRP_INIT: 2185 break; 2186 } 2187 2188 musb->is_active = 0; 2189 } 2190 2191 void musb_g_reset(struct musb *musb) 2192 __releases(musb->lock) 2193 __acquires(musb->lock) 2194 { 2195 void __iomem *mbase = musb->mregs; 2196 u8 devctl = musb_readb(mbase, MUSB_DEVCTL); 2197 u8 power; 2198 2199 dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n", 2200 (devctl & MUSB_DEVCTL_BDEVICE) 2201 ? "B-Device" : "A-Device", 2202 musb_readb(mbase, MUSB_FADDR), 2203 musb->gadget_driver 2204 ? musb->gadget_driver->driver.name 2205 : NULL 2206 ); 2207 2208 /* report disconnect, if we didn't already (flushing EP state) */ 2209 if (musb->g.speed != USB_SPEED_UNKNOWN) 2210 musb_g_disconnect(musb); 2211 2212 /* clear HR */ 2213 else if (devctl & MUSB_DEVCTL_HR) 2214 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); 2215 2216 2217 /* what speed did we negotiate? */ 2218 power = musb_readb(mbase, MUSB_POWER); 2219 musb->g.speed = (power & MUSB_POWER_HSMODE) 2220 ? USB_SPEED_HIGH : USB_SPEED_FULL; 2221 2222 /* start in USB_STATE_DEFAULT */ 2223 musb->is_active = 1; 2224 musb->is_suspended = 0; 2225 MUSB_DEV_MODE(musb); 2226 musb->address = 0; 2227 musb->ep0_state = MUSB_EP0_STAGE_SETUP; 2228 2229 musb->may_wakeup = 0; 2230 musb->g.b_hnp_enable = 0; 2231 musb->g.a_alt_hnp_support = 0; 2232 musb->g.a_hnp_support = 0; 2233 2234 /* Normal reset, as B-Device; 2235 * or else after HNP, as A-Device 2236 */ 2237 if (devctl & MUSB_DEVCTL_BDEVICE) { 2238 musb->xceiv->state = OTG_STATE_B_PERIPHERAL; 2239 musb->g.is_a_peripheral = 0; 2240 } else if (is_otg_enabled(musb)) { 2241 musb->xceiv->state = OTG_STATE_A_PERIPHERAL; 2242 musb->g.is_a_peripheral = 1; 2243 } else 2244 WARN_ON(1); 2245 2246 /* start with default limits on VBUS power draw */ 2247 (void) musb_gadget_vbus_draw(&musb->g, 2248 is_otg_enabled(musb) ? 8 : 100); 2249 } 2250